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Repository: linklayer/cantact-fw
Branch: master
Commit: 26bedc6359e2
Files: 198
Total size: 8.1 MB

Directory structure:
gitextract_b4tw7xpg/

├── .gitignore
├── .travis.yml
├── Drivers/
│   ├── CMSIS/
│   │   ├── Device/
│   │   │   └── ST/
│   │   │       └── STM32F0xx/
│   │   │           ├── Include/
│   │   │           │   ├── stm32f030x6.h
│   │   │           │   ├── stm32f030x8.h
│   │   │           │   ├── stm32f031x6.h
│   │   │           │   ├── stm32f038xx.h
│   │   │           │   ├── stm32f042x6.h
│   │   │           │   ├── stm32f048xx.h
│   │   │           │   ├── stm32f051x8.h
│   │   │           │   ├── stm32f058xx.h
│   │   │           │   ├── stm32f071xb.h
│   │   │           │   ├── stm32f072xb.h
│   │   │           │   ├── stm32f078xx.h
│   │   │           │   ├── stm32f091xc.h
│   │   │           │   ├── stm32f098xx.h
│   │   │           │   ├── stm32f0xx.h
│   │   │           │   └── system_stm32f0xx.h
│   │   │           └── Source/
│   │   │               └── Templates/
│   │   │                   ├── arm/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   ├── gcc/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   ├── iar/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   └── system_stm32f0xx.c
│   │   ├── Include/
│   │   │   ├── arm_common_tables.h
│   │   │   ├── arm_const_structs.h
│   │   │   ├── arm_math.h
│   │   │   ├── core_cm0.h
│   │   │   ├── core_cm0plus.h
│   │   │   ├── core_cm3.h
│   │   │   ├── core_cm4.h
│   │   │   ├── core_cm4_simd.h
│   │   │   ├── core_cmFunc.h
│   │   │   ├── core_cmInstr.h
│   │   │   ├── core_sc000.h
│   │   │   └── core_sc300.h
│   │   └── RTOS/
│   │       └── cmsis_os.h
│   └── STM32F0xx_HAL_Driver/
│       ├── Inc/
│       │   ├── stm32f0xx_hal.h
│       │   ├── stm32f0xx_hal_adc.h
│       │   ├── stm32f0xx_hal_adc_ex.h
│       │   ├── stm32f0xx_hal_can.h
│       │   ├── stm32f0xx_hal_cec.h
│       │   ├── stm32f0xx_hal_comp.h
│       │   ├── stm32f0xx_hal_conf_template.h
│       │   ├── stm32f0xx_hal_cortex.h
│       │   ├── stm32f0xx_hal_crc.h
│       │   ├── stm32f0xx_hal_crc_ex.h
│       │   ├── stm32f0xx_hal_dac.h
│       │   ├── stm32f0xx_hal_dac_ex.h
│       │   ├── stm32f0xx_hal_def.h
│       │   ├── stm32f0xx_hal_dma.h
│       │   ├── stm32f0xx_hal_dma_ex.h
│       │   ├── stm32f0xx_hal_flash.h
│       │   ├── stm32f0xx_hal_flash_ex.h
│       │   ├── stm32f0xx_hal_gpio.h
│       │   ├── stm32f0xx_hal_gpio_ex.h
│       │   ├── stm32f0xx_hal_i2c.h
│       │   ├── stm32f0xx_hal_i2c_ex.h
│       │   ├── stm32f0xx_hal_i2s.h
│       │   ├── stm32f0xx_hal_irda.h
│       │   ├── stm32f0xx_hal_irda_ex.h
│       │   ├── stm32f0xx_hal_iwdg.h
│       │   ├── stm32f0xx_hal_pcd.h
│       │   ├── stm32f0xx_hal_pcd_ex.h
│       │   ├── stm32f0xx_hal_ppp.h
│       │   ├── stm32f0xx_hal_pwr.h
│       │   ├── stm32f0xx_hal_pwr_ex.h
│       │   ├── stm32f0xx_hal_rcc.h
│       │   ├── stm32f0xx_hal_rcc_ex.h
│       │   ├── stm32f0xx_hal_rtc.h
│       │   ├── stm32f0xx_hal_rtc_ex.h
│       │   ├── stm32f0xx_hal_smartcard.h
│       │   ├── stm32f0xx_hal_smartcard_ex.h
│       │   ├── stm32f0xx_hal_smbus.h
│       │   ├── stm32f0xx_hal_spi.h
│       │   ├── stm32f0xx_hal_tim.h
│       │   ├── stm32f0xx_hal_tim_ex.h
│       │   ├── stm32f0xx_hal_tsc.h
│       │   ├── stm32f0xx_hal_uart.h
│       │   ├── stm32f0xx_hal_uart_ex.h
│       │   ├── stm32f0xx_hal_usart.h
│       │   ├── stm32f0xx_hal_usart_ex.h
│       │   └── stm32f0xx_hal_wwdg.h
│       └── Src/
│           ├── stm32f0xx_hal.c
│           ├── stm32f0xx_hal_adc.c
│           ├── stm32f0xx_hal_adc_ex.c
│           ├── stm32f0xx_hal_can.c
│           ├── stm32f0xx_hal_cec.c
│           ├── stm32f0xx_hal_comp.c
│           ├── stm32f0xx_hal_cortex.c
│           ├── stm32f0xx_hal_crc.c
│           ├── stm32f0xx_hal_crc_ex.c
│           ├── stm32f0xx_hal_dac.c
│           ├── stm32f0xx_hal_dac_ex.c
│           ├── stm32f0xx_hal_dma.c
│           ├── stm32f0xx_hal_flash.c
│           ├── stm32f0xx_hal_flash_ex.c
│           ├── stm32f0xx_hal_gpio.c
│           ├── stm32f0xx_hal_i2c.c
│           ├── stm32f0xx_hal_i2c_ex.c
│           ├── stm32f0xx_hal_i2s.c
│           ├── stm32f0xx_hal_irda.c
│           ├── stm32f0xx_hal_iwdg.c
│           ├── stm32f0xx_hal_msp_template.c
│           ├── stm32f0xx_hal_pcd.c
│           ├── stm32f0xx_hal_pcd_ex.c
│           ├── stm32f0xx_hal_ppp.c
│           ├── stm32f0xx_hal_pwr.c
│           ├── stm32f0xx_hal_pwr_ex.c
│           ├── stm32f0xx_hal_rcc.c
│           ├── stm32f0xx_hal_rcc_ex.c
│           ├── stm32f0xx_hal_rtc.c
│           ├── stm32f0xx_hal_rtc_ex.c
│           ├── stm32f0xx_hal_smartcard.c
│           ├── stm32f0xx_hal_smartcard_ex.c
│           ├── stm32f0xx_hal_smbus.c
│           ├── stm32f0xx_hal_spi.c
│           ├── stm32f0xx_hal_tim.c
│           ├── stm32f0xx_hal_tim_ex.c
│           ├── stm32f0xx_hal_tsc.c
│           ├── stm32f0xx_hal_uart.c
│           ├── stm32f0xx_hal_uart_ex.c
│           ├── stm32f0xx_hal_usart.c
│           └── stm32f0xx_hal_wwdg.c
├── Inc/
│   ├── can.h
│   ├── led.h
│   ├── slcan.h
│   ├── stm32f0xx_hal_conf.h
│   ├── stm32f0xx_it.h
│   ├── usb_device.h
│   ├── usbd_cdc_if.h
│   ├── usbd_conf.h
│   └── usbd_desc.h
├── LICENSE.md
├── Makefile
├── Middlewares/
│   └── ST/
│       └── STM32_USB_Device_Library/
│           ├── Class/
│           │   └── CDC/
│           │       ├── Inc/
│           │       │   ├── usbd_cdc.h
│           │       │   └── usbd_cdc_if_template.h
│           │       └── Src/
│           │           ├── usbd_cdc.c
│           │           └── usbd_cdc_if_template.c
│           └── Core/
│               ├── Inc/
│               │   ├── usbd_conf_template.h
│               │   ├── usbd_core.h
│               │   ├── usbd_ctlreq.h
│               │   ├── usbd_def.h
│               │   └── usbd_ioreq.h
│               └── Src/
│                   ├── usbd_conf_template.c
│                   ├── usbd_core.c
│                   ├── usbd_ctlreq.c
│                   └── usbd_ioreq.c
├── README.md
├── STM32F042C6_FLASH.ld
├── Src/
│   ├── can.c
│   ├── led.c
│   ├── main.c
│   ├── slcan.c
│   ├── startup_stm32f042x6.s
│   ├── stm32f0xx_hal_msp.c
│   ├── stm32f0xx_it.c
│   ├── system_stm32f0xx.c
│   ├── usb_device.c
│   ├── usbd_cdc_if.c
│   ├── usbd_conf.c
│   └── usbd_desc.c
├── cantact.ioc
├── stm32f0x.cfg
└── windows-driver/
    └── cantact.inf

================================================
FILE CONTENTS
================================================

================================================
FILE: .gitignore
================================================
build/*


================================================
FILE: .travis.yml
================================================
notifications:
  email: false

language: c

env:
  global:
    - "ARTIFACTS_AWS_REGION=us-east-1"
    - "ARTIFACTS_S3_BUCKET=cantact-builds"
    - secure: "gol8KyPaZuEpibS+JIrzfWuwaYNtHF0gLR0Lol6PM49KZPnHfAg9P2zMNhESL6ZTmWFwEmhxuntFvOQbGqB55cJbmOv3ZeuYkMw4y+GRwKB3pRAqQTQXOx8uBSCvBw+zmwmbswUA+dlKVQAgGvHxjQRwSfByedZsDaCz/ACd7qs="
    - secure: "dxFGsRnHyQWQgFBJztagS7OBWSef/p+tn9JhTgIOAZlI86dEe1bI/grkELsq4EV9IdgHFz6ks9+TT9Sb4IFu7+275sBJKAJOZw7Q2nILkUreF2WMwOJQd2ih0uQu3b68ccQxqQhp3s5FrOcUedwqnrM+Jk3+MhpKWO+cVgQ0SqQ="

before_script:
  - sudo apt-add-repository 'deb http://archive.ubuntu.com/ubuntu trusty main universe multiverse restricted'
  - sudo apt-get update -qq
  - sudo apt-get install -y gcc-arm-none-eabi
  - curl -sL https://raw.githubusercontent.com/travis-ci/artifacts/master/install | bash
  - export PATH=$PATH:~/bin/

script: make BUILD_NUMBER=$TRAVIS_BUILD_NUMBER

after_success:
  "artifacts upload --target-paths=builds/b$TRAVIS_BUILD_NUMBER build/CANtact*"

================================================
FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h
================================================
/**
  ******************************************************************************
  * @file    stm32f030x6.h
  * @author  MCD Application Team
  * @version V2.1.0
  * @date    03-Oct-2014
  * @brief   CMSIS STM32F030x4/STM32F030x6 devices Peripheral Access Layer Header File.
  *
  *          This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripherals registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/** @addtogroup CMSIS_Device
  * @{
  */

/** @addtogroup stm32f030x6
  * @{
  */

#ifndef __STM32F030x6_H
#define __STM32F030x6_H

#ifdef __cplusplus
 extern "C" {
#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS
  * @{
  */

/**
 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
 */
#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */

/**
  * @}
  */
   
/** @addtogroup Peripheral_interrupt_number_definition
  * @{
  */

/**
 * @brief STM32F030x4/STM32F030x6 device Interrupt Number Definition
 */
typedef enum
{
/******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */

/******  STM32F030x4/STM32F030x6 specific Interrupt Numbers **************************************/
  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                       */
  RTC_IRQn                    = 2,      /*!< RTC Interrupt through EXTI Lines 17, 19 and 20                  */
  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                          */
  RCC_IRQn                    = 4,      /*!< RCC Global Interrupts                                           */
  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                                    */
  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                    */
  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                    */
  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                        */
  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                         */
  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                         */
  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                                 */
  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts          */
  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                  */
  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                           */
  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                          */
  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                          */
  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                          */
  I2C1_IRQn                   = 23,     /*!< I2C1 Event Interrupt                                            */
  SPI1_IRQn                   = 25,     /*!< SPI1 global Interrupt                                           */
  USART1_IRQn                 = 27      /*!< USART1 global Interrupt                                         */
} IRQn_Type;

/**
  * @}
  */

#include "core_cm0.h"            /* Cortex-M0 processor and core peripherals */
#include "system_stm32f0xx.h"    /* STM32F0xx System Header */
#include <stdint.h>

/** @addtogroup Peripheral_registers_structures
  * @{
  */

/**
  * @brief Analog to Digital Converter
  */

typedef struct
{
  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
}ADC_TypeDef;

typedef struct
{
  __IO uint32_t CCR;
}ADC_Common_TypeDef;

/**
  * @brief CRC calculation unit
  */

typedef struct
{
  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
}CRC_TypeDef;

/**
  * @brief Debug MCU
  */

typedef struct
{
  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
}DBGMCU_TypeDef;

/**
  * @brief DMA Controller
  */

typedef struct
{
  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
}DMA_Channel_TypeDef;

typedef struct
{
  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
}DMA_TypeDef;

/** 
  * @brief External Interrupt/Event Controller
  */

typedef struct
{
  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
}EXTI_TypeDef;

/** 
  * @brief FLASH Registers
  */
typedef struct
{
  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
}FLASH_TypeDef;


/** 
  * @brief Option Bytes Registers
  */
typedef struct
{
  __IO uint16_t RDP;          /*!< FLASH option byte Read protection,             Address offset: 0x00 */
  __IO uint16_t USER;         /*!< FLASH option byte user options,                Address offset: 0x02 */
  __IO uint16_t DATA0;        /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
  __IO uint16_t DATA1;        /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
  __IO uint16_t WRP0;         /*!< FLASH option byte write protection 0,          Address offset: 0x08 */
  __IO uint16_t WRP1;         /*!< FLASH option byte write protection 1,          Address offset: 0x0A */
  __IO uint16_t WRP2;         /*!< FLASH option byte write protection 2,          Address offset: 0x0C */
  __IO uint16_t WRP3;         /*!< FLASH option byte write protection 3,          Address offset: 0x0E */
}OB_TypeDef;

/**
  * @brief General Purpose I/O
  */

typedef struct
{
  __IO uint32_t MODER;        /*!< GPIO port mode register,               Address offset: 0x00 */
  __IO uint32_t OTYPER;       /*!< GPIO port output type register,        Address offset: 0x04 */
  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,       Address offset: 0x08 */
  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C */
  __IO uint32_t IDR;          /*!< GPIO port input data register,         Address offset: 0x10 */
  __IO uint32_t ODR;          /*!< GPIO port output data register,        Address offset: 0x14 */
  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset register,      Address offset: 0x1A */
  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register, Address offset: 0x1C */
  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,  Address offset: 0x20-0x24 */
  __IO uint32_t BRR;          /*!< GPIO bit reset register,               Address offset: 0x28 */
}GPIO_TypeDef;

/**
  * @brief SysTem Configuration
  */

typedef struct
{
  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
}SYSCFG_TypeDef;

/** 
  * @brief Inter-integrated Circuit Interface
  */

typedef struct
{
  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
}I2C_TypeDef;

/**
  * @brief Independent WATCHDOG
  */

typedef struct
{
  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
}IWDG_TypeDef;

/**
  * @brief Power Control
  */

typedef struct
{
  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
}PWR_TypeDef;

/**
  * @brief Reset and Clock Control
  */
typedef struct
{
  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */
  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
}RCC_TypeDef;

/** 
  * @brief Real-Time Clock
  */

typedef struct
{
  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x14 */
       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x18 */
  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x20 */
  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
}RTC_TypeDef;

/**
  * @brief Serial Peripheral Interface
  */

typedef struct
{
  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
}SPI_TypeDef;

/**
  * @brief TIM
  */
typedef struct
{
  __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
  __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
  __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
  __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
  __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
  __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
  __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
  __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
  __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
  __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
  __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
  __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
  __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
  __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
  __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
}TIM_TypeDef;


/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */

typedef struct
{
  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
  uint16_t  RESERVED1;  /*!< Reserved, 0x26                                                 */
  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
  uint16_t  RESERVED2;  /*!< Reserved, 0x2A                                                 */
}USART_TypeDef;

/**
  * @brief Window WATCHDOG
  */
typedef struct
{
  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
}WWDG_TypeDef;

/**
  * @}
  */
  
/** @addtogroup Peripheral_memory_map
  * @{
  */

#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

/*!< Peripheral memory map */
#define APBPERIPH_BASE        PERIPH_BASE
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)

#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)

#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)

#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)

#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)

/**
  * @}
  */

/** @addtogroup Peripheral_declaration
  * @{
  */

#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
#define RTC                 ((RTC_TypeDef *) RTC_BASE)
#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
#define PWR                 ((PWR_TypeDef *) PWR_BASE)
#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
#define USART1              ((USART_TypeDef *) USART1_BASE)
#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB                  ((OB_TypeDef *) OB_BASE) 
#define RCC                 ((RCC_TypeDef *) RCC_BASE)
#define CRC                 ((CRC_TypeDef *) CRC_BASE)
#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

/**
  * @}
  */

/** @addtogroup Exported_constants
  * @{
  */

  /** @addtogroup Peripheral_Registers_Bits_Definition
  * @{
  */

/******************************************************************************/
/*                         Peripheral Registers Bits Definition               */
/******************************************************************************/
/******************************************************************************/
/*                                                                            */
/*                      Analog to Digital Converter (ADC)                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for ADC_ISR register  ******************/
#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */

/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS                          ADC_ISR_EOSEQ

/********************  Bits definition for ADC_IER register  ******************/
#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */

/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE

/********************  Bits definition for ADC_CR register  *******************/
#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */

/*******************  Bits definition for ADC_CFGR1 register  *****************/
#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */

/* Old WAIT bit definition, maintained for legacy purpose */
#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT

/*******************  Bits definition for ADC_CFGR2 register  *****************/
#define  ADC_CFGR2_CKMODE                     ((uint32_t)0xC0000000)       /*!< ADC clock mode */
#define  ADC_CFGR2_CKMODE_1                   ((uint32_t)0x80000000)       /*!< ADC clocked by PCLK div4 */
#define  ADC_CFGR2_CKMODE_0                   ((uint32_t)0x40000000)       /*!< ADC clocked by PCLK div2 */

/* Old bit definition, maintained for legacy purpose */
#define  ADC_CFGR2_JITOFFDIV4                 ADC_CFGR2_CKMODE_1           /*!< ADC clocked by PCLK div4 */
#define  ADC_CFGR2_JITOFFDIV2                 ADC_CFGR2_CKMODE_0           /*!< ADC clocked by PCLK div2 */

/******************  Bit definition for ADC_SMPR register  ********************/
#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */

/* Old bit definition, maintained for legacy purpose */
#define  ADC_SMPR1_SMPR                      ADC_SMPR_SMP        /*!< SMP[2:0] bits (Sampling time selection) */
#define  ADC_SMPR1_SMPR_0                    ADC_SMPR_SMP_0        /*!< Bit 0 */
#define  ADC_SMPR1_SMPR_1                    ADC_SMPR_SMP_1        /*!< Bit 1 */
#define  ADC_SMPR1_SMPR_2                    ADC_SMPR_SMP_2        /*!< Bit 2 */

/*******************  Bit definition for ADC_TR register  ********************/
#define  ADC_TR_HT                          ((uint32_t)0x0FFF0000)        /*!< Analog watchdog high threshold */
#define  ADC_TR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */

/* Old bit definition, maintained for legacy purpose */
#define  ADC_HTR_HT                          ADC_TR_HT                    /*!< Analog watchdog high threshold */
#define  ADC_LTR_LT                          ADC_TR_LT                    /*!< Analog watchdog low threshold */

/******************  Bit definition for ADC_CHSELR register  ******************/
#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */

/********************  Bit definition for ADC_DR register  ********************/
#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */

/*******************  Bit definition for ADC_CCR register  ********************/
#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */

/******************************************************************************/
/*                                                                            */
/*                       CRC calculation unit (CRC)                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_DR register  *********************/
#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */

/*******************  Bit definition for CRC_IDR register  ********************/
#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */

/********************  Bit definition for CRC_CR register  ********************/
#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */

/*******************  Bit definition for CRC_INIT register  *******************/
#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */

/******************************************************************************/
/*                                                                            */
/*                           Debug MCU (DBGMCU)                               */
/*                                                                            */
/******************************************************************************/

/****************  Bit definition for DBGMCU_IDCODE register  *****************/
#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */

#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */

/******************  Bit definition for DBGMCU_CR register  *******************/
#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */

/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */

/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */

/******************************************************************************/
/*                                                                            */
/*                           DMA Controller (DMA)                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for DMA_ISR register  ********************/
#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */

/*******************  Bit definition for DMA_IFCR register  *******************/
#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */

/*******************  Bit definition for DMA_CCR register  ********************/
#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */

#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */

#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */

#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */

#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */

/******************  Bit definition for DMA_CNDTR register  *******************/
#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */

/******************  Bit definition for DMA_CPAR register  ********************/
#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */

/******************  Bit definition for DMA_CMAR register  ********************/
#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */

/******************************************************************************/
/*                                                                            */
/*                 External Interrupt/Event Controller (EXTI)                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for EXTI_IMR register  *******************/
#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */

/******************  Bit definition for EXTI_EMR register  ********************/
#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */

/*******************  Bit definition for EXTI_RTSR register  ******************/
#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */

/*******************  Bit definition for EXTI_FTSR register *******************/
#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */

/******************* Bit definition for EXTI_SWIER register *******************/
#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */

/******************  Bit definition for EXTI_PR register  *********************/
#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */

/******************************************************************************/
/*                                                                            */
/*                      FLASH and Option Bytes Registers                      */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for FLASH_ACR register  ******************/
#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */

#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */

/******************  Bit definition for FLASH_KEYR register  ******************/
#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */

/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */

/******************  FLASH Keys  **********************************************/
#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
                                                                                to unlock the write access to the FPEC. */
                                                               
#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
                                                                                unlock the write access to the option byte block */

/******************  Bit definition for FLASH_SR register  *******************/
#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
#define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
#define  FLASH_SR_WRPERR                     FLASH_SR_WRPRTERR             /*!< Legacy of Write Protection Error */

/*******************  Bit definition for FLASH_CR register  *******************/
#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */

/*******************  Bit definition for FLASH_AR register  *******************/
#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */

/******************  Bit definition for FLASH_OBR register  *******************/
#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */

#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */

/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1

/* Old OBR_VDDA bit definition, maintained for legacy purpose */
#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR

/******************  Bit definition for FLASH_WRPR register  ******************/
#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protect */

/*----------------------------------------------------------------------------*/

/******************  Bit definition for OB_RDP register  **********************/
#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */

/******************  Bit definition for OB_USER register  *********************/
#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */

/******************  Bit definition for OB_WRP0 register  *********************/
#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */

/******************  Bit definition for OB_WRP1 register  *********************/
#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */

/******************************************************************************/
/*                                                                            */
/*                       General Purpose IOs (GPIO)                           */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for GPIO_MODER register  *****************/
#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)

/******************  Bit definition for GPIO_OTYPER register  *****************/
#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)

/****************  Bit definition for GPIO_OSPEEDR register  ******************/
#define GPIO_OSPEEDR_OSPEEDR0     ((uint32_t)0x00000003)
#define GPIO_OSPEEDR_OSPEEDR0_0   ((uint32_t)0x00000001)
#define GPIO_OSPEEDR_OSPEEDR0_1   ((uint32_t)0x00000002)
#define GPIO_OSPEEDR_OSPEEDR1     ((uint32_t)0x0000000C)
#define GPIO_OSPEEDR_OSPEEDR1_0   ((uint32_t)0x00000004)
#define GPIO_OSPEEDR_OSPEEDR1_1   ((uint32_t)0x00000008)
#define GPIO_OSPEEDR_OSPEEDR2     ((uint32_t)0x00000030)
#define GPIO_OSPEEDR_OSPEEDR2_0   ((uint32_t)0x00000010)
#define GPIO_OSPEEDR_OSPEEDR2_1   ((uint32_t)0x00000020)
#define GPIO_OSPEEDR_OSPEEDR3     ((uint32_t)0x000000C0)
#define GPIO_OSPEEDR_OSPEEDR3_0   ((uint32_t)0x00000040)
#define GPIO_OSPEEDR_OSPEEDR3_1   ((uint32_t)0x00000080)
#define GPIO_OSPEEDR_OSPEEDR4     ((uint32_t)0x00000300)
#define GPIO_OSPEEDR_OSPEEDR4_0   ((uint32_t)0x00000100)
#define GPIO_OSPEEDR_OSPEEDR4_1   ((uint32_t)0x00000200)
#define GPIO_OSPEEDR_OSPEEDR5     ((uint32_t)0x00000C00)
#define GPIO_OSPEEDR_OSPEEDR5_0   ((uint32_t)0x00000400)
#define GPIO_OSPEEDR_OSPEEDR5_1   ((uint32_t)0x00000800)
#define GPIO_OSPEEDR_OSPEEDR6     ((uint32_t)0x00003000)
#define GPIO_OSPEEDR_OSPEEDR6_0   ((uint32_t)0x00001000)
#define GPIO_OSPEEDR_OSPEEDR6_1   ((uint32_t)0x00002000)
#define GPIO_OSPEEDR_OSPEEDR7     ((uint32_t)0x0000C000)
#define GPIO_OSPEEDR_OSPEEDR7_0   ((uint32_t)0x00004000)
#define GPIO_OSPEEDR_OSPEEDR7_1   ((uint32_t)0x00008000)
#define GPIO_OSPEEDR_OSPEEDR8     ((uint32_t)0x00030000)
#define GPIO_OSPEEDR_OSPEEDR8_0   ((uint32_t)0x00010000)
#define GPIO_OSPEEDR_OSPEEDR8_1   ((uint32_t)0x00020000)
#define GPIO_OSPEEDR_OSPEEDR9     ((uint32_t)0x000C0000)
#define GPIO_OSPEEDR_OSPEEDR9_0   ((uint32_t)0x00040000)
#define GPIO_OSPEEDR_OSPEEDR9_1   ((uint32_t)0x00080000)
#define GPIO_OSPEEDR_OSPEEDR10    ((uint32_t)0x00300000)
#define GPIO_OSPEEDR_OSPEEDR10_0  ((uint32_t)0x00100000)
#define GPIO_OSPEEDR_OSPEEDR10_1  ((uint32_t)0x00200000)
#define GPIO_OSPEEDR_OSPEEDR11    ((uint32_t)0x00C00000)
#define GPIO_OSPEEDR_OSPEEDR11_0  ((uint32_t)0x00400000)
#define GPIO_OSPEEDR_OSPEEDR11_1  ((uint32_t)0x00800000)
#define GPIO_OSPEEDR_OSPEEDR12    ((uint32_t)0x03000000)
#define GPIO_OSPEEDR_OSPEEDR12_0  ((uint32_t)0x01000000)
#define GPIO_OSPEEDR_OSPEEDR12_1  ((uint32_t)0x02000000)
#define GPIO_OSPEEDR_OSPEEDR13    ((uint32_t)0x0C000000)
#define GPIO_OSPEEDR_OSPEEDR13_0  ((uint32_t)0x04000000)
#define GPIO_OSPEEDR_OSPEEDR13_1  ((uint32_t)0x08000000)
#define GPIO_OSPEEDR_OSPEEDR14    ((uint32_t)0x30000000)
#define GPIO_OSPEEDR_OSPEEDR14_0  ((uint32_t)0x10000000)
#define GPIO_OSPEEDR_OSPEEDR14_1  ((uint32_t)0x20000000)
#define GPIO_OSPEEDR_OSPEEDR15    ((uint32_t)0xC0000000)
#define GPIO_OSPEEDR_OSPEEDR15_0  ((uint32_t)0x40000000)
#define GPIO_OSPEEDR_OSPEEDR15_1  ((uint32_t)0x80000000)

/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
#define GPIO_OSPEEDER_OSPEEDR0     GPIO_OSPEEDR_OSPEEDR0
#define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEEDR0_0
#define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEEDR0_1
#define GPIO_OSPEEDER_OSPEEDR1     GPIO_OSPEEDR_OSPEEDR1
#define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEEDR1_0
#define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEEDR1_1
#define GPIO_OSPEEDER_OSPEEDR2     GPIO_OSPEEDR_OSPEEDR2
#define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEEDR2_0
#define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEEDR2_1
#define GPIO_OSPEEDER_OSPEEDR3     GPIO_OSPEEDR_OSPEEDR3
#define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEEDR3_0
#define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEEDR3_1
#define GPIO_OSPEEDER_OSPEEDR4     GPIO_OSPEEDR_OSPEEDR4
#define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEEDR4_0
#define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEEDR4_1
#define GPIO_OSPEEDER_OSPEEDR5     GPIO_OSPEEDR_OSPEEDR5
#define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEEDR5_0
#define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEEDR5_1
#define GPIO_OSPEEDER_OSPEEDR6     GPIO_OSPEEDR_OSPEEDR6
#define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEEDR6_0
#define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEEDR6_1
#define GPIO_OSPEEDER_OSPEEDR7     GPIO_OSPEEDR_OSPEEDR7
#define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEEDR7_0
#define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEEDR7_1
#define GPIO_OSPEEDER_OSPEEDR8     GPIO_OSPEEDR_OSPEEDR8
#define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEEDR8_0
#define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEEDR8_1
#define GPIO_OSPEEDER_OSPEEDR9     GPIO_OSPEEDR_OSPEEDR9
#define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEEDR9_0
#define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEEDR9_1
#define GPIO_OSPEEDER_OSPEEDR10    GPIO_OSPEEDR_OSPEEDR10
#define GPIO_OSPEEDER_OSPEEDR10_0  GPIO_OSPEEDR_OSPEEDR10_0
#define GPIO_OSPEEDER_OSPEEDR10_1  GPIO_OSPEEDR_OSPEEDR10_1
#define GPIO_OSPEEDER_OSPEEDR11    GPIO_OSPEEDR_OSPEEDR11
#define GPIO_OSPEEDER_OSPEEDR11_0  GPIO_OSPEEDR_OSPEEDR11_0
#define GPIO_OSPEEDER_OSPEEDR11_1  GPIO_OSPEEDR_OSPEEDR11_1
#define GPIO_OSPEEDER_OSPEEDR12    GPIO_OSPEEDR_OSPEEDR12
#define GPIO_OSPEEDER_OSPEEDR12_0  GPIO_OSPEEDR_OSPEEDR12_0
#define GPIO_OSPEEDER_OSPEEDR12_1  GPIO_OSPEEDR_OSPEEDR12_1
#define GPIO_OSPEEDER_OSPEEDR13    GPIO_OSPEEDR_OSPEEDR13
#define GPIO_OSPEEDER_OSPEEDR13_0  GPIO_OSPEEDR_OSPEEDR13_0
#define GPIO_OSPEEDER_OSPEEDR13_1  GPIO_OSPEEDR_OSPEEDR13_1
#define GPIO_OSPEEDER_OSPEEDR14    GPIO_OSPEEDR_OSPEEDR14
#define GPIO_OSPEEDER_OSPEEDR14_0  GPIO_OSPEEDR_OSPEEDR14_0
#define GPIO_OSPEEDER_OSPEEDR14_1  GPIO_OSPEEDR_OSPEEDR14_1
#define GPIO_OSPEEDER_OSPEEDR15    GPIO_OSPEEDR_OSPEEDR15
#define GPIO_OSPEEDER_OSPEEDR15_0  GPIO_OSPEEDR_OSPEEDR15_0
#define GPIO_OSPEEDER_OSPEEDR15_1  GPIO_OSPEEDR_OSPEEDR15_1

/*******************  Bit definition for GPIO_PUPDR register ******************/
#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)

/*******************  Bit definition for GPIO_IDR register  *******************/
#define GPIO_IDR_0                 ((uint32_t)0x00000001)
#define GPIO_IDR_1                 ((uint32_t)0x00000002)
#define GPIO_IDR_2                 ((uint32_t)0x00000004)
#define GPIO_IDR_3                 ((uint32_t)0x00000008)
#define GPIO_IDR_4                 ((uint32_t)0x00000010)
#define GPIO_IDR_5                 ((uint32_t)0x00000020)
#define GPIO_IDR_6                 ((uint32_t)0x00000040)
#define GPIO_IDR_7                 ((uint32_t)0x00000080)
#define GPIO_IDR_8                 ((uint32_t)0x00000100)
#define GPIO_IDR_9                 ((uint32_t)0x00000200)
#define GPIO_IDR_10                ((uint32_t)0x00000400)
#define GPIO_IDR_11                ((uint32_t)0x00000800)
#define GPIO_IDR_12                ((uint32_t)0x00001000)
#define GPIO_IDR_13                ((uint32_t)0x00002000)
#define GPIO_IDR_14                ((uint32_t)0x00004000)
#define GPIO_IDR_15                ((uint32_t)0x00008000)

/******************  Bit definition for GPIO_ODR register  ********************/
#define GPIO_ODR_0                 ((uint32_t)0x00000001)
#define GPIO_ODR_1                 ((uint32_t)0x00000002)
#define GPIO_ODR_2                 ((uint32_t)0x00000004)
#define GPIO_ODR_3                 ((uint32_t)0x00000008)
#define GPIO_ODR_4                 ((uint32_t)0x00000010)
#define GPIO_ODR_5                 ((uint32_t)0x00000020)
#define GPIO_ODR_6                 ((uint32_t)0x00000040)
#define GPIO_ODR_7                 ((uint32_t)0x00000080)
#define GPIO_ODR_8                 ((uint32_t)0x00000100)
#define GPIO_ODR_9                 ((uint32_t)0x00000200)
#define GPIO_ODR_10                ((uint32_t)0x00000400)
#define GPIO_ODR_11                ((uint32_t)0x00000800)
#define GPIO_ODR_12                ((uint32_t)0x00001000)
#define GPIO_ODR_13                ((uint32_t)0x00002000)
#define GPIO_ODR_14                ((uint32_t)0x00004000)
#define GPIO_ODR_15                ((uint32_t)0x00008000)

/****************** Bit definition for GPIO_BSRR register  ********************/
#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)

/****************** Bit definition for GPIO_LCKR register  ********************/
#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)

/****************** Bit definition for GPIO_AFRL register  ********************/
#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)

/****************** Bit definition for GPIO_AFRH register  ********************/
#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)

/****************** Bit definition for GPIO_BRR register  *********************/
#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)

/******************************************************************************/
/*                                                                            */
/*                   Inter-integrated Circuit Interface (I2C)                 */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for I2C_CR1 register  *******************/
#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */

/******************  Bit definition for I2C_CR2 register  ********************/
#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */

/*******************  Bit definition for I2C_OAR1 register  ******************/
#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */

/*******************  Bit definition for I2C_OAR2 register  ******************/
#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */

/*******************  Bit definition for I2C_TIMINGR register ****************/
#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */

/******************* Bit definition for I2C_TIMEOUTR register ****************/
#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */

/******************  Bit definition for I2C_ISR register  ********************/
#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */

/******************  Bit definition for I2C_ICR register  ********************/
#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */

/******************  Bit definition for I2C_PECR register  *******************/
#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */

/******************  Bit definition for I2C_RXDR register  *********************/
#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */

/******************  Bit definition for I2C_TXDR register  *******************/
#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */

/*****************************************************************************/
/*                                                                           */
/*                        Independent WATCHDOG (IWDG)                        */
/*                                                                           */
/*****************************************************************************/
/*******************  Bit definition for IWDG_KR register  *******************/
#define  IWDG_KR_KEY                         ((uint32_t)0xFFFF)            /*!< Key value (write only, read 0000h) */

/*******************  Bit definition for IWDG_PR register  *******************/
#define  IWDG_PR_PR                          ((uint32_t)0x07)              /*!< PR[2:0] (Prescaler divider) */
#define  IWDG_PR_PR_0                        ((uint32_t)0x01)              /*!< Bit 0 */
#define  IWDG_PR_PR_1                        ((uint32_t)0x02)              /*!< Bit 1 */
#define  IWDG_PR_PR_2                        ((uint32_t)0x04)              /*!< Bit 2 */

/*******************  Bit definition for IWDG_RLR register  ******************/
#define  IWDG_RLR_RL                         ((uint32_t)0x0FFF)            /*!< Watchdog counter reload value */

/*******************  Bit definition for IWDG_SR register  *******************/
#define  IWDG_SR_PVU                         ((uint32_t)0x01)              /*!< Watchdog prescaler value update */
#define  IWDG_SR_RVU                         ((uint32_t)0x02)              /*!< Watchdog counter reload value update */
#define  IWDG_SR_WVU                         ((uint32_t)0x04)              /*!< Watchdog counter window value update */

/*******************  Bit definition for IWDG_KR register  *******************/
#define  IWDG_WINR_WIN                       ((uint32_t)0x0FFF)            /*!< Watchdog counter window value */

/*****************************************************************************/
/*                                                                           */
/*                          Power Control (PWR)                              */
/*                                                                           */
/*****************************************************************************/

/********************  Bit definition for PWR_CR register  *******************/
#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)        /*!< Low-power Deepsleep */
#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)        /*!< Power Down Deepsleep */
#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)        /*!< Clear Wakeup Flag */
#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)        /*!< Clear Standby Flag */
#define  PWR_CR_DBP                          ((uint32_t)0x00000100)        /*!< Disable Backup Domain write protection */

/*******************  Bit definition for PWR_CSR register  *******************/
#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)        /*!< Wakeup Flag */
#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)        /*!< Standby Flag */
#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100)        /*!< Enable WKUP pin 1 */
#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000200)        /*!< Enable WKUP pin 2 */

/*****************************************************************************/
/*                                                                           */
/*                         Reset and Clock Control                           */
/*                                                                           */
/*****************************************************************************/

/********************  Bit definition for RCC_CR register  *******************/
#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */

#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */
#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */
#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */
#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)        /*!<Bit 3 */
#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)        /*!<Bit 4 */

#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */
#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */
#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */
#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */
#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)        /*!<Bit 4 */
#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)        /*!<Bit 5 */
#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)        /*!<Bit 6 */
#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)        /*!<Bit 7 */

#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */

/********************  Bit definition for RCC_CFGR register  *****************/
/*!< SW configuration */
#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */

#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */

/*!< SWS configuration */
#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */

#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */

/*!< HPRE configuration */
#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */

#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */

/*!< PPRE configuration */
#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */

#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */

/*!< ADCPPRE configuration */
#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADCPRE bit (ADC prescaler) */

#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK divided by 2 */
#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK divided by 4 */

#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
#define  RCC_CFGR_PLLSRC_HSI_DIV2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define  RCC_CFGR_PLLSRC_HSE_PREDIV          ((uint32_t)0x00010000)        /*!< HSE/PREDIV clock selected as PLL entry clock source */

#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
#define  RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1   ((uint32_t)0x00000000)        /*!< HSE/PREDIV clock not divided for PLL entry */
#define  RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2   ((uint32_t)0x00020000)        /*!< HSE/PREDIV clock divided by 2 for PLL entry */

/*!< PLLMUL configuration */
#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */

#define  RCC_CFGR_PLLMUL2                    ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
#define  RCC_CFGR_PLLMUL5                    ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
#define  RCC_CFGR_PLLMUL7                    ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
#define  RCC_CFGR_PLLMUL9                    ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
#define  RCC_CFGR_PLLMUL10                   ((uint32_t)0x00200000)        /*!< PLL input clock10 */
#define  RCC_CFGR_PLLMUL11                   ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
#define  RCC_CFGR_PLLMUL13                   ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
#define  RCC_CFGR_PLLMUL14                   ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
#define  RCC_CFGR_PLLMUL15                   ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00380000)        /*!< PLL input clock*16 */

/*!< MCO configuration */
#define  RCC_CFGR_MCO                        ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
#define  RCC_CFGR_MCO_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */

#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */

#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCO prescaler  */
#define  RCC_CFGR_MCOPRE_DIV1                ((uint32_t)0x00000000)        /*!< MCO is divided by 1  */
#define  RCC_CFGR_MCOPRE_DIV2                ((uint32_t)0x10000000)        /*!< MCO is divided by 2  */
#define  RCC_CFGR_MCOPRE_DIV4                ((uint32_t)0x20000000)        /*!< MCO is divided by 4  */
#define  RCC_CFGR_MCOPRE_DIV8                ((uint32_t)0x30000000)        /*!< MCO is divided by 8  */
#define  RCC_CFGR_MCOPRE_DIV16               ((uint32_t)0x40000000)        /*!< MCO is divided by 16  */
#define  RCC_CFGR_MCOPRE_DIV32               ((uint32_t)0x50000000)        /*!< MCO is divided by 32  */
#define  RCC_CFGR_MCOPRE_DIV64               ((uint32_t)0x60000000)        /*!< MCO is divided by 64  */
#define  RCC_CFGR_MCOPRE_DIV128              ((uint32_t)0x70000000)        /*!< MCO is divided by 128  */

#define  RCC_CFGR_PLLNODIV                   ((uint32_t)0x80000000)        /*!< PLL is not divided to MCO */

/*!<******************  Bit definition for RCC_CIR register  *****************/
#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */

/*****************  Bit definition for RCC_APB2RSTR register  ****************/
#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000200)        /*!< ADC clock reset */
#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */

/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
#define  RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST          

/*****************  Bit definition for RCC_APB1RSTR register  ****************/
#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */

/******************  Bit definition for RCC_AHBENR register  *****************/
#define  RCC_AHBENR_DMAEN                    ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */

/* Old Bit definition maintained for legacy purpose */
#define  RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN        /*!< DMA1 clock enable */
#define  RCC_AHBENR_TSEN                     RCC_AHBENR_TSCEN        /*!< TS clock enable */

/*****************  Bit definition for RCC_APB2ENR register  *****************/
#define  RCC_APB2ENR_SYSCFGCOMPEN            ((uint32_t)0x00000001)        /*!< SYSCFG and comparator clock enable */
#define  RCC_APB2ENR_ADCEN                   ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */

/* Old Bit definition maintained for legacy purpose */
#define  RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGCOMPEN        /*!< SYSCFG clock enable */
#define  RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN               /*!< ADC1 clock enable */

/*****************  Bit definition for RCC_APB1ENR register  *****************/
#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */

/*******************  Bit definition for RCC_BDCR register  ******************/
#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */

#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */

#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */

/*!< RTC configuration */
#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */

#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */

/*******************  Bit definition for RCC_CSR register  *******************/
#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
#define  RCC_CSR_OBLRSTF                     ((uint32_t)0x02000000)        /*!< OBL reset flag */
#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */

/* Old Bit definition maintained for legacy purpose */
#define  RCC_CSR_OBL                         RCC_CSR_OBLRSTF        /*!< OBL reset flag */

/*******************  Bit definition for RCC_AHBRSTR register  ***************/
#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00100000)         /*!< GPIOD clock reset */
#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00400000)         /*!< GPIOF clock reset */

/*******************  Bit definition for RCC_CFGR2 register  *****************/
/*!< PREDIV configuration */
#define  RCC_CFGR2_PREDIV                    ((uint32_t)0x0000000F)        /*!< PREDIV[3:0] bits */
#define  RCC_CFGR2_PREDIV_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
#define  RCC_CFGR2_PREDIV_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
#define  RCC_CFGR2_PREDIV_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
#define  RCC_CFGR2_PREDIV_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */

#define  RCC_CFGR2_PREDIV_DIV1               ((uint32_t)0x00000000)        /*!< PREDIV input clock not divided */
#define  RCC_CFGR2_PREDIV_DIV2               ((uint32_t)0x00000001)        /*!< PREDIV input clock divided by 2 */
#define  RCC_CFGR2_PREDIV_DIV3               ((uint32_t)0x00000002)        /*!< PREDIV input clock divided by 3 */
#define  RCC_CFGR2_PREDIV_DIV4               ((uint32_t)0x00000003)        /*!< PREDIV input clock divided by 4 */
#define  RCC_CFGR2_PREDIV_DIV5               ((uint32_t)0x00000004)        /*!< PREDIV input clock divided by 5 */
#define  RCC_CFGR2_PREDIV_DIV6               ((uint32_t)0x00000005)        /*!< PREDIV input clock divided by 6 */
#define  RCC_CFGR2_PREDIV_DIV7               ((uint32_t)0x00000006)        /*!< PREDIV input clock divided by 7 */
#define  RCC_CFGR2_PREDIV_DIV8               ((uint32_t)0x00000007)        /*!< PREDIV input clock divided by 8 */
#define  RCC_CFGR2_PREDIV_DIV9               ((uint32_t)0x00000008)        /*!< PREDIV input clock divided by 9 */
#define  RCC_CFGR2_PREDIV_DIV10              ((uint32_t)0x00000009)        /*!< PREDIV input clock divided by 10 */
#define  RCC_CFGR2_PREDIV_DIV11              ((uint32_t)0x0000000A)        /*!< PREDIV input clock divided by 11 */
#define  RCC_CFGR2_PREDIV_DIV12              ((uint32_t)0x0000000B)        /*!< PREDIV input clock divided by 12 */
#define  RCC_CFGR2_PREDIV_DIV13              ((uint32_t)0x0000000C)        /*!< PREDIV input clock divided by 13 */
#define  RCC_CFGR2_PREDIV_DIV14              ((uint32_t)0x0000000D)        /*!< PREDIV input clock divided by 14 */
#define  RCC_CFGR2_PREDIV_DIV15              ((uint32_t)0x0000000E)        /*!< PREDIV input clock divided by 15 */
#define  RCC_CFGR2_PREDIV_DIV16              ((uint32_t)0x0000000F)        /*!< PREDIV input clock divided by 16 */

/*******************  Bit definition for RCC_CFGR3 register  *****************/
/*!< USART1 Clock source selection */
#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */

#define  RCC_CFGR3_USART1SW_PCLK             ((uint32_t)0x00000000)        /*!< PCLK clock used as USART1 clock source */
#define  RCC_CFGR3_USART1SW_SYSCLK           ((uint32_t)0x00000001)        /*!< System clock selected as USART1 clock source */
#define  RCC_CFGR3_USART1SW_LSE              ((uint32_t)0x00000002)        /*!< LSE oscillator clock used as USART1 clock source */
#define  RCC_CFGR3_USART1SW_HSI              ((uint32_t)0x00000003)        /*!< HSI oscillator clock used as USART1 clock source */

/*!< I2C1 Clock source selection */
#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 

#define  RCC_CFGR3_I2C1SW_HSI                ((uint32_t)0x00000000)        /*!< HSI oscillator clock used as I2C1 clock source */
#define  RCC_CFGR3_I2C1SW_SYSCLK             ((uint32_t)0x00000010)        /*!< System clock selected as I2C1 clock source */

/*******************  Bit definition for RCC_CR2 register  *******************/
#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */

/*****************************************************************************/
/*                                                                           */
/*                           Real-Time Clock (RTC)                           */
/*                                                                           */
/*****************************************************************************/
/********************  Bits definition for RTC_TR register  ******************/
#define RTC_TR_PM                            ((uint32_t)0x00400000)
#define RTC_TR_HT                            ((uint32_t)0x00300000)
#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
#define RTC_TR_HU                            ((uint32_t)0x000F0000)
#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
#define RTC_TR_MNT                           ((uint32_t)0x00007000)
#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
#define RTC_TR_ST                            ((uint32_t)0x00000070)
#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
#define RTC_TR_SU                            ((uint32_t)0x0000000F)
#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
#define RTC_TR_SU_3                          ((uint32_t)0x00000008)

/********************  Bits definition for RTC_DR register  ******************/
#define RTC_DR_YT                            ((uint32_t)0x00F00000)
#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
#define RTC_DR_YU                            ((uint32_t)0x000F0000)
#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
#define RTC_DR_MT                            ((uint32_t)0x00001000)
#define RTC_DR_MU                            ((uint32_t)0x00000F00)
#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
#define RTC_DR_DT                            ((uint32_t)0x00000030)
#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
#define RTC_DR_DU                            ((uint32_t)0x0000000F)
#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
#define RTC_DR_DU_3                          ((uint32_t)0x00000008)

/********************  Bits definition for RTC_CR register  ******************/
#define RTC_CR_COE                           ((uint32_t)0x00800000)
#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
#define RTC_CR_POL                           ((uint32_t)0x00100000)
#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
#define RTC_CR_BCK                           ((uint32_t)0x00040000)
#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
#define RTC_CR_TSE                           ((uint32_t)0x00000800)
#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
#define RTC_CR_FMT                           ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)

/********************  Bits definition for RTC_ISR register  *****************/
#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)

/********************  Bits definition for RTC_PRER register  ****************/
#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)

/********************  Bits definition for RTC_ALRMAR register  **************/
#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)

/********************  Bits definition for RTC_WPR register  *****************/
#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)

/********************  Bits definition for RTC_SSR register  *****************/
#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)

/********************  Bits definition for RTC_SHIFTR register  **************/
#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)

/********************  Bits definition for RTC_TSTR register  ****************/
#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)

/********************  Bits definition for RTC_TSDR register  ****************/
#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)

/********************  Bits definition for RTC_TSSSR register  ***************/
#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)

/********************  Bits definition for RTC_CALR register  ****************/
#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)

/********************  Bits definition for RTC_TAFCR register  ***************/
#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)

/********************  Bits definition for RTC_ALRMASSR register  ************/
#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)

/*****************************************************************************/
/*                                                                           */
/*                        Serial Peripheral Interface (SPI)                  */
/*                                                                           */
/*****************************************************************************/
/*******************  Bit definition for SPI_CR1 register  *******************/
#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
#define  SPI_CR1_CRCL                        ((uint32_t)0x00000800)            /*!< CRC Length */
#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */

/*******************  Bit definition for SPI_CR2 register  *******************/
#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)            /*!< Rx Buffer DMA Enable */
#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)            /*!< Tx Buffer DMA Enable */
#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)            /*!< SS Output Enable */
#define  SPI_CR2_NSSP                        ((uint32_t)0x00000008)            /*!< NSS pulse management Enable */
#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)            /*!< Frame Format Enable */
#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)            /*!< Error Interrupt Enable */
#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)            /*!< RX buffer Not Empty Interrupt Enable */
#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)            /*!< Tx buffer Empty Interrupt Enable */
#define  SPI_CR2_DS                          ((uint32_t)0x00000F00)            /*!< DS[3:0] Data Size */
#define  SPI_CR2_DS_0                        ((uint32_t)0x00000100)            /*!< Bit 0 */
#define  SPI_CR2_DS_1                        ((uint32_t)0x00000200)            /*!< Bit 1 */
#define  SPI_CR2_DS_2                        ((uint32_t)0x00000400)            /*!< Bit 2 */
#define  SPI_CR2_DS_3                        ((uint32_t)0x00000800)            /*!< Bit 3 */
#define  SPI_CR2_FRXTH                       ((uint32_t)0x00001000)            /*!< FIFO reception Threshold */
#define  SPI_CR2_LDMARX                      ((uint32_t)0x00002000)            /*!< Last DMA transfer for reception */
#define  SPI_CR2_LDMATX                      ((uint32_t)0x00004000)            /*!< Last DMA transfer for transmission */

/********************  Bit definition for SPI_SR register  *******************/
#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)            /*!< Receive buffer Not Empty */
#define  SPI_SR_TXE                          ((uint32_t)0x00000002)            /*!< Transmit buffer Empty */
#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)            /*!< Channel side */
#define  SPI_SR_UDR                          ((uint32_t)0x00000008)            /*!< Underrun flag */
#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)            /*!< CRC Error flag */
#define  SPI_SR_MODF                         ((uint32_t)0x00000020)            /*!< Mode fault */
#define  SPI_SR_OVR                          ((uint32_t)0x00000040)            /*!< Overrun flag */
#define  SPI_SR_BSY                          ((uint32_t)0x00000080)            /*!< Busy flag */
#define  SPI_SR_FRE                          ((uint32_t)0x00000100)            /*!< TI frame format error */
#define  SPI_SR_FRLVL                        ((uint32_t)0x00000600)            /*!< FIFO Reception Level */
#define  SPI_SR_FRLVL_0                      ((uint32_t)0x00000200)            /*!< Bit 0 */
#define  SPI_SR_FRLVL_1                      ((uint32_t)0x00000400)            /*!< Bit 1 */
#define  SPI_SR_FTLVL                        ((uint32_t)0x00001800)            /*!< FIFO Transmission Level */
#define  SPI_SR_FTLVL_0                      ((uint32_t)0x00000800)            /*!< Bit 0 */
#define  SPI_SR_FTLVL_1                      ((uint32_t)0x00001000)            /*!< Bit 1 */  

/********************  Bit definition for SPI_DR register  *******************/
#define  SPI_DR_DR                           ((uint32_t)0xFFFFFFFF)            /*!< Data Register */

/*******************  Bit definition for SPI_CRCPR register  *****************/
#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0xFFFFFFFF)            /*!< CRC polynomial register */

/******************  Bit definition for SPI_RXCRCR register  *****************/
#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0xFFFFFFFF)            /*!< Rx CRC Register */

/******************  Bit definition for SPI_TXCRCR register  *****************/
#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0xFFFFFFFF)            /*!< Tx CRC Register */

/******************  Bit definition for SPI_I2SCFGR register  ****************/
#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */

/******************  Bit definition for SPI_I2SPR register  ******************/
#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */

/*****************************************************************************/
/*                                                                           */
/*                       System Configuration (SYSCFG)                       */
/*                                                                           */
/*****************************************************************************/
/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */

#define SYSCFG_CFGR1_DMA_RMP                ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */

#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
#define SYSCFG_CFGR1_I2C_FMP_PA9            ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9  */
#define SYSCFG_CFGR1_I2C_FMP_PA10           ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */

/*****************  Bit definition for SYSCFG_EXTICR1 register  **************/
#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */

/** 
  * @brief  EXTI0 configuration
  */
#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */

/** 
  * @brief  EXTI1 configuration  
  */ 
#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */

/** 
  * @brief  EXTI2 configuration  
  */
#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */

/** 
  * @brief  EXTI3 configuration  
  */
#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!< PF[3] pin */

/*****************  Bit definition for SYSCFG_EXTICR2 register  **************/
#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */

/** 
  * @brief  EXTI4 configuration  
  */
#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */

/** 
  * @brief  EXTI5 configuration  
  */
#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!< PF[5] pin */

/** 
  * @brief  EXTI6 configuration  
  */
#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */

/** 
  * @brief  EXTI7 configuration  
  */
#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!< PF[7] pin */

/*****************  Bit definition for SYSCFG_EXTICR3 register  **************/
#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */

/** 
  * @brief  EXTI8 configuration  
  */
#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!< PF[8] pin */

/** 
  * @brief  EXTI9 configuration  
  */
#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */

/** 
  * @brief  EXTI10 configuration  
  */
#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */

/** 
  * @brief  EXTI11 configuration  
  */
#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!< PF[11] pin */

/*****************  Bit definition for SYSCFG_EXTICR4 register  **************/
#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */

/** 
  * @brief  EXTI12 configuration  
  */
#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!< PF[12] pin */

/** 
  * @brief  EXTI13 configuration  
  */
#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!< PF[13] pin */

/** 
  * @brief  EXTI14 configuration  
  */
#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!< PF[14] pin */

/** 
  * @brief  EXTI15 configuration  
  */
#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!< PF[15] pin */

/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
#define SYSCFG_CFGR2_SRAM_PEF                  ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
#define SYSCFG_CFGR2_SRAM_PE                   SYSCFG_CFGR2_SRAM_PEF  /*!< SRAM Parity error flag (define maintained for legacy purpose) */

/*****************************************************************************/
/*                                                                           */
/*                               Timers (TIM)                                */
/*                                                                           */
/*****************************************************************************/
/*******************  Bit definition for TIM_CR1 register  *******************/
#define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
#define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
#define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
#define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
#define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */

#define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
#define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */

#define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */

#define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
#define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */

/*******************  Bit definition for TIM_CR2 register  *******************/
#define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
#define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */

#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */

#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
#define  TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
#define  TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
#define  TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
#define  TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
#define  TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
#define  TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
#define  TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */

/*******************  Bit definition for TIM_SMCR register  ******************/
#define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */

#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */

#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */

#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */

#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */

#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */

#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */

/*******************  Bit definition for TIM_DIER register  ******************/
#define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
#define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
#define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
#define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
#define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
#define  TIM_DIER_COMIE                      ((uint32_t)0x00000020)            /*!<COM interrupt enable */
#define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
#define  TIM_DIER_BIE                        ((uint32_t)0x00000080)            /*!<Break interrupt enable */
#define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
#define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
#define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
#define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
#define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
#define  TIM_DIER_COMDE                      ((uint32_t)0x00002000)            /*!<COM DMA request enable */
#define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */

/********************  Bit definition for TIM_SR register  *******************/
#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
#define  TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
#define  TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */

/*******************  Bit definition for TIM_EGR register  *******************/
#define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
#define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
#define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
#define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
#define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
#define  TIM_EGR_COMG                        ((uint32_t)0x00000020)               /*!<Capture/Compare Control Update Generation */
#define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
#define  TIM_EGR_BG                          ((uint32_t)0x00000080)               /*!<Break Generation */

/******************  Bit definition for TIM_CCMR1 register  ******************/
#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */

#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */

#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */

#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */

#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */

#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */

#define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */

#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */

/*---------------------------------------------------------------------------*/

#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */

#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */

#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */

#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */

/******************  Bit definition for TIM_CCMR2 register  ******************/
#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */

#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */

#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */

#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */

#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */

#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */

#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */

#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */

/*---------------------------------------------------------------------------*/

#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */

#define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */

#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */

#define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */

/*******************  Bit definition for TIM_CCER register  ******************/
#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
#define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
#define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
#define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */

/*******************  Bit definition for TIM_CNT register  *******************/
#define  TIM_CNT_CNT                         ((uint32_t)0xFFFFFFFF)            /*!<Counter Value */

/*******************  Bit definition for TIM_PSC register  *******************/
#define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */

/*******************  Bit definition for TIM_ARR register  *******************/
#define  TIM_ARR_ARR                         ((uint32_t)0xFFFFFFFF)            /*!<actual auto-reload Value */

/*******************  Bit definition for TIM_RCR register  *******************/
#define  TIM_RCR_REP                         ((uint32_t)0x000000FF)               /*!<Repetition Counter Value */

/*******************  Bit definition for TIM_CCR1 register  ******************/
#define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */

/*******************  Bit definition for TIM_CCR2 register  ******************/
#define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */

/*******************  Bit definition for TIM_CCR3 register  ******************/
#define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */

/*******************  Bit definition for TIM_CCR4 register  ******************/
#define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */

/*******************  Bit definition for TIM_BDTR register  ******************/
#define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
#define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
#define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
#define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
#define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
#define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
#define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
#define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */

#define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
#define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
#define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */

#define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
#define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
#define  TIM_BDTR_BKE               
Download .txt
gitextract_b4tw7xpg/

├── .gitignore
├── .travis.yml
├── Drivers/
│   ├── CMSIS/
│   │   ├── Device/
│   │   │   └── ST/
│   │   │       └── STM32F0xx/
│   │   │           ├── Include/
│   │   │           │   ├── stm32f030x6.h
│   │   │           │   ├── stm32f030x8.h
│   │   │           │   ├── stm32f031x6.h
│   │   │           │   ├── stm32f038xx.h
│   │   │           │   ├── stm32f042x6.h
│   │   │           │   ├── stm32f048xx.h
│   │   │           │   ├── stm32f051x8.h
│   │   │           │   ├── stm32f058xx.h
│   │   │           │   ├── stm32f071xb.h
│   │   │           │   ├── stm32f072xb.h
│   │   │           │   ├── stm32f078xx.h
│   │   │           │   ├── stm32f091xc.h
│   │   │           │   ├── stm32f098xx.h
│   │   │           │   ├── stm32f0xx.h
│   │   │           │   └── system_stm32f0xx.h
│   │   │           └── Source/
│   │   │               └── Templates/
│   │   │                   ├── arm/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   ├── gcc/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   ├── iar/
│   │   │                   │   ├── startup_stm32f030x6.s
│   │   │                   │   ├── startup_stm32f030x8.s
│   │   │                   │   ├── startup_stm32f031x6.s
│   │   │                   │   ├── startup_stm32f038xx.s
│   │   │                   │   ├── startup_stm32f042x6.s
│   │   │                   │   ├── startup_stm32f048xx.s
│   │   │                   │   ├── startup_stm32f051x8.s
│   │   │                   │   ├── startup_stm32f058xx.s
│   │   │                   │   ├── startup_stm32f071xb.s
│   │   │                   │   ├── startup_stm32f072xb.s
│   │   │                   │   ├── startup_stm32f078xx.s
│   │   │                   │   ├── startup_stm32f091xc.s
│   │   │                   │   └── startup_stm32f098xx.s
│   │   │                   └── system_stm32f0xx.c
│   │   ├── Include/
│   │   │   ├── arm_common_tables.h
│   │   │   ├── arm_const_structs.h
│   │   │   ├── arm_math.h
│   │   │   ├── core_cm0.h
│   │   │   ├── core_cm0plus.h
│   │   │   ├── core_cm3.h
│   │   │   ├── core_cm4.h
│   │   │   ├── core_cm4_simd.h
│   │   │   ├── core_cmFunc.h
│   │   │   ├── core_cmInstr.h
│   │   │   ├── core_sc000.h
│   │   │   └── core_sc300.h
│   │   └── RTOS/
│   │       └── cmsis_os.h
│   └── STM32F0xx_HAL_Driver/
│       ├── Inc/
│       │   ├── stm32f0xx_hal.h
│       │   ├── stm32f0xx_hal_adc.h
│       │   ├── stm32f0xx_hal_adc_ex.h
│       │   ├── stm32f0xx_hal_can.h
│       │   ├── stm32f0xx_hal_cec.h
│       │   ├── stm32f0xx_hal_comp.h
│       │   ├── stm32f0xx_hal_conf_template.h
│       │   ├── stm32f0xx_hal_cortex.h
│       │   ├── stm32f0xx_hal_crc.h
│       │   ├── stm32f0xx_hal_crc_ex.h
│       │   ├── stm32f0xx_hal_dac.h
│       │   ├── stm32f0xx_hal_dac_ex.h
│       │   ├── stm32f0xx_hal_def.h
│       │   ├── stm32f0xx_hal_dma.h
│       │   ├── stm32f0xx_hal_dma_ex.h
│       │   ├── stm32f0xx_hal_flash.h
│       │   ├── stm32f0xx_hal_flash_ex.h
│       │   ├── stm32f0xx_hal_gpio.h
│       │   ├── stm32f0xx_hal_gpio_ex.h
│       │   ├── stm32f0xx_hal_i2c.h
│       │   ├── stm32f0xx_hal_i2c_ex.h
│       │   ├── stm32f0xx_hal_i2s.h
│       │   ├── stm32f0xx_hal_irda.h
│       │   ├── stm32f0xx_hal_irda_ex.h
│       │   ├── stm32f0xx_hal_iwdg.h
│       │   ├── stm32f0xx_hal_pcd.h
│       │   ├── stm32f0xx_hal_pcd_ex.h
│       │   ├── stm32f0xx_hal_ppp.h
│       │   ├── stm32f0xx_hal_pwr.h
│       │   ├── stm32f0xx_hal_pwr_ex.h
│       │   ├── stm32f0xx_hal_rcc.h
│       │   ├── stm32f0xx_hal_rcc_ex.h
│       │   ├── stm32f0xx_hal_rtc.h
│       │   ├── stm32f0xx_hal_rtc_ex.h
│       │   ├── stm32f0xx_hal_smartcard.h
│       │   ├── stm32f0xx_hal_smartcard_ex.h
│       │   ├── stm32f0xx_hal_smbus.h
│       │   ├── stm32f0xx_hal_spi.h
│       │   ├── stm32f0xx_hal_tim.h
│       │   ├── stm32f0xx_hal_tim_ex.h
│       │   ├── stm32f0xx_hal_tsc.h
│       │   ├── stm32f0xx_hal_uart.h
│       │   ├── stm32f0xx_hal_uart_ex.h
│       │   ├── stm32f0xx_hal_usart.h
│       │   ├── stm32f0xx_hal_usart_ex.h
│       │   └── stm32f0xx_hal_wwdg.h
│       └── Src/
│           ├── stm32f0xx_hal.c
│           ├── stm32f0xx_hal_adc.c
│           ├── stm32f0xx_hal_adc_ex.c
│           ├── stm32f0xx_hal_can.c
│           ├── stm32f0xx_hal_cec.c
│           ├── stm32f0xx_hal_comp.c
│           ├── stm32f0xx_hal_cortex.c
│           ├── stm32f0xx_hal_crc.c
│           ├── stm32f0xx_hal_crc_ex.c
│           ├── stm32f0xx_hal_dac.c
│           ├── stm32f0xx_hal_dac_ex.c
│           ├── stm32f0xx_hal_dma.c
│           ├── stm32f0xx_hal_flash.c
│           ├── stm32f0xx_hal_flash_ex.c
│           ├── stm32f0xx_hal_gpio.c
│           ├── stm32f0xx_hal_i2c.c
│           ├── stm32f0xx_hal_i2c_ex.c
│           ├── stm32f0xx_hal_i2s.c
│           ├── stm32f0xx_hal_irda.c
│           ├── stm32f0xx_hal_iwdg.c
│           ├── stm32f0xx_hal_msp_template.c
│           ├── stm32f0xx_hal_pcd.c
│           ├── stm32f0xx_hal_pcd_ex.c
│           ├── stm32f0xx_hal_ppp.c
│           ├── stm32f0xx_hal_pwr.c
│           ├── stm32f0xx_hal_pwr_ex.c
│           ├── stm32f0xx_hal_rcc.c
│           ├── stm32f0xx_hal_rcc_ex.c
│           ├── stm32f0xx_hal_rtc.c
│           ├── stm32f0xx_hal_rtc_ex.c
│           ├── stm32f0xx_hal_smartcard.c
│           ├── stm32f0xx_hal_smartcard_ex.c
│           ├── stm32f0xx_hal_smbus.c
│           ├── stm32f0xx_hal_spi.c
│           ├── stm32f0xx_hal_tim.c
│           ├── stm32f0xx_hal_tim_ex.c
│           ├── stm32f0xx_hal_tsc.c
│           ├── stm32f0xx_hal_uart.c
│           ├── stm32f0xx_hal_uart_ex.c
│           ├── stm32f0xx_hal_usart.c
│           └── stm32f0xx_hal_wwdg.c
├── Inc/
│   ├── can.h
│   ├── led.h
│   ├── slcan.h
│   ├── stm32f0xx_hal_conf.h
│   ├── stm32f0xx_it.h
│   ├── usb_device.h
│   ├── usbd_cdc_if.h
│   ├── usbd_conf.h
│   └── usbd_desc.h
├── LICENSE.md
├── Makefile
├── Middlewares/
│   └── ST/
│       └── STM32_USB_Device_Library/
│           ├── Class/
│           │   └── CDC/
│           │       ├── Inc/
│           │       │   ├── usbd_cdc.h
│           │       │   └── usbd_cdc_if_template.h
│           │       └── Src/
│           │           ├── usbd_cdc.c
│           │           └── usbd_cdc_if_template.c
│           └── Core/
│               ├── Inc/
│               │   ├── usbd_conf_template.h
│               │   ├── usbd_core.h
│               │   ├── usbd_ctlreq.h
│               │   ├── usbd_def.h
│               │   └── usbd_ioreq.h
│               └── Src/
│                   ├── usbd_conf_template.c
│                   ├── usbd_core.c
│                   ├── usbd_ctlreq.c
│                   └── usbd_ioreq.c
├── README.md
├── STM32F042C6_FLASH.ld
├── Src/
│   ├── can.c
│   ├── led.c
│   ├── main.c
│   ├── slcan.c
│   ├── startup_stm32f042x6.s
│   ├── stm32f0xx_hal_msp.c
│   ├── stm32f0xx_it.c
│   ├── system_stm32f0xx.c
│   ├── usb_device.c
│   ├── usbd_cdc_if.c
│   ├── usbd_conf.c
│   └── usbd_desc.c
├── cantact.ioc
├── stm32f0x.cfg
└── windows-driver/
    └── cantact.inf
Download .txt
SYMBOL INDEX (1864 symbols across 117 files)

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 130) | typedef struct
  type ADC_Common_TypeDef (line 147) | typedef struct
  type CRC_TypeDef (line 156) | typedef struct
  type DBGMCU_TypeDef (line 172) | typedef struct
  type DMA_Channel_TypeDef (line 184) | typedef struct
  type DMA_TypeDef (line 192) | typedef struct
  type EXTI_TypeDef (line 202) | typedef struct
  type FLASH_TypeDef (line 215) | typedef struct
  type OB_TypeDef (line 232) | typedef struct
  type GPIO_TypeDef (line 248) | typedef struct
  type SYSCFG_TypeDef (line 266) | typedef struct
  type I2C_TypeDef (line 278) | typedef struct
  type IWDG_TypeDef (line 297) | typedef struct
  type PWR_TypeDef (line 310) | typedef struct
  type RCC_TypeDef (line 319) | typedef struct
  type RTC_TypeDef (line 341) | typedef struct
  type SPI_TypeDef (line 367) | typedef struct
  type TIM_TypeDef (line 392) | typedef struct
  type USART_TypeDef (line 422) | typedef struct
  type WWDG_TypeDef (line 442) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 135) | typedef struct
  type ADC_Common_TypeDef (line 152) | typedef struct
  type CRC_TypeDef (line 161) | typedef struct
  type DBGMCU_TypeDef (line 177) | typedef struct
  type DMA_Channel_TypeDef (line 189) | typedef struct
  type DMA_TypeDef (line 197) | typedef struct
  type EXTI_TypeDef (line 207) | typedef struct
  type FLASH_TypeDef (line 220) | typedef struct
  type OB_TypeDef (line 237) | typedef struct
  type GPIO_TypeDef (line 253) | typedef struct
  type SYSCFG_TypeDef (line 271) | typedef struct
  type I2C_TypeDef (line 283) | typedef struct
  type IWDG_TypeDef (line 302) | typedef struct
  type PWR_TypeDef (line 315) | typedef struct
  type RCC_TypeDef (line 324) | typedef struct
  type RTC_TypeDef (line 346) | typedef struct
  type SPI_TypeDef (line 372) | typedef struct
  type TIM_TypeDef (line 397) | typedef struct
  type USART_TypeDef (line 427) | typedef struct
  type WWDG_TypeDef (line 447) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 132) | typedef struct
  type ADC_Common_TypeDef (line 149) | typedef struct
  type CRC_TypeDef (line 158) | typedef struct
  type DBGMCU_TypeDef (line 174) | typedef struct
  type DMA_Channel_TypeDef (line 186) | typedef struct
  type DMA_TypeDef (line 194) | typedef struct
  type EXTI_TypeDef (line 204) | typedef struct
  type FLASH_TypeDef (line 217) | typedef struct
  type OB_TypeDef (line 234) | typedef struct
  type GPIO_TypeDef (line 250) | typedef struct
  type SYSCFG_TypeDef (line 268) | typedef struct
  type I2C_TypeDef (line 280) | typedef struct
  type IWDG_TypeDef (line 299) | typedef struct
  type PWR_TypeDef (line 312) | typedef struct
  type RCC_TypeDef (line 321) | typedef struct
  type RTC_TypeDef (line 343) | typedef struct
  type SPI_TypeDef (line 376) | typedef struct
  type TIM_TypeDef (line 401) | typedef struct
  type USART_TypeDef (line 431) | typedef struct
  type WWDG_TypeDef (line 451) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f038xx.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 131) | typedef struct
  type ADC_Common_TypeDef (line 148) | typedef struct
  type CRC_TypeDef (line 157) | typedef struct
  type DBGMCU_TypeDef (line 173) | typedef struct
  type DMA_Channel_TypeDef (line 185) | typedef struct
  type DMA_TypeDef (line 193) | typedef struct
  type EXTI_TypeDef (line 203) | typedef struct
  type FLASH_TypeDef (line 216) | typedef struct
  type OB_TypeDef (line 233) | typedef struct
  type GPIO_TypeDef (line 249) | typedef struct
  type SYSCFG_TypeDef (line 267) | typedef struct
  type I2C_TypeDef (line 279) | typedef struct
  type IWDG_TypeDef (line 298) | typedef struct
  type PWR_TypeDef (line 311) | typedef struct
  type RCC_TypeDef (line 320) | typedef struct
  type RTC_TypeDef (line 342) | typedef struct
  type SPI_TypeDef (line 375) | typedef struct
  type TIM_TypeDef (line 400) | typedef struct
  type USART_TypeDef (line 430) | typedef struct
  type WWDG_TypeDef (line 450) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 137) | typedef struct
  type ADC_Common_TypeDef (line 154) | typedef struct
  type CAN_TxMailBox_TypeDef (line 162) | typedef struct
  type CAN_FIFOMailBox_TypeDef (line 173) | typedef struct
  type CAN_FilterRegister_TypeDef (line 184) | typedef struct
  type CAN_TypeDef (line 193) | typedef struct
  type CEC_TypeDef (line 223) | typedef struct
  type CRC_TypeDef (line 237) | typedef struct
  type CRS_TypeDef (line 252) | typedef struct
  type DBGMCU_TypeDef (line 264) | typedef struct
  type DMA_Channel_TypeDef (line 276) | typedef struct
  type DMA_TypeDef (line 284) | typedef struct
  type EXTI_TypeDef (line 294) | typedef struct
  type FLASH_TypeDef (line 307) | typedef struct
  type OB_TypeDef (line 324) | typedef struct
  type GPIO_TypeDef (line 340) | typedef struct
  type SYSCFG_TypeDef (line 358) | typedef struct
  type I2C_TypeDef (line 370) | typedef struct
  type IWDG_TypeDef (line 389) | typedef struct
  type PWR_TypeDef (line 402) | typedef struct
  type RCC_TypeDef (line 411) | typedef struct
  type RTC_TypeDef (line 433) | typedef struct
  type SPI_TypeDef (line 466) | typedef struct
  type TIM_TypeDef (line 491) | typedef struct
  type TSC_TypeDef (line 519) | typedef struct
  type USART_TypeDef (line 541) | typedef struct
  type USB_TypeDef (line 562) | typedef struct
  type WWDG_TypeDef (line 599) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f048xx.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 137) | typedef struct
  type ADC_Common_TypeDef (line 154) | typedef struct
  type CAN_TxMailBox_TypeDef (line 162) | typedef struct
  type CAN_FIFOMailBox_TypeDef (line 173) | typedef struct
  type CAN_FilterRegister_TypeDef (line 184) | typedef struct
  type CAN_TypeDef (line 193) | typedef struct
  type CEC_TypeDef (line 223) | typedef struct
  type CRC_TypeDef (line 237) | typedef struct
  type CRS_TypeDef (line 252) | typedef struct
  type DBGMCU_TypeDef (line 264) | typedef struct
  type DMA_Channel_TypeDef (line 276) | typedef struct
  type DMA_TypeDef (line 284) | typedef struct
  type EXTI_TypeDef (line 294) | typedef struct
  type FLASH_TypeDef (line 307) | typedef struct
  type OB_TypeDef (line 324) | typedef struct
  type GPIO_TypeDef (line 340) | typedef struct
  type SYSCFG_TypeDef (line 358) | typedef struct
  type I2C_TypeDef (line 370) | typedef struct
  type IWDG_TypeDef (line 389) | typedef struct
  type PWR_TypeDef (line 402) | typedef struct
  type RCC_TypeDef (line 411) | typedef struct
  type RTC_TypeDef (line 433) | typedef struct
  type SPI_TypeDef (line 466) | typedef struct
  type TIM_TypeDef (line 491) | typedef struct
  type TSC_TypeDef (line 519) | typedef struct
  type USART_TypeDef (line 541) | typedef struct
  type USB_TypeDef (line 562) | typedef struct
  type WWDG_TypeDef (line 599) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f051x8.h
  type IRQn_Type (line 83) | typedef enum
  type ADC_TypeDef (line 140) | typedef struct
  type ADC_Common_TypeDef (line 157) | typedef struct
  type CEC_TypeDef (line 166) | typedef struct
  type COMP1_2_TypeDef (line 180) | typedef struct
  type COMP_TypeDef (line 185) | typedef struct
  type CRC_TypeDef (line 194) | typedef struct
  type DAC_TypeDef (line 210) | typedef struct
  type DBGMCU_TypeDef (line 225) | typedef struct
  type DMA_Channel_TypeDef (line 237) | typedef struct
  type DMA_TypeDef (line 245) | typedef struct
  type EXTI_TypeDef (line 255) | typedef struct
  type FLASH_TypeDef (line 268) | typedef struct
  type OB_TypeDef (line 285) | typedef struct
  type GPIO_TypeDef (line 301) | typedef struct
  type SYSCFG_TypeDef (line 319) | typedef struct
  type I2C_TypeDef (line 331) | typedef struct
  type IWDG_TypeDef (line 350) | typedef struct
  type PWR_TypeDef (line 363) | typedef struct
  type RCC_TypeDef (line 372) | typedef struct
  type RTC_TypeDef (line 394) | typedef struct
  type SPI_TypeDef (line 427) | typedef struct
  type TIM_TypeDef (line 452) | typedef struct
  type TSC_TypeDef (line 480) | typedef struct
  type USART_TypeDef (line 502) | typedef struct
  type WWDG_TypeDef (line 522) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f058xx.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 138) | typedef struct
  type ADC_Common_TypeDef (line 155) | typedef struct
  type CEC_TypeDef (line 164) | typedef struct
  type COMP1_2_TypeDef (line 178) | typedef struct
  type COMP_TypeDef (line 183) | typedef struct
  type CRC_TypeDef (line 192) | typedef struct
  type DAC_TypeDef (line 208) | typedef struct
  type DBGMCU_TypeDef (line 223) | typedef struct
  type DMA_Channel_TypeDef (line 235) | typedef struct
  type DMA_TypeDef (line 243) | typedef struct
  type EXTI_TypeDef (line 253) | typedef struct
  type FLASH_TypeDef (line 266) | typedef struct
  type OB_TypeDef (line 283) | typedef struct
  type GPIO_TypeDef (line 299) | typedef struct
  type SYSCFG_TypeDef (line 317) | typedef struct
  type I2C_TypeDef (line 329) | typedef struct
  type IWDG_TypeDef (line 348) | typedef struct
  type PWR_TypeDef (line 361) | typedef struct
  type RCC_TypeDef (line 370) | typedef struct
  type RTC_TypeDef (line 392) | typedef struct
  type SPI_TypeDef (line 425) | typedef struct
  type TIM_TypeDef (line 450) | typedef struct
  type TSC_TypeDef (line 478) | typedef struct
  type USART_TypeDef (line 500) | typedef struct
  type WWDG_TypeDef (line 520) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f071xb.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 141) | typedef struct
  type ADC_Common_TypeDef (line 158) | typedef struct
  type CEC_TypeDef (line 167) | typedef struct
  type COMP1_2_TypeDef (line 181) | typedef struct
  type COMP_TypeDef (line 186) | typedef struct
  type CRC_TypeDef (line 195) | typedef struct
  type CRS_TypeDef (line 210) | typedef struct
  type DAC_TypeDef (line 222) | typedef struct
  type DBGMCU_TypeDef (line 244) | typedef struct
  type DMA_Channel_TypeDef (line 256) | typedef struct
  type DMA_TypeDef (line 264) | typedef struct
  type EXTI_TypeDef (line 274) | typedef struct
  type FLASH_TypeDef (line 287) | typedef struct
  type OB_TypeDef (line 304) | typedef struct
  type GPIO_TypeDef (line 320) | typedef struct
  type SYSCFG_TypeDef (line 338) | typedef struct
  type I2C_TypeDef (line 350) | typedef struct
  type IWDG_TypeDef (line 369) | typedef struct
  type PWR_TypeDef (line 382) | typedef struct
  type RCC_TypeDef (line 391) | typedef struct
  type RTC_TypeDef (line 413) | typedef struct
  type SPI_TypeDef (line 446) | typedef struct
  type TIM_TypeDef (line 471) | typedef struct
  type TSC_TypeDef (line 499) | typedef struct
  type USART_TypeDef (line 521) | typedef struct
  type WWDG_TypeDef (line 541) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 142) | typedef struct
  type ADC_Common_TypeDef (line 159) | typedef struct
  type CAN_TxMailBox_TypeDef (line 167) | typedef struct
  type CAN_FIFOMailBox_TypeDef (line 178) | typedef struct
  type CAN_FilterRegister_TypeDef (line 189) | typedef struct
  type CAN_TypeDef (line 198) | typedef struct
  type CEC_TypeDef (line 228) | typedef struct
  type COMP1_2_TypeDef (line 242) | typedef struct
  type COMP_TypeDef (line 247) | typedef struct
  type CRC_TypeDef (line 256) | typedef struct
  type CRS_TypeDef (line 271) | typedef struct
  type DAC_TypeDef (line 283) | typedef struct
  type DBGMCU_TypeDef (line 305) | typedef struct
  type DMA_Channel_TypeDef (line 317) | typedef struct
  type DMA_TypeDef (line 325) | typedef struct
  type EXTI_TypeDef (line 335) | typedef struct
  type FLASH_TypeDef (line 348) | typedef struct
  type OB_TypeDef (line 365) | typedef struct
  type GPIO_TypeDef (line 381) | typedef struct
  type SYSCFG_TypeDef (line 399) | typedef struct
  type I2C_TypeDef (line 411) | typedef struct
  type IWDG_TypeDef (line 430) | typedef struct
  type PWR_TypeDef (line 443) | typedef struct
  type RCC_TypeDef (line 452) | typedef struct
  type RTC_TypeDef (line 474) | typedef struct
  type SPI_TypeDef (line 507) | typedef struct
  type TIM_TypeDef (line 532) | typedef struct
  type TSC_TypeDef (line 560) | typedef struct
  type USART_TypeDef (line 582) | typedef struct
  type USB_TypeDef (line 603) | typedef struct
  type WWDG_TypeDef (line 640) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f078xx.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 142) | typedef struct
  type ADC_Common_TypeDef (line 159) | typedef struct
  type CEC_TypeDef (line 168) | typedef struct
  type COMP1_2_TypeDef (line 182) | typedef struct
  type COMP_TypeDef (line 187) | typedef struct
  type CRC_TypeDef (line 196) | typedef struct
  type CRS_TypeDef (line 211) | typedef struct
  type DAC_TypeDef (line 223) | typedef struct
  type DBGMCU_TypeDef (line 245) | typedef struct
  type DMA_Channel_TypeDef (line 257) | typedef struct
  type DMA_TypeDef (line 265) | typedef struct
  type EXTI_TypeDef (line 275) | typedef struct
  type FLASH_TypeDef (line 288) | typedef struct
  type OB_TypeDef (line 305) | typedef struct
  type GPIO_TypeDef (line 321) | typedef struct
  type SYSCFG_TypeDef (line 339) | typedef struct
  type I2C_TypeDef (line 351) | typedef struct
  type IWDG_TypeDef (line 370) | typedef struct
  type PWR_TypeDef (line 383) | typedef struct
  type RCC_TypeDef (line 392) | typedef struct
  type RTC_TypeDef (line 414) | typedef struct
  type SPI_TypeDef (line 447) | typedef struct
  type TIM_TypeDef (line 472) | typedef struct
  type TSC_TypeDef (line 500) | typedef struct
  type USART_TypeDef (line 522) | typedef struct
  type USB_TypeDef (line 543) | typedef struct
  type WWDG_TypeDef (line 580) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 141) | typedef struct
  type ADC_Common_TypeDef (line 158) | typedef struct
  type CAN_TxMailBox_TypeDef (line 166) | typedef struct
  type CAN_FIFOMailBox_TypeDef (line 177) | typedef struct
  type CAN_FilterRegister_TypeDef (line 188) | typedef struct
  type CAN_TypeDef (line 197) | typedef struct
  type CEC_TypeDef (line 227) | typedef struct
  type COMP1_2_TypeDef (line 241) | typedef struct
  type COMP_TypeDef (line 246) | typedef struct
  type CRC_TypeDef (line 255) | typedef struct
  type CRS_TypeDef (line 270) | typedef struct
  type DAC_TypeDef (line 282) | typedef struct
  type DBGMCU_TypeDef (line 304) | typedef struct
  type DMA_Channel_TypeDef (line 316) | typedef struct
  type DMA_TypeDef (line 324) | typedef struct
  type EXTI_TypeDef (line 336) | typedef struct
  type FLASH_TypeDef (line 349) | typedef struct
  type OB_TypeDef (line 366) | typedef struct
  type GPIO_TypeDef (line 382) | typedef struct
  type SYSCFG_TypeDef (line 400) | typedef struct
  type I2C_TypeDef (line 415) | typedef struct
  type IWDG_TypeDef (line 434) | typedef struct
  type PWR_TypeDef (line 447) | typedef struct
  type RCC_TypeDef (line 456) | typedef struct
  type RTC_TypeDef (line 478) | typedef struct
  type SPI_TypeDef (line 511) | typedef struct
  type TIM_TypeDef (line 536) | typedef struct
  type TSC_TypeDef (line 564) | typedef struct
  type USART_TypeDef (line 586) | typedef struct
  type WWDG_TypeDef (line 606) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h
  type IRQn_Type (line 82) | typedef enum
  type ADC_TypeDef (line 141) | typedef struct
  type ADC_Common_TypeDef (line 158) | typedef struct
  type CAN_TxMailBox_TypeDef (line 166) | typedef struct
  type CAN_FIFOMailBox_TypeDef (line 177) | typedef struct
  type CAN_FilterRegister_TypeDef (line 188) | typedef struct
  type CAN_TypeDef (line 197) | typedef struct
  type CEC_TypeDef (line 227) | typedef struct
  type COMP1_2_TypeDef (line 241) | typedef struct
  type COMP_TypeDef (line 246) | typedef struct
  type CRC_TypeDef (line 255) | typedef struct
  type CRS_TypeDef (line 270) | typedef struct
  type DAC_TypeDef (line 282) | typedef struct
  type DBGMCU_TypeDef (line 304) | typedef struct
  type DMA_Channel_TypeDef (line 316) | typedef struct
  type DMA_TypeDef (line 324) | typedef struct
  type EXTI_TypeDef (line 336) | typedef struct
  type FLASH_TypeDef (line 349) | typedef struct
  type OB_TypeDef (line 366) | typedef struct
  type GPIO_TypeDef (line 382) | typedef struct
  type SYSCFG_TypeDef (line 400) | typedef struct
  type I2C_TypeDef (line 415) | typedef struct
  type IWDG_TypeDef (line 434) | typedef struct
  type PWR_TypeDef (line 447) | typedef struct
  type RCC_TypeDef (line 456) | typedef struct
  type RTC_TypeDef (line 478) | typedef struct
  type SPI_TypeDef (line 511) | typedef struct
  type TIM_TypeDef (line 536) | typedef struct
  type TSC_TypeDef (line 564) | typedef struct
  type USART_TypeDef (line 586) | typedef struct
  type WWDG_TypeDef (line 606) | typedef struct

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h
  type FlagStatus (line 161) | typedef enum
  type FunctionalState (line 167) | typedef enum
  type ErrorStatus (line 174) | typedef enum

FILE: Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c
  function SystemInit (line 159) | void SystemInit(void)
  function SystemCoreClockUpdate (line 240) | void SystemCoreClockUpdate (void)

FILE: Drivers/CMSIS/Include/arm_math.h
  type arm_status (line 336) | typedef enum
  type q7_t (line 350) | typedef int8_t q7_t;
  type q15_t (line 355) | typedef int16_t q15_t;
  type q31_t (line 360) | typedef int32_t q31_t;
  type q63_t (line 365) | typedef int64_t q63_t;
  type float32_t (line 370) | typedef float float32_t;
  type float64_t (line 375) | typedef double float64_t;
  function __INLINE (line 434) | static __INLINE q31_t clip_q63_to_q31(
  function __INLINE (line 444) | static __INLINE q15_t clip_q63_to_q15(
  function __INLINE (line 454) | static __INLINE q7_t clip_q31_to_q7(
  function __INLINE (line 464) | static __INLINE q15_t clip_q31_to_q15(
  function __INLINE (line 475) | static __INLINE q63_t mult32x64(
  function __INLINE (line 494) | static __INLINE uint32_t __CLZ(
  function __INLINE (line 516) | static __INLINE uint32_t arm_recip_q31(
  function __INLINE (line 567) | static __INLINE uint32_t arm_recip_q15(
  function __INLINE (line 620) | static __INLINE q31_t __SSAT(
  function __INLINE (line 668) | static __INLINE q31_t __QADD8(
  function __INLINE (line 695) | static __INLINE q31_t __QSUB8(
  function __INLINE (line 725) | static __INLINE q31_t __QADD16(
  function __INLINE (line 748) | static __INLINE q31_t __SHADD16(
  function __INLINE (line 771) | static __INLINE q31_t __QSUB16(
  function __INLINE (line 793) | static __INLINE q31_t __SHSUB16(
  function __INLINE (line 815) | static __INLINE q31_t __QASX(
  function __INLINE (line 833) | static __INLINE q31_t __SHASX(
  function __INLINE (line 856) | static __INLINE q31_t __QSAX(
  function __INLINE (line 874) | static __INLINE q31_t __SHSAX(
  function __INLINE (line 896) | static __INLINE q31_t __SMUSDX(
  function __INLINE (line 908) | static __INLINE q31_t __SMUADX(
  function __INLINE (line 920) | static __INLINE q31_t __QADD(
  function __INLINE (line 930) | static __INLINE q31_t __QSUB(
  function __INLINE (line 940) | static __INLINE q31_t __SMLAD(
  function __INLINE (line 953) | static __INLINE q31_t __SMLADX(
  function __INLINE (line 966) | static __INLINE q31_t __SMLSDX(
  function __INLINE (line 979) | static __INLINE q63_t __SMLALD(
  function __INLINE (line 992) | static __INLINE q63_t __SMLALDX(
  function __INLINE (line 1005) | static __INLINE q31_t __SMUAD(
  function __INLINE (line 1017) | static __INLINE q31_t __SMUSD(
  function __INLINE (line 1030) | static __INLINE q31_t __SXTB16(
  type arm_fir_instance_q7 (line 1045) | typedef struct
  type arm_fir_instance_q15 (line 1055) | typedef struct
  type arm_fir_instance_q31 (line 1065) | typedef struct
  type arm_fir_instance_f32 (line 1075) | typedef struct
  type arm_biquad_casd_df1_inst_q15 (line 1239) | typedef struct
  type arm_biquad_casd_df1_inst_q31 (line 1252) | typedef struct
  type arm_biquad_casd_df1_inst_f32 (line 1264) | typedef struct
  type arm_matrix_instance_f32 (line 1406) | typedef struct
  type arm_matrix_instance_q15 (line 1417) | typedef struct
  type arm_matrix_instance_q31 (line 1429) | typedef struct
  type arm_pid_instance_q15 (line 1734) | typedef struct
  type arm_pid_instance_q31 (line 1752) | typedef struct
  type arm_pid_instance_f32 (line 1767) | typedef struct
  type arm_linear_interp_instance_f32 (line 1841) | typedef struct
  type arm_bilinear_interp_instance_f32 (line 1853) | typedef struct
  type arm_bilinear_interp_instance_q31 (line 1864) | typedef struct
  type arm_bilinear_interp_instance_q15 (line 1875) | typedef struct
  type arm_bilinear_interp_instance_q7 (line 1886) | typedef struct
  type arm_cfft_radix2_instance_q15 (line 1963) | typedef struct
  type arm_cfft_radix4_instance_q15 (line 1990) | typedef struct
  type arm_cfft_radix2_instance_q31 (line 2015) | typedef struct
  type arm_cfft_radix4_instance_q31 (line 2040) | typedef struct
  type arm_cfft_radix2_instance_f32 (line 2066) | typedef struct
  type arm_cfft_radix4_instance_f32 (line 2094) | typedef struct
  type arm_cfft_instance_f32 (line 2122) | typedef struct
  type arm_rfft_instance_q15 (line 2140) | typedef struct
  type arm_rfft_instance_q31 (line 2168) | typedef struct
  type arm_rfft_instance_f32 (line 2196) | typedef struct
  type arm_rfft_fast_instance_f32 (line 2224) | typedef struct
  type arm_dct4_instance_f32 (line 2244) | typedef struct
  type arm_dct4_instance_q31 (line 2291) | typedef struct
  type arm_dct4_instance_q15 (line 2338) | typedef struct
  type arm_fir_decimate_instance_q15 (line 3317) | typedef struct
  type arm_fir_decimate_instance_q31 (line 3329) | typedef struct
  type arm_fir_decimate_instance_f32 (line 3342) | typedef struct
  type arm_fir_interpolate_instance_q15 (line 3498) | typedef struct
  type arm_fir_interpolate_instance_q31 (line 3510) | typedef struct
  type arm_fir_interpolate_instance_f32 (line 3522) | typedef struct
  type arm_biquad_cas_df1_32x64_ins_q31 (line 3642) | typedef struct
  type arm_biquad_cascade_df2T_instance_f32 (line 3689) | typedef struct
  type arm_fir_lattice_instance_q15 (line 3734) | typedef struct
  type arm_fir_lattice_instance_q31 (line 3745) | typedef struct
  type arm_fir_lattice_instance_f32 (line 3756) | typedef struct
  type arm_iir_lattice_instance_q15 (line 3857) | typedef struct
  type arm_iir_lattice_instance_q31 (line 3868) | typedef struct
  type arm_iir_lattice_instance_f32 (line 3879) | typedef struct
  type arm_lms_instance_f32 (line 3997) | typedef struct
  type arm_lms_instance_q15 (line 4047) | typedef struct
  type arm_lms_instance_q31 (line 4102) | typedef struct
  type arm_lms_norm_instance_f32 (line 4156) | typedef struct
  type arm_lms_norm_instance_q31 (line 4208) | typedef struct
  type arm_lms_norm_instance_q15 (line 4264) | typedef struct
  type arm_fir_sparse_instance_f32 (line 4488) | typedef struct
  type arm_fir_sparse_instance_q31 (line 4502) | typedef struct
  type arm_fir_sparse_instance_q15 (line 4516) | typedef struct
  type arm_fir_sparse_instance_q7 (line 4530) | typedef struct
  function __INLINE (line 4880) | static __INLINE float32_t arm_pid_f32(
  function __INLINE (line 4915) | static __INLINE q31_t arm_pid_q31(
  function __INLINE (line 4963) | static __INLINE q15_t arm_pid_q15(
  function __INLINE (line 5069) | static __INLINE void arm_clarke_f32(
  function __INLINE (line 5099) | static __INLINE void arm_clarke_q31(
  function __INLINE (line 5174) | static __INLINE void arm_inv_clarke_f32(
  function __INLINE (line 5203) | static __INLINE void arm_inv_clarke_q31(
  function __INLINE (line 5290) | static __INLINE void arm_park_f32(
  function __INLINE (line 5324) | static __INLINE void arm_park_q31(
  function __INLINE (line 5409) | static __INLINE void arm_inv_park_f32(
  function __INLINE (line 5444) | static __INLINE void arm_inv_park_q31(
  function __INLINE (line 5542) | static __INLINE float32_t arm_linear_interp_f32(
  function __INLINE (line 5601) | static __INLINE q31_t arm_linear_interp_q31(
  function __INLINE (line 5663) | static __INLINE q15_t arm_linear_interp_q15(
  function __INLINE (line 5723) | static __INLINE q7_t arm_linear_interp_q7(
  function __INLINE (line 5868) | static __INLINE arm_status arm_sqrt_f32(
  function __INLINE (line 5928) | static __INLINE void arm_circularWrite_f32(
  function __INLINE (line 5973) | static __INLINE void arm_circularRead_f32(
  function __INLINE (line 6028) | static __INLINE void arm_circularWrite_q15(
  function __INLINE (line 6073) | static __INLINE void arm_circularRead_q15(
  function __INLINE (line 6130) | static __INLINE void arm_circularWrite_q7(
  function __INLINE (line 6175) | static __INLINE void arm_circularRead_q7(
  function __INLINE (line 6916) | static __INLINE float32_t arm_bilinear_interp_f32(
  function __INLINE (line 6984) | static __INLINE q31_t arm_bilinear_interp_q31(
  function __INLINE (line 7060) | static __INLINE q15_t arm_bilinear_interp_q15(
  function __INLINE (line 7140) | static __INLINE q7_t arm_bilinear_interp_q7(

FILE: Drivers/CMSIS/Include/core_cm0.h
  type APSR_Type (line 195) | typedef union
  type IPSR_Type (line 218) | typedef union
  type xPSR_Type (line 231) | typedef union
  type CONTROL_Type (line 257) | typedef union
  type NVIC_Type (line 280) | typedef struct
  type SCB_Type (line 305) | typedef struct
  type SysTick_Type (line 410) | typedef struct
  function __STATIC_INLINE (line 515) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 527) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 543) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 555) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 567) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 582) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 604) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 618) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 656) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

FILE: Drivers/CMSIS/Include/core_cm0plus.h
  type APSR_Type (line 206) | typedef union
  type IPSR_Type (line 229) | typedef union
  type xPSR_Type (line 242) | typedef union
  type CONTROL_Type (line 268) | typedef union
  type NVIC_Type (line 291) | typedef struct
  type SCB_Type (line 316) | typedef struct
  type SysTick_Type (line 431) | typedef struct
  type MPU_Type (line 481) | typedef struct
  function __STATIC_INLINE (line 626) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 638) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 654) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 666) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 678) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 693) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 715) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 729) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 767) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

FILE: Drivers/CMSIS/Include/core_cm3.h
  type APSR_Type (line 211) | typedef union
  type IPSR_Type (line 234) | typedef union
  type xPSR_Type (line 247) | typedef union
  type CONTROL_Type (line 273) | typedef union
  type NVIC_Type (line 296) | typedef struct
  type SCB_Type (line 328) | typedef struct
  type SCnSCB_Type (line 553) | typedef struct
  type SysTick_Type (line 590) | typedef struct
  type DWT_Type (line 741) | typedef struct
  type TPI_Type (line 886) | typedef struct
  type MPU_Type (line 1040) | typedef struct
  type CoreDebug_Type (line 1132) | typedef struct
  function __STATIC_INLINE (line 1291) | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  function __STATIC_INLINE (line 1311) | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  function __STATIC_INLINE (line 1323) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1335) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1351) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1363) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1375) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1390) | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1405) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 1425) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1447) | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, ui...
  function __STATIC_INLINE (line 1475) | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t Pr...
  function __STATIC_INLINE (line 1493) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 1532) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  function __STATIC_INLINE (line 1572) | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
  function __STATIC_INLINE (line 1591) | __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
  function __STATIC_INLINE (line 1610) | __STATIC_INLINE int32_t ITM_CheckChar (void) {

FILE: Drivers/CMSIS/Include/core_cm4.h
  type APSR_Type (line 251) | typedef union
  type IPSR_Type (line 274) | typedef union
  type xPSR_Type (line 287) | typedef union
  type CONTROL_Type (line 313) | typedef union
  type NVIC_Type (line 336) | typedef struct
  type SCB_Type (line 368) | typedef struct
  type SCnSCB_Type (line 585) | typedef struct
  type SysTick_Type (line 623) | typedef struct
  type DWT_Type (line 774) | typedef struct
  type TPI_Type (line 919) | typedef struct
  type MPU_Type (line 1073) | typedef struct
  type FPU_Type (line 1166) | typedef struct
  type CoreDebug_Type (line 1271) | typedef struct
  function __STATIC_INLINE (line 1435) | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  function __STATIC_INLINE (line 1455) | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  function __STATIC_INLINE (line 1467) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1480) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1496) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1508) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1520) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1535) | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1550) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 1570) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1592) | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, ui...
  function __STATIC_INLINE (line 1620) | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t Pr...
  function __STATIC_INLINE (line 1638) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 1677) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  function __STATIC_INLINE (line 1717) | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
  function __STATIC_INLINE (line 1736) | __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
  function __STATIC_INLINE (line 1755) | __STATIC_INLINE int32_t ITM_CheckChar (void) {

FILE: Drivers/CMSIS/Include/core_cm4_simd.h
  function __STATIC_INLINE (line 158) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint...
  function __STATIC_INLINE (line 166) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint...
  function __STATIC_INLINE (line 174) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uin...
  function __STATIC_INLINE (line 182) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint...
  function __STATIC_INLINE (line 190) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uin...
  function __STATIC_INLINE (line 198) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uin...
  function __STATIC_INLINE (line 207) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint...
  function __STATIC_INLINE (line 215) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint...
  function __STATIC_INLINE (line 223) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uin...
  function __STATIC_INLINE (line 231) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint...
  function __STATIC_INLINE (line 239) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uin...
  function __STATIC_INLINE (line 247) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uin...
  function __STATIC_INLINE (line 256) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uin...
  function __STATIC_INLINE (line 264) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uin...
  function __STATIC_INLINE (line 272) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(ui...
  function __STATIC_INLINE (line 280) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uin...
  function __STATIC_INLINE (line 288) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(ui...
  function __STATIC_INLINE (line 296) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(ui...
  function __STATIC_INLINE (line 304) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uin...
  function __STATIC_INLINE (line 312) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uin...
  function __STATIC_INLINE (line 320) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(ui...
  function __STATIC_INLINE (line 328) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uin...
  function __STATIC_INLINE (line 336) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(ui...
  function __STATIC_INLINE (line 344) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(ui...
  function __STATIC_INLINE (line 352) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint3...
  function __STATIC_INLINE (line 360) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint3...
  function __STATIC_INLINE (line 368) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint...
  function __STATIC_INLINE (line 376) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint3...
  function __STATIC_INLINE (line 384) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint...
  function __STATIC_INLINE (line 392) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint...
  function __STATIC_INLINE (line 400) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint3...
  function __STATIC_INLINE (line 408) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint3...
  function __STATIC_INLINE (line 416) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint...
  function __STATIC_INLINE (line 424) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint3...
  function __STATIC_INLINE (line 432) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint...
  function __STATIC_INLINE (line 440) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint...
  function __STATIC_INLINE (line 448) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint...
  function __STATIC_INLINE (line 456) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uin...
  function __STATIC_INLINE (line 478) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uin...
  function __STATIC_INLINE (line 486) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(ui...
  function __STATIC_INLINE (line 494) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uin...
  function __STATIC_INLINE (line 502) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(ui...
  function __STATIC_INLINE (line 510) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (ui...
  function __STATIC_INLINE (line 518) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (ui...
  function __STATIC_INLINE (line 526) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uin...
  function __STATIC_INLINE (line 534) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (ui...
  function __STATIC_INLINE (line 556) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (ui...
  function __STATIC_INLINE (line 564) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (ui...
  function __STATIC_INLINE (line 572) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uin...
  function __STATIC_INLINE (line 580) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (ui...
  function __STATIC_INLINE (line 602) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint...
  function __STATIC_INLINE (line 610) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint3...
  function __STATIC_INLINE (line 618) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint3...
  function __STATIC_INLINE (line 643) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int...

FILE: Drivers/CMSIS/Include/core_cmFunc.h
  function __STATIC_INLINE (line 64) | __STATIC_INLINE uint32_t __get_CONTROL(void)
  function __STATIC_INLINE (line 77) | __STATIC_INLINE void __set_CONTROL(uint32_t control)
  function __STATIC_INLINE (line 90) | __STATIC_INLINE uint32_t __get_IPSR(void)
  function __STATIC_INLINE (line 103) | __STATIC_INLINE uint32_t __get_APSR(void)
  function __STATIC_INLINE (line 116) | __STATIC_INLINE uint32_t __get_xPSR(void)
  function __STATIC_INLINE (line 129) | __STATIC_INLINE uint32_t __get_PSP(void)
  function __STATIC_INLINE (line 142) | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  function __STATIC_INLINE (line 155) | __STATIC_INLINE uint32_t __get_MSP(void)
  function __STATIC_INLINE (line 168) | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  function __STATIC_INLINE (line 181) | __STATIC_INLINE uint32_t __get_PRIMASK(void)
  function __STATIC_INLINE (line 194) | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  function __STATIC_INLINE (line 225) | __STATIC_INLINE uint32_t  __get_BASEPRI(void)
  function __STATIC_INLINE (line 238) | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  function __STATIC_INLINE (line 251) | __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  function __STATIC_INLINE (line 264) | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  function __STATIC_INLINE (line 281) | __STATIC_INLINE uint32_t __get_FPSCR(void)
  function __STATIC_INLINE (line 298) | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  function __STATIC_INLINE (line 352) | __STATIC_INLINE uint32_t __get_CONTROL(void)
  function __STATIC_INLINE (line 367) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(ui...
  function __STATIC_INLINE (line 379) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(v...
  function __STATIC_INLINE (line 394) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(v...
  function __STATIC_INLINE (line 409) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(v...
  function __STATIC_INLINE (line 424) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
  function __STATIC_INLINE (line 439) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32...
  function __STATIC_INLINE (line 451) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
  function __STATIC_INLINE (line 466) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32...
  function __STATIC_INLINE (line 478) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMAS...
  function __STATIC_INLINE (line 493) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(ui...
  function __STATIC_INLINE (line 529) | __STATIC_INLINE uint32_t __get_BASEPRI(void)
  function __STATIC_INLINE (line 544) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(ui...
  function __STATIC_INLINE (line 556) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTM...
  function __STATIC_INLINE (line 571) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(...
  function __STATIC_INLINE (line 587) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(...
  function __STATIC_INLINE (line 609) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint...

FILE: Drivers/CMSIS/Include/core_cmInstr.h
  function __REV16 (line 129) | uint32_t __REV16(uint32_t value)
  function __REVSH (line 144) | int32_t __REVSH(int32_t value)
  function __STATIC_INLINE (line 325) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
  function __STATIC_INLINE (line 336) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
  function __STATIC_INLINE (line 347) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
  function __STATIC_INLINE (line 357) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
  function __STATIC_INLINE (line 369) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
  function __STATIC_INLINE (line 380) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
  function __STATIC_INLINE (line 391) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
  function __STATIC_INLINE (line 404) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32...
  function __STATIC_INLINE (line 424) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint...
  function __STATIC_INLINE (line 440) | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32...
  function __STATIC_INLINE (line 461) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32...
  function __STATIC_INLINE (line 487) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint3...
  function __STATIC_INLINE (line 503) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(vola...
  function __STATIC_INLINE (line 526) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(vol...
  function __STATIC_INLINE (line 549) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(vol...
  function __STATIC_INLINE (line 567) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uin...
  function __STATIC_INLINE (line 585) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uin...
  function __STATIC_INLINE (line 603) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uin...
  function __STATIC_INLINE (line 617) | __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
  function __STATIC_INLINE (line 662) | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_...

FILE: Drivers/CMSIS/Include/core_sc000.h
  type APSR_Type (line 201) | typedef union
  type IPSR_Type (line 224) | typedef union
  type xPSR_Type (line 237) | typedef union
  type CONTROL_Type (line 263) | typedef union
  type NVIC_Type (line 286) | typedef struct
  type SCB_Type (line 311) | typedef struct
  type SCnSCB_Type (line 429) | typedef struct
  type SysTick_Type (line 450) | typedef struct
  type MPU_Type (line 500) | typedef struct
  function __STATIC_INLINE (line 646) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 658) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 674) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 686) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 698) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 713) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 735) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 749) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 787) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

FILE: Drivers/CMSIS/Include/core_sc300.h
  type APSR_Type (line 202) | typedef union
  type IPSR_Type (line 225) | typedef union
  type xPSR_Type (line 238) | typedef union
  type CONTROL_Type (line 264) | typedef union
  type NVIC_Type (line 287) | typedef struct
  type SCB_Type (line 319) | typedef struct
  type SCnSCB_Type (line 539) | typedef struct
  type SysTick_Type (line 561) | typedef struct
  type DWT_Type (line 712) | typedef struct
  type TPI_Type (line 857) | typedef struct
  type MPU_Type (line 1011) | typedef struct
  type CoreDebug_Type (line 1103) | typedef struct
  function __STATIC_INLINE (line 1262) | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  function __STATIC_INLINE (line 1282) | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  function __STATIC_INLINE (line 1294) | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1306) | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1322) | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1334) | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1346) | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1361) | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1376) | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  function __STATIC_INLINE (line 1396) | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  function __STATIC_INLINE (line 1418) | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, ui...
  function __STATIC_INLINE (line 1446) | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t Pr...
  function __STATIC_INLINE (line 1464) | __STATIC_INLINE void NVIC_SystemReset(void)
  function __STATIC_INLINE (line 1503) | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  function __STATIC_INLINE (line 1543) | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
  function __STATIC_INLINE (line 1562) | __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
  function __STATIC_INLINE (line 1581) | __STATIC_INLINE int32_t ITM_CheckChar (void) {

FILE: Drivers/CMSIS/RTOS/cmsis_os.h
  type osPriority (line 165) | typedef enum  {
  type osStatus (line 182) | typedef enum  {
  type os_timer_type (line 203) | typedef enum  {
  type os_thread_cb (line 220) | struct os_thread_cb
  type os_timer_cb (line 224) | struct os_timer_cb
  type os_mutex_cb (line 228) | struct os_mutex_cb
  type os_semaphore_cb (line 232) | struct os_semaphore_cb
  type os_pool_cb (line 236) | struct os_pool_cb
  type os_messageQ_cb (line 240) | struct os_messageQ_cb
  type os_mailQ_cb (line 244) | struct os_mailQ_cb
  type osThreadDef_t (line 249) | typedef struct os_thread_def  {
  type osTimerDef_t (line 258) | typedef struct os_timer_def  {
  type osMutexDef_t (line 264) | typedef struct os_mutex_def  {
  type osSemaphoreDef_t (line 270) | typedef struct os_semaphore_def  {
  type osPoolDef_t (line 276) | typedef struct os_pool_def  {
  type osMessageQDef_t (line 284) | typedef struct os_messageQ_def  {
  type osMailQDef_t (line 292) | typedef struct os_mailQ_def  {
  type osEvent (line 301) | typedef struct  {

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h
  type ADC_InitTypeDef (line 71) | typedef struct
  type ADC_ChannelConfTypeDef (line 132) | typedef struct
  type ADC_AnalogWDGConfTypeDef (line 156) | typedef struct
  type HAL_ADC_StateTypeDef (line 174) | typedef enum
  type ADC_HandleTypeDef (line 196) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h
  type HAL_CAN_StateTypeDef (line 66) | typedef enum
  type HAL_CAN_ErrorTypeDef (line 82) | typedef enum
  type CAN_InitTypeDef (line 99) | typedef struct
  type CAN_FilterConfTypeDef (line 140) | typedef struct
  type CanTxMsgTypeDef (line 183) | typedef struct
  type CanRxMsgTypeDef (line 208) | typedef struct
  type CAN_HandleTypeDef (line 239) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cec.h
  type CEC_InitTypeDef (line 69) | typedef struct
  type HAL_CEC_StateTypeDef (line 134) | typedef enum
  type HAL_CEC_ErrorTypeDef (line 149) | typedef enum
  type CEC_HandleTypeDef (line 167) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_comp.h
  type COMP_InitTypeDef (line 69) | typedef struct
  type HAL_COMP_StateTypeDef (line 102) | typedef enum
  type COMP_HandleTypeDef (line 114) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_crc.h
  type HAL_CRC_StateTypeDef (line 64) | typedef enum
  type CRC_InitTypeDef (line 77) | typedef struct
  type CRC_HandleTypeDef (line 122) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dac.h
  type HAL_DAC_StateTypeDef (line 70) | typedef enum
  type DAC_HandleTypeDef (line 83) | typedef struct
  type DAC_ChannelConfTypeDef (line 102) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h
  type HAL_StatusTypeDef (line 55) | typedef enum
  type HAL_LockTypeDef (line 66) | typedef enum

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h
  type DMA_InitTypeDef (line 65) | typedef struct
  type DMA_ControlTypeDef (line 96) | typedef enum
  type HAL_DMA_StateTypeDef (line 106) | typedef enum
  type HAL_DMA_LevelCompleteTypeDef (line 120) | typedef enum
  type DMA_HandleTypeDef (line 131) | typedef struct __DMA_HandleTypeDef

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h
  type FLASH_ErrorTypeDef (line 66) | typedef enum
  type FLASH_EraseInitTypeDef (line 75) | typedef struct
  type FLASH_OBProgramInitTypeDef (line 91) | typedef struct
  type FLASH_ProcedureTypeDef (line 122) | typedef enum
  type FLASH_ProcessTypeDef (line 135) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h
  type GPIO_InitTypeDef (line 65) | typedef struct
  type GPIO_PinState (line 86) | typedef enum

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h
  type I2C_InitTypeDef (line 66) | typedef struct
  type HAL_I2C_StateTypeDef (line 104) | typedef enum
  type HAL_I2C_ErrorTypeDef (line 129) | typedef enum
  type I2C_HandleTypeDef (line 150) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2s.h
  type I2S_InitTypeDef (line 71) | typedef struct
  type HAL_I2S_StateTypeDef (line 95) | typedef enum
  type HAL_I2S_ErrorTypeDef (line 109) | typedef enum
  type I2S_HandleTypeDef (line 122) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_irda.h
  type IRDA_InitTypeDef (line 68) | typedef struct
  type HAL_IRDA_StateTypeDef (line 98) | typedef enum
  type HAL_IRDA_ErrorTypeDef (line 113) | typedef enum
  type IRDA_ClockSourceTypeDef (line 126) | typedef enum
  type IRDA_HandleTypeDef (line 138) | typedef struct
  type IRDA_ControlTypeDef (line 173) | typedef enum

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_iwdg.h
  type HAL_IWDG_StateTypeDef (line 66) | typedef enum
  type IWDG_InitTypeDef (line 79) | typedef struct
  type IWDG_HandleTypeDef (line 95) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pcd.h
  type PCD_StateTypeDef (line 67) | typedef enum
  type PCD_EP_DBUF_DIR (line 75) | typedef enum
  type PCD_EP_BUF_NUM (line 84) | typedef enum
  type PCD_InitTypeDef (line 94) | typedef struct
  type PCD_EPTypeDef (line 123) | typedef struct
  type USB_TypeDef (line 164) | typedef   USB_TypeDef PCD_TypeDef;
  type PCD_HandleTypeDef (line 169) | typedef struct
  function else (line 654) | else if((bDir) == PCD_EP_DBUF_IN)\

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_ppp.h
  type PPP_TypeDef (line 67) | typedef struct
  type PPP_InitTypeDef (line 75) | typedef struct
  type HAL_PPP_StateTypeDef (line 99) | typedef enum
  type PPP_HandleTypeDef (line 116) | typedef struct
  type PPP_ControlTypeDef (line 132) | typedef enum

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
  type PWR_PVDTypeDef (line 70) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h
  type RCC_PLLInitTypeDef (line 66) | typedef struct
  type RCC_OscInitTypeDef (line 85) | typedef struct
  type RCC_ClkInitTypeDef (line 121) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h
  type RCC_PeriphCLKInitTypeDef (line 67) | typedef struct
  type RCC_PeriphCLKInitTypeDef (line 85) | typedef struct
  type RCC_PeriphCLKInitTypeDef (line 109) | typedef struct
  type RCC_PeriphCLKInitTypeDef (line 130) | typedef struct
  type RCC_PeriphCLKInitTypeDef (line 154) | typedef struct
  type RCC_PeriphCLKInitTypeDef (line 182) | typedef struct
  type RCC_CRSStatusTypeDef (line 215) | typedef enum
  type RCC_CRSInitTypeDef (line 229) | typedef struct
  type RCC_CRSSynchroInfoTypeDef (line 255) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc.h
  type HAL_RTCStateTypeDef (line 65) | typedef enum
  type RTC_InitTypeDef (line 78) | typedef struct
  type RTC_TimeTypeDef (line 102) | typedef struct
  type RTC_DateTypeDef (line 131) | typedef struct
  type RTC_AlarmTypeDef (line 150) | typedef struct
  type RTC_HandleTypeDef (line 174) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rtc_ex.h
  type RTC_TamperTypeDef (line 66) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smartcard.h
  type SMARTCARD_InitTypeDef (line 68) | typedef struct
  type SMARTCARD_AdvFeatureInitTypeDef (line 131) | typedef struct
  type HAL_SMARTCARD_StateTypeDef (line 163) | typedef enum
  type HAL_SMARTCARD_ErrorTypeDef (line 178) | typedef enum
  type SMARTCARD_ClockSourceTypeDef (line 192) | typedef enum
  type SMARTCARD_HandleTypeDef (line 204) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_smbus.h
  type SMBUS_InitTypeDef (line 65) | typedef struct
  type HAL_SMBUS_StateTypeDef (line 109) | typedef enum
  type HAL_SMBUS_ErrorTypeDef (line 128) | typedef enum
  type SMBUS_HandleTypeDef (line 145) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_spi.h
  type SPI_InitTypeDef (line 65) | typedef struct
  type HAL_SPI_StateTypeDef (line 118) | typedef enum
  type HAL_SPI_ErrorTypeDef (line 134) | typedef enum
  type SPI_HandleTypeDef (line 149) | typedef struct __SPI_HandleTypeDef

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h
  type TIM_Base_InitTypeDef (line 65) | typedef struct
  type TIM_OC_InitTypeDef (line 93) | typedef struct
  type TIM_OnePulse_InitTypeDef (line 125) | typedef struct
  type TIM_IC_InitTypeDef (line 162) | typedef struct
  type TIM_Encoder_InitTypeDef (line 180) | typedef struct
  type TIM_ClockConfigTypeDef (line 214) | typedef struct
  type TIM_ClearInputConfigTypeDef (line 229) | typedef struct
  type TIM_SlaveConfigTypeDef (line 246) | typedef struct {
  type HAL_TIM_StateTypeDef (line 263) | typedef enum
  type HAL_TIM_ActiveChannel (line 275) | typedef enum
  type TIM_HandleTypeDef (line 287) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h
  type TIM_HallSensor_InitTypeDef (line 66) | typedef struct
  type TIM_MasterConfigTypeDef (line 84) | typedef struct {
  type TIM_BreakDeadTimeConfigTypeDef (line 94) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tsc.h
  type HAL_TSC_StateTypeDef (line 70) | typedef enum
  type TSC_GroupStatusTypeDef (line 81) | typedef enum
  type TSC_InitTypeDef (line 90) | typedef struct
  type TSC_IOConfigTypeDef (line 111) | typedef struct
  type TSC_HandleTypeDef (line 121) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h
  type UART_InitTypeDef (line 66) | typedef struct
  type UART_AdvFeatureInitTypeDef (line 108) | typedef struct
  type UART_WakeUpTypeDef (line 147) | typedef struct
  type HAL_UART_StateTypeDef (line 163) | typedef enum
  type HAL_UART_ErrorTypeDef (line 178) | typedef enum
  type UART_ClockSourceTypeDef (line 191) | typedef enum
  type UART_HandleTypeDef (line 203) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_usart.h
  type USART_InitTypeDef (line 66) | typedef struct
  type HAL_USART_StateTypeDef (line 102) | typedef enum
  type HAL_USART_ErrorTypeDef (line 117) | typedef enum
  type USART_ClockSourceTypeDef (line 130) | typedef enum
  type USART_HandleTypeDef (line 142) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_wwdg.h
  type HAL_WWDG_StateTypeDef (line 66) | typedef enum
  type WWDG_InitTypeDef (line 78) | typedef struct
  type WWDG_HandleTypeDef (line 94) | typedef struct

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
  function HAL_StatusTypeDef (line 150) | HAL_StatusTypeDef HAL_Init(void)
  function HAL_StatusTypeDef (line 174) | HAL_StatusTypeDef HAL_DeInit(void)
  function __weak (line 197) | __weak void HAL_MspInit(void)
  function __weak (line 208) | __weak void HAL_MspDeInit(void)
  function __weak (line 231) | __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
  function __weak (line 279) | __weak void HAL_IncTick(void)
  function __weak (line 290) | __weak uint32_t HAL_GetTick(void)
  function __weak (line 305) | __weak void HAL_SuspendTick(void)
  function __weak (line 323) | __weak void HAL_ResumeTick(void)
  function __weak (line 341) | __weak void HAL_Delay(__IO uint32_t Delay)
  function HAL_GetHalVersion (line 354) | uint32_t HAL_GetHalVersion(void)
  function HAL_GetREVID (line 363) | uint32_t HAL_GetREVID(void)
  function HAL_GetDEVID (line 372) | uint32_t HAL_GetDEVID(void)
  function HAL_EnableDBGStopMode (line 381) | void HAL_EnableDBGStopMode(void)
  function HAL_DisableDBGStopMode (line 390) | void HAL_DisableDBGStopMode(void)
  function HAL_EnableDBGStandbyMode (line 399) | void HAL_EnableDBGStandbyMode(void)
  function HAL_DisableDBGStandbyMode (line 408) | void HAL_DisableDBGStandbyMode(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c
  function HAL_StatusTypeDef (line 248) | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 429) | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
  function __weak (line 547) | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
  function __weak (line 559) | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 598) | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 648) | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 688) | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uin...
  function HAL_StatusTypeDef (line 759) | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t...
  function HAL_StatusTypeDef (line 831) | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 897) | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 946) | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* p...
  function HAL_StatusTypeDef (line 1023) | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
  function HAL_ADC_GetValue (line 1089) | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
  function ADC_DMAConvCplt (line 1109) | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
  function ADC_DMAHalfConvCplt (line 1130) | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
  function ADC_DMAError (line 1144) | static void ADC_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_ADC_IRQHandler (line 1164) | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
  function __weak (line 1275) | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
  function __weak (line 1287) | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
  function __weak (line 1299) | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
  function __weak (line 1312) | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
  function HAL_StatusTypeDef (line 1363) | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_Cha...
  function HAL_StatusTypeDef (line 1499) | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_A...
  function HAL_ADC_StateTypeDef (line 1611) | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
  function HAL_ADC_GetError (line 1625) | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
  function HAL_StatusTypeDef (line 1649) | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 1713) | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
  function HAL_StatusTypeDef (line 1769) | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c
  function HAL_StatusTypeDef (line 198) | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c
  function HAL_StatusTypeDef (line 166) | HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
  function HAL_StatusTypeDef (line 342) | HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_Filt...
  function HAL_StatusTypeDef (line 439) | HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
  function __weak (line 472) | __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
  function __weak (line 485) | __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
  function HAL_StatusTypeDef (line 520) | HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Tim...
  function HAL_StatusTypeDef (line 647) | HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
  function HAL_StatusTypeDef (line 764) | HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFON...
  function HAL_StatusTypeDef (line 868) | HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FI...
  function HAL_StatusTypeDef (line 937) | HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
  function HAL_StatusTypeDef (line 992) | HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
  function HAL_CAN_IRQHandler (line 1044) | void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
  function __weak (line 1159) | __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
  function __weak (line 1172) | __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
  function __weak (line 1185) | __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
  function HAL_CAN_StateTypeDef (line 1218) | HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
  function HAL_CAN_GetError (line 1230) | uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
  function HAL_StatusTypeDef (line 1255) | static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
  function HAL_StatusTypeDef (line 1303) | static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cec.c
  function HAL_StatusTypeDef (line 153) | HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
  function HAL_StatusTypeDef (line 215) | HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
  function __weak (line 247) | __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
  function __weak (line 259) | __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
  function HAL_StatusTypeDef (line 324) | HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t Dest...
  function HAL_StatusTypeDef (line 473) | HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pDat...
  function HAL_StatusTypeDef (line 577) | HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t D...
  function HAL_StatusTypeDef (line 711) | HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *p...
  function HAL_CEC_IRQHandler (line 765) | void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
  function __weak (line 874) | __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
  function __weak (line 886) | __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
  function __weak (line 898) | __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
  function HAL_CEC_StateTypeDef (line 928) | HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
  function HAL_CEC_GetError (line 939) | uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
  function HAL_StatusTypeDef (line 963) | static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
  function HAL_StatusTypeDef (line 1029) | static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_comp.c
  function HAL_StatusTypeDef (line 212) | HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 294) | HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
  function __weak (line 332) | __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
  function __weak (line 344) | __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 375) | HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 415) | HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 455) | HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 500) | HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
  function HAL_COMP_IRQHandler (line 517) | void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
  function HAL_StatusTypeDef (line 556) | HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
  function HAL_COMP_GetOutputLevel (line 602) | uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
  function __weak (line 628) | __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
  function HAL_COMP_StateTypeDef (line 660) | HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
  function HAL_NVIC_SetPriority (line 152) | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint...
  function HAL_NVIC_EnableIRQ (line 168) | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
  function HAL_NVIC_DisableIRQ (line 181) | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
  function HAL_NVIC_SystemReset (line 191) | void HAL_NVIC_SystemReset(void)
  function HAL_SYSTICK_Config (line 204) | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
  function HAL_NVIC_GetPriority (line 236) | uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
  function HAL_NVIC_SetPendingIRQ (line 249) | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
  function HAL_NVIC_GetPendingIRQ (line 264) | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
  function HAL_NVIC_ClearPendingIRQ (line 277) | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  function HAL_SYSTICK_CLKSourceConfig (line 291) | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
  function HAL_SYSTICK_IRQHandler (line 309) | void HAL_SYSTICK_IRQHandler(void)
  function __weak (line 318) | __weak void HAL_SYSTICK_Callback(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc.c
  function HAL_StatusTypeDef (line 120) | HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
  function HAL_StatusTypeDef (line 186) | HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
  function __weak (line 224) | __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
  function __weak (line 236) | __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
  function HAL_CRC_Accumulate (line 276) | uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[],...
  function HAL_CRC_Calculate (line 330) | uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], ...
  function HAL_CRC_StateTypeDef (line 403) | HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
  function CRC_Handle_8 (line 427) | static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[],...
  function CRC_Handle_16 (line 470) | static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_crc_ex.c
  function HAL_StatusTypeDef (line 105) | HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
  function HAL_StatusTypeDef (line 141) | HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, ...
  function HAL_StatusTypeDef (line 167) | HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc,...
  function HAL_StatusTypeDef (line 201) | HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac.c
  function HAL_StatusTypeDef (line 229) | HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
  function HAL_StatusTypeDef (line 264) | HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
  function __weak (line 300) | __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
  function __weak (line 313) | __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
  function __weak (line 352) | __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t...
  function HAL_StatusTypeDef (line 371) | HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function __weak (line 403) | __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint...
  function HAL_StatusTypeDef (line 422) | HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Cha...
  function __weak (line 460) | __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
  function __weak (line 473) | __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
  function __weak (line 486) | __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
  function __weak (line 499) | __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
  function __weak (line 536) | __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, ...
  function HAL_StatusTypeDef (line 561) | HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Cha...
  function __weak (line 597) | __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function HAL_DAC_StateTypeDef (line 632) | HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
  function HAL_DAC_GetError (line 645) | uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
  function __weak (line 656) | __weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dac_ex.c
  function HAL_StatusTypeDef (line 131) | HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Cha...
  function HAL_StatusTypeDef (line 187) | HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Cha...
  function HAL_DAC_GetValue (line 245) | uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function HAL_DAC_GetValue (line 277) | uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function HAL_StatusTypeDef (line 303) | HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function HAL_StatusTypeDef (line 369) | HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Ch...
  function HAL_StatusTypeDef (line 485) | HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
  function HAL_StatusTypeDef (line 539) | HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Ch...
  function HAL_DAC_IRQHandler (line 619) | void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
  function HAL_DAC_IRQHandler (line 670) | void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
  function HAL_DACEx_DualGetValue (line 703) | uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
  function HAL_DACEx_DualGetValue (line 727) | uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
  function HAL_StatusTypeDef (line 765) | HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac...
  function HAL_StatusTypeDef (line 813) | HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, u...
  function HAL_StatusTypeDef (line 860) | HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32...
  function DAC_DMAConvCpltCh1 (line 907) | static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
  function DAC_DMAHalfConvCpltCh1 (line 922) | static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
  function DAC_DMAErrorCh1 (line 935) | static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
  function __weak (line 970) | __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
  function __weak (line 983) | __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
  function __weak (line 996) | __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
  function __weak (line 1009) | __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
  function DAC_DMAConvCpltCh2 (line 1022) | void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
  function DAC_DMAHalfConvCpltCh2 (line 1037) | void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
  function DAC_DMAErrorCh2 (line 1050) | void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
  function HAL_StatusTypeDef (line 170) | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 225) | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 306) | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAdd...
  function HAL_StatusTypeDef (line 338) | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t Src...
  function HAL_StatusTypeDef (line 382) | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 427) | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint3...
  function HAL_DMA_IRQHandler (line 516) | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
  function HAL_DMA_StateTypeDef (line 628) | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
  function HAL_DMA_GetError (line 639) | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
  function DMA_SetConfig (line 665) | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
  function HAL_StatusTypeDef (line 182) | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Addre...
  function HAL_StatusTypeDef (line 256) | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Ad...
  function HAL_FLASH_IRQHandler (line 302) | void HAL_FLASH_IRQHandler(void)
  function __weak (line 426) | __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
  function __weak (line 441) | __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
  function HAL_StatusTypeDef (line 471) | HAL_StatusTypeDef HAL_FLASH_Unlock(void)
  function HAL_StatusTypeDef (line 491) | HAL_StatusTypeDef HAL_FLASH_Lock(void)
  function HAL_StatusTypeDef (line 504) | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
  function HAL_StatusTypeDef (line 524) | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
  function HAL_StatusTypeDef (line 536) | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
  function FLASH_ErrorTypeDef (line 569) | FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
  function FLASH_PageErase (line 592) | void FLASH_PageErase(uint32_t PageAddress)
  function FLASH_Program_HalfWord (line 609) | static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
  function HAL_StatusTypeDef (line 625) | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
  function FLASH_SetErrorCode (line 660) | static void FLASH_SetErrorCode(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
  function HAL_StatusTypeDef (line 160) | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, ...
  function HAL_StatusTypeDef (line 248) | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
  function HAL_StatusTypeDef (line 314) | HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
  function HAL_StatusTypeDef (line 370) | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBI...
  function HAL_FLASHEx_OBGetConfig (line 421) | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
  function FLASH_MassErase (line 451) | static void FLASH_MassErase(void)
  function HAL_StatusTypeDef (line 471) | static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
  function HAL_StatusTypeDef (line 580) | static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
  function HAL_StatusTypeDef (line 689) | static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
  function HAL_StatusTypeDef (line 726) | static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
  function HAL_StatusTypeDef (line 781) | static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t ...
  function FLASH_OB_GetWRP (line 814) | static uint32_t FLASH_OB_GetWRP(void)
  function FlagStatus (line 826) | static FlagStatus FLASH_OB_GetRDP(void)
  function FLASH_OB_GetUser (line 843) | static uint8_t FLASH_OB_GetUser(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
  function HAL_GPIO_Init (line 193) | void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  function HAL_GPIO_DeInit (line 338) | void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
  function GPIO_PinState (line 421) | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
  function HAL_GPIO_WritePin (line 455) | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinS...
  function HAL_GPIO_TogglePin (line 479) | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
  function HAL_StatusTypeDef (line 500) | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
  function HAL_GPIO_EXTI_IRQHandler (line 534) | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
  function __weak (line 549) | __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
  function HAL_StatusTypeDef (line 293) | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 373) | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
  function __weak (line 407) | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
  function __weak (line 420) | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 500) | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint1...
  function HAL_StatusTypeDef (line 620) | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16...
  function HAL_StatusTypeDef (line 733) | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_...
  function HAL_StatusTypeDef (line 862) | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t...
  function HAL_StatusTypeDef (line 974) | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, ui...
  function HAL_StatusTypeDef (line 1046) | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uin...
  function HAL_StatusTypeDef (line 1116) | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uin...
  function HAL_StatusTypeDef (line 1166) | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint...
  function HAL_StatusTypeDef (line 1217) | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, u...
  function HAL_StatusTypeDef (line 1308) | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, ui...
  function HAL_StatusTypeDef (line 1388) | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, ui...
  function HAL_StatusTypeDef (line 1474) | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uin...
  function HAL_StatusTypeDef (line 1549) | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t De...
  function HAL_StatusTypeDef (line 1692) | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t Dev...
  function HAL_StatusTypeDef (line 1829) | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t...
  function HAL_StatusTypeDef (line 1922) | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t ...
  function HAL_StatusTypeDef (line 2014) | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_...
  function HAL_StatusTypeDef (line 2123) | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t...
  function HAL_StatusTypeDef (line 2222) | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_...
  function HAL_I2C_EV_IRQHandler (line 2335) | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
  function HAL_I2C_ER_IRQHandler (line 2381) | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
  function __weak (line 2425) | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2438) | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2450) | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2463) | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2476) | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2489) | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
  function __weak (line 2502) | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
  function HAL_I2C_StateTypeDef (line 2533) | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
  function HAL_I2C_GetError (line 2544) | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 2567) | static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 2674) | static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 2782) | static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 2868) | static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 2931) | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c,...
  function HAL_StatusTypeDef (line 2996) | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, ...
  function I2C_DMAMasterTransmitCplt (line 3056) | static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMASlaveTransmitCplt (line 3212) | static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMAMasterReceiveCplt (line 3263) | static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMASlaveReceiveCplt (line 3426) | static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMAMemTransmitCplt (line 3478) | static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMAMemReceiveCplt (line 3634) | static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
  function I2C_DMAError (line 3796) | static void I2C_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 3821) | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *h...
  function HAL_StatusTypeDef (line 3870) | static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDe...
  function HAL_StatusTypeDef (line 3907) | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDe...
  function HAL_StatusTypeDef (line 3942) | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDe...
  function HAL_StatusTypeDef (line 3989) | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c...
  function I2C_TransferConfig (line 4065) | static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAdd...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
  function HAL_StatusTypeDef (line 110) | HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c,...
  function HAL_StatusTypeDef (line 153) | HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c...
  function HAL_StatusTypeDef (line 203) | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
  function HAL_StatusTypeDef (line 242) | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2s.c
  function HAL_StatusTypeDef (line 213) | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
  function HAL_StatusTypeDef (line 329) | HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
  function __weak (line 363) | __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
  function __weak (line 376) | __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
  function HAL_StatusTypeDef (line 444) | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pD...
  function HAL_StatusTypeDef (line 534) | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pDa...
  function HAL_StatusTypeDef (line 612) | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t ...
  function HAL_StatusTypeDef (line 679) | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *...
  function HAL_StatusTypeDef (line 744) | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t...
  function HAL_StatusTypeDef (line 825) | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t ...
  function HAL_StatusTypeDef (line 907) | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
  function HAL_StatusTypeDef (line 935) | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
  function HAL_StatusTypeDef (line 970) | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
  function HAL_I2S_IRQHandler (line 1011) | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  function __weak (line 1065) | __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  function __weak (line 1078) | __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
  function __weak (line 1091) | __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  function __weak (line 1104) | __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
  function __weak (line 1117) | __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
  function HAL_I2S_StateTypeDef (line 1149) | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
  function HAL_I2S_ErrorTypeDef (line 1160) | HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
  function I2S_DMATxCplt (line 1182) | static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
  function I2S_DMATxHalfCplt (line 1203) | static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  function I2S_DMARxCplt (line 1216) | static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
  function I2S_DMARxHalfCplt (line 1236) | static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  function I2S_DMAError (line 1249) | static void I2S_DMAError(DMA_HandleTypeDef *hdma)
  function I2S_Transmit_IT (line 1271) | static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
  function I2S_Receive_IT (line 1292) | static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
  function HAL_StatusTypeDef (line 1318) | static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_irda.c
  function HAL_StatusTypeDef (line 238) | HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 287) | HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
  function __weak (line 319) | __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
  function __weak (line 331) | __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 404) | HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *...
  function HAL_StatusTypeDef (line 483) | HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *p...
  function HAL_StatusTypeDef (line 564) | HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_...
  function HAL_StatusTypeDef (line 614) | HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t...
  function HAL_StatusTypeDef (line 671) | HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8...
  function HAL_StatusTypeDef (line 734) | HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_...
  function HAL_IRDA_IRQHandler (line 791) | void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
  function IRDA_DMATransmitCplt (line 878) | static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  function IRDA_DMAReceiveCplt (line 896) | static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  function IRDA_DMAError (line 922) | static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
  function __weak (line 948) | __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
  function __weak (line 960) | __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
  function __weak (line 972) | __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 998) | static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 1044) | static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 1075) | static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
  function HAL_IRDA_StateTypeDef (line 1154) | HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
  function HAL_IRDA_GetError (line 1165) | uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 1187) | static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 1246) | static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
  function HAL_StatusTypeDef (line 1288) | static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef ...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_iwdg.c
  function HAL_StatusTypeDef (line 169) | HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
  function __weak (line 243) | __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
  function HAL_StatusTypeDef (line 275) | HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
  function HAL_StatusTypeDef (line 329) | HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
  function HAL_IWDG_StateTypeDef (line 394) | HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_msp_template.c
  function HAL_MspInit (line 77) | void HAL_MspInit(void)
  function HAL_MspDeInit (line 88) | void HAL_MspDeInit(void)
  function HAL_PPP_MspInit (line 99) | void HAL_PPP_MspInit(void)
  function HAL_PPP_MspDeInit (line 110) | void HAL_PPP_MspDeInit(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd.c
  function HAL_StatusTypeDef (line 138) | HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 213) | HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
  function __weak (line 239) | __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
  function __weak (line 251) | __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 282) | HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 295) | HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 327) | static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_IRQHandler (line 544) | void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
  function __weak (line 623) | __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_...
  function __weak (line 636) | __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t...
  function __weak (line 647) | __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 659) | __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 671) | __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 683) | __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 695) | __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 708) | __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, ui...
  function __weak (line 721) | __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uin...
  function __weak (line 733) | __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
  function __weak (line 745) | __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 775) | HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 791) | HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 808) | HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t ad...
  function HAL_StatusTypeDef (line 833) | HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_ad...
  function HAL_StatusTypeDef (line 937) | HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_a...
  function HAL_StatusTypeDef (line 1010) | HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep...
  function HAL_PCD_EP_GetRxCount (line 1063) | uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
  function HAL_StatusTypeDef (line 1075) | HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t e...
  function HAL_StatusTypeDef (line 1144) | HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t e...
  function HAL_StatusTypeDef (line 1190) | HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t e...
  function HAL_StatusTypeDef (line 1230) | HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_a...
  function HAL_StatusTypeDef (line 1240) | HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
  function HAL_StatusTypeDef (line 1251) | HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
  function PCD_WritePMA (line 1275) | void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABu...
  function PCD_ReadPMA (line 1301) | void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABuf...
  function PCD_StateTypeDef (line 1341) | PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pcd_ex.c
  function HAL_StatusTypeDef (line 96) | HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_ppp.c
  function HAL_StatusTypeDef (line 134) | HAL_StatusTypeDef HAL_PPP_Init(PPP_HandleTypeDef *hppp)
  function HAL_StatusTypeDef (line 164) | HAL_StatusTypeDef HAL_PPP_DeInit(PPP_HandleTypeDef *hppp)
  function __weak (line 186) | __weak void HAL_PPP_MspInit(PPP_HandleTypeDef *hppp)
  function __weak (line 198) | __weak void HAL_PPP_MspDeInit(PPP_HandleTypeDef *hppp)
  function HAL_StatusTypeDef (line 231) | HAL_StatusTypeDef HAL_PPP_Transmit(PPP_HandleTypeDef *hppp, uint8_t *pDa...
  function HAL_StatusTypeDef (line 253) | HAL_StatusTypeDef HAL_PPP_Receive(PPP_HandleTypeDef *hppp, uint8_t *pDat...
  function HAL_StatusTypeDef (line 275) | HAL_StatusTypeDef HAL_PPP_Transmit_IT(PPP_HandleTypeDef *hppp, uint8_t *...
  function HAL_StatusTypeDef (line 297) | HAL_StatusTypeDef HAL_PPP_Receive_IT(PPP_HandleTypeDef *hppp, uint8_t *p...
  function HAL_PPP_IRQHandler (line 317) | void HAL_PPP_IRQHandler(PPP_HandleTypeDef *hppp)
  function __weak (line 339) | __weak void HAL_PPP_TxCpltCallback(PPP_HandleTypeDef *hppp)
  function __weak (line 351) | __weak void HAL_PPP_RxCpltCallback(PPP_HandleTypeDef *hppp)
  function HAL_StatusTypeDef (line 365) | HAL_StatusTypeDef HAL_PPP_Transmit_DMA(PPP_HandleTypeDef *hppp, uint8_t ...
  function HAL_StatusTypeDef (line 393) | HAL_StatusTypeDef HAL_PPP_Receive_DMA(PPP_HandleTypeDef *hppp, uint8_t *...
  function HAL_StatusTypeDef (line 440) | HAL_StatusTypeDef HAL_PPP_Ctl(PPP_HandleTypeDef *hppp, PPP_ControlTypeDe...
  function HAL_PPP_StateTypeDef (line 480) | HAL_PPP_StateTypeDef HAL_PPP_GetState(PPP_HandleTypeDef *hppp)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
  function HAL_PWR_DeInit (line 93) | void HAL_PWR_DeInit(void)
  function HAL_PWR_EnableBkUpAccess (line 106) | void HAL_PWR_EnableBkUpAccess(void)
  function HAL_PWR_DisableBkUpAccess (line 118) | void HAL_PWR_DisableBkUpAccess(void)
  function HAL_PWR_EnableWakeUpPin (line 249) | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  function HAL_PWR_DisableWakeUpPin (line 263) | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  function HAL_PWR_EnterSLEEPMode (line 285) | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  function HAL_PWR_EnterSTOPMode (line 342) | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  function HAL_PWR_EnterSTANDBYMode (line 397) | void HAL_PWR_EnterSTANDBYMode(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
  function HAL_PWR_PVDConfig (line 126) | void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
  function HAL_PWR_EnablePVD (line 168) | void HAL_PWR_EnablePVD(void)
  function HAL_PWR_DisablePVD (line 177) | void HAL_PWR_DisablePVD(void)
  function HAL_PWR_PVD_IRQHandler (line 187) | void HAL_PWR_PVD_IRQHandler(void)
  function __weak (line 204) | __weak void HAL_PWR_PVDCallback(void)
  function HAL_PWR_EnableVddio2Monitor (line 226) | void HAL_PWR_EnableVddio2Monitor(void)
  function HAL_PWR_DisableVddio2Monitor (line 236) | void HAL_PWR_DisableVddio2Monitor(void)
  function HAL_PWR_Vddio2Monitor_IRQHandler (line 248) | void HAL_PWR_Vddio2Monitor_IRQHandler(void)
  function __weak (line 265) | __weak void HAL_PWR_Vddio2MonitorCallback(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
  function HAL_RCC_DeInit (line 213) | void HAL_RCC_DeInit(void)
  function __weak (line 248) | __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscI...
  function __weak (line 282) | __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_Cl...
  function HAL_RCC_MCOConfig (line 331) | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32...
  function HAL_RCC_EnableCSS (line 364) | void HAL_RCC_EnableCSS(void)
  function HAL_RCC_DisableCSS (line 373) | void HAL_RCC_DisableCSS(void)
  function __weak (line 409) | __weak uint32_t HAL_RCC_GetSysClockFreq(void)
  function HAL_RCC_GetHCLKFreq (line 429) | uint32_t HAL_RCC_GetHCLKFreq(void)
  function HAL_RCC_GetPCLK1Freq (line 441) | uint32_t HAL_RCC_GetPCLK1Freq(void)
  function HAL_RCC_GetOscConfig (line 454) | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  function HAL_RCC_GetClockConfig (line 546) | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint...
  function HAL_RCC_NMI_IRQHandler (line 569) | void HAL_RCC_NMI_IRQHandler(void)
  function __weak (line 586) | __weak void HAL_RCC_CCSCallback(void)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c
  function HAL_StatusTypeDef (line 166) | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
  function HAL_StatusTypeDef (line 633) | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitSt...
  function HAL_RCC_GetSysClockFreq (line 922) | uint32_t HAL_RCC_GetSysClockFreq(void)
  function HAL_StatusTypeDef (line 999) | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *P...
  function HAL_RCCEx_GetPeriphCLKConfig (line 1144) | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
  function HAL_RCCEx_CRSConfig (line 1198) | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
  function HAL_RCCEx_CRSSoftwareSynchronizationGenerate (line 1260) | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
  function HAL_RCCEx_CRSGetSynchronizationInfo (line 1271) | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSyn...
  function RCC_CRSStatusTypeDef (line 1306) | RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc.c
  function HAL_StatusTypeDef (line 203) | HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
  function HAL_StatusTypeDef (line 276) | HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
  function __weak (line 351) | __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
  function __weak (line 363) | __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
  function HAL_StatusTypeDef (line 398) | HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeD...
  function HAL_StatusTypeDef (line 524) | HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeD...
  function HAL_StatusTypeDef (line 565) | HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeD...
  function HAL_StatusTypeDef (line 673) | HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeD...
  function HAL_StatusTypeDef (line 727) | HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTyp...
  function HAL_StatusTypeDef (line 876) | HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_Alarm...
  function HAL_StatusTypeDef (line 1023) | HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint3...
  function HAL_StatusTypeDef (line 1085) | HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTyp...
  function HAL_RTC_AlarmIRQHandler (line 1124) | void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
  function __weak (line 1151) | __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
  function HAL_StatusTypeDef (line 1164) | HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, ui...
  function HAL_StatusTypeDef (line 1225) | HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
  function HAL_RTCStateTypeDef (line 1269) | HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
  function HAL_StatusTypeDef (line 1295) | HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
  function RTC_ByteToBcd2 (line 1326) | uint8_t RTC_ByteToBcd2(uint8_t Value)
  function RTC_Bcd2ToByte (line 1344) | uint8_t RTC_Bcd2ToByte(uint8_t Value)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rtc_ex.c
  function HAL_StatusTypeDef (line 149) | HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32...
  function HAL_StatusTypeDef (line 203) | HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uin...
  function HAL_StatusTypeDef (line 253) | HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
  function HAL_StatusTypeDef (line 296) | HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_Ti...
  function HAL_StatusTypeDef (line 347) | HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_Tampe...
  function HAL_StatusTypeDef (line 395) | HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_Ta...
  function HAL_StatusTypeDef (line 452) | HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, ui...
  function HAL_RTCEx_TamperTimeStampIRQHandler (line 477) | void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
  function __weak (line 548) | __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
  function __weak (line 560) | __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
  function __weak (line 572) | __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
  function __weak (line 585) | __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
  function HAL_StatusTypeDef (line 599) | HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrt...
  function HAL_StatusTypeDef (line 641) | HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc,...
  function HAL_StatusTypeDef (line 676) | HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc,...
  function HAL_StatusTypeDef (line 712) | HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc,...
  function HAL_StatusTypeDef (line 768) | HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint...
  function HAL_StatusTypeDef (line 835) | HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, u...
  function HAL_RTCEx_DeactivateWakeUpTimer (line 908) | uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
  function HAL_RTCEx_GetWakeUpTimer (line 961) | uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
  function HAL_RTCEx_WakeUpTimerIRQHandler (line 972) | void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
  function __weak (line 999) | __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
  function HAL_StatusTypeDef (line 1012) | HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *h...
  function HAL_RTCEx_BKUPWrite (line 1082) | void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegiste...
  function HAL_RTCEx_BKUPRead (line 1104) | uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegi...
  function HAL_StatusTypeDef (line 1138) | HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint...
  function HAL_StatusTypeDef (line 1206) | HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uin...
  function HAL_StatusTypeDef (line 1299) | HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc...
  function HAL_StatusTypeDef (line 1337) | HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDe...
  function HAL_StatusTypeDef (line 1366) | HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
  function HAL_StatusTypeDef (line 1415) | HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
  function HAL_StatusTypeDef (line 1466) | HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
  function HAL_StatusTypeDef (line 1498) | HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard.c
  function HAL_StatusTypeDef (line 258) | HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
  function HAL_StatusTypeDef (line 313) | HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
  function __weak (line 352) | __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
  function __weak (line 364) | __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
  function HAL_StatusTypeDef (line 435) | HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmart...
  function HAL_StatusTypeDef (line 501) | HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartc...
  function HAL_StatusTypeDef (line 565) | HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsm...
  function HAL_StatusTypeDef (line 616) | HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsma...
  function HAL_StatusTypeDef (line 670) | HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hs...
  function HAL_StatusTypeDef (line 733) | HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsm...
  function HAL_SMARTCARD_IRQHandler (line 791) | void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
  function __weak (line 881) | __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmart...
  function __weak (line 893) | __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmart...
  function __weak (line 905) | __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartc...
  function HAL_SMARTCARD_StateTypeDef (line 942) | HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDe...
  function HAL_SMARTCARD_GetError (line 953) | uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
  function HAL_StatusTypeDef (line 978) | static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_Hand...
  function SMARTCARD_DMATransmitCplt (line 1042) | static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  function SMARTCARD_DMAReceiveCplt (line 1061) | static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  function SMARTCARD_DMAError (line 1089) | static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 1106) | static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *...
  function HAL_StatusTypeDef (line 1142) | static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDe...
  function HAL_StatusTypeDef (line 1173) | static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *h...
  function HAL_StatusTypeDef (line 1218) | static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hs...
  function HAL_StatusTypeDef (line 1320) | static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDe...
  function SMARTCARD_AdvFeatureConfig (line 1359) | static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smartcard_ex.c
  function HAL_SMARTCARDEx_BlockLength_Config (line 110) | void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartc...
  function HAL_SMARTCARDEx_TimeOut_Config (line 122) | void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard,...
  function HAL_StatusTypeDef (line 133) | HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_Handle...
  function HAL_StatusTypeDef (line 157) | HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_Handl...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_smbus.c
  function HAL_StatusTypeDef (line 237) | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 336) | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 371) | __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 384) | __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 448) | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmb...
  function HAL_StatusTypeDef (line 536) | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbu...
  function HAL_StatusTypeDef (line 615) | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus,...
  function HAL_StatusTypeDef (line 676) | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbu...
  function HAL_StatusTypeDef (line 767) | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus...
  function HAL_StatusTypeDef (line 841) | HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 857) | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 881) | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 900) | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 921) | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, u...
  function HAL_SMBUS_EV_IRQHandler (line 1035) | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
  function HAL_SMBUS_ER_IRQHandler (line 1090) | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1173) | __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1186) | __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1198) | __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1211) | __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1226) | __weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uin...
  function __weak (line 1239) | __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
  function __weak (line 1252) | __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
  function HAL_SMBUS_StateTypeDef (line 1283) | HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
  function HAL_SMBUS_GetError (line 1294) | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 1318) | static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 1515) | static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
  function HAL_StatusTypeDef (line 1719) | static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, u...
  function HAL_StatusTypeDef (line 1761) | static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, ...
  function HAL_StatusTypeDef (line 1837) | static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDe...
  function SMBUS_TransferConfig (line 1905) | static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t ...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c
  type __SPI_HandleTypeDef (line 149) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 150) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 151) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 152) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 153) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 154) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 155) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 156) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 157) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 158) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 159) | struct __SPI_HandleTypeDef
  type __SPI_HandleTypeDef (line 160) | struct __SPI_HandleTypeDef
  function HAL_StatusTypeDef (line 217) | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
  function HAL_StatusTypeDef (line 317) | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
  function __weak (line 349) | __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
  function __weak (line 361) | __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
  function HAL_StatusTypeDef (line 431) | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pDa...
  function HAL_StatusTypeDef (line 562) | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pDat...
  function HAL_StatusTypeDef (line 749) | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8...
  function HAL_StatusTypeDef (line 971) | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *...
  function HAL_StatusTypeDef (line 1050) | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *p...
  function HAL_StatusTypeDef (line 1155) | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, ui...
  function HAL_StatusTypeDef (line 1251) | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t ...
  function HAL_StatusTypeDef (line 1338) | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *...
  function HAL_StatusTypeDef (line 1437) | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, u...
  function HAL_SPI_IRQHandler (line 1575) | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
  function HAL_SPI_DMATransmitCplt (line 1635) | static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  function HAL_SPI_DMAReceiveCplt (line 1679) | static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  function HAL_SPI_DMATransmitReceiveCplt (line 1749) | static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
  function HAL_SPI_DMAError (line 1815) | static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma)
  function __weak (line 1830) | __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
  function __weak (line 1842) | __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
  function __weak (line 1854) | __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
  function __weak (line 1866) | __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
  function HAL_SPI_StateTypeDef (line 1898) | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
  function SPI_2linesRxISR_8BIT (line 1919) | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_2linesRxISR_8BITCRC (line 1963) | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  function SPI_2linesTxISR_8BIT (line 1987) | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_2linesRxISR_16BIT (line 2024) | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_2linesRxISR_16BITCRC (line 2053) | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  function SPI_2linesTxISR_16BIT (line 2069) | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_RxISR_8BITCRC (line 2097) | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
  function SPI_RxISR_8BIT (line 2113) | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_RxISR_16BITCRC (line 2139) | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
  function SPI_RxISR_16BIT (line 2155) | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_TxISR_8BIT (line 2182) | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
  function SPI_TxISR_16BIT (line 2202) | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
  function HAL_StatusTypeDef (line 2228) | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef...
  function HAL_StatusTypeDef (line 2278) | static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef...
  function HAL_StatusTypeDef (line 2330) | static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  ...
  function HAL_StatusTypeDef (line 2356) | static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi,...
  function SPI_CloseRxTx_ISR (line 2381) | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
  function SPI_CloseRx_ISR (line 2424) | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
  function SPI_CloseTx_ISR (line 2458) | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c
  function HAL_StatusTypeDef (line 207) | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 243) | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 270) | __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 282) | __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 295) | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 318) | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 341) | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 361) | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 382) | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32...
  function HAL_StatusTypeDef (line 426) | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 475) | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
  function HAL_StatusTypeDef (line 511) | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 538) | __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 550) | __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 568) | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Cha...
  function HAL_StatusTypeDef (line 600) | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Chan...
  function HAL_StatusTypeDef (line 632) | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t ...
  function HAL_StatusTypeDef (line 698) | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t C...
  function HAL_StatusTypeDef (line 766) | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 883) | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t ...
  function HAL_StatusTypeDef (line 972) | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 1008) | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 1035) | __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 1047) | __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 1065) | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Ch...
  function HAL_StatusTypeDef (line 1097) | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Cha...
  function HAL_StatusTypeDef (line 1132) | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 1198) | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 1266) | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 1383) | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 1472) | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 1508) | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 1535) | __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 1547) | __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 1565) | HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Ch...
  function HAL_StatusTypeDef (line 1591) | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Chan...
  function HAL_StatusTypeDef (line 1617) | HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 1676) | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t C...
  function HAL_StatusTypeDef (line 1738) | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 1851) | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t ...
  function HAL_StatusTypeDef (line 1938) | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 1981) | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 2008) | __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 2020) | __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 2036) | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32...
  function HAL_StatusTypeDef (line 2069) | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 2102) | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uin...
  function HAL_StatusTypeDef (line 2141) | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint...
  function HAL_StatusTypeDef (line 2201) | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Enc...
  function HAL_StatusTypeDef (line 2288) | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 2315) | __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 2327) | __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 2343) | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 2384) | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 2427) | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint...
  function HAL_StatusTypeDef (line 2474) | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint3...
  function HAL_StatusTypeDef (line 2527) | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uin...
  function HAL_StatusTypeDef (line 2643) | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint...
  function HAL_TIM_IRQHandler (line 2705) | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 2868) | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_...
  function HAL_StatusTypeDef (line 2940) | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_...
  function HAL_StatusTypeDef (line 3036) | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM...
  function HAL_StatusTypeDef (line 3139) | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim...
  function HAL_StatusTypeDef (line 3275) | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, u...
  function HAL_StatusTypeDef (line 3406) | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, ui...
  function HAL_StatusTypeDef (line 3498) | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, ui...
  function HAL_StatusTypeDef (line 3630) | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uin...
  function HAL_StatusTypeDef (line 3702) | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 3739) | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_...
  function HAL_StatusTypeDef (line 3864) | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM...
  function HAL_StatusTypeDef (line 4019) | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32...
  function HAL_StatusTypeDef (line 4051) | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *...
  function HAL_StatusTypeDef (line 4086) | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDe...
  function HAL_TIM_ReadCapturedValue (line 4124) | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Cha...
  function __weak (line 4211) | __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  function __weak (line 4223) | __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  function __weak (line 4234) | __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  function __weak (line 4246) | __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  function __weak (line 4258) | __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  function __weak (line 4270) | __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4301) | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4311) | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4321) | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4331) | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4341) | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_StateTypeDef (line 4351) | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
  function HAL_TIM_DMAError (line 4373) | void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_TIM_DMADelayPulseCplt (line 4387) | void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  function HAL_TIM_DMACaptureCplt (line 4419) | void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  function TIM_DMAPeriodElapsedCplt (line 4452) | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  function TIM_DMATriggerCplt (line 4466) | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  function TIM_Base_SetConfig (line 4481) | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  function TIM_OC1_SetConfig (line 4526) | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_...
  function TIM_OC2_SetConfig (line 4600) | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  function TIM_OC3_SetConfig (line 4678) | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_...
  function TIM_OC4_SetConfig (line 4754) | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_...
  function TIM_SlaveTimer_SetConfig (line 4806) | void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  function TIM_TI1_SetConfig (line 4951) | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint3...
  function TIM_TI1_ConfigInputStage (line 4998) | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICP...
  function TIM_TI2_SetConfig (line 5041) | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity...
  function TIM_TI2_ConfigInputStage (line 5081) | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICP...
  function TIM_TI3_SetConfig (line 5124) | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity...
  function TIM_TI4_SetConfig (line 5172) | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity...
  function TIM_ITRx_SetConfig (line 5215) | static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerS...
  function TIM_ETR_SetConfig (line 5245) | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPres...
  function TIM_CCxChannelCmd (line 5275) | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c
  function HAL_StatusTypeDef (line 160) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM...
  function HAL_StatusTypeDef (line 232) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
  function __weak (line 259) | __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
  function __weak (line 271) | __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 283) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 304) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 325) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 349) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 375) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim...
  function HAL_StatusTypeDef (line 422) | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
  function HAL_StatusTypeDef (line 478) | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t ...
  function HAL_StatusTypeDef (line 508) | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t C...
  function HAL_StatusTypeDef (line 538) | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32...
  function HAL_StatusTypeDef (line 605) | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_...
  function HAL_StatusTypeDef (line 680) | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint3...
  function HAL_StatusTypeDef (line 795) | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32...
  function HAL_StatusTypeDef (line 895) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t...
  function HAL_StatusTypeDef (line 924) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t ...
  function HAL_StatusTypeDef (line 954) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint3...
  function HAL_StatusTypeDef (line 1021) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint3...
  function HAL_StatusTypeDef (line 1096) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint...
  function HAL_StatusTypeDef (line 1211) | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint3...
  function HAL_StatusTypeDef (line 1298) | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uin...
  function HAL_StatusTypeDef (line 1323) | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint...
  function HAL_StatusTypeDef (line 1352) | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, ...
  function HAL_StatusTypeDef (line 1383) | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, u...
  function HAL_StatusTypeDef (line 1451) | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *ht...
  function HAL_StatusTypeDef (line 1500) | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef ...
  function HAL_StatusTypeDef (line 1553) | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef...
  function HAL_StatusTypeDef (line 1597) | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDe...
  function HAL_StatusTypeDef (line 1633) | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
  function HAL_StatusTypeDef (line 1680) | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_...
  function __weak (line 1723) | __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
  function __weak (line 1735) | __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  function HAL_TIMEx_DMACommutationCplt (line 1747) | void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
  function HAL_TIM_StateTypeDef (line 1780) | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
  function TIM_CCxNChannelCmd (line 1809) | static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tsc.c
  function HAL_StatusTypeDef (line 161) | HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 244) | HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
  function __weak (line 277) | __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
  function __weak (line 290) | __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 325) | HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 361) | HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 408) | HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 438) | HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
  function TSC_GroupStatusTypeDef (line 472) | TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, u...
  function HAL_TSC_GroupGetValue (line 489) | uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
  function HAL_StatusTypeDef (line 524) | HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfig...
  function HAL_StatusTypeDef (line 561) | HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t ...
  function HAL_TSC_StateTypeDef (line 612) | HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
  function HAL_StatusTypeDef (line 648) | HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
  function HAL_TSC_IRQHandler (line 674) | void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
  function __weak (line 720) | __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
  function __weak (line 733) | __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
  function TSC_extract_groups (line 757) | static uint32_t TSC_extract_groups(uint32_t iomask)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c
  function HAL_StatusTypeDef (line 264) | HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 324) | HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 392) | HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uin...
  function HAL_StatusTypeDef (line 452) | HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
  function __weak (line 489) | __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
  function __weak (line 501) | __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 577) | HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *...
  function HAL_StatusTypeDef (line 655) | HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *p...
  function HAL_StatusTypeDef (line 735) | HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_...
  function HAL_StatusTypeDef (line 786) | HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t...
  function HAL_StatusTypeDef (line 843) | HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8...
  function HAL_StatusTypeDef (line 909) | HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_...
  function HAL_StatusTypeDef (line 970) | HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1004) | HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1043) | HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
  function __weak (line 1079) | __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  function __weak (line 1091) | __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
  function __weak (line 1103) | __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  function __weak (line 1115) | __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  function __weak (line 1127) | __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1170) | HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *...
  function HAL_StatusTypeDef (line 1191) | HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef ...
  function HAL_MultiProcessor_EnterMuteMode (line 1212) | void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1223) | HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *h...
  function HAL_StatusTypeDef (line 1246) | HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
  function HAL_UART_StateTypeDef (line 1277) | HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
  function HAL_UART_GetError (line 1288) | uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1312) | HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1360) | HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1417) | HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 1460) | HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,...
  function UART_DMATransmitCplt (line 1523) | static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  function UART_DMATxHalfCplt (line 1560) | static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  function UART_DMAReceiveCplt (line 1572) | static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  function UART_DMARxHalfCplt (line 1598) | static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  function UART_DMAError (line 1610) | static void UART_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 1625) | HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
  function UART_AdvFeatureConfig (line 1729) | void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c
  function HAL_UART_IRQHandler (line 123) | void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
  function __weak (line 210) | __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 296) | HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t U...
  function HAL_StatusTypeDef (line 369) | HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t Break...
  function HAL_StatusTypeDef (line 461) | HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeD...
  function HAL_StatusTypeDef (line 507) | HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 533) | HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
  function HAL_StatusTypeDef (line 570) | HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleType...
  function UART_Wakeup_AddressConfig (line 604) | static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_Wa...
  function HAL_StatusTypeDef (line 636) | static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_usart.c
  function HAL_StatusTypeDef (line 253) | HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 299) | HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
  function __weak (line 333) | __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
  function __weak (line 345) | __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 423) | HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_...
  function HAL_StatusTypeDef (line 490) | HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t...
  function HAL_StatusTypeDef (line 569) | HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart,...
  function HAL_StatusTypeDef (line 655) | HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uin...
  function HAL_StatusTypeDef (line 702) | HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint...
  function HAL_StatusTypeDef (line 761) | HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husa...
  function HAL_StatusTypeDef (line 815) | HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, ui...
  function HAL_StatusTypeDef (line 873) | HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uin...
  function HAL_StatusTypeDef (line 942) | HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *hus...
  function HAL_StatusTypeDef (line 1013) | HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1047) | HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1088) | HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
  function HAL_USART_IRQHandler (line 1124) | void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
  function __weak (line 1209) | __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
  function __weak (line 1221) | __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
  function __weak (line 1233) | __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
  function __weak (line 1245) | __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
  function __weak (line 1257) | __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
  function __weak (line 1269) | __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
  function HAL_USART_StateTypeDef (line 1302) | HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
  function HAL_USART_GetError (line 1313) | uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1336) | static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1406) | static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1449) | static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDe...
  function USART_DMATransmitCplt (line 1513) | static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
  function USART_DMATxHalfCplt (line 1551) | static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  function USART_DMAReceiveCplt (line 1563) | static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
  function USART_DMARxHalfCplt (line 1586) | static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  function USART_DMAError (line 1598) | static void USART_DMAError(DMA_HandleTypeDef *hdma)
  function HAL_StatusTypeDef (line 1618) | static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1666) | static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1689) | static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
  function HAL_StatusTypeDef (line 1742) | static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *h...

FILE: Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_wwdg.c
  function HAL_StatusTypeDef (line 153) | HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
  function HAL_StatusTypeDef (line 195) | HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
  function __weak (line 231) | __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
  function __weak (line 244) | __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
  function HAL_StatusTypeDef (line 278) | HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
  function HAL_StatusTypeDef (line 305) | HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
  function HAL_StatusTypeDef (line 330) | HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t C...
  function HAL_WWDG_IRQHandler (line 367) | void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
  function __weak (line 392) | __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
  function HAL_WWDG_StateTypeDef (line 424) | HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)

FILE: Inc/can.h
  type can_bitrate (line 4) | enum can_bitrate {
  type can_bus_state (line 16) | enum can_bus_state {
  type can_bitrate (line 24) | enum can_bitrate

FILE: Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h
  type USBD_CDC_LineCodingTypeDef (line 90) | typedef struct
  type USBD_CDC_ItfTypeDef (line 98) | typedef struct _USBD_CDC_Itf
  type USBD_CDC_HandleTypeDef (line 108) | typedef struct

FILE: Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c
  function USBD_CDC_Init (line 475) | static uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev,
  function USBD_CDC_DeInit (line 563) | static uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,
  function USBD_CDC_Setup (line 599) | static uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev,
  function USBD_CDC_DataIn (line 650) | static uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)
  function USBD_CDC_DataOut (line 674) | static uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)
  function USBD_CDC_EP0_RxReady (line 704) | static uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)
  function USBD_CDC_RegisterInterface (line 776) | uint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev,
  function USBD_CDC_SetTxBuffer (line 796) | uint8_t  USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev,
  function USBD_CDC_SetRxBuffer (line 815) | uint8_t  USBD_CDC_SetRxBuffer  (USBD_HandleTypeDef   *pdev,
  function USBD_CDC_TransmitPacket (line 832) | uint8_t  USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
  function USBD_CDC_ReceivePacket (line 869) | uint8_t  USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)

FILE: Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c
  function TEMPLATE_Init (line 99) | static int8_t TEMPLATE_Init(void)
  function TEMPLATE_DeInit (line 113) | static int8_t TEMPLATE_DeInit(void)
  function TEMPLATE_Control (line 130) | static int8_t TEMPLATE_Control  (uint8_t cmd, uint8_t* pbuf, uint16_t le...
  function TEMPLATE_Receive (line 206) | static int8_t TEMPLATE_Receive (uint8_t* Buf, uint32_t *Len)

FILE: Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
  type USBD_SetupReqTypedef (line 144) | typedef  struct  usb_setup_req
  type _USBD_HandleTypeDef (line 154) | struct _USBD_HandleTypeDef
  type USBD_ClassTypeDef (line 156) | typedef struct _Device_cb
  type USBD_SpeedTypeDef (line 182) | typedef enum
  type USBD_StatusTypeDef (line 190) | typedef enum {
  type USBD_DescriptorsTypeDef (line 197) | typedef struct
  type USBD_EndpointTypeDef (line 209) | typedef struct
  type USBD_HandleTypeDef (line 218) | typedef struct _USBD_HandleTypeDef

FILE: Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
  function USBD_StatusTypeDef (line 43) | USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 53) | USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 63) | USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 73) | USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 86) | USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
  function USBD_StatusTypeDef (line 100) | USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_...
  function USBD_StatusTypeDef (line 111) | USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_...
  function USBD_StatusTypeDef (line 122) | USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_...
  function USBD_StatusTypeDef (line 133) | USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_...
  function USBD_LL_IsStallEP (line 144) | uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  function USBD_StatusTypeDef (line 155) | USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8...
  function USBD_StatusTypeDef (line 168) | USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
  function USBD_StatusTypeDef (line 184) | USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
  function USBD_LL_GetRxDataSize (line 198) | uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  function USBD_LL_Delay (line 208) | void USBD_LL_Delay(uint32_t Delay)

FILE: Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
  function USBD_StatusTypeDef (line 96) | USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsT...
  function USBD_StatusTypeDef (line 132) | USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 157) | USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_Cl...
  function USBD_StatusTypeDef (line 181) | USBD_StatusTypeDef  USBD_Start  (USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 196) | USBD_StatusTypeDef  USBD_Stop   (USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 213) | USBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 227) | USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_...
  function USBD_StatusTypeDef (line 249) | USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_...
  function USBD_StatusTypeDef (line 263) | USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t ...
  function USBD_StatusTypeDef (line 299) | USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8...
  function USBD_StatusTypeDef (line 343) | USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t...
  function USBD_StatusTypeDef (line 403) | USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 439) | USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_Spee...
  function USBD_StatusTypeDef (line 452) | USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 466) | USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 479) | USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 497) | USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, ui...
  function USBD_StatusTypeDef (line 508) | USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, u...
  function USBD_StatusTypeDef (line 519) | USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 530) | USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev)

FILE: Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
  function USBD_StatusTypeDef (line 119) | USBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_Setu...
  function USBD_StatusTypeDef (line 170) | USBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_Setu...
  function USBD_StatusTypeDef (line 207) | USBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_Setup...
  function USBD_GetDescriptor (line 323) | static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
  function USBD_SetAddress (line 436) | static void USBD_SetAddress(USBD_HandleTypeDef *pdev ,
  function USBD_SetConfig (line 478) | static void USBD_SetConfig(USBD_HandleTypeDef *pdev ,
  function USBD_GetConfig (line 555) | static void USBD_GetConfig(USBD_HandleTypeDef *pdev ,
  function USBD_GetStatus (line 595) | static void USBD_GetStatus(USBD_HandleTypeDef *pdev ,
  function USBD_SetFeature (line 635) | static void USBD_SetFeature(USBD_HandleTypeDef *pdev ,
  function USBD_ClrFeature (line 656) | static void USBD_ClrFeature(USBD_HandleTypeDef *pdev ,
  function USBD_ParseSetupRequest (line 685) | void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
  function USBD_CtlError (line 703) | void USBD_CtlError( USBD_HandleTypeDef *pdev ,
  function USBD_GetString (line 719) | void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
  function USBD_GetLen (line 743) | static uint8_t USBD_GetLen(uint8_t *buf)

FILE: Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
  function USBD_StatusTypeDef (line 95) | USBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev,
  function USBD_StatusTypeDef (line 117) | USBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev,
  function USBD_StatusTypeDef (line 135) | USBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,
  function USBD_StatusTypeDef (line 160) | USBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev,
  function USBD_StatusTypeDef (line 177) | USBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)
  function USBD_StatusTypeDef (line 195) | USBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)
  function USBD_GetRxCount (line 217) | uint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , uint8_t ep_addr)

FILE: Src/can.c
  type can_bus_state (line 8) | enum can_bus_state
  function can_init (line 10) | void can_init(void) {
  function can_set_filter (line 17) | void can_set_filter(uint32_t id, uint32_t mask) {
  function can_enable (line 45) | void can_enable(void) {
  function can_disable (line 65) | void can_disable(void) {
  function can_set_bitrate (line 74) | void can_set_bitrate(enum can_bitrate bitrate) {
  function can_set_silent (line 111) | void can_set_silent(uint8_t silent) {
  function can_tx (line 123) | uint32_t can_tx(CanTxMsgTypeDef *tx_msg, uint32_t timeout) {
  function can_rx (line 134) | uint32_t can_rx(CanRxMsgTypeDef *rx_msg, uint32_t timeout) {
  function is_can_msg_pending (line 145) | uint8_t is_can_msg_pending(uint8_t fifo) {

FILE: Src/led.c
  function led_on (line 12) | void led_on(void)
  function led_process (line 25) | void led_process(void)

FILE: Src/main.c
  function main (line 71) | int main(void)
  function SystemClock_Config (line 132) | void SystemClock_Config(void)
  function MX_GPIO_Init (line 201) | void MX_GPIO_Init(void)
  function led_init (line 211) | static void led_init() {
  function assert_failed (line 231) | void assert_failed(uint8_t* file, uint32_t line)

FILE: Src/slcan.c
  function slcan_parse_frame (line 8) | int8_t slcan_parse_frame(uint8_t *buf, CanRxMsgTypeDef *frame) {
  function slcan_parse_str (line 69) | int8_t slcan_parse_str(uint8_t *buf, uint8_t len) {

FILE: Src/stm32f0xx_hal_msp.c
  function HAL_MspInit (line 45) | void HAL_MspInit(void)
  function HAL_CAN_MspInit (line 60) | void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
  function HAL_CAN_MspDeInit (line 90) | void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)

FILE: Src/stm32f0xx_it.c
  function USB_IRQHandler (line 52) | void USB_IRQHandler(void)
  function SysTick_Handler (line 66) | void SysTick_Handler(void)

FILE: Src/system_stm32f0xx.c
  function SystemInit (line 159) | void SystemInit(void)
  function SystemCoreClockUpdate (line 240) | void SystemCoreClockUpdate (void)

FILE: Src/usb_device.c
  function MX_USB_DEVICE_Init (line 48) | void MX_USB_DEVICE_Init(void)

FILE: Src/usbd_cdc_if.c
  function CDC_Init_FS (line 128) | static int8_t CDC_Init_FS(void)
  function CDC_DeInit_FS (line 144) | static int8_t CDC_DeInit_FS(void)
  function CDC_Control_FS (line 159) | static int8_t CDC_Control_FS  (uint8_t cmd, uint8_t* pbuf, uint16_t length)
  function CDC_Receive_FS (line 250) | static int8_t CDC_Receive_FS (uint8_t* Buf, uint32_t *Len)
  function CDC_Transmit_FS (line 283) | uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)

FILE: Src/usbd_conf.c
  function HAL_PCD_MspInit (line 63) | void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
  function HAL_PCD_MspDeInit (line 80) | void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
  function HAL_PCD_SetupStageCallback (line 104) | void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_DataOutStageCallback (line 115) | void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  function HAL_PCD_DataInStageCallback (line 126) | void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
  function HAL_PCD_SOFCallback (line 136) | void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_ResetCallback (line 146) | void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_SuspendCallback (line 172) | void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_ResumeCallback (line 190) | void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_ISOOUTIncompleteCallback (line 211) | void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t e...
  function HAL_PCD_ISOINIncompleteCallback (line 222) | void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t ep...
  function HAL_PCD_ConnectCallback (line 232) | void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
  function HAL_PCD_DisconnectCallback (line 242) | void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
  function USBD_StatusTypeDef (line 255) | USBD_StatusTypeDef  USBD_LL_Init (USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 284) | USBD_StatusTypeDef  USBD_LL_DeInit (USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 295) | USBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 306) | USBD_StatusTypeDef  USBD_LL_Stop (USBD_HandleTypeDef *pdev)
  function USBD_StatusTypeDef (line 320) | USBD_StatusTypeDef  USBD_LL_OpenEP  (USBD_HandleTypeDef *pdev,
  function USBD_StatusTypeDef (line 340) | USBD_StatusTypeDef  USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t e...
  function USBD_StatusTypeDef (line 353) | USBD_StatusTypeDef  USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t e...
  function USBD_StatusTypeDef (line 366) | USBD_StatusTypeDef  USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t e...
  function USBD_StatusTypeDef (line 379) | USBD_StatusTypeDef  USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint...
  function USBD_LL_IsStallEP (line 392) | uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
  function USBD_StatusTypeDef (line 411) | USBD_StatusTypeDef  USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uin...
  function USBD_StatusTypeDef (line 426) | USBD_StatusTypeDef  USBD_LL_Transmit (USBD_HandleTypeDef *pdev,
  function USBD_StatusTypeDef (line 444) | USBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
  function USBD_LL_GetRxDataSize (line 460) | uint32_t USBD_LL_GetRxDataSize  (USBD_HandleTypeDef *pdev, uint8_t  ep_a...
  function USBD_LL_Delay (line 470) | void  USBD_LL_Delay (uint32_t Delay)
  function USBD_static_free (line 491) | void USBD_static_free(void *p)
  function SystemClockConfig_Resume (line 503) | static void SystemClockConfig_Resume(void)
  function HAL_PCDEx_SetConnectionState (line 515) | void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)

FILE: Src/usbd_desc.c
  function IntToAscii (line 232) | static void IntToAscii (uint32_t value , uint8_t *pbuf , uint8_t len)
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    "path": "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c",
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    "path": "Inc/can.h",
    "chars": 681,
    "preview": "#ifndef _CAN_H\n#define _CAN_H\n\nenum can_bitrate {\n    CAN_BITRATE_10K,\n    CAN_BITRATE_20K,\n    CAN_BITRATE_50K,\n    CAN"
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  {
    "path": "Inc/led.h",
    "chars": 108,
    "preview": "#ifndef _LED_H\n#define _LED_H\n\n\n#define LED_DURATION 50\n\nvoid led_on(void);\nvoid led_process(void);\n\n#endif\n"
  },
  {
    "path": "Inc/slcan.h",
    "chars": 359,
    "preview": "#ifndef _SLCAN_H\n#define _SLCAN_H\n\nint8_t slcan_parse_frame(uint8_t *buf, CanRxMsgTypeDef *frame);\nint8_t slcan_parse_st"
  },
  {
    "path": "Inc/stm32f0xx_hal_conf.h",
    "chars": 11150,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f0xx_hal_conf.h"
  },
  {
    "path": "Inc/stm32f0xx_it.h",
    "chars": 2810,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f0xx_it.h\r\n  * "
  },
  {
    "path": "Inc/usb_device.h",
    "chars": 2626,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : USB_DEVICE\r"
  },
  {
    "path": "Inc/usbd_cdc_if.h",
    "chars": 3002,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : usbd_cdc_if"
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    "path": "Inc/usbd_conf.h",
    "chars": 4720,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : usbd_conf.h"
  },
  {
    "path": "Inc/usbd_desc.h",
    "chars": 3015,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : usbd_desc.h"
  },
  {
    "path": "LICENSE.md",
    "chars": 1384,
    "preview": "# Licenses\n\n## CANtact Sources\n\nThe MIT License (MIT)\n\nCopyright (c) 2015 Eric Evenchick\n\nPermission is hereby granted, "
  },
  {
    "path": "Makefile",
    "chars": 5294,
    "preview": "# STM32F0xx Makefile\n# #####################################\n#\n# Part of the uCtools project\n# uctools.github.com\n#\n####"
  },
  {
    "path": "Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h",
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    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.h\r\n  * @aut"
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h",
    "chars": 1894,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc_if_template"
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c",
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c",
    "chars": 5656,
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h",
    "chars": 4061,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_conf_template.h"
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h",
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h",
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    "chars": 11300,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_def.h\r\n  * @aut"
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    "path": "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h",
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  {
    "path": "README.md",
    "chars": 1257,
    "preview": "# CANtact Firmware\n\n[![Build Status](https://travis-ci.org/linklayer/cantact-fw.svg?branch=master)](https://travis-ci.or"
  },
  {
    "path": "STM32F042C6_FLASH.ld",
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    "preview": "/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x200017FF;    /* end of "
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    "chars": 3611,
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  },
  {
    "path": "Src/led.c",
    "chars": 777,
    "preview": "//\n// LED: Handles blinking of status light\n//\n\n#include \"stm32f0xx_hal.h\"\n#include \"led.h\"\n\nstatic uint32_t led_laston "
  },
  {
    "path": "Src/main.c",
    "chars": 7799,
    "preview": "/**\r\n******************************************************************************\r\n* File Name          : main.c\r\n* Da"
  },
  {
    "path": "Src/slcan.c",
    "chars": 5071,
    "preview": "#include \"stm32f0xx_hal.h\"\n#include \"can.h\"\n#include \"slcan.h\"\n\nstatic uint32_t current_filter_id = 0;\nstatic uint32_t c"
  },
  {
    "path": "Src/startup_stm32f042x6.s",
    "chars": 10801,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file      startup_stm32f042x"
  },
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    "path": "Src/stm32f0xx_hal_msp.c",
    "chars": 3951,
    "preview": "/**\r\n  ******************************************************************************\r\n  * File Name          : stm32f0x"
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    "path": "Src/stm32f0xx_it.c",
    "chars": 3305,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f0xx_it.c\r\n  * "
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    "path": "Src/system_stm32f0xx.c",
    "chars": 11927,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32f0xx.c\r\n"
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    "path": "Src/usbd_cdc_if.c",
    "chars": 9707,
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  },
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    "path": "Src/usbd_conf.c",
    "chars": 14747,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : usbd_conf.c"
  },
  {
    "path": "Src/usbd_desc.c",
    "chars": 9946,
    "preview": "/**\r\n  ******************************************************************************\r\n  * @file           : usbd_desc.c"
  },
  {
    "path": "cantact.ioc",
    "chars": 3128,
    "preview": "#MicroXplorer Configuration settings - do not modify\r\n#Fri Dec 05 20:22:26 EST 2014\r\nCAN.CalculateTimeBit-Master=3000\r\nC"
  },
  {
    "path": "stm32f0x.cfg",
    "chars": 228,
    "preview": "set CHIPNAME STM32F042C6T6\n\nadapter_khz 100\n\nsource [find interface/stlink-v2.cfg]\n\ntransport select hla_swd\n\nset WORKAR"
  },
  {
    "path": "windows-driver/cantact.inf",
    "chars": 2092,
    "preview": "; Windows CANtact CDC ACM Setup File\r\n; Copyright (c) 2000 Microsoft Corporation\r\n\r\n[DefaultInstall]\r\nCopyINF=\"cantact.i"
  }
]

About this extraction

This page contains the full source code of the linklayer/cantact-fw GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 198 files (8.1 MB), approximately 2.1M tokens, and a symbol index with 1864 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.

Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.

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