Repository: losehu/uv-k5-firmware-chinese Branch: main Commit: a2db00363194 Files: 4130 Total size: 28.7 MB Directory structure: gitextract_g9i0p3qt/ ├── .github/ │ └── workflows/ │ ├── build.yml │ └── docker-image.yml ├── .gitignore ├── .vscode/ │ └── launch.json ├── DP32G030.svd ├── Dockerfile ├── Dockerfile_cn ├── Doxyfile ├── LICENSE ├── Makefile ├── README.md ├── README_en.md ├── am_fix.c ├── am_fix.h ├── app/ │ ├── action.c │ ├── action.h │ ├── aircopy.c │ ├── aircopy.h │ ├── app.c │ ├── app.h │ ├── chFrScanner.c │ ├── chFrScanner.h │ ├── common.c │ ├── common.h │ ├── doppler.c │ ├── doppler.h │ ├── dtmf.c │ ├── dtmf.h │ ├── flashlight.c │ ├── flashlight.h │ ├── fm.c │ ├── fm.h │ ├── generic.c │ ├── generic.h │ ├── main.c │ ├── main.h │ ├── mdc1200.c │ ├── mdc1200.h │ ├── menu.c │ ├── menu.h │ ├── messenger.c │ ├── messenger.h │ ├── scanner.c │ ├── scanner.h │ ├── si.c │ ├── si.h │ ├── spectrum.c │ ├── spectrum.h │ ├── uart.c │ └── uart.h ├── audio.c ├── audio.h ├── bitmaps.c ├── bitmaps.h ├── board.c ├── board.h ├── bsp/ │ └── dp32g030/ │ ├── aes.h │ ├── crc.h │ ├── dma.h │ ├── flash.h │ ├── gpio.h │ ├── irq.h │ ├── pmu.h │ ├── portcon.h │ ├── pwmplus.h │ ├── rtc.h │ ├── saradc.h │ ├── spi.h │ ├── syscon.h │ ├── timer.h │ └── uart.h ├── build/ │ ├── .cmake/ │ │ └── api/ │ │ └── v1/ │ │ └── query/ │ │ └── client-vscode/ │ │ └── query.json │ ├── CMakeCache.txt │ └── CMakeFiles/ │ └── cmake.check_cache ├── chinese.h ├── compile-with-docker.bat ├── compile-with-docker.sh ├── dcs.c ├── dcs.h ├── debugging.h ├── del_linux.sh ├── del_win.bat ├── doc/ │ ├── LoseHu固件多普勒使用说明.docx │ ├── 多普勒eeprom详细说明.txt │ └── 输入法编码表.xlsx ├── dp32g030.cfg ├── driver/ │ ├── adc.c │ ├── adc.h │ ├── aes.c │ ├── aes.h │ ├── backlight.c │ ├── backlight.h │ ├── bk1080-regs.h │ ├── bk1080.c │ ├── bk1080.h │ ├── bk4819-regs.h │ ├── bk4819.c │ ├── bk4819.h │ ├── crc.c │ ├── crc.h │ ├── eeprom.c │ ├── eeprom.h │ ├── flash.c │ ├── flash.h │ ├── gpio.c │ ├── gpio.h │ ├── i2c.c │ ├── i2c.h │ ├── keyboard.c │ ├── keyboard.h │ ├── rtc.c │ ├── si473x.c │ ├── si473x.h │ ├── spi.c │ ├── spi.h │ ├── st7565.c │ ├── st7565.h │ ├── system.c │ ├── system.h │ ├── systick.c │ ├── systick.h │ ├── timer.c │ ├── uart.c │ └── uart.h ├── external/ │ ├── CMSIS_5/ │ │ ├── .gitattributes │ │ ├── .github/ │ │ │ ├── fileheader.json │ │ │ ├── linkchecker.json │ │ │ ├── workflows/ │ │ │ │ ├── caller-corevalidation.yml │ │ │ │ ├── codeql-analysis.yml │ │ │ │ ├── corevalidation-report.yml │ │ │ │ ├── corevalidation.yml │ │ │ │ ├── fileheader.yml │ │ │ │ ├── gh-pages.yaml │ │ │ │ ├── packdesc.yml │ │ │ │ └── release.yaml │ │ │ └── xmllint.json │ │ ├── .gitignore │ │ ├── ARM.CMSIS.pdsc │ │ ├── CMSIS/ │ │ │ ├── Core/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── cachel1_armv7.h │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ ├── cmsis_armclang_ltm.h │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ ├── cmsis_tiarmclang.h │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ ├── core_armv81mml.h │ │ │ │ │ ├── core_armv8mbl.h │ │ │ │ │ ├── core_armv8mml.h │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ ├── core_cm1.h │ │ │ │ │ ├── core_cm23.h │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ ├── core_cm33.h │ │ │ │ │ ├── core_cm35p.h │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ ├── core_cm55.h │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ ├── core_cm85.h │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ ├── core_starmc1.h │ │ │ │ │ ├── mpu_armv7.h │ │ │ │ │ ├── mpu_armv8.h │ │ │ │ │ ├── pac_armv81.h │ │ │ │ │ ├── pmu_armv8.h │ │ │ │ │ └── tz_context.h │ │ │ │ └── Template/ │ │ │ │ └── ARMv8-M/ │ │ │ │ ├── main_s.c │ │ │ │ └── tz_context.c │ │ │ ├── CoreValidation/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── CV_Framework.h │ │ │ │ │ ├── CV_Report.h │ │ │ │ │ ├── CV_Typedefs.h │ │ │ │ │ └── cmsis_cv.h │ │ │ │ ├── LICENSE.txt │ │ │ │ ├── Layer/ │ │ │ │ │ ├── App/ │ │ │ │ │ │ ├── Bootloader_Cortex-M/ │ │ │ │ │ │ │ ├── App.clayer.yml │ │ │ │ │ │ │ └── bootloader.c │ │ │ │ │ │ ├── Validation_Cortex-A/ │ │ │ │ │ │ │ ├── App.clayer.yml │ │ │ │ │ │ │ └── main.c │ │ │ │ │ │ └── Validation_Cortex-M/ │ │ │ │ │ │ ├── App.clayer.yml │ │ │ │ │ │ └── main.c │ │ │ │ │ └── Target/ │ │ │ │ │ ├── CA5/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCA5/ │ │ │ │ │ │ │ ├── ARMCA5.icf │ │ │ │ │ │ │ ├── ARMCA5.icf.base@1.0.0 │ │ │ │ │ │ │ ├── ARMCA5.ld │ │ │ │ │ │ │ ├── ARMCA5.sct │ │ │ │ │ │ │ ├── mem_ARMCA5.h │ │ │ │ │ │ │ ├── mmu_ARMCA5.c │ │ │ │ │ │ │ ├── startup_ARMCA5.c │ │ │ │ │ │ │ ├── startup_ARMCA5.c.base@1.0.1 │ │ │ │ │ │ │ ├── startup_ARMCA5.s │ │ │ │ │ │ │ ├── startup_ARMCA5.s.base@1.0.0 │ │ │ │ │ │ │ ├── system_ARMCA5.c │ │ │ │ │ │ │ ├── system_ARMCA5.c.base@1.0.1 │ │ │ │ │ │ │ ├── system_ARMCA5.h │ │ │ │ │ │ │ └── system_ARMCA5.h.base@1.0.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CA7/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCA7/ │ │ │ │ │ │ │ ├── ARMCA7.icf │ │ │ │ │ │ │ ├── ARMCA7.icf.base@1.0.0 │ │ │ │ │ │ │ ├── ARMCA7.ld │ │ │ │ │ │ │ ├── ARMCA7.sct │ │ │ │ │ │ │ ├── mem_ARMCA7.h │ │ │ │ │ │ │ ├── mmu_ARMCA7.c │ │ │ │ │ │ │ ├── startup_ARMCA7.c │ │ │ │ │ │ │ ├── startup_ARMCA7.c.base@1.0.1 │ │ │ │ │ │ │ ├── startup_ARMCA7.s │ │ │ │ │ │ │ ├── startup_ARMCA7.s.base@1.0.0 │ │ │ │ │ │ │ ├── system_ARMCA7.c │ │ │ │ │ │ │ ├── system_ARMCA7.c.base@1.0.1 │ │ │ │ │ │ │ ├── system_ARMCA7.h │ │ │ │ │ │ │ └── system_ARMCA7.h.base@1.0.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CA9/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCA9/ │ │ │ │ │ │ │ ├── ARMCA9.icf │ │ │ │ │ │ │ ├── ARMCA9.icf.base@1.0.0 │ │ │ │ │ │ │ ├── ARMCA9.ld │ │ │ │ │ │ │ ├── ARMCA9.sct │ │ │ │ │ │ │ ├── mem_ARMCA9.h │ │ │ │ │ │ │ ├── mmu_ARMCA9.c │ │ │ │ │ │ │ ├── startup_ARMCA9.c │ │ │ │ │ │ │ ├── startup_ARMCA9.s │ │ │ │ │ │ │ ├── startup_ARMCA9.s.base@1.0.0 │ │ │ │ │ │ │ ├── system_ARMCA9.c │ │ │ │ │ │ │ ├── system_ARMCA9.h │ │ │ │ │ │ │ └── system_ARMCA9.h.base@1.0.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM0/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM0/ │ │ │ │ │ │ │ ├── ARMCM0_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM0.c │ │ │ │ │ │ │ ├── startup_ARMCM0.c.base@2.0.3 │ │ │ │ │ │ │ ├── system_ARMCM0.c │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM0plus/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM0P/ │ │ │ │ │ │ │ ├── ARMCM0plus_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM0plus.c │ │ │ │ │ │ │ ├── startup_ARMCM0plus.c.base@2.0.3 │ │ │ │ │ │ │ ├── system_ARMCM0plus.c │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM23/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM23/ │ │ │ │ │ │ │ ├── ARMCM23_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM23.c │ │ │ │ │ │ │ ├── startup_ARMCM23.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM23.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM23NS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM23_TZ/ │ │ │ │ │ │ │ ├── ARMCM23_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM23.c │ │ │ │ │ │ │ ├── startup_ARMCM23.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM23.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM23S/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM23_TZ/ │ │ │ │ │ │ │ ├── ARMCM23_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM23.h │ │ │ │ │ │ │ ├── startup_ARMCM23.c │ │ │ │ │ │ │ ├── startup_ARMCM23.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM23.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM23S_BL/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM23_TZ/ │ │ │ │ │ │ │ ├── ARMCM23_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM23.h │ │ │ │ │ │ │ ├── startup_ARMCM23.c │ │ │ │ │ │ │ ├── startup_ARMCM23.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM23.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM3/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM3/ │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct.base@1.0.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ │ │ ├── startup_ARMCM3.c.base@2.0.3 │ │ │ │ │ │ │ ├── system_ARMCM3.c │ │ │ │ │ │ │ ├── system_ARMCM3.c.base@1.0.1 │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM33/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP/ │ │ │ │ │ │ │ ├── ARMCM33_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ ├── startup_ARMCM33.c.base@2.1.0 │ │ │ │ │ │ │ ├── system_ARMCM33.c │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM33NS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM33_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ ├── startup_ARMCM33.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM33S/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ ├── startup_ARMCM33.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM33S_BL/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ ├── startup_ARMCM33.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM35P/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM35P_DSP_FP/ │ │ │ │ │ │ │ ├── ARMCM35P_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM35P.c │ │ │ │ │ │ │ ├── startup_ARMCM35P.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM35P.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM35PNS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM35P_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM35P_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM35P.c │ │ │ │ │ │ │ ├── startup_ARMCM35P.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM35P.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM35PS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM35P_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM35P_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM35P.h │ │ │ │ │ │ │ ├── startup_ARMCM35P.c │ │ │ │ │ │ │ ├── startup_ARMCM35P.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM35P.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM35PS_BL/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM35P_DSP_FP_TZ/ │ │ │ │ │ │ │ ├── ARMCM35P_ac6_s.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM35P.h │ │ │ │ │ │ │ ├── startup_ARMCM35P.c │ │ │ │ │ │ │ ├── startup_ARMCM35P.c.base@2.1.0 │ │ │ │ │ │ │ └── system_ARMCM35P.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM4/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM4/ │ │ │ │ │ │ │ ├── ARMCM4_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM4.c │ │ │ │ │ │ │ ├── startup_ARMCM4.c.base@2.0.3 │ │ │ │ │ │ │ ├── system_ARMCM4.c │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM4FP/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM4_FP/ │ │ │ │ │ │ │ ├── ARMCM4_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM4.c │ │ │ │ │ │ │ ├── startup_ARMCM4.c.base@2.0.3 │ │ │ │ │ │ │ ├── system_ARMCM4.c │ │ │ │ │ │ │ └── tiac_arm.cmd │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM55NS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM55/ │ │ │ │ │ │ │ ├── ARMCM55_ac6.sct │ │ │ │ │ │ │ ├── ARMCM55_ac6.sct.base@1.1.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM55.c │ │ │ │ │ │ │ ├── startup_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ │ ├── system_ARMCM55.c │ │ │ │ │ │ │ └── system_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM55S/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM55/ │ │ │ │ │ │ │ ├── ARMCM55_ac6_s.sct │ │ │ │ │ │ │ ├── ARMCM55_ac6_s.sct.base@1.1.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM55.h │ │ │ │ │ │ │ ├── startup_ARMCM55.c │ │ │ │ │ │ │ ├── startup_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ │ ├── system_ARMCM55.c │ │ │ │ │ │ │ └── system_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM55S_BL/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM55/ │ │ │ │ │ │ │ ├── ARMCM55_ac6_s.sct │ │ │ │ │ │ │ ├── ARMCM55_ac6_s.sct.base@1.1.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── partition_ARMCM55.h │ │ │ │ │ │ │ ├── startup_ARMCM55.c │ │ │ │ │ │ │ ├── startup_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ │ ├── system_ARMCM55.c │ │ │ │ │ │ │ └── system_ARMCM55.c.base@1.1.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM7/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM7/ │ │ │ │ │ │ │ ├── ARMCM7_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM7.c │ │ │ │ │ │ │ ├── startup_ARMCM7.c.base@2.0.3 │ │ │ │ │ │ │ └── system_ARMCM7.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM7DP/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM7_DP/ │ │ │ │ │ │ │ ├── ARMCM7_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM7.c │ │ │ │ │ │ │ ├── startup_ARMCM7.c.base@2.0.3 │ │ │ │ │ │ │ └── system_ARMCM7.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM7SP/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM7_SP/ │ │ │ │ │ │ │ ├── ARMCM7_ac6.sct │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── startup_ARMCM7.c │ │ │ │ │ │ │ ├── startup_ARMCM7.c.base@2.0.3 │ │ │ │ │ │ │ └── system_ARMCM7.c │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM85NS/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM85/ │ │ │ │ │ │ │ ├── ARMCM85_ac6.sct │ │ │ │ │ │ │ ├── ARMCM85_ac6.sct.base@1.0.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── gcc_arm.ld.base@1.0.0 │ │ │ │ │ │ │ ├── startup_ARMCM85.c │ │ │ │ │ │ │ ├── startup_ARMCM85.c.base@1.0.0 │ │ │ │ │ │ │ ├── system_ARMCM85.c │ │ │ │ │ │ │ └── system_ARMCM85.c.base@1.0.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ ├── CM85S/ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM85/ │ │ │ │ │ │ │ ├── ARMCM85_ac6_s.sct │ │ │ │ │ │ │ ├── ARMCM85_ac6_s.sct.base@1.0.0 │ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ │ ├── gcc_arm.ld.base@1.0.0 │ │ │ │ │ │ │ ├── partition_ARMCM85.h │ │ │ │ │ │ │ ├── partition_ARMCM85.h.base@1.0.0 │ │ │ │ │ │ │ ├── startup_ARMCM85.c │ │ │ │ │ │ │ ├── startup_ARMCM85.c.base@1.0.0 │ │ │ │ │ │ │ ├── system_ARMCM85.c │ │ │ │ │ │ │ └── system_ARMCM85.c.base@1.0.0 │ │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ │ └── model_config.txt │ │ │ │ │ └── CM85S_BL/ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ └── ARMCM85/ │ │ │ │ │ │ ├── ARMCM85_ac6_s.sct │ │ │ │ │ │ ├── ARMCM85_ac6_s.sct.base@1.0.0 │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ ├── gcc_arm.ld.base@1.0.0 │ │ │ │ │ │ ├── partition_ARMCM85.h │ │ │ │ │ │ ├── partition_ARMCM85.h.base@1.0.0 │ │ │ │ │ │ ├── startup_ARMCM85.c │ │ │ │ │ │ ├── startup_ARMCM85.c.base@1.0.0 │ │ │ │ │ │ ├── system_ARMCM85.c │ │ │ │ │ │ └── system_ARMCM85.c.base@1.0.0 │ │ │ │ │ ├── Target.clayer.yml │ │ │ │ │ └── model_config.txt │ │ │ │ ├── Project/ │ │ │ │ │ ├── Bootloader.cproject.yml │ │ │ │ │ ├── Validation.cproject.yml │ │ │ │ │ ├── Validation.csolution.yml │ │ │ │ │ ├── avh.yml │ │ │ │ │ ├── build.py │ │ │ │ │ ├── cpacklist.txt │ │ │ │ │ ├── requirements.txt │ │ │ │ │ └── validation.xsl │ │ │ │ ├── README.md │ │ │ │ └── Source/ │ │ │ │ ├── CV_CAL1Cache.c │ │ │ │ ├── CV_CML1Cache.c │ │ │ │ ├── CV_CoreAFunc.c │ │ │ │ ├── CV_CoreFunc.c │ │ │ │ ├── CV_CoreInstr.c │ │ │ │ ├── CV_CoreSimd.c │ │ │ │ ├── CV_Framework.c │ │ │ │ ├── CV_GenTimer.c │ │ │ │ ├── CV_MPU_ARMv7.c │ │ │ │ ├── CV_MPU_ARMv8.c │ │ │ │ ├── CV_Report.c │ │ │ │ ├── Config/ │ │ │ │ │ ├── CV_Config.h │ │ │ │ │ ├── CV_Config_template.h │ │ │ │ │ ├── partition_ARMCM23.h │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ ├── partition_ARMCM35P.h │ │ │ │ │ └── partition_ARMCM55.h │ │ │ │ ├── ConfigA/ │ │ │ │ │ ├── CV_Config.h │ │ │ │ │ └── CV_Config_template.h │ │ │ │ └── cmsis_cv.c │ │ │ ├── Core_A/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ ├── cmsis_cp15.h │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ ├── core_ca.h │ │ │ │ │ └── irq_ctrl.h │ │ │ │ └── Source/ │ │ │ │ └── irq_ctrl_gic.c │ │ │ ├── DSP/ │ │ │ │ └── README.md │ │ │ ├── DoxyGen/ │ │ │ │ ├── Build/ │ │ │ │ │ └── html/ │ │ │ │ │ ├── CmdLineBuild.html │ │ │ │ │ ├── build_revisionHistory.html │ │ │ │ │ ├── cbuild.html │ │ │ │ │ ├── cbuild_install.html │ │ │ │ │ ├── cbuild_uv.html │ │ │ │ │ ├── cbuildgen.html │ │ │ │ │ ├── ccmerge.html │ │ │ │ │ ├── cmake.html │ │ │ │ │ ├── cmsis.css │ │ │ │ │ ├── cmsis_footer.js │ │ │ │ │ ├── cp_init.html │ │ │ │ │ ├── cp_install.html │ │ │ │ │ ├── cprjFormat_pg.html │ │ │ │ │ ├── cprj_types.html │ │ │ │ │ ├── doxygen.css │ │ │ │ │ ├── dynsections.js │ │ │ │ │ ├── element_compilers.html │ │ │ │ │ ├── element_components.html │ │ │ │ │ ├── element_cprj.html │ │ │ │ │ ├── element_created.html │ │ │ │ │ ├── element_files.html │ │ │ │ │ ├── element_info.html │ │ │ │ │ ├── element_layers.html │ │ │ │ │ ├── element_packages.html │ │ │ │ │ ├── element_target.html │ │ │ │ │ ├── index.html │ │ │ │ │ ├── jquery.js │ │ │ │ │ ├── make.html │ │ │ │ │ ├── navtree.css │ │ │ │ │ ├── navtree.js │ │ │ │ │ ├── navtreeindex0.js │ │ │ │ │ ├── pages.html │ │ │ │ │ ├── printComponentTabs.js │ │ │ │ │ ├── projectDescriptionSchema.html │ │ │ │ │ ├── resize.js │ │ │ │ │ ├── search/ │ │ │ │ │ │ ├── nomatches.html │ │ │ │ │ │ ├── search.css │ │ │ │ │ │ └── search.js │ │ │ │ │ └── tabs.css │ │ │ │ ├── Core/ │ │ │ │ │ ├── core.dxy │ │ │ │ │ ├── core_CM0-7.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── MISRA.txt │ │ │ │ │ ├── Overview.txt │ │ │ │ │ ├── Ref_CompilerControl.txt │ │ │ │ │ ├── Ref_CoreReg.txt │ │ │ │ │ ├── Ref_DataStructs.txt │ │ │ │ │ ├── Ref_Debug.txt │ │ │ │ │ ├── Ref_FPU.txt │ │ │ │ │ ├── Ref_MPU.txt │ │ │ │ │ ├── Ref_MPU8.txt │ │ │ │ │ ├── Ref_MVE.txt │ │ │ │ │ ├── Ref_NVIC.txt │ │ │ │ │ ├── Ref_PMU8.txt │ │ │ │ │ ├── Ref_Peripheral.txt │ │ │ │ │ ├── Ref_SystemAndClock.txt │ │ │ │ │ ├── Ref_Systick.txt │ │ │ │ │ ├── Ref_Trustzone.txt │ │ │ │ │ ├── Ref_VersionControl.txt │ │ │ │ │ ├── Ref_cm4_simd.txt │ │ │ │ │ ├── Ref_cmInstr.txt │ │ │ │ │ ├── RegMap_CMSIS2ARM_Doc.txt │ │ │ │ │ ├── Template.txt │ │ │ │ │ ├── Using.txt │ │ │ │ │ ├── UsingTrustZone.txt │ │ │ │ │ ├── core_cm7.txt │ │ │ │ │ └── images/ │ │ │ │ │ ├── ARMv8-M_images.pptx │ │ │ │ │ └── CMSIS_V3_V5.pptx │ │ │ │ ├── Core_A/ │ │ │ │ │ ├── core_A.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── MISRA.txt │ │ │ │ │ ├── Overview.txt │ │ │ │ │ ├── Ref_SystemAndClock.txt │ │ │ │ │ ├── Template.txt │ │ │ │ │ ├── Using.txt │ │ │ │ │ ├── cmsis_armcc.txt │ │ │ │ │ ├── cmsis_compiler.txt │ │ │ │ │ ├── core_ca.txt │ │ │ │ │ ├── images/ │ │ │ │ │ │ └── CMSIS_Core_A.pptx │ │ │ │ │ ├── irq_ctrl.txt │ │ │ │ │ ├── ref_cache.txt │ │ │ │ │ ├── ref_core_register.txt │ │ │ │ │ ├── ref_gic.txt │ │ │ │ │ ├── ref_mmu.txt │ │ │ │ │ └── ref_timer.txt │ │ │ │ ├── DAP/ │ │ │ │ │ ├── CMSIS_DAP.pptx │ │ │ │ │ ├── CMSIS_DAP2.pptx │ │ │ │ │ ├── dap.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── dap.txt │ │ │ │ │ ├── dap_USB_cmds.txt │ │ │ │ │ ├── dap_config.txt │ │ │ │ │ └── images/ │ │ │ │ │ └── CMSIS_DAP_SWStack.pptx │ │ │ │ ├── DSP/ │ │ │ │ │ └── html/ │ │ │ │ │ ├── BasicMathFunctionsF16_8c.html │ │ │ │ │ ├── BasicMathFunctions_8c.html │ │ │ │ │ ├── BayesFunctionsF16_8c.html │ │ │ │ │ ├── BayesFunctions_8c.html │ │ │ │ │ ├── ChangeLog_pg.html │ │ │ │ │ ├── CommonTablesF16_8c.html │ │ │ │ │ ├── CommonTables_8c.html │ │ │ │ │ ├── ComplexMathFunctionsF16_8c.html │ │ │ │ │ ├── ComplexMathFunctions_8c.html │ │ │ │ │ ├── ControllerFunctions_8c.html │ │ │ │ │ ├── DistanceFunctionsF16_8c.html │ │ │ │ │ ├── DistanceFunctions_8c.html │ │ │ │ │ ├── Examples_2ARM_2CMakeLists_8txt.html │ │ │ │ │ ├── FastMathFunctionsF16_8c.html │ │ │ │ │ ├── FastMathFunctions_8c.html │ │ │ │ │ ├── FilteringFunctionsF16_8c.html │ │ │ │ │ ├── FilteringFunctions_8c.html │ │ │ │ │ ├── InterpolationFunctionsF16_8c.html │ │ │ │ │ ├── InterpolationFunctions_8c.html │ │ │ │ │ ├── MatrixFunctionsF16_8c.html │ │ │ │ │ ├── MatrixFunctions_8c.html │ │ │ │ │ ├── QuaternionMathFunctions_8c.html │ │ │ │ │ ├── SVMFunctionsF16_8c.html │ │ │ │ │ ├── SVMFunctions_8c.html │ │ │ │ │ ├── Source_2CMakeLists_8txt.html │ │ │ │ │ ├── StatisticsFunctionsF16_8c.html │ │ │ │ │ ├── StatisticsFunctions_8c.html │ │ │ │ │ ├── SupportFunctionsF16_8c.html │ │ │ │ │ ├── SupportFunctions_8c.html │ │ │ │ │ ├── TransformFunctionsF16_8c.html │ │ │ │ │ ├── TransformFunctions_8c.html │ │ │ │ │ ├── annotated.html │ │ │ │ │ ├── arm__abs__f16_8c.html │ │ │ │ │ ├── arm__abs__f32_8c.html │ │ │ │ │ ├── arm__abs__f64_8c.html │ │ │ │ │ ├── arm__abs__q15_8c.html │ │ │ │ │ ├── arm__abs__q31_8c.html │ │ │ │ │ ├── arm__abs__q7_8c.html │ │ │ │ │ ├── arm__absmax__f16_8c.html │ │ │ │ │ ├── arm__absmax__f32_8c.html │ │ │ │ │ ├── arm__absmax__f64_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__f16_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__f32_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__f64_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__q15_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__q31_8c.html │ │ │ │ │ ├── arm__absmax__no__idx__q7_8c.html │ │ │ │ │ ├── arm__absmax__q15_8c.html │ │ │ │ │ ├── arm__absmax__q31_8c.html │ │ │ │ │ ├── arm__absmax__q7_8c.html │ │ │ │ │ ├── arm__absmin__f16_8c.html │ │ │ │ │ ├── arm__absmin__f32_8c.html │ │ │ │ │ ├── arm__absmin__f64_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__f16_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__f32_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__f64_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__q15_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__q31_8c.html │ │ │ │ │ ├── arm__absmin__no__idx__q7_8c.html │ │ │ │ │ ├── arm__absmin__q15_8c.html │ │ │ │ │ ├── arm__absmin__q31_8c.html │ │ │ │ │ ├── arm__absmin__q7_8c.html │ │ │ │ │ ├── arm__add__f16_8c.html │ │ │ │ │ ├── arm__add__f32_8c.html │ │ │ │ │ ├── arm__add__f64_8c.html │ │ │ │ │ ├── arm__add__q15_8c.html │ │ │ │ │ ├── arm__add__q31_8c.html │ │ │ │ │ ├── arm__add__q7_8c.html │ │ │ │ │ ├── arm__and__u16_8c.html │ │ │ │ │ ├── arm__and__u32_8c.html │ │ │ │ │ ├── arm__and__u8_8c.html │ │ │ │ │ ├── arm__atan2__f16_8c.html │ │ │ │ │ ├── arm__atan2__f32_8c.html │ │ │ │ │ ├── arm__atan2__q15_8c.html │ │ │ │ │ ├── arm__atan2__q31_8c.html │ │ │ │ │ ├── arm__barycenter__f16_8c.html │ │ │ │ │ ├── arm__barycenter__f32_8c.html │ │ │ │ │ ├── arm__bayes__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__bayes__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__bayes__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__bayes__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__bayes__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__bayes__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__bayes__example_2train_8py.html │ │ │ │ │ ├── arm__bayes__example__f32_8c.html │ │ │ │ │ ├── arm__bilinear__interp__f16_8c.html │ │ │ │ │ ├── arm__bilinear__interp__f32_8c.html │ │ │ │ │ ├── arm__bilinear__interp__q15_8c.html │ │ │ │ │ ├── arm__bilinear__interp__q31_8c.html │ │ │ │ │ ├── arm__bilinear__interp__q7_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__32x64__init__q31_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__32x64__q31_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__f32_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__fast__q15_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__fast__q31_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__init__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__init__f32_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__init__q15_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__init__q31_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__q15_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df1__q31_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__f32_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__f64_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__init__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__init__f32_8c.html │ │ │ │ │ ├── arm__biquad__cascade__df2T__init__f64_8c.html │ │ │ │ │ ├── arm__biquad__cascade__stereo__df2T__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__stereo__df2T__f32_8c.html │ │ │ │ │ ├── arm__biquad__cascade__stereo__df2T__init__f16_8c.html │ │ │ │ │ ├── arm__biquad__cascade__stereo__df2T__init__f32_8c.html │ │ │ │ │ ├── arm__bitonic__sort__f32_8c.html │ │ │ │ │ ├── arm__bitreversal2_8c.html │ │ │ │ │ ├── arm__bitreversal_8c.html │ │ │ │ │ ├── arm__bitreversal__f16_8c.html │ │ │ │ │ ├── arm__braycurtis__distance__f16_8c.html │ │ │ │ │ ├── arm__braycurtis__distance__f32_8c.html │ │ │ │ │ ├── arm__bubble__sort__f32_8c.html │ │ │ │ │ ├── arm__canberra__distance__f16_8c.html │ │ │ │ │ ├── arm__canberra__distance__f32_8c.html │ │ │ │ │ ├── arm__cfft__f16_8c.html │ │ │ │ │ ├── arm__cfft__f32_8c.html │ │ │ │ │ ├── arm__cfft__f64_8c.html │ │ │ │ │ ├── arm__cfft__init__f16_8c.html │ │ │ │ │ ├── arm__cfft__init__f32_8c.html │ │ │ │ │ ├── arm__cfft__init__f64_8c.html │ │ │ │ │ ├── arm__cfft__init__q15_8c.html │ │ │ │ │ ├── arm__cfft__init__q31_8c.html │ │ │ │ │ ├── arm__cfft__q15_8c.html │ │ │ │ │ ├── arm__cfft__q31_8c.html │ │ │ │ │ ├── arm__cfft__radix2__f16_8c.html │ │ │ │ │ ├── arm__cfft__radix2__f32_8c.html │ │ │ │ │ ├── arm__cfft__radix2__init__f16_8c.html │ │ │ │ │ ├── arm__cfft__radix2__init__f32_8c.html │ │ │ │ │ ├── arm__cfft__radix2__init__q15_8c.html │ │ │ │ │ ├── arm__cfft__radix2__init__q31_8c.html │ │ │ │ │ ├── arm__cfft__radix2__q15_8c.html │ │ │ │ │ ├── arm__cfft__radix2__q31_8c.html │ │ │ │ │ ├── arm__cfft__radix4__f16_8c.html │ │ │ │ │ ├── arm__cfft__radix4__f32_8c.html │ │ │ │ │ ├── arm__cfft__radix4__init__f16_8c.html │ │ │ │ │ ├── arm__cfft__radix4__init__f32_8c.html │ │ │ │ │ ├── arm__cfft__radix4__init__q15_8c.html │ │ │ │ │ ├── arm__cfft__radix4__init__q31_8c.html │ │ │ │ │ ├── arm__cfft__radix4__q15_8c.html │ │ │ │ │ ├── arm__cfft__radix4__q31_8c.html │ │ │ │ │ ├── arm__cfft__radix8__f16_8c.html │ │ │ │ │ ├── arm__cfft__radix8__f32_8c.html │ │ │ │ │ ├── arm__chebyshev__distance__f16_8c.html │ │ │ │ │ ├── arm__chebyshev__distance__f32_8c.html │ │ │ │ │ ├── arm__chebyshev__distance__f64_8c.html │ │ │ │ │ ├── arm__cityblock__distance__f16_8c.html │ │ │ │ │ ├── arm__cityblock__distance__f32_8c.html │ │ │ │ │ ├── arm__cityblock__distance__f64_8c.html │ │ │ │ │ ├── arm__class__marks__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__class__marks__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__class__marks__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__class__marks__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__class__marks__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__class__marks__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__class__marks__example__f32_8c.html │ │ │ │ │ ├── arm__clip__f16_8c.html │ │ │ │ │ ├── arm__clip__f32_8c.html │ │ │ │ │ ├── arm__clip__q15_8c.html │ │ │ │ │ ├── arm__clip__q31_8c.html │ │ │ │ │ ├── arm__clip__q7_8c.html │ │ │ │ │ ├── arm__cmplx__conj__f16_8c.html │ │ │ │ │ ├── arm__cmplx__conj__f32_8c.html │ │ │ │ │ ├── arm__cmplx__conj__q15_8c.html │ │ │ │ │ ├── arm__cmplx__conj__q31_8c.html │ │ │ │ │ ├── arm__cmplx__dot__prod__f16_8c.html │ │ │ │ │ ├── arm__cmplx__dot__prod__f32_8c.html │ │ │ │ │ ├── arm__cmplx__dot__prod__q15_8c.html │ │ │ │ │ ├── arm__cmplx__dot__prod__q31_8c.html │ │ │ │ │ ├── arm__cmplx__mag__f16_8c.html │ │ │ │ │ ├── arm__cmplx__mag__f32_8c.html │ │ │ │ │ ├── arm__cmplx__mag__f64_8c.html │ │ │ │ │ ├── arm__cmplx__mag__fast__q15_8c.html │ │ │ │ │ ├── arm__cmplx__mag__q15_8c.html │ │ │ │ │ ├── arm__cmplx__mag__q31_8c.html │ │ │ │ │ ├── arm__cmplx__mag__squared__f16_8c.html │ │ │ │ │ ├── arm__cmplx__mag__squared__f32_8c.html │ │ │ │ │ ├── arm__cmplx__mag__squared__f64_8c.html │ │ │ │ │ ├── arm__cmplx__mag__squared__q15_8c.html │ │ │ │ │ ├── arm__cmplx__mag__squared__q31_8c.html │ │ │ │ │ ├── arm__cmplx__mult__cmplx__f16_8c.html │ │ │ │ │ ├── arm__cmplx__mult__cmplx__f32_8c.html │ │ │ │ │ ├── arm__cmplx__mult__cmplx__f64_8c.html │ │ │ │ │ ├── arm__cmplx__mult__cmplx__q15_8c.html │ │ │ │ │ ├── arm__cmplx__mult__cmplx__q31_8c.html │ │ │ │ │ ├── arm__cmplx__mult__real__f16_8c.html │ │ │ │ │ ├── arm__cmplx__mult__real__f32_8c.html │ │ │ │ │ ├── arm__cmplx__mult__real__q15_8c.html │ │ │ │ │ ├── arm__cmplx__mult__real__q31_8c.html │ │ │ │ │ ├── arm__common__tables_8c.html │ │ │ │ │ ├── arm__common__tables_8h.html │ │ │ │ │ ├── arm__common__tables__f16_8c.html │ │ │ │ │ ├── arm__common__tables__f16_8h.html │ │ │ │ │ ├── arm__const__structs_8c.html │ │ │ │ │ ├── arm__const__structs_8h.html │ │ │ │ │ ├── arm__const__structs__f16_8c.html │ │ │ │ │ ├── arm__const__structs__f16_8h.html │ │ │ │ │ ├── arm__conv__f32_8c.html │ │ │ │ │ ├── arm__conv__fast__opt__q15_8c.html │ │ │ │ │ ├── arm__conv__fast__q15_8c.html │ │ │ │ │ ├── arm__conv__fast__q31_8c.html │ │ │ │ │ ├── arm__conv__opt__q15_8c.html │ │ │ │ │ ├── arm__conv__opt__q7_8c.html │ │ │ │ │ ├── arm__conv__partial__f32_8c.html │ │ │ │ │ ├── arm__conv__partial__fast__opt__q15_8c.html │ │ │ │ │ ├── arm__conv__partial__fast__q15_8c.html │ │ │ │ │ ├── arm__conv__partial__fast__q31_8c.html │ │ │ │ │ ├── arm__conv__partial__opt__q15_8c.html │ │ │ │ │ ├── arm__conv__partial__opt__q7_8c.html │ │ │ │ │ ├── arm__conv__partial__q15_8c.html │ │ │ │ │ ├── arm__conv__partial__q31_8c.html │ │ │ │ │ ├── arm__conv__partial__q7_8c.html │ │ │ │ │ ├── arm__conv__q15_8c.html │ │ │ │ │ ├── arm__conv__q31_8c.html │ │ │ │ │ ├── arm__conv__q7_8c.html │ │ │ │ │ ├── arm__convolution__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__convolution__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__convolution__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__convolution__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__convolution__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__convolution__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__convolution__example_2math__helper_8c.html │ │ │ │ │ ├── arm__convolution__example_2math__helper_8h.html │ │ │ │ │ ├── arm__convolution__example__f32_8c.html │ │ │ │ │ ├── arm__copy__f16_8c.html │ │ │ │ │ ├── arm__copy__f32_8c.html │ │ │ │ │ ├── arm__copy__f64_8c.html │ │ │ │ │ ├── arm__copy__q15_8c.html │ │ │ │ │ ├── arm__copy__q31_8c.html │ │ │ │ │ ├── arm__copy__q7_8c.html │ │ │ │ │ ├── arm__correlate__f16_8c.html │ │ │ │ │ ├── arm__correlate__f32_8c.html │ │ │ │ │ ├── arm__correlate__f64_8c.html │ │ │ │ │ ├── arm__correlate__fast__opt__q15_8c.html │ │ │ │ │ ├── arm__correlate__fast__q15_8c.html │ │ │ │ │ ├── arm__correlate__fast__q31_8c.html │ │ │ │ │ ├── arm__correlate__opt__q15_8c.html │ │ │ │ │ ├── arm__correlate__opt__q7_8c.html │ │ │ │ │ ├── arm__correlate__q15_8c.html │ │ │ │ │ ├── arm__correlate__q31_8c.html │ │ │ │ │ ├── arm__correlate__q7_8c.html │ │ │ │ │ ├── arm__correlation__distance__f16_8c.html │ │ │ │ │ ├── arm__correlation__distance__f32_8c.html │ │ │ │ │ ├── arm__cos__f32_8c.html │ │ │ │ │ ├── arm__cos__q15_8c.html │ │ │ │ │ ├── arm__cos__q31_8c.html │ │ │ │ │ ├── arm__cosine__distance__f16_8c.html │ │ │ │ │ ├── arm__cosine__distance__f32_8c.html │ │ │ │ │ ├── arm__cosine__distance__f64_8c.html │ │ │ │ │ ├── arm__dct4__f32_8c.html │ │ │ │ │ ├── arm__dct4__init__f32_8c.html │ │ │ │ │ ├── arm__dct4__init__q15_8c.html │ │ │ │ │ ├── arm__dct4__init__q31_8c.html │ │ │ │ │ ├── arm__dct4__q15_8c.html │ │ │ │ │ ├── arm__dct4__q31_8c.html │ │ │ │ │ ├── arm__dice__distance_8c.html │ │ │ │ │ ├── arm__divide__q15_8c.html │ │ │ │ │ ├── arm__divide__q31_8c.html │ │ │ │ │ ├── arm__dot__prod__f16_8c.html │ │ │ │ │ ├── arm__dot__prod__f32_8c.html │ │ │ │ │ ├── arm__dot__prod__f64_8c.html │ │ │ │ │ ├── arm__dot__prod__q15_8c.html │ │ │ │ │ ├── arm__dot__prod__q31_8c.html │ │ │ │ │ ├── arm__dot__prod__q7_8c.html │ │ │ │ │ ├── arm__dotproduct__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__dotproduct__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__dotproduct__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__dotproduct__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__dotproduct__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__dotproduct__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__dotproduct__example__f32_8c.html │ │ │ │ │ ├── arm__entropy__f16_8c.html │ │ │ │ │ ├── arm__entropy__f32_8c.html │ │ │ │ │ ├── arm__entropy__f64_8c.html │ │ │ │ │ ├── arm__euclidean__distance__f16_8c.html │ │ │ │ │ ├── arm__euclidean__distance__f32_8c.html │ │ │ │ │ ├── arm__euclidean__distance__f64_8c.html │ │ │ │ │ ├── arm__f16__to__float_8c.html │ │ │ │ │ ├── arm__f16__to__q15_8c.html │ │ │ │ │ ├── arm__fft__bin__data_8c.html │ │ │ │ │ ├── arm__fft__bin__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__fft__bin__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__fft__bin__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__fft__bin__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__fft__bin__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__fft__bin__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__fft__bin__example__f32_8c.html │ │ │ │ │ ├── arm__fill__f16_8c.html │ │ │ │ │ ├── arm__fill__f32_8c.html │ │ │ │ │ ├── arm__fill__f64_8c.html │ │ │ │ │ ├── arm__fill__q15_8c.html │ │ │ │ │ ├── arm__fill__q31_8c.html │ │ │ │ │ ├── arm__fill__q7_8c.html │ │ │ │ │ ├── arm__fir__data_8c.html │ │ │ │ │ ├── arm__fir__decimate__f32_8c.html │ │ │ │ │ ├── arm__fir__decimate__fast__q15_8c.html │ │ │ │ │ ├── arm__fir__decimate__fast__q31_8c.html │ │ │ │ │ ├── arm__fir__decimate__init__f32_8c.html │ │ │ │ │ ├── arm__fir__decimate__init__q15_8c.html │ │ │ │ │ ├── arm__fir__decimate__init__q31_8c.html │ │ │ │ │ ├── arm__fir__decimate__q15_8c.html │ │ │ │ │ ├── arm__fir__decimate__q31_8c.html │ │ │ │ │ ├── arm__fir__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__fir__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__fir__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__fir__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__fir__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__fir__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__fir__example_2math__helper_8c.html │ │ │ │ │ ├── arm__fir__example_2math__helper_8h.html │ │ │ │ │ ├── arm__fir__example__f32_8c.html │ │ │ │ │ ├── arm__fir__f16_8c.html │ │ │ │ │ ├── arm__fir__f32_8c.html │ │ │ │ │ ├── arm__fir__f64_8c.html │ │ │ │ │ ├── arm__fir__fast__q15_8c.html │ │ │ │ │ ├── arm__fir__fast__q31_8c.html │ │ │ │ │ ├── arm__fir__init__f16_8c.html │ │ │ │ │ ├── arm__fir__init__f32_8c.html │ │ │ │ │ ├── arm__fir__init__f64_8c.html │ │ │ │ │ ├── arm__fir__init__q15_8c.html │ │ │ │ │ ├── arm__fir__init__q31_8c.html │ │ │ │ │ ├── arm__fir__init__q7_8c.html │ │ │ │ │ ├── arm__fir__interpolate__f32_8c.html │ │ │ │ │ ├── arm__fir__interpolate__init__f32_8c.html │ │ │ │ │ ├── arm__fir__interpolate__init__q15_8c.html │ │ │ │ │ ├── arm__fir__interpolate__init__q31_8c.html │ │ │ │ │ ├── arm__fir__interpolate__q15_8c.html │ │ │ │ │ ├── arm__fir__interpolate__q31_8c.html │ │ │ │ │ ├── arm__fir__lattice__f32_8c.html │ │ │ │ │ ├── arm__fir__lattice__init__f32_8c.html │ │ │ │ │ ├── arm__fir__lattice__init__q15_8c.html │ │ │ │ │ ├── arm__fir__lattice__init__q31_8c.html │ │ │ │ │ ├── arm__fir__lattice__q15_8c.html │ │ │ │ │ ├── arm__fir__lattice__q31_8c.html │ │ │ │ │ ├── arm__fir__q15_8c.html │ │ │ │ │ ├── arm__fir__q31_8c.html │ │ │ │ │ ├── arm__fir__q7_8c.html │ │ │ │ │ ├── arm__fir__sparse__f32_8c.html │ │ │ │ │ ├── arm__fir__sparse__init__f32_8c.html │ │ │ │ │ ├── arm__fir__sparse__init__q15_8c.html │ │ │ │ │ ├── arm__fir__sparse__init__q31_8c.html │ │ │ │ │ ├── arm__fir__sparse__init__q7_8c.html │ │ │ │ │ ├── arm__fir__sparse__q15_8c.html │ │ │ │ │ ├── arm__fir__sparse__q31_8c.html │ │ │ │ │ ├── arm__fir__sparse__q7_8c.html │ │ │ │ │ ├── arm__float__to__f16_8c.html │ │ │ │ │ ├── arm__float__to__q15_8c.html │ │ │ │ │ ├── arm__float__to__q31_8c.html │ │ │ │ │ ├── arm__float__to__q7_8c.html │ │ │ │ │ ├── arm__gaussian__naive__bayes__predict__f16_8c.html │ │ │ │ │ ├── arm__gaussian__naive__bayes__predict__f32_8c.html │ │ │ │ │ ├── arm__graphic__equalizer__data_8c.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2math__helper_8c.html │ │ │ │ │ ├── arm__graphic__equalizer__example_2math__helper_8h.html │ │ │ │ │ ├── arm__graphic__equalizer__example__q31_8c.html │ │ │ │ │ ├── arm__hamming__distance_8c.html │ │ │ │ │ ├── arm__heap__sort__f32_8c.html │ │ │ │ │ ├── arm__helium__utils_8h.html │ │ │ │ │ ├── arm__iir__lattice__f32_8c.html │ │ │ │ │ ├── arm__iir__lattice__init__f32_8c.html │ │ │ │ │ ├── arm__iir__lattice__init__q15_8c.html │ │ │ │ │ ├── arm__iir__lattice__init__q31_8c.html │ │ │ │ │ ├── arm__iir__lattice__q15_8c.html │ │ │ │ │ ├── arm__iir__lattice__q31_8c.html │ │ │ │ │ ├── arm__insertion__sort__f32_8c.html │ │ │ │ │ ├── arm__jaccard__distance_8c.html │ │ │ │ │ ├── arm__jensenshannon__distance__f16_8c.html │ │ │ │ │ ├── arm__jensenshannon__distance__f32_8c.html │ │ │ │ │ ├── arm__kullback__leibler__f16_8c.html │ │ │ │ │ ├── arm__kullback__leibler__f32_8c.html │ │ │ │ │ ├── arm__kullback__leibler__f64_8c.html │ │ │ │ │ ├── arm__kulsinski__distance_8c.html │ │ │ │ │ ├── arm__levinson__durbin__f16_8c.html │ │ │ │ │ ├── arm__levinson__durbin__f32_8c.html │ │ │ │ │ ├── arm__levinson__durbin__q31_8c.html │ │ │ │ │ ├── arm__linear__interp__data_8c.html │ │ │ │ │ ├── arm__linear__interp__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__linear__interp__example_2math__helper_8c.html │ │ │ │ │ ├── arm__linear__interp__example_2math__helper_8h.html │ │ │ │ │ ├── arm__linear__interp__example__f32_8c.html │ │ │ │ │ ├── arm__linear__interp__f16_8c.html │ │ │ │ │ ├── arm__linear__interp__f32_8c.html │ │ │ │ │ ├── arm__linear__interp__q15_8c.html │ │ │ │ │ ├── arm__linear__interp__q31_8c.html │ │ │ │ │ ├── arm__linear__interp__q7_8c.html │ │ │ │ │ ├── arm__lms__f32_8c.html │ │ │ │ │ ├── arm__lms__init__f32_8c.html │ │ │ │ │ ├── arm__lms__init__q15_8c.html │ │ │ │ │ ├── arm__lms__init__q31_8c.html │ │ │ │ │ ├── arm__lms__norm__f32_8c.html │ │ │ │ │ ├── arm__lms__norm__init__f32_8c.html │ │ │ │ │ ├── arm__lms__norm__init__q15_8c.html │ │ │ │ │ ├── arm__lms__norm__init__q31_8c.html │ │ │ │ │ ├── arm__lms__norm__q15_8c.html │ │ │ │ │ ├── arm__lms__norm__q31_8c.html │ │ │ │ │ ├── arm__lms__q15_8c.html │ │ │ │ │ ├── arm__lms__q31_8c.html │ │ │ │ │ ├── arm__logsumexp__dot__prod__f16_8c.html │ │ │ │ │ ├── arm__logsumexp__dot__prod__f32_8c.html │ │ │ │ │ ├── arm__logsumexp__f16_8c.html │ │ │ │ │ ├── arm__logsumexp__f32_8c.html │ │ │ │ │ ├── arm__mat__add__f16_8c.html │ │ │ │ │ ├── arm__mat__add__f32_8c.html │ │ │ │ │ ├── arm__mat__add__q15_8c.html │ │ │ │ │ ├── arm__mat__add__q31_8c.html │ │ │ │ │ ├── arm__mat__cholesky__f16_8c.html │ │ │ │ │ ├── arm__mat__cholesky__f32_8c.html │ │ │ │ │ ├── arm__mat__cholesky__f64_8c.html │ │ │ │ │ ├── arm__mat__cmplx__mult__f16_8c.html │ │ │ │ │ ├── arm__mat__cmplx__mult__f32_8c.html │ │ │ │ │ ├── arm__mat__cmplx__mult__q15_8c.html │ │ │ │ │ ├── arm__mat__cmplx__mult__q31_8c.html │ │ │ │ │ ├── arm__mat__cmplx__trans__f16_8c.html │ │ │ │ │ ├── arm__mat__cmplx__trans__f32_8c.html │ │ │ │ │ ├── arm__mat__cmplx__trans__q15_8c.html │ │ │ │ │ ├── arm__mat__cmplx__trans__q31_8c.html │ │ │ │ │ ├── arm__mat__init__f16_8c.html │ │ │ │ │ ├── arm__mat__init__f32_8c.html │ │ │ │ │ ├── arm__mat__init__q15_8c.html │ │ │ │ │ ├── arm__mat__init__q31_8c.html │ │ │ │ │ ├── arm__mat__inverse__f16_8c.html │ │ │ │ │ ├── arm__mat__inverse__f32_8c.html │ │ │ │ │ ├── arm__mat__inverse__f64_8c.html │ │ │ │ │ ├── arm__mat__ldlt__f32_8c.html │ │ │ │ │ ├── arm__mat__ldlt__f64_8c.html │ │ │ │ │ ├── arm__mat__mult__f16_8c.html │ │ │ │ │ ├── arm__mat__mult__f32_8c.html │ │ │ │ │ ├── arm__mat__mult__f64_8c.html │ │ │ │ │ ├── arm__mat__mult__fast__q15_8c.html │ │ │ │ │ ├── arm__mat__mult__fast__q31_8c.html │ │ │ │ │ ├── arm__mat__mult__opt__q31_8c.html │ │ │ │ │ ├── arm__mat__mult__q15_8c.html │ │ │ │ │ ├── arm__mat__mult__q31_8c.html │ │ │ │ │ ├── arm__mat__mult__q7_8c.html │ │ │ │ │ ├── arm__mat__scale__f16_8c.html │ │ │ │ │ ├── arm__mat__scale__f32_8c.html │ │ │ │ │ ├── arm__mat__scale__q15_8c.html │ │ │ │ │ ├── arm__mat__scale__q31_8c.html │ │ │ │ │ ├── arm__mat__solve__lower__triangular__f16_8c.html │ │ │ │ │ ├── arm__mat__solve__lower__triangular__f32_8c.html │ │ │ │ │ ├── arm__mat__solve__lower__triangular__f64_8c.html │ │ │ │ │ ├── arm__mat__solve__upper__triangular__f16_8c.html │ │ │ │ │ ├── arm__mat__solve__upper__triangular__f32_8c.html │ │ │ │ │ ├── arm__mat__solve__upper__triangular__f64_8c.html │ │ │ │ │ ├── arm__mat__sub__f16_8c.html │ │ │ │ │ ├── arm__mat__sub__f32_8c.html │ │ │ │ │ ├── arm__mat__sub__f64_8c.html │ │ │ │ │ ├── arm__mat__sub__q15_8c.html │ │ │ │ │ ├── arm__mat__sub__q31_8c.html │ │ │ │ │ ├── arm__mat__trans__f16_8c.html │ │ │ │ │ ├── arm__mat__trans__f32_8c.html │ │ │ │ │ ├── arm__mat__trans__f64_8c.html │ │ │ │ │ ├── arm__mat__trans__q15_8c.html │ │ │ │ │ ├── arm__mat__trans__q31_8c.html │ │ │ │ │ ├── arm__mat__trans__q7_8c.html │ │ │ │ │ ├── arm__mat__vec__mult__f16_8c.html │ │ │ │ │ ├── arm__mat__vec__mult__f32_8c.html │ │ │ │ │ ├── arm__mat__vec__mult__q15_8c.html │ │ │ │ │ ├── arm__mat__vec__mult__q31_8c.html │ │ │ │ │ ├── arm__mat__vec__mult__q7_8c.html │ │ │ │ │ ├── arm__math_8h.html │ │ │ │ │ ├── arm__math__f16_8h.html │ │ │ │ │ ├── arm__math__memory_8h.html │ │ │ │ │ ├── arm__math__types_8h.html │ │ │ │ │ ├── arm__math__types__f16_8h.html │ │ │ │ │ ├── arm__matrix__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__matrix__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__matrix__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__matrix__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__matrix__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__matrix__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__matrix__example_2math__helper_8c.html │ │ │ │ │ ├── arm__matrix__example_2math__helper_8h.html │ │ │ │ │ ├── arm__matrix__example__f32_8c.html │ │ │ │ │ ├── arm__max__f16_8c.html │ │ │ │ │ ├── arm__max__f32_8c.html │ │ │ │ │ ├── arm__max__f64_8c.html │ │ │ │ │ ├── arm__max__no__idx__f16_8c.html │ │ │ │ │ ├── arm__max__no__idx__f32_8c.html │ │ │ │ │ ├── arm__max__no__idx__f64_8c.html │ │ │ │ │ ├── arm__max__no__idx__q15_8c.html │ │ │ │ │ ├── arm__max__no__idx__q31_8c.html │ │ │ │ │ ├── arm__max__no__idx__q7_8c.html │ │ │ │ │ ├── arm__max__q15_8c.html │ │ │ │ │ ├── arm__max__q31_8c.html │ │ │ │ │ ├── arm__max__q7_8c.html │ │ │ │ │ ├── arm__mean__f16_8c.html │ │ │ │ │ ├── arm__mean__f32_8c.html │ │ │ │ │ ├── arm__mean__f64_8c.html │ │ │ │ │ ├── arm__mean__q15_8c.html │ │ │ │ │ ├── arm__mean__q31_8c.html │ │ │ │ │ ├── arm__mean__q7_8c.html │ │ │ │ │ ├── arm__merge__sort__f32_8c.html │ │ │ │ │ ├── arm__merge__sort__init__f32_8c.html │ │ │ │ │ ├── arm__mfcc__f16_8c.html │ │ │ │ │ ├── arm__mfcc__f32_8c.html │ │ │ │ │ ├── arm__mfcc__init__f16_8c.html │ │ │ │ │ ├── arm__mfcc__init__f32_8c.html │ │ │ │ │ ├── arm__mfcc__init__q15_8c.html │ │ │ │ │ ├── arm__mfcc__init__q31_8c.html │ │ │ │ │ ├── arm__mfcc__q15_8c.html │ │ │ │ │ ├── arm__mfcc__q31_8c.html │ │ │ │ │ ├── arm__min__f16_8c.html │ │ │ │ │ ├── arm__min__f32_8c.html │ │ │ │ │ ├── arm__min__f64_8c.html │ │ │ │ │ ├── arm__min__no__idx__f16_8c.html │ │ │ │ │ ├── arm__min__no__idx__f32_8c.html │ │ │ │ │ ├── arm__min__no__idx__f64_8c.html │ │ │ │ │ ├── arm__min__no__idx__q15_8c.html │ │ │ │ │ ├── arm__min__no__idx__q31_8c.html │ │ │ │ │ ├── arm__min__no__idx__q7_8c.html │ │ │ │ │ ├── arm__min__q15_8c.html │ │ │ │ │ ├── arm__min__q31_8c.html │ │ │ │ │ ├── arm__min__q7_8c.html │ │ │ │ │ ├── arm__minkowski__distance__f16_8c.html │ │ │ │ │ ├── arm__minkowski__distance__f32_8c.html │ │ │ │ │ ├── arm__mse__f16_8c.html │ │ │ │ │ ├── arm__mse__f32_8c.html │ │ │ │ │ ├── arm__mse__f64_8c.html │ │ │ │ │ ├── arm__mse__q15_8c.html │ │ │ │ │ ├── arm__mse__q31_8c.html │ │ │ │ │ ├── arm__mse__q7_8c.html │ │ │ │ │ ├── arm__mult__f16_8c.html │ │ │ │ │ ├── arm__mult__f32_8c.html │ │ │ │ │ ├── arm__mult__f64_8c.html │ │ │ │ │ ├── arm__mult__q15_8c.html │ │ │ │ │ ├── arm__mult__q31_8c.html │ │ │ │ │ ├── arm__mult__q7_8c.html │ │ │ │ │ ├── arm__mve__tables_8c.html │ │ │ │ │ ├── arm__mve__tables_8h.html │ │ │ │ │ ├── arm__mve__tables__f16_8c.html │ │ │ │ │ ├── arm__mve__tables__f16_8h.html │ │ │ │ │ ├── arm__negate__f16_8c.html │ │ │ │ │ ├── arm__negate__f32_8c.html │ │ │ │ │ ├── arm__negate__f64_8c.html │ │ │ │ │ ├── arm__negate__q15_8c.html │ │ │ │ │ ├── arm__negate__q31_8c.html │ │ │ │ │ ├── arm__negate__q7_8c.html │ │ │ │ │ ├── arm__not__u16_8c.html │ │ │ │ │ ├── arm__not__u32_8c.html │ │ │ │ │ ├── arm__not__u8_8c.html │ │ │ │ │ ├── arm__offset__f16_8c.html │ │ │ │ │ ├── arm__offset__f32_8c.html │ │ │ │ │ ├── arm__offset__f64_8c.html │ │ │ │ │ ├── arm__offset__q15_8c.html │ │ │ │ │ ├── arm__offset__q31_8c.html │ │ │ │ │ ├── arm__offset__q7_8c.html │ │ │ │ │ ├── arm__or__u16_8c.html │ │ │ │ │ ├── arm__or__u32_8c.html │ │ │ │ │ ├── arm__or__u8_8c.html │ │ │ │ │ ├── arm__pid__init__f32_8c.html │ │ │ │ │ ├── arm__pid__init__q15_8c.html │ │ │ │ │ ├── arm__pid__init__q31_8c.html │ │ │ │ │ ├── arm__pid__reset__f32_8c.html │ │ │ │ │ ├── arm__pid__reset__q15_8c.html │ │ │ │ │ ├── arm__pid__reset__q31_8c.html │ │ │ │ │ ├── arm__power__f16_8c.html │ │ │ │ │ ├── arm__power__f32_8c.html │ │ │ │ │ ├── arm__power__f64_8c.html │ │ │ │ │ ├── arm__power__q15_8c.html │ │ │ │ │ ├── arm__power__q31_8c.html │ │ │ │ │ ├── arm__power__q7_8c.html │ │ │ │ │ ├── arm__q15__to__f16_8c.html │ │ │ │ │ ├── arm__q15__to__float_8c.html │ │ │ │ │ ├── arm__q15__to__q31_8c.html │ │ │ │ │ ├── arm__q15__to__q7_8c.html │ │ │ │ │ ├── arm__q31__to__float_8c.html │ │ │ │ │ ├── arm__q31__to__q15_8c.html │ │ │ │ │ ├── arm__q31__to__q7_8c.html │ │ │ │ │ ├── arm__q7__to__float_8c.html │ │ │ │ │ ├── arm__q7__to__q15_8c.html │ │ │ │ │ ├── arm__q7__to__q31_8c.html │ │ │ │ │ ├── arm__quaternion2rotation__f32_8c.html │ │ │ │ │ ├── arm__quaternion__conjugate__f32_8c.html │ │ │ │ │ ├── arm__quaternion__inverse__f32_8c.html │ │ │ │ │ ├── arm__quaternion__norm__f32_8c.html │ │ │ │ │ ├── arm__quaternion__normalize__f32_8c.html │ │ │ │ │ ├── arm__quaternion__product__f32_8c.html │ │ │ │ │ ├── arm__quaternion__product__single__f32_8c.html │ │ │ │ │ ├── arm__quick__sort__f32_8c.html │ │ │ │ │ ├── arm__rfft__f32_8c.html │ │ │ │ │ ├── arm__rfft__fast__f16_8c.html │ │ │ │ │ ├── arm__rfft__fast__f32_8c.html │ │ │ │ │ ├── arm__rfft__fast__f64_8c.html │ │ │ │ │ ├── arm__rfft__fast__init__f16_8c.html │ │ │ │ │ ├── arm__rfft__fast__init__f32_8c.html │ │ │ │ │ ├── arm__rfft__fast__init__f64_8c.html │ │ │ │ │ ├── arm__rfft__init__f32_8c.html │ │ │ │ │ ├── arm__rfft__init__q15_8c.html │ │ │ │ │ ├── arm__rfft__init__q31_8c.html │ │ │ │ │ ├── arm__rfft__q15_8c.html │ │ │ │ │ ├── arm__rfft__q31_8c.html │ │ │ │ │ ├── arm__rms__f16_8c.html │ │ │ │ │ ├── arm__rms__f32_8c.html │ │ │ │ │ ├── arm__rms__q15_8c.html │ │ │ │ │ ├── arm__rms__q31_8c.html │ │ │ │ │ ├── arm__rogerstanimoto__distance_8c.html │ │ │ │ │ ├── arm__rotation2quaternion__f32_8c.html │ │ │ │ │ ├── arm__russellrao__distance_8c.html │ │ │ │ │ ├── arm__scale__f16_8c.html │ │ │ │ │ ├── arm__scale__f32_8c.html │ │ │ │ │ ├── arm__scale__f64_8c.html │ │ │ │ │ ├── arm__scale__q15_8c.html │ │ │ │ │ ├── arm__scale__q31_8c.html │ │ │ │ │ ├── arm__scale__q7_8c.html │ │ │ │ │ ├── arm__selection__sort__f32_8c.html │ │ │ │ │ ├── arm__shift__q15_8c.html │ │ │ │ │ ├── arm__shift__q31_8c.html │ │ │ │ │ ├── arm__shift__q7_8c.html │ │ │ │ │ ├── arm__signal__converge__data_8c.html │ │ │ │ │ ├── arm__signal__converge__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__signal__converge__example_2math__helper_8c.html │ │ │ │ │ ├── arm__signal__converge__example_2math__helper_8h.html │ │ │ │ │ ├── arm__signal__converge__example__f32_8c.html │ │ │ │ │ ├── arm__sin__cos__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__sin__cos__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__sin__cos__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__sin__cos__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__sin__cos__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__sin__cos__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__sin__cos__example__f32_8c.html │ │ │ │ │ ├── arm__sin__cos__f32_8c.html │ │ │ │ │ ├── arm__sin__cos__q31_8c.html │ │ │ │ │ ├── arm__sin__f32_8c.html │ │ │ │ │ ├── arm__sin__q15_8c.html │ │ │ │ │ ├── arm__sin__q31_8c.html │ │ │ │ │ ├── arm__sokalmichener__distance_8c.html │ │ │ │ │ ├── arm__sokalsneath__distance_8c.html │ │ │ │ │ ├── arm__sort__f32_8c.html │ │ │ │ │ ├── arm__sort__init__f32_8c.html │ │ │ │ │ ├── arm__spline__interp__f32_8c.html │ │ │ │ │ ├── arm__spline__interp__init__f32_8c.html │ │ │ │ │ ├── arm__sqrt__q15_8c.html │ │ │ │ │ ├── arm__sqrt__q31_8c.html │ │ │ │ │ ├── arm__std__f16_8c.html │ │ │ │ │ ├── arm__std__f32_8c.html │ │ │ │ │ ├── arm__std__f64_8c.html │ │ │ │ │ ├── arm__std__q15_8c.html │ │ │ │ │ ├── arm__std__q31_8c.html │ │ │ │ │ ├── arm__sub__f16_8c.html │ │ │ │ │ ├── arm__sub__f32_8c.html │ │ │ │ │ ├── arm__sub__f64_8c.html │ │ │ │ │ ├── arm__sub__q15_8c.html │ │ │ │ │ ├── arm__sub__q31_8c.html │ │ │ │ │ ├── arm__sub__q7_8c.html │ │ │ │ │ ├── arm__svm__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__svm__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__svm__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__svm__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__svm__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__svm__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__svm__example_2train_8py.html │ │ │ │ │ ├── arm__svm__example__f32_8c.html │ │ │ │ │ ├── arm__svm__linear__init__f16_8c.html │ │ │ │ │ ├── arm__svm__linear__init__f32_8c.html │ │ │ │ │ ├── arm__svm__linear__predict__f16_8c.html │ │ │ │ │ ├── arm__svm__linear__predict__f32_8c.html │ │ │ │ │ ├── arm__svm__polynomial__init__f16_8c.html │ │ │ │ │ ├── arm__svm__polynomial__init__f32_8c.html │ │ │ │ │ ├── arm__svm__polynomial__predict__f16_8c.html │ │ │ │ │ ├── arm__svm__polynomial__predict__f32_8c.html │ │ │ │ │ ├── arm__svm__rbf__init__f16_8c.html │ │ │ │ │ ├── arm__svm__rbf__init__f32_8c.html │ │ │ │ │ ├── arm__svm__rbf__predict__f16_8c.html │ │ │ │ │ ├── arm__svm__rbf__predict__f32_8c.html │ │ │ │ │ ├── arm__svm__sigmoid__init__f16_8c.html │ │ │ │ │ ├── arm__svm__sigmoid__init__f32_8c.html │ │ │ │ │ ├── arm__svm__sigmoid__predict__f16_8c.html │ │ │ │ │ ├── arm__svm__sigmoid__predict__f32_8c.html │ │ │ │ │ ├── arm__var__f16_8c.html │ │ │ │ │ ├── arm__var__f32_8c.html │ │ │ │ │ ├── arm__var__f64_8c.html │ │ │ │ │ ├── arm__var__q15_8c.html │ │ │ │ │ ├── arm__var__q31_8c.html │ │ │ │ │ ├── arm__variance__example_2ARMCM0__config_8txt.html │ │ │ │ │ ├── arm__variance__example_2ARMCM3__config_8txt.html │ │ │ │ │ ├── arm__variance__example_2ARMCM4__FP__config_8txt.html │ │ │ │ │ ├── arm__variance__example_2ARMCM55__FP__MVE__config_8txt.html │ │ │ │ │ ├── arm__variance__example_2ARMCM7__SP__config_8txt.html │ │ │ │ │ ├── arm__variance__example_2Abstract_8txt.html │ │ │ │ │ ├── arm__variance__example__f32_8c.html │ │ │ │ │ ├── arm__vec__math_8h.html │ │ │ │ │ ├── arm__vec__math__f16_8h.html │ │ │ │ │ ├── arm__vexp__f16_8c.html │ │ │ │ │ ├── arm__vexp__f32_8c.html │ │ │ │ │ ├── arm__vexp__f64_8c.html │ │ │ │ │ ├── arm__vinverse__f16_8c.html │ │ │ │ │ ├── arm__vlog__f16_8c.html │ │ │ │ │ ├── arm__vlog__f32_8c.html │ │ │ │ │ ├── arm__vlog__f64_8c.html │ │ │ │ │ ├── arm__vlog__q15_8c.html │ │ │ │ │ ├── arm__vlog__q31_8c.html │ │ │ │ │ ├── arm__weighted__sum__f16_8c.html │ │ │ │ │ ├── arm__weighted__sum__f32_8c.html │ │ │ │ │ ├── arm__xor__u16_8c.html │ │ │ │ │ ├── arm__xor__u32_8c.html │ │ │ │ │ ├── arm__xor__u8_8c.html │ │ │ │ │ ├── arm__yule__distance_8c.html │ │ │ │ │ ├── arm_bayes_example_f32_8c-example.html │ │ │ │ │ ├── arm_class_marks_example_f32_8c-example.html │ │ │ │ │ ├── arm_convolution_example_f32_8c-example.html │ │ │ │ │ ├── arm_dotproduct_example_f32_8c-example.html │ │ │ │ │ ├── arm_fft_bin_example_f32_8c-example.html │ │ │ │ │ ├── arm_fir_example_f32_8c-example.html │ │ │ │ │ ├── arm_graphic_equalizer_example_q31_8c-example.html │ │ │ │ │ ├── arm_linear_interp_example_f32_8c-example.html │ │ │ │ │ ├── arm_matrix_example_f32_8c-example.html │ │ │ │ │ ├── arm_signal_converge_example_f32_8c-example.html │ │ │ │ │ ├── arm_sin_cos_example_f32_8c-example.html │ │ │ │ │ ├── arm_svm_example_f32_8c-example.html │ │ │ │ │ ├── arm_variance_example_f32_8c-example.html │ │ │ │ │ ├── basic__math__functions_8h.html │ │ │ │ │ ├── basic__math__functions__f16_8h.html │ │ │ │ │ ├── bayes__functions_8h.html │ │ │ │ │ ├── bayes__functions__f16_8h.html │ │ │ │ │ ├── classes.html │ │ │ │ │ ├── cmsis.css │ │ │ │ │ ├── complex__math__functions_8h.html │ │ │ │ │ ├── complex__math__functions__f16_8h.html │ │ │ │ │ ├── controller__functions_8h.html │ │ │ │ │ ├── controller__functions__f16_8h.html │ │ │ │ │ ├── deprecated.html │ │ │ │ │ ├── distance__functions_8h.html │ │ │ │ │ ├── distance__functions__f16_8h.html │ │ │ │ │ ├── doxygen.css │ │ │ │ │ ├── dynsections.js │ │ │ │ │ ├── examples.html │ │ │ │ │ ├── fast__math__functions_8h.html │ │ │ │ │ ├── fast__math__functions__f16_8h.html │ │ │ │ │ ├── files.html │ │ │ │ │ ├── filtering__functions_8h.html │ │ │ │ │ ├── filtering__functions__f16_8h.html │ │ │ │ │ ├── footer.js │ │ │ │ │ ├── functions.html │ │ │ │ │ ├── functions_b.html │ │ │ │ │ ├── functions_c.html │ │ │ │ │ ├── functions_d.html │ │ │ │ │ ├── functions_e.html │ │ │ │ │ ├── functions_f.html │ │ │ │ │ ├── functions_g.html │ │ │ │ │ ├── functions_i.html │ │ │ │ │ ├── functions_k.html │ │ │ │ │ ├── functions_l.html │ │ │ │ │ ├── functions_m.html │ │ │ │ │ ├── functions_n.html │ │ │ │ │ ├── functions_o.html │ │ │ │ │ ├── functions_p.html │ │ │ │ │ ├── functions_r.html │ │ │ │ │ ├── functions_s.html │ │ │ │ │ ├── functions_t.html │ │ │ │ │ ├── functions_v.html │ │ │ │ │ ├── functions_vars.html │ │ │ │ │ ├── functions_vars_b.html │ │ │ │ │ ├── functions_vars_c.html │ │ │ │ │ ├── functions_vars_d.html │ │ │ │ │ ├── functions_vars_e.html │ │ │ │ │ ├── functions_vars_f.html │ │ │ │ │ ├── functions_vars_g.html │ │ │ │ │ ├── functions_vars_i.html │ │ │ │ │ ├── functions_vars_k.html │ │ │ │ │ ├── functions_vars_l.html │ │ │ │ │ ├── functions_vars_m.html │ │ │ │ │ ├── functions_vars_n.html │ │ │ │ │ ├── functions_vars_o.html │ │ │ │ │ ├── functions_vars_p.html │ │ │ │ │ ├── functions_vars_r.html │ │ │ │ │ ├── functions_vars_s.html │ │ │ │ │ ├── functions_vars_t.html │ │ │ │ │ ├── functions_vars_v.html │ │ │ │ │ ├── functions_vars_w.html │ │ │ │ │ ├── functions_vars_x.html │ │ │ │ │ ├── functions_vars_y.html │ │ │ │ │ ├── functions_w.html │ │ │ │ │ ├── functions_x.html │ │ │ │ │ ├── functions_y.html │ │ │ │ │ ├── globals.html │ │ │ │ │ ├── globals_a.html │ │ │ │ │ ├── globals_b.html │ │ │ │ │ ├── globals_c.html │ │ │ │ │ ├── globals_d.html │ │ │ │ │ ├── globals_defs.html │ │ │ │ │ ├── globals_e.html │ │ │ │ │ ├── globals_enum.html │ │ │ │ │ ├── globals_eval.html │ │ │ │ │ ├── globals_f.html │ │ │ │ │ ├── globals_func.html │ │ │ │ │ ├── globals_func_a.html │ │ │ │ │ ├── globals_func_b.html │ │ │ │ │ ├── globals_func_c.html │ │ │ │ │ ├── globals_func_d.html │ │ │ │ │ ├── globals_func_e.html │ │ │ │ │ ├── globals_func_f.html │ │ │ │ │ ├── globals_func_g.html │ │ │ │ │ ├── globals_func_h.html │ │ │ │ │ ├── globals_func_i.html │ │ │ │ │ ├── globals_func_j.html │ │ │ │ │ ├── globals_func_k.html │ │ │ │ │ ├── globals_func_l.html │ │ │ │ │ ├── globals_func_m.html │ │ │ │ │ ├── globals_func_n.html │ │ │ │ │ ├── globals_func_o.html │ │ │ │ │ ├── globals_func_p.html │ │ │ │ │ ├── globals_func_q.html │ │ │ │ │ ├── globals_func_r.html │ │ │ │ │ ├── globals_func_s.html │ │ │ │ │ ├── globals_func_t.html │ │ │ │ │ ├── globals_func_v.html │ │ │ │ │ ├── globals_func_w.html │ │ │ │ │ ├── globals_func_x.html │ │ │ │ │ ├── globals_func_y.html │ │ │ │ │ ├── globals_g.html │ │ │ │ │ ├── globals_h.html │ │ │ │ │ ├── globals_i.html │ │ │ │ │ ├── globals_j.html │ │ │ │ │ ├── globals_k.html │ │ │ │ │ ├── globals_l.html │ │ │ │ │ ├── globals_m.html │ │ │ │ │ ├── globals_n.html │ │ │ │ │ ├── globals_o.html │ │ │ │ │ ├── globals_p.html │ │ │ │ │ ├── globals_q.html │ │ │ │ │ ├── globals_r.html │ │ │ │ │ ├── globals_s.html │ │ │ │ │ ├── globals_t.html │ │ │ │ │ ├── globals_type.html │ │ │ │ │ ├── globals_u.html │ │ │ │ │ ├── globals_v.html │ │ │ │ │ ├── globals_vars.html │ │ │ │ │ ├── globals_vars_b.html │ │ │ │ │ ├── globals_vars_c.html │ │ │ │ │ ├── globals_vars_d.html │ │ │ │ │ ├── globals_vars_e.html │ │ │ │ │ ├── globals_vars_f.html │ │ │ │ │ ├── globals_vars_g.html │ │ │ │ │ ├── globals_vars_i.html │ │ │ │ │ ├── globals_vars_l.html │ │ │ │ │ ├── globals_vars_m.html │ │ │ │ │ ├── globals_vars_n.html │ │ │ │ │ ├── globals_vars_o.html │ │ │ │ │ ├── globals_vars_p.html │ │ │ │ │ ├── globals_vars_r.html │ │ │ │ │ ├── globals_vars_s.html │ │ │ │ │ ├── globals_vars_t.html │ │ │ │ │ ├── globals_vars_v.html │ │ │ │ │ ├── globals_vars_w.html │ │ │ │ │ ├── globals_vars_x.html │ │ │ │ │ ├── globals_w.html │ │ │ │ │ ├── globals_x.html │ │ │ │ │ ├── globals_y.html │ │ │ │ │ ├── group__AbsMax.html │ │ │ │ │ ├── group__AbsMin.html │ │ │ │ │ ├── group__And.html │ │ │ │ │ ├── group__BasicAbs.html │ │ │ │ │ ├── group__BasicAdd.html │ │ │ │ │ ├── group__BasicClip.html │ │ │ │ │ ├── group__BasicDotProd.html │ │ │ │ │ ├── group__BasicMult.html │ │ │ │ │ ├── group__BasicNegate.html │ │ │ │ │ ├── group__BasicOffset.html │ │ │ │ │ ├── group__BasicScale.html │ │ │ │ │ ├── group__BasicShift.html │ │ │ │ │ ├── group__BasicSub.html │ │ │ │ │ ├── group__BayesExample.html │ │ │ │ │ ├── group__BilinearInterpolate.html │ │ │ │ │ ├── group__BiquadCascadeDF1.html │ │ │ │ │ ├── group__BiquadCascadeDF1__32x64.html │ │ │ │ │ ├── group__BiquadCascadeDF2T.html │ │ │ │ │ ├── group__BoolDist.html │ │ │ │ │ ├── group__CFFT__CIFFT.html │ │ │ │ │ ├── group__Canberra.html │ │ │ │ │ ├── group__Chebyshev.html │ │ │ │ │ ├── group__ClassMarks.html │ │ │ │ │ ├── group__CmplxByCmplxMult.html │ │ │ │ │ ├── group__CmplxByRealMult.html │ │ │ │ │ ├── group__CmplxMatrixMult.html │ │ │ │ │ ├── group__ComplexFFT.html │ │ │ │ │ ├── group__Conv.html │ │ │ │ │ ├── group__ConvolutionExample.html │ │ │ │ │ ├── group__Corr.html │ │ │ │ │ ├── group__Correlation.html │ │ │ │ │ ├── group__CosineDist.html │ │ │ │ │ ├── group__DCT4__IDCT4.html │ │ │ │ │ ├── group__DCT4__IDCT4__Table.html │ │ │ │ │ ├── group__DotproductExample.html │ │ │ │ │ ├── group__Entropy.html │ │ │ │ │ ├── group__Euclidean.html │ │ │ │ │ ├── group__FIR.html │ │ │ │ │ ├── group__FIRLPF.html │ │ │ │ │ ├── group__FIR__Interpolate.html │ │ │ │ │ ├── group__FIR__Lattice.html │ │ │ │ │ ├── group__FIR__Sparse.html │ │ │ │ │ ├── group__FIR__decimate.html │ │ │ │ │ ├── group__Fill.html │ │ │ │ │ ├── group__FloatDist.html │ │ │ │ │ ├── group__FrequencyBin.html │ │ │ │ │ ├── group__GEQ5Band.html │ │ │ │ │ ├── group__IIR__Lattice.html │ │ │ │ │ ├── group__JensenShannon.html │ │ │ │ │ ├── group__Kullback-Leibler.html │ │ │ │ │ ├── group__LD.html │ │ │ │ │ ├── group__LMS.html │ │ │ │ │ ├── group__LMS__NORM.html │ │ │ │ │ ├── group__LinearInterpExample.html │ │ │ │ │ ├── group__LinearInterpolate.html │ │ │ │ │ ├── group__LogSumExp.html │ │ │ │ │ ├── group__MFCC.html │ │ │ │ │ ├── group__MSE.html │ │ │ │ │ ├── group__Manhattan.html │ │ │ │ │ ├── group__MatrixAdd.html │ │ │ │ │ ├── group__MatrixChol.html │ │ │ │ │ ├── group__MatrixComplexTrans.html │ │ │ │ │ ├── group__MatrixExample.html │ │ │ │ │ ├── group__MatrixInit.html │ │ │ │ │ ├── group__MatrixInv.html │ │ │ │ │ ├── group__MatrixMult.html │ │ │ │ │ ├── group__MatrixScale.html │ │ │ │ │ ├── group__MatrixSub.html │ │ │ │ │ ├── group__MatrixTrans.html │ │ │ │ │ ├── group__MatrixVectMult.html │ │ │ │ │ ├── group__Max.html │ │ │ │ │ ├── group__Min.html │ │ │ │ │ ├── group__Minkowski.html │ │ │ │ │ ├── group__Not.html │ │ │ │ │ ├── group__Or.html │ │ │ │ │ ├── group__PID.html │ │ │ │ │ ├── group__PartialConv.html │ │ │ │ │ ├── group__QuatConjugate.html │ │ │ │ │ ├── group__QuatConv.html │ │ │ │ │ ├── group__QuatInverse.html │ │ │ │ │ ├── group__QuatNorm.html │ │ │ │ │ ├── group__QuatNormalized.html │ │ │ │ │ ├── group__QuatProd.html │ │ │ │ │ ├── group__QuatProdSingle.html │ │ │ │ │ ├── group__QuatProdVect.html │ │ │ │ │ ├── group__QuatRot.html │ │ │ │ │ ├── group__RMS.html │ │ │ │ │ ├── group__RealFFT.html │ │ │ │ │ ├── group__RealFFT__Table.html │ │ │ │ │ ├── group__RotQuat.html │ │ │ │ │ ├── group__SQRT.html │ │ │ │ │ ├── group__STD.html │ │ │ │ │ ├── group__SVMExample.html │ │ │ │ │ ├── group__SignalConvergence.html │ │ │ │ │ ├── group__SinCos.html │ │ │ │ │ ├── group__SinCosExample.html │ │ │ │ │ ├── group__Sorting.html │ │ │ │ │ ├── group__SplineInterpolate.html │ │ │ │ │ ├── group__VarianceExample.html │ │ │ │ │ ├── group__Xor.html │ │ │ │ │ ├── group__atan2.html │ │ │ │ │ ├── group__barycenter.html │ │ │ │ │ ├── group__braycurtis.html │ │ │ │ │ ├── group__clarke.html │ │ │ │ │ ├── group__cmplx__conj.html │ │ │ │ │ ├── group__cmplx__dot__prod.html │ │ │ │ │ ├── group__cmplx__mag.html │ │ │ │ │ ├── group__cmplx__mag__squared.html │ │ │ │ │ ├── group__copy.html │ │ │ │ │ ├── group__cos.html │ │ │ │ │ ├── group__divide.html │ │ │ │ │ ├── group__f16__to__x.html │ │ │ │ │ ├── group__float__to__x.html │ │ │ │ │ ├── group__groupBayes.html │ │ │ │ │ ├── group__groupCmplxMath.html │ │ │ │ │ ├── group__groupController.html │ │ │ │ │ ├── group__groupDistance.html │ │ │ │ │ ├── group__groupExamples.html │ │ │ │ │ ├── group__groupFastMath.html │ │ │ │ │ ├── group__groupFilters.html │ │ │ │ │ ├── group__groupInterpolation.html │ │ │ │ │ ├── group__groupMath.html │ │ │ │ │ ├── group__groupMatrix.html │ │ │ │ │ ├── group__groupQuaternionMath.html │ │ │ │ │ ├── group__groupSVM.html │ │ │ │ │ ├── group__groupStats.html │ │ │ │ │ ├── group__groupSupport.html │ │ │ │ │ ├── group__groupTransforms.html │ │ │ │ │ ├── group__inv__clarke.html │ │ │ │ │ ├── group__inv__park.html │ │ │ │ │ ├── group__linearsvm.html │ │ │ │ │ ├── group__mean.html │ │ │ │ │ ├── group__park.html │ │ │ │ │ ├── group__polysvm.html │ │ │ │ │ ├── group__power.html │ │ │ │ │ ├── group__q15__to__x.html │ │ │ │ │ ├── group__q31__to__x.html │ │ │ │ │ ├── group__q7__to__x.html │ │ │ │ │ ├── group__rbfsvm.html │ │ │ │ │ ├── group__sigmoidsvm.html │ │ │ │ │ ├── group__sin.html │ │ │ │ │ ├── group__typecast.html │ │ │ │ │ ├── group__variance.html │ │ │ │ │ ├── group__vlog.html │ │ │ │ │ ├── group__weightedsum.html │ │ │ │ │ ├── history_8txt.html │ │ │ │ │ ├── index.html │ │ │ │ │ ├── index.html.bak │ │ │ │ │ ├── interpolation__functions_8h.html │ │ │ │ │ ├── interpolation__functions__f16_8h.html │ │ │ │ │ ├── jquery.js │ │ │ │ │ ├── matrix__functions_8h.html │ │ │ │ │ ├── matrix__functions__f16_8h.html │ │ │ │ │ ├── matrix__utils_8h.html │ │ │ │ │ ├── modules.html │ │ │ │ │ ├── namespacemembers.html │ │ │ │ │ ├── namespacemembers_vars.html │ │ │ │ │ ├── namespaces.html │ │ │ │ │ ├── namespacetrain.html │ │ │ │ │ ├── navtree.css │ │ │ │ │ ├── navtree.js │ │ │ │ │ ├── navtreeindex0.js │ │ │ │ │ ├── none_8h.html │ │ │ │ │ ├── pages.html │ │ │ │ │ ├── printComponentTabs.js │ │ │ │ │ ├── quaternion__math__functions_8h.html │ │ │ │ │ ├── resize.js │ │ │ │ │ ├── search/ │ │ │ │ │ │ ├── all_0.html │ │ │ │ │ │ ├── all_0.js │ │ │ │ │ │ ├── all_1.html │ │ │ │ │ │ ├── all_1.js │ │ │ │ │ │ ├── all_10.html │ │ │ │ │ │ ├── all_10.js │ │ │ │ │ │ ├── all_11.html │ │ │ │ │ │ ├── all_11.js │ │ │ │ │ │ ├── all_12.html │ │ │ │ │ │ ├── all_12.js │ │ │ │ │ │ ├── all_13.html │ │ │ │ │ │ ├── all_13.js │ │ │ │ │ │ ├── all_14.html │ │ │ │ │ │ ├── all_14.js │ │ │ │ │ │ ├── all_15.html │ │ │ │ │ │ ├── all_15.js │ │ │ │ │ │ ├── all_16.html │ │ │ │ │ │ ├── all_16.js │ │ │ │ │ │ ├── all_17.html │ │ │ │ │ │ ├── all_17.js │ │ │ │ │ │ ├── all_18.html │ │ │ │ │ │ ├── all_18.js │ │ │ │ │ │ ├── all_19.html │ │ │ │ │ │ ├── all_19.js │ │ │ │ │ │ ├── all_1a.html │ │ │ │ │ │ ├── all_1a.js │ │ │ │ │ │ ├── all_2.html │ │ │ │ │ │ ├── all_2.js │ │ │ │ │ │ ├── all_3.html │ │ │ │ │ │ ├── all_3.js │ │ │ │ │ │ ├── all_4.html │ │ │ │ │ │ ├── all_4.js │ │ │ │ │ │ ├── all_5.html │ │ │ │ │ │ ├── all_5.js │ │ │ │ │ │ ├── all_6.html │ │ │ │ │ │ ├── all_6.js │ │ │ │ │ │ ├── all_7.html │ │ │ │ │ │ ├── all_7.js │ │ │ │ │ │ ├── all_8.html │ │ │ │ │ │ ├── all_8.js │ │ │ │ │ │ ├── all_9.html │ │ │ │ │ │ ├── all_9.js │ │ │ │ │ │ ├── all_a.html │ │ │ │ │ │ ├── all_a.js │ │ │ │ │ │ ├── all_b.html │ │ │ │ │ │ ├── all_b.js │ │ │ │ │ │ ├── all_c.html │ │ │ │ │ │ ├── all_c.js │ │ │ │ │ │ ├── all_d.html │ │ │ │ │ │ ├── all_d.js │ │ │ │ │ │ ├── all_e.html │ │ │ │ │ │ ├── all_e.js │ │ │ │ │ │ ├── all_f.html │ │ │ │ │ │ ├── all_f.js │ │ │ │ │ │ ├── classes_0.html │ │ │ │ │ │ ├── classes_0.js │ │ │ │ │ │ ├── defines_0.html │ │ │ │ │ │ ├── defines_0.js │ │ │ │ │ │ ├── defines_1.html │ │ │ │ │ │ ├── defines_1.js │ │ │ │ │ │ ├── defines_10.html │ │ │ │ │ │ ├── defines_10.js │ │ │ │ │ │ ├── defines_11.html │ │ │ │ │ │ ├── defines_11.js │ │ │ │ │ │ ├── defines_12.html │ │ │ │ │ │ ├── defines_12.js │ │ │ │ │ │ ├── defines_13.html │ │ │ │ │ │ ├── defines_13.js │ │ │ │ │ │ ├── defines_14.html │ │ │ │ │ │ ├── defines_14.js │ │ │ │ │ │ ├── defines_15.html │ │ │ │ │ │ ├── defines_15.js │ │ │ │ │ │ ├── defines_2.html │ │ │ │ │ │ ├── defines_2.js │ │ │ │ │ │ ├── defines_3.html │ │ │ │ │ │ ├── defines_3.js │ │ │ │ │ │ ├── defines_4.html │ │ │ │ │ │ ├── defines_4.js │ │ │ │ │ │ ├── defines_5.html │ │ │ │ │ │ ├── defines_5.js │ │ │ │ │ │ ├── defines_6.html │ │ │ │ │ │ ├── defines_6.js │ │ │ │ │ │ ├── defines_7.html │ │ │ │ │ │ ├── defines_7.js │ │ │ │ │ │ ├── defines_8.html │ │ │ │ │ │ ├── defines_8.js │ │ │ │ │ │ ├── defines_9.html │ │ │ │ │ │ ├── defines_9.js │ │ │ │ │ │ ├── defines_a.html │ │ │ │ │ │ ├── defines_a.js │ │ │ │ │ │ ├── defines_b.html │ │ │ │ │ │ ├── defines_b.js │ │ │ │ │ │ ├── defines_c.html │ │ │ │ │ │ ├── defines_c.js │ │ │ │ │ │ ├── defines_d.html │ │ │ │ │ │ ├── defines_d.js │ │ │ │ │ │ ├── defines_e.html │ │ │ │ │ │ ├── defines_e.js │ │ │ │ │ │ ├── defines_f.html │ │ │ │ │ │ ├── defines_f.js │ │ │ │ │ │ ├── enums_0.html │ │ │ │ │ │ ├── enums_0.js │ │ │ │ │ │ ├── enumvalues_0.html │ │ │ │ │ │ ├── enumvalues_0.js │ │ │ │ │ │ ├── files_0.html │ │ │ │ │ │ ├── files_0.js │ │ │ │ │ │ ├── files_1.html │ │ │ │ │ │ ├── files_1.js │ │ │ │ │ │ ├── files_2.html │ │ │ │ │ │ ├── files_2.js │ │ │ │ │ │ ├── files_3.html │ │ │ │ │ │ ├── files_3.js │ │ │ │ │ │ ├── files_4.html │ │ │ │ │ │ ├── files_4.js │ │ │ │ │ │ ├── files_5.html │ │ │ │ │ │ ├── files_5.js │ │ │ │ │ │ ├── files_6.html │ │ │ │ │ │ ├── files_6.js │ │ │ │ │ │ ├── files_7.html │ │ │ │ │ │ ├── files_7.js │ │ │ │ │ │ ├── files_8.html │ │ │ │ │ │ ├── files_8.js │ │ │ │ │ │ ├── files_9.html │ │ │ │ │ │ ├── files_9.js │ │ │ │ │ │ ├── files_a.html │ │ │ │ │ │ ├── files_a.js │ │ │ │ │ │ ├── files_b.html │ │ │ │ │ │ ├── files_b.js │ │ │ │ │ │ ├── files_c.html │ │ │ │ │ │ ├── files_c.js │ │ │ │ │ │ ├── files_d.html │ │ │ │ │ │ ├── files_d.js │ │ │ │ │ │ ├── functions_0.html │ │ │ │ │ │ ├── functions_0.js │ │ │ │ │ │ ├── functions_1.html │ │ │ │ │ │ ├── functions_1.js │ │ │ │ │ │ ├── functions_2.html │ │ │ │ │ │ ├── functions_2.js │ │ │ │ │ │ ├── functions_3.html │ │ │ │ │ │ ├── functions_3.js │ │ │ │ │ │ ├── functions_4.html │ │ │ │ │ │ ├── functions_4.js │ │ │ │ │ │ ├── functions_5.html │ │ │ │ │ │ ├── functions_5.js │ │ │ │ │ │ ├── functions_6.html │ │ │ │ │ │ ├── functions_6.js │ │ │ │ │ │ ├── functions_7.html │ │ │ │ │ │ ├── functions_7.js │ │ │ │ │ │ ├── functions_8.html │ │ │ │ │ │ ├── functions_8.js │ │ │ │ │ │ ├── functions_9.html │ │ │ │ │ │ ├── functions_9.js │ │ │ │ │ │ ├── functions_a.html │ │ │ │ │ │ ├── functions_a.js │ │ │ │ │ │ ├── functions_b.html │ │ │ │ │ │ ├── functions_b.js │ │ │ │ │ │ ├── functions_c.html │ │ │ │ │ │ ├── functions_c.js │ │ │ │ │ │ ├── groups_0.html │ │ │ │ │ │ ├── groups_0.js │ │ │ │ │ │ ├── groups_1.html │ │ │ │ │ │ ├── groups_1.js │ │ │ │ │ │ ├── groups_10.html │ │ │ │ │ │ ├── groups_10.js │ │ │ │ │ │ ├── groups_11.html │ │ │ │ │ │ ├── groups_11.js │ │ │ │ │ │ ├── groups_12.html │ │ │ │ │ │ ├── groups_12.js │ │ │ │ │ │ ├── groups_13.html │ │ │ │ │ │ ├── groups_13.js │ │ │ │ │ │ ├── groups_14.html │ │ │ │ │ │ ├── groups_14.js │ │ │ │ │ │ ├── groups_2.html │ │ │ │ │ │ ├── groups_2.js │ │ │ │ │ │ ├── groups_3.html │ │ │ │ │ │ ├── groups_3.js │ │ │ │ │ │ ├── groups_4.html │ │ │ │ │ │ ├── groups_4.js │ │ │ │ │ │ ├── groups_5.html │ │ │ │ │ │ ├── groups_5.js │ │ │ │ │ │ ├── groups_6.html │ │ │ │ │ │ ├── groups_6.js │ │ │ │ │ │ ├── groups_7.html │ │ │ │ │ │ ├── groups_7.js │ │ │ │ │ │ ├── groups_8.html │ │ │ │ │ │ ├── groups_8.js │ │ │ │ │ │ ├── groups_9.html │ │ │ │ │ │ ├── groups_9.js │ │ │ │ │ │ ├── groups_a.html │ │ │ │ │ │ ├── groups_a.js │ │ │ │ │ │ ├── groups_b.html │ │ │ │ │ │ ├── groups_b.js │ │ │ │ │ │ ├── groups_c.html │ │ │ │ │ │ ├── groups_c.js │ │ │ │ │ │ ├── groups_d.html │ │ │ │ │ │ ├── groups_d.js │ │ │ │ │ │ ├── groups_e.html │ │ │ │ │ │ ├── groups_e.js │ │ │ │ │ │ ├── groups_f.html │ │ │ │ │ │ ├── groups_f.js │ │ │ │ │ │ ├── namespaces_0.html │ │ │ │ │ │ ├── namespaces_0.js │ │ │ │ │ │ ├── nomatches.html │ │ │ │ │ │ ├── pages_0.html │ │ │ │ │ │ ├── pages_0.js │ │ │ │ │ │ ├── pages_1.html │ │ │ │ │ │ ├── pages_1.js │ │ │ │ │ │ ├── pages_2.html │ │ │ │ │ │ ├── pages_2.js │ │ │ │ │ │ ├── search.css │ │ │ │ │ │ ├── search.js │ │ │ │ │ │ ├── search.js.bak │ │ │ │ │ │ ├── typedefs_0.html │ │ │ │ │ │ ├── typedefs_0.js │ │ │ │ │ │ ├── typedefs_1.html │ │ │ │ │ │ ├── typedefs_1.js │ │ │ │ │ │ ├── typedefs_2.html │ │ │ │ │ │ ├── typedefs_2.js │ │ │ │ │ │ ├── variables_0.html │ │ │ │ │ │ ├── variables_0.js │ │ │ │ │ │ ├── variables_1.html │ │ │ │ │ │ ├── variables_1.js │ │ │ │ │ │ ├── variables_10.html │ │ │ │ │ │ ├── variables_10.js │ │ │ │ │ │ ├── variables_11.html │ │ │ │ │ │ ├── variables_11.js │ │ │ │ │ │ ├── variables_12.html │ │ │ │ │ │ ├── variables_12.js │ │ │ │ │ │ ├── variables_13.html │ │ │ │ │ │ ├── variables_13.js │ │ │ │ │ │ ├── variables_14.html │ │ │ │ │ │ ├── variables_14.js │ │ │ │ │ │ ├── variables_15.html │ │ │ │ │ │ ├── variables_15.js │ │ │ │ │ │ ├── variables_2.html │ │ │ │ │ │ ├── variables_2.js │ │ │ │ │ │ ├── variables_3.html │ │ │ │ │ │ ├── variables_3.js │ │ │ │ │ │ ├── variables_4.html │ │ │ │ │ │ ├── variables_4.js │ │ │ │ │ │ ├── variables_5.html │ │ │ │ │ │ ├── variables_5.js │ │ │ │ │ │ ├── variables_6.html │ │ │ │ │ │ ├── variables_6.js │ │ │ │ │ │ ├── variables_7.html │ │ │ │ │ │ ├── variables_7.js │ │ │ │ │ │ ├── variables_8.html │ │ │ │ │ │ ├── variables_8.js │ │ │ │ │ │ ├── variables_9.html │ │ │ │ │ │ ├── variables_9.js │ │ │ │ │ │ ├── variables_a.html │ │ │ │ │ │ ├── variables_a.js │ │ │ │ │ │ ├── variables_b.html │ │ │ │ │ │ ├── variables_b.js │ │ │ │ │ │ ├── variables_c.html │ │ │ │ │ │ ├── variables_c.js │ │ │ │ │ │ ├── variables_d.html │ │ │ │ │ │ ├── variables_d.js │ │ │ │ │ │ ├── variables_e.html │ │ │ │ │ │ ├── variables_e.js │ │ │ │ │ │ ├── variables_f.html │ │ │ │ │ │ └── variables_f.js │ │ │ │ │ ├── statistics__functions_8h.html │ │ │ │ │ ├── statistics__functions__f16_8h.html │ │ │ │ │ ├── structarm__bilinear__interp__instance__f16.html │ │ │ │ │ ├── structarm__bilinear__interp__instance__f32.html │ │ │ │ │ ├── structarm__bilinear__interp__instance__q15.html │ │ │ │ │ ├── structarm__bilinear__interp__instance__q31.html │ │ │ │ │ ├── structarm__bilinear__interp__instance__q7.html │ │ │ │ │ ├── structarm__biquad__cas__df1__32x64__ins__q31.html │ │ │ │ │ ├── structarm__biquad__cascade__df2T__instance__f16.html │ │ │ │ │ ├── structarm__biquad__cascade__df2T__instance__f32.html │ │ │ │ │ ├── structarm__biquad__cascade__df2T__instance__f64.html │ │ │ │ │ ├── structarm__biquad__cascade__stereo__df2T__instance__f16.html │ │ │ │ │ ├── structarm__biquad__cascade__stereo__df2T__instance__f32.html │ │ │ │ │ ├── structarm__biquad__casd__df1__inst__f16.html │ │ │ │ │ ├── structarm__biquad__casd__df1__inst__f32.html │ │ │ │ │ ├── structarm__biquad__casd__df1__inst__q15.html │ │ │ │ │ ├── structarm__biquad__casd__df1__inst__q31.html │ │ │ │ │ ├── structarm__cfft__instance__f16.html │ │ │ │ │ ├── structarm__cfft__instance__f32.html │ │ │ │ │ ├── structarm__cfft__instance__f64.html │ │ │ │ │ ├── structarm__cfft__instance__q15.html │ │ │ │ │ ├── structarm__cfft__instance__q31.html │ │ │ │ │ ├── structarm__cfft__radix2__instance__f16.html │ │ │ │ │ ├── structarm__cfft__radix2__instance__f32.html │ │ │ │ │ ├── structarm__cfft__radix2__instance__q15.html │ │ │ │ │ ├── structarm__cfft__radix2__instance__q31.html │ │ │ │ │ ├── structarm__cfft__radix4__instance__f16.html │ │ │ │ │ ├── structarm__cfft__radix4__instance__f32.html │ │ │ │ │ ├── structarm__cfft__radix4__instance__q15.html │ │ │ │ │ ├── structarm__cfft__radix4__instance__q31.html │ │ │ │ │ ├── structarm__dct4__instance__f32.html │ │ │ │ │ ├── structarm__dct4__instance__q15.html │ │ │ │ │ ├── structarm__dct4__instance__q31.html │ │ │ │ │ ├── structarm__fir__decimate__instance__f32.html │ │ │ │ │ ├── structarm__fir__decimate__instance__q15.html │ │ │ │ │ ├── structarm__fir__decimate__instance__q31.html │ │ │ │ │ ├── structarm__fir__instance__f16.html │ │ │ │ │ ├── structarm__fir__instance__f32.html │ │ │ │ │ ├── structarm__fir__instance__f64.html │ │ │ │ │ ├── structarm__fir__instance__q15.html │ │ │ │ │ ├── structarm__fir__instance__q31.html │ │ │ │ │ ├── structarm__fir__instance__q7.html │ │ │ │ │ ├── structarm__fir__interpolate__instance__f32.html │ │ │ │ │ ├── structarm__fir__interpolate__instance__q15.html │ │ │ │ │ ├── structarm__fir__interpolate__instance__q31.html │ │ │ │ │ ├── structarm__fir__lattice__instance__f32.html │ │ │ │ │ ├── structarm__fir__lattice__instance__q15.html │ │ │ │ │ ├── structarm__fir__lattice__instance__q31.html │ │ │ │ │ ├── structarm__fir__sparse__instance__f32.html │ │ │ │ │ ├── structarm__fir__sparse__instance__q15.html │ │ │ │ │ ├── structarm__fir__sparse__instance__q31.html │ │ │ │ │ ├── structarm__fir__sparse__instance__q7.html │ │ │ │ │ ├── structarm__gaussian__naive__bayes__instance__f16.html │ │ │ │ │ ├── structarm__gaussian__naive__bayes__instance__f32.html │ │ │ │ │ ├── structarm__iir__lattice__instance__f32.html │ │ │ │ │ ├── structarm__iir__lattice__instance__q15.html │ │ │ │ │ ├── structarm__iir__lattice__instance__q31.html │ │ │ │ │ ├── structarm__linear__interp__instance__f16.html │ │ │ │ │ ├── structarm__linear__interp__instance__f32.html │ │ │ │ │ ├── structarm__lms__instance__f32.html │ │ │ │ │ ├── structarm__lms__instance__q15.html │ │ │ │ │ ├── structarm__lms__instance__q31.html │ │ │ │ │ ├── structarm__lms__norm__instance__f32.html │ │ │ │ │ ├── structarm__lms__norm__instance__q15.html │ │ │ │ │ ├── structarm__lms__norm__instance__q31.html │ │ │ │ │ ├── structarm__matrix__instance__f16.html │ │ │ │ │ ├── structarm__matrix__instance__f32.html │ │ │ │ │ ├── structarm__matrix__instance__f64.html │ │ │ │ │ ├── structarm__matrix__instance__q15.html │ │ │ │ │ ├── structarm__matrix__instance__q31.html │ │ │ │ │ ├── structarm__matrix__instance__q7.html │ │ │ │ │ ├── structarm__merge__sort__instance__f32.html │ │ │ │ │ ├── structarm__mfcc__instance__f16.html │ │ │ │ │ ├── structarm__mfcc__instance__f32.html │ │ │ │ │ ├── structarm__mfcc__instance__q15.html │ │ │ │ │ ├── structarm__mfcc__instance__q31.html │ │ │ │ │ ├── structarm__pid__instance__f32.html │ │ │ │ │ ├── structarm__pid__instance__q15.html │ │ │ │ │ ├── structarm__pid__instance__q31.html │ │ │ │ │ ├── structarm__rfft__fast__instance__f16.html │ │ │ │ │ ├── structarm__rfft__fast__instance__f32.html │ │ │ │ │ ├── structarm__rfft__fast__instance__f64.html │ │ │ │ │ ├── structarm__rfft__instance__f32.html │ │ │ │ │ ├── structarm__rfft__instance__q15.html │ │ │ │ │ ├── structarm__rfft__instance__q31.html │ │ │ │ │ ├── structarm__sort__instance__f32.html │ │ │ │ │ ├── structarm__spline__instance__f32.html │ │ │ │ │ ├── structarm__svm__linear__instance__f16.html │ │ │ │ │ ├── structarm__svm__linear__instance__f32.html │ │ │ │ │ ├── structarm__svm__polynomial__instance__f16.html │ │ │ │ │ ├── structarm__svm__polynomial__instance__f32.html │ │ │ │ │ ├── structarm__svm__rbf__instance__f16.html │ │ │ │ │ ├── structarm__svm__rbf__instance__f32.html │ │ │ │ │ ├── structarm__svm__sigmoid__instance__f16.html │ │ │ │ │ ├── structarm__svm__sigmoid__instance__f32.html │ │ │ │ │ ├── support__functions_8h.html │ │ │ │ │ ├── support__functions__f16_8h.html │ │ │ │ │ ├── svm__defines_8h.html │ │ │ │ │ ├── svm__functions_8h.html │ │ │ │ │ ├── svm__functions__f16_8h.html │ │ │ │ │ ├── tabs.css │ │ │ │ │ ├── transform__functions_8h.html │ │ │ │ │ ├── transform__functions__f16_8h.html │ │ │ │ │ ├── unionany32x2__t.html │ │ │ │ │ ├── unionany32x4__t.html │ │ │ │ │ └── utils_8h.html │ │ │ │ ├── Doxygen_Templates/ │ │ │ │ │ ├── DoxygenLayout_forUser.xml │ │ │ │ │ ├── cmsis.css │ │ │ │ │ ├── cmsis_dap_header.html │ │ │ │ │ ├── cmsis_footer.html │ │ │ │ │ ├── cmsis_footer.js │ │ │ │ │ ├── cmsis_header.html │ │ │ │ │ ├── navtree.css │ │ │ │ │ ├── printComponentTabs.js │ │ │ │ │ ├── search.css │ │ │ │ │ └── tabs.css │ │ │ │ ├── Driver/ │ │ │ │ │ ├── Driver.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── Driver_CAN.c │ │ │ │ │ ├── Driver_Common.c │ │ │ │ │ ├── Driver_ETH.c │ │ │ │ │ ├── Driver_ETH_MAC.c │ │ │ │ │ ├── Driver_ETH_PHY.c │ │ │ │ │ ├── Driver_Flash.c │ │ │ │ │ ├── Driver_I2C.c │ │ │ │ │ ├── Driver_MCI.c │ │ │ │ │ ├── Driver_NAND.c │ │ │ │ │ ├── Driver_NAND_AddOn.txt │ │ │ │ │ ├── Driver_SAI.c │ │ │ │ │ ├── Driver_SPI.c │ │ │ │ │ ├── Driver_Storage.c │ │ │ │ │ ├── Driver_USART.c │ │ │ │ │ ├── Driver_USB.c │ │ │ │ │ ├── Driver_USBD.c │ │ │ │ │ ├── Driver_USBH.c │ │ │ │ │ ├── Driver_WiFi.c │ │ │ │ │ ├── Flash_Demo.c │ │ │ │ │ ├── General.txt │ │ │ │ │ ├── I2C_Demo.c │ │ │ │ │ ├── I2C_SlaveDemo.c │ │ │ │ │ ├── MCI_Demo.c │ │ │ │ │ ├── NAND_Demo.c │ │ │ │ │ ├── SPI_Demo.c │ │ │ │ │ ├── USART_Demo.c │ │ │ │ │ ├── VIO.txt │ │ │ │ │ └── images/ │ │ │ │ │ ├── CAN_Bit_Timing.vsd │ │ │ │ │ ├── CAN_Node.vsd │ │ │ │ │ ├── EthernetSchematic.vsd │ │ │ │ │ ├── I2C_BlockDiagram.vsd │ │ │ │ │ ├── NAND_PageLayout.vsd │ │ │ │ │ ├── NAND_Schematics.vsd │ │ │ │ │ ├── NAND_SpareArea.vsd │ │ │ │ │ ├── NOR_Schematics.vsd │ │ │ │ │ ├── SAI_Schematics.vsd │ │ │ │ │ ├── SAI_TimingDiagrams.vsd │ │ │ │ │ ├── SD_1BitBusMode.vsd │ │ │ │ │ ├── SD_4BitBusMode.vsd │ │ │ │ │ ├── SPI_BusMode.vsd │ │ │ │ │ ├── SPI_Master1Slaves.vsd │ │ │ │ │ ├── SPI_Master2Slaves.vsd │ │ │ │ │ ├── SPI_Master3Slaves.vsd │ │ │ │ │ ├── Storage.vsd │ │ │ │ │ ├── USB_Schematics.vsd │ │ │ │ │ └── driver.pptx │ │ │ │ ├── General/ │ │ │ │ │ ├── general.dxy │ │ │ │ │ └── src/ │ │ │ │ │ └── introduction.txt │ │ │ │ ├── How2Doc.txt │ │ │ │ ├── NN/ │ │ │ │ │ └── html/ │ │ │ │ │ ├── ActivationFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── BasicMathFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── CMakeLists_8txt.html │ │ │ │ │ ├── ChangeLog_pg.html │ │ │ │ │ ├── ConcatenationFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── ConvolutionFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── FullyConnectedFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── NNSupportFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── PoolingFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── ReshapeFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── SVDFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── SoftmaxFunctions_2CMakeLists_8txt.html │ │ │ │ │ ├── annotated.html │ │ │ │ │ ├── annotated.js │ │ │ │ │ ├── arm__avgpool__s16_8c.html │ │ │ │ │ ├── arm__avgpool__s8_8c.html │ │ │ │ │ ├── arm__concatenation__s8__w_8c.html │ │ │ │ │ ├── arm__concatenation__s8__x_8c.html │ │ │ │ │ ├── arm__concatenation__s8__y_8c.html │ │ │ │ │ ├── arm__concatenation__s8__z_8c.html │ │ │ │ │ ├── arm__convolve__1__x__n__s8_8c.html │ │ │ │ │ ├── arm__convolve__1x1__HWC__q7__fast__nonsquare_8c.html │ │ │ │ │ ├── arm__convolve__1x1__s8__fast_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q15__basic_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q15__fast_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q15__fast__nonsquare_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q7__RGB_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q7__basic_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q7__basic__nonsquare_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q7__fast_8c.html │ │ │ │ │ ├── arm__convolve__HWC__q7__fast__nonsquare_8c.html │ │ │ │ │ ├── arm__convolve__fast__s16_8c.html │ │ │ │ │ ├── arm__convolve__s16_8c.html │ │ │ │ │ ├── arm__convolve__s8_8c.html │ │ │ │ │ ├── arm__convolve__wrapper__s16_8c.html │ │ │ │ │ ├── arm__convolve__wrapper__s8_8c.html │ │ │ │ │ ├── arm__depthwise__conv__3x3__s8_8c.html │ │ │ │ │ ├── arm__depthwise__conv__fast__s16_8c.html │ │ │ │ │ ├── arm__depthwise__conv__s16_8c.html │ │ │ │ │ ├── arm__depthwise__conv__s8_8c.html │ │ │ │ │ ├── arm__depthwise__conv__s8__opt_8c.html │ │ │ │ │ ├── arm__depthwise__conv__u8__basic__ver1_8c.html │ │ │ │ │ ├── arm__depthwise__conv__wrapper__s16_8c.html │ │ │ │ │ ├── arm__depthwise__conv__wrapper__s8_8c.html │ │ │ │ │ ├── arm__depthwise__separable__conv__HWC__q7_8c.html │ │ │ │ │ ├── arm__depthwise__separable__conv__HWC__q7__nonsquare_8c.html │ │ │ │ │ ├── arm__elementwise__add__s16_8c.html │ │ │ │ │ ├── arm__elementwise__add__s8_8c.html │ │ │ │ │ ├── arm__elementwise__mul__s16_8c.html │ │ │ │ │ ├── arm__elementwise__mul__s8_8c.html │ │ │ │ │ ├── arm__fully__connected__mat__q7__vec__q15_8c.html │ │ │ │ │ ├── arm__fully__connected__mat__q7__vec__q15__opt_8c.html │ │ │ │ │ ├── arm__fully__connected__q15_8c.html │ │ │ │ │ ├── arm__fully__connected__q15__opt_8c.html │ │ │ │ │ ├── arm__fully__connected__q7_8c.html │ │ │ │ │ ├── arm__fully__connected__q7__opt_8c.html │ │ │ │ │ ├── arm__fully__connected__s16_8c.html │ │ │ │ │ ├── arm__fully__connected__s8_8c.html │ │ │ │ │ ├── arm__max__pool__s16_8c.html │ │ │ │ │ ├── arm__max__pool__s8_8c.html │ │ │ │ │ ├── arm__nn__accumulate__q7__to__q15_8c.html │ │ │ │ │ ├── arm__nn__activations__q15_8c.html │ │ │ │ │ ├── arm__nn__activations__q7_8c.html │ │ │ │ │ ├── arm__nn__add__q7_8c.html │ │ │ │ │ ├── arm__nn__depthwise__conv__nt__t__padded__s8_8c.html │ │ │ │ │ ├── arm__nn__depthwise__conv__nt__t__s16_8c.html │ │ │ │ │ ├── arm__nn__depthwise__conv__nt__t__s8_8c.html │ │ │ │ │ ├── arm__nn__depthwise__conv__s8__core_8c.html │ │ │ │ │ ├── arm__nn__mat__mul__core__1x__s8_8c.html │ │ │ │ │ ├── arm__nn__mat__mul__core__4x__s8_8c.html │ │ │ │ │ ├── arm__nn__mat__mul__kernel__s16_8c.html │ │ │ │ │ ├── arm__nn__mat__mult__kernel__q7__q15_8c.html │ │ │ │ │ ├── arm__nn__mat__mult__kernel__q7__q15__reordered_8c.html │ │ │ │ │ ├── arm__nn__mat__mult__kernel__s8__s16_8c.html │ │ │ │ │ ├── arm__nn__mat__mult__nt__t__s8_8c.html │ │ │ │ │ ├── arm__nn__mat__mult__s8_8c.html │ │ │ │ │ ├── arm__nn__math__types_8h.html │ │ │ │ │ ├── arm__nn__mult__q15_8c.html │ │ │ │ │ ├── arm__nn__mult__q7_8c.html │ │ │ │ │ ├── arm__nn__softmax__common__s8_8c.html │ │ │ │ │ ├── arm__nn__tables_8h.html │ │ │ │ │ ├── arm__nn__types_8h.html │ │ │ │ │ ├── arm__nn__vec__mat__mult__t__s16_8c.html │ │ │ │ │ ├── arm__nn__vec__mat__mult__t__s8_8c.html │ │ │ │ │ ├── arm__nn__vec__mat__mult__t__svdf__s8_8c.html │ │ │ │ │ ├── arm__nnfunctions_8h.html │ │ │ │ │ ├── arm__nnsupportfunctions_8h.html │ │ │ │ │ ├── arm__nntables_8c.html │ │ │ │ │ ├── arm__pool__q7__HWC_8c.html │ │ │ │ │ ├── arm__q7__to__q15__no__shift_8c.html │ │ │ │ │ ├── arm__q7__to__q15__reordered__no__shift_8c.html │ │ │ │ │ ├── arm__q7__to__q15__reordered__with__offset_8c.html │ │ │ │ │ ├── arm__q7__to__q15__with__offset_8c.html │ │ │ │ │ ├── arm__relu6__s8_8c.html │ │ │ │ │ ├── arm__relu__q15_8c.html │ │ │ │ │ ├── arm__relu__q7_8c.html │ │ │ │ │ ├── arm__reshape__s8_8c.html │ │ │ │ │ ├── arm__softmax__q15_8c.html │ │ │ │ │ ├── arm__softmax__q7_8c.html │ │ │ │ │ ├── arm__softmax__s16_8c.html │ │ │ │ │ ├── arm__softmax__s8_8c.html │ │ │ │ │ ├── arm__softmax__s8__s16_8c.html │ │ │ │ │ ├── arm__softmax__u8_8c.html │ │ │ │ │ ├── arm__softmax__with__batch__q7_8c.html │ │ │ │ │ ├── arm__svdf__s8_8c.html │ │ │ │ │ ├── arm__svdf__state__s16__s8_8c.html │ │ │ │ │ ├── classes.html │ │ │ │ │ ├── cmsis.css │ │ │ │ │ ├── cmsis_footer.js │ │ │ │ │ ├── doxygen.css │ │ │ │ │ ├── dynsections.js │ │ │ │ │ ├── files.html │ │ │ │ │ ├── functions.html │ │ │ │ │ ├── functions_vars.html │ │ │ │ │ ├── globals.html │ │ │ │ │ ├── globals_a.html │ │ │ │ │ ├── globals_c.html │ │ │ │ │ ├── globals_d.html │ │ │ │ │ ├── globals_defs.html │ │ │ │ │ ├── globals_e.html │ │ │ │ │ ├── globals_enum.html │ │ │ │ │ ├── globals_eval.html │ │ │ │ │ ├── globals_f.html │ │ │ │ │ ├── globals_func.html │ │ │ │ │ ├── globals_func_a.html │ │ │ │ │ ├── globals_func_c.html │ │ │ │ │ ├── globals_func_d.html │ │ │ │ │ ├── globals_func_e.html │ │ │ │ │ ├── globals_func_f.html │ │ │ │ │ ├── globals_func_l.html │ │ │ │ │ ├── globals_func_m.html │ │ │ │ │ ├── globals_func_n.html │ │ │ │ │ ├── globals_func_q.html │ │ │ │ │ ├── globals_func_r.html │ │ │ │ │ ├── globals_func_s.html │ │ │ │ │ ├── globals_func_t.html │ │ │ │ │ ├── globals_l.html │ │ │ │ │ ├── globals_m.html │ │ │ │ │ ├── globals_n.html │ │ │ │ │ ├── globals_o.html │ │ │ │ │ ├── globals_p.html │ │ │ │ │ ├── globals_q.html │ │ │ │ │ ├── globals_r.html │ │ │ │ │ ├── globals_s.html │ │ │ │ │ ├── globals_t.html │ │ │ │ │ ├── globals_type.html │ │ │ │ │ ├── globals_u.html │ │ │ │ │ ├── globals_vars.html │ │ │ │ │ ├── group__Acti.html │ │ │ │ │ ├── group__BasicMath.html │ │ │ │ │ ├── group__Concatenation.html │ │ │ │ │ ├── group__FC.html │ │ │ │ │ ├── group__NNBasicMath.html │ │ │ │ │ ├── group__NNConv.html │ │ │ │ │ ├── group__Pooling.html │ │ │ │ │ ├── group__Reshape.html │ │ │ │ │ ├── group__SVDF.html │ │ │ │ │ ├── group__Softmax.html │ │ │ │ │ ├── group__groupNN.html │ │ │ │ │ ├── group__nndata__convert.html │ │ │ │ │ ├── history_8txt.html │ │ │ │ │ ├── index.html │ │ │ │ │ ├── jquery.js │ │ │ │ │ ├── modules.html │ │ │ │ │ ├── modules.js │ │ │ │ │ ├── navtree.css │ │ │ │ │ ├── navtree.js │ │ │ │ │ ├── navtreeindex0.js │ │ │ │ │ ├── pages.html │ │ │ │ │ ├── printComponentTabs.js │ │ │ │ │ ├── resize.js │ │ │ │ │ ├── structarm__nn__double.html │ │ │ │ │ ├── structarm__nn__double.js │ │ │ │ │ ├── structcmsis__nn__activation.html │ │ │ │ │ ├── structcmsis__nn__activation.js │ │ │ │ │ ├── structcmsis__nn__context.html │ │ │ │ │ ├── structcmsis__nn__context.js │ │ │ │ │ ├── structcmsis__nn__conv__params.html │ │ │ │ │ ├── structcmsis__nn__conv__params.js │ │ │ │ │ ├── structcmsis__nn__dims.html │ │ │ │ │ ├── structcmsis__nn__dims.js │ │ │ │ │ ├── structcmsis__nn__dw__conv__params.html │ │ │ │ │ ├── structcmsis__nn__dw__conv__params.js │ │ │ │ │ ├── structcmsis__nn__fc__params.html │ │ │ │ │ ├── structcmsis__nn__fc__params.js │ │ │ │ │ ├── structcmsis__nn__per__channel__quant__params.html │ │ │ │ │ ├── structcmsis__nn__per__channel__quant__params.js │ │ │ │ │ ├── structcmsis__nn__per__tensor__quant__params.html │ │ │ │ │ ├── structcmsis__nn__per__tensor__quant__params.js │ │ │ │ │ ├── structcmsis__nn__pool__params.html │ │ │ │ │ ├── structcmsis__nn__pool__params.js │ │ │ │ │ ├── structcmsis__nn__softmax__lut__s16.html │ │ │ │ │ ├── structcmsis__nn__softmax__lut__s16.js │ │ │ │ │ ├── structcmsis__nn__svdf__params.html │ │ │ │ │ ├── structcmsis__nn__svdf__params.js │ │ │ │ │ ├── structcmsis__nn__tile.html │ │ │ │ │ ├── structcmsis__nn__tile.js │ │ │ │ │ ├── tabs.css │ │ │ │ │ ├── todo.html │ │ │ │ │ ├── unionarm__nn__long__long.html │ │ │ │ │ ├── unionarm__nn__long__long.js │ │ │ │ │ ├── unionarm__nnword.html │ │ │ │ │ └── unionarm__nnword.js │ │ │ │ ├── Pack/ │ │ │ │ │ └── html/ │ │ │ │ │ ├── algorithmFunc.html │ │ │ │ │ ├── bash_script.html │ │ │ │ │ ├── cmsis.css │ │ │ │ │ ├── cmsis_footer.js │ │ │ │ │ ├── configWizard.html │ │ │ │ │ ├── coresight_setup.html │ │ │ │ │ ├── cp_Editors.html │ │ │ │ │ ├── cp_PackTutorial.html │ │ │ │ │ ├── cp_Packs.html │ │ │ │ │ ├── cp_ZIPTool.html │ │ │ │ │ ├── createPackPublish.html │ │ │ │ │ ├── createPackUtil.html │ │ │ │ │ ├── dbg_debug_sqns.html │ │ │ │ │ ├── dbg_setup_access.html │ │ │ │ │ ├── dbg_setup_tutorial.html │ │ │ │ │ ├── dbg_sqns_ds.html │ │ │ │ │ ├── dbg_sqns_ide.html │ │ │ │ │ ├── dbg_sqns_uvision.html │ │ │ │ │ ├── debug_description.html │ │ │ │ │ ├── doxygen.css │ │ │ │ │ ├── dynsections.js │ │ │ │ │ ├── element_dominate.html │ │ │ │ │ ├── element_keywords.html │ │ │ │ │ ├── element_releases.html │ │ │ │ │ ├── element_repository.html │ │ │ │ │ ├── element_requirements_pg.html │ │ │ │ │ ├── element_taxonomy.html │ │ │ │ │ ├── flashAlgorithm.html │ │ │ │ │ ├── index.html │ │ │ │ │ ├── jquery.js │ │ │ │ │ ├── navtree.css │ │ │ │ │ ├── navtree.js │ │ │ │ │ ├── navtreeindex0.js │ │ │ │ │ ├── packChk.html │ │ │ │ │ ├── packFormat.html │ │ │ │ │ ├── packIndexFile.html │ │ │ │ │ ├── pack_revisionHistory.html │ │ │ │ │ ├── pages.html │ │ │ │ │ ├── pdsc_apis_pg.html │ │ │ │ │ ├── pdsc_boards_pg.html │ │ │ │ │ ├── pdsc_components_pg.html │ │ │ │ │ ├── pdsc_conditions_pg.html │ │ │ │ │ ├── pdsc_devices_pg.html │ │ │ │ │ ├── pdsc_examples_pg.html │ │ │ │ │ ├── pdsc_family_pg.html │ │ │ │ │ ├── pdsc_generators_pg.html │ │ │ │ │ ├── pdsc_package_pg.html │ │ │ │ │ ├── printComponentTabs.js │ │ │ │ │ ├── resize.js │ │ │ │ │ ├── sdf_pg.html │ │ │ │ │ ├── search/ │ │ │ │ │ │ ├── nomatches.html │ │ │ │ │ │ ├── search.css │ │ │ │ │ │ └── search.js │ │ │ │ │ └── tabs.css │ │ │ │ ├── RTOS/ │ │ │ │ │ ├── rtos.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── RTX/ │ │ │ │ │ │ └── cmsis_os_rtx_extensions.h │ │ │ │ │ ├── cmsis_os.txt │ │ │ │ │ └── images/ │ │ │ │ │ ├── Reference_Section.vsd │ │ │ │ │ └── TimerValues.vsd │ │ │ │ ├── RTOS2/ │ │ │ │ │ ├── rtos.dxy │ │ │ │ │ ├── rtos_CM0-7.dxy │ │ │ │ │ └── src/ │ │ │ │ │ ├── cmsis_os2.txt │ │ │ │ │ ├── cmsis_os2_Event.txt │ │ │ │ │ ├── cmsis_os2_Kernel.txt │ │ │ │ │ ├── cmsis_os2_MemPool.txt │ │ │ │ │ ├── cmsis_os2_Message.txt │ │ │ │ │ ├── cmsis_os2_Migration.txt │ │ │ │ │ ├── cmsis_os2_MigrationGuide.txt │ │ │ │ │ ├── cmsis_os2_Mutex.txt │ │ │ │ │ ├── cmsis_os2_ProcessIsolation.txt │ │ │ │ │ ├── cmsis_os2_Sema.txt │ │ │ │ │ ├── cmsis_os2_Status.txt │ │ │ │ │ ├── cmsis_os2_Thread.txt │ │ │ │ │ ├── cmsis_os2_ThreadFlags.txt │ │ │ │ │ ├── cmsis_os2_Timer.txt │ │ │ │ │ ├── cmsis_os2_Tutorial.txt │ │ │ │ │ ├── cmsis_os2_Wait.txt │ │ │ │ │ ├── cmsis_os2_tick.txt │ │ │ │ │ ├── history.txt │ │ │ │ │ ├── images/ │ │ │ │ │ │ ├── API_Structure.vsd │ │ │ │ │ │ ├── MessageQueue.vsd │ │ │ │ │ │ ├── Mutex.vsd │ │ │ │ │ │ ├── Semaphores.vsd │ │ │ │ │ │ ├── TheoryOfOperation.pptx │ │ │ │ │ │ ├── ThreadStatus.vsd │ │ │ │ │ │ ├── TimerValues.vsd │ │ │ │ │ │ └── cmsis_rtos_file_structure.vsd │ │ │ │ │ ├── mainpage.txt │ │ │ │ │ ├── rtx_evr.txt │ │ │ │ │ ├── rtx_os.txt │ │ │ │ │ └── validation.txt │ │ │ │ ├── SVD/ │ │ │ │ │ ├── src/ │ │ │ │ │ │ ├── ARM_ExampleT0.h │ │ │ │ │ │ ├── ARM_ExampleT0Struct.h │ │ │ │ │ │ ├── images/ │ │ │ │ │ │ │ └── CMSIS_SVD_Schema_Gen.vsd │ │ │ │ │ │ ├── svd.txt │ │ │ │ │ │ └── svd_schema.txt │ │ │ │ │ └── svd.dxy │ │ │ │ ├── Zone/ │ │ │ │ │ ├── src/ │ │ │ │ │ │ ├── ErrorMessages.txt │ │ │ │ │ │ ├── GenDataModel.txt │ │ │ │ │ │ ├── Overview.txt │ │ │ │ │ │ ├── XML_Format.txt │ │ │ │ │ │ └── images/ │ │ │ │ │ │ ├── CMSIS_Zone.pptx │ │ │ │ │ │ ├── Zone.vsdx │ │ │ │ │ │ ├── genmodel.graphml │ │ │ │ │ │ ├── images.odp │ │ │ │ │ │ ├── soc-memorymap.graphml │ │ │ │ │ │ ├── som-decomposition.graphml │ │ │ │ │ │ ├── storagemodel.graphml │ │ │ │ │ │ └── zone-assignment.graphml │ │ │ │ │ └── zone.dxy │ │ │ │ ├── gen_doc.sh │ │ │ │ └── index.html │ │ │ ├── Driver/ │ │ │ │ ├── DriverTemplates/ │ │ │ │ │ ├── Driver_CAN.c │ │ │ │ │ ├── Driver_ETH_MAC.c │ │ │ │ │ ├── Driver_ETH_PHY.c │ │ │ │ │ ├── Driver_Flash.c │ │ │ │ │ ├── Driver_I2C.c │ │ │ │ │ ├── Driver_MCI.c │ │ │ │ │ ├── Driver_NAND.c │ │ │ │ │ ├── Driver_SAI.c │ │ │ │ │ ├── Driver_SPI.c │ │ │ │ │ ├── Driver_Storage.c │ │ │ │ │ ├── Driver_USART.c │ │ │ │ │ ├── Driver_USBD.c │ │ │ │ │ ├── Driver_USBH.c │ │ │ │ │ └── Driver_WiFi.c │ │ │ │ ├── Include/ │ │ │ │ │ ├── Driver_CAN.h │ │ │ │ │ ├── Driver_Common.h │ │ │ │ │ ├── Driver_ETH.h │ │ │ │ │ ├── Driver_ETH_MAC.h │ │ │ │ │ ├── Driver_ETH_PHY.h │ │ │ │ │ ├── Driver_Flash.h │ │ │ │ │ ├── Driver_I2C.h │ │ │ │ │ ├── Driver_MCI.h │ │ │ │ │ ├── Driver_NAND.h │ │ │ │ │ ├── Driver_SAI.h │ │ │ │ │ ├── Driver_SPI.h │ │ │ │ │ ├── Driver_Storage.h │ │ │ │ │ ├── Driver_USART.h │ │ │ │ │ ├── Driver_USB.h │ │ │ │ │ ├── Driver_USBD.h │ │ │ │ │ ├── Driver_USBH.h │ │ │ │ │ └── Driver_WiFi.h │ │ │ │ └── VIO/ │ │ │ │ ├── Include/ │ │ │ │ │ └── cmsis_vio.h │ │ │ │ ├── Source/ │ │ │ │ │ ├── vio.c │ │ │ │ │ └── vio_memory.c │ │ │ │ └── cmsis_vio.scvd │ │ │ ├── NN/ │ │ │ │ └── README.md │ │ │ ├── Pack/ │ │ │ │ └── Bash/ │ │ │ │ ├── Include/ │ │ │ │ │ └── component.h │ │ │ │ ├── License.txt │ │ │ │ ├── MyVendor.MyPack.pdsc.txt │ │ │ │ ├── README.md │ │ │ │ ├── Source/ │ │ │ │ │ └── component.c │ │ │ │ └── gen_pack.sh │ │ │ ├── RTOS/ │ │ │ │ ├── RTX/ │ │ │ │ │ ├── INC/ │ │ │ │ │ │ ├── RTX_CM_lib.h │ │ │ │ │ │ └── cmsis_os.h │ │ │ │ │ ├── LIB/ │ │ │ │ │ │ └── fetch_libs.sh │ │ │ │ │ ├── SRC/ │ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ │ ├── HAL_CM0.c │ │ │ │ │ │ │ ├── HAL_CM3.c │ │ │ │ │ │ │ ├── HAL_CM4.c │ │ │ │ │ │ │ ├── RTX_Lib_CM.uvoptx │ │ │ │ │ │ │ ├── RTX_Lib_CM.uvprojx │ │ │ │ │ │ │ └── SVC_Table.s │ │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ │ ├── HAL_CM0.S │ │ │ │ │ │ │ ├── HAL_CM3.S │ │ │ │ │ │ │ ├── HAL_CM4.S │ │ │ │ │ │ │ ├── RTX_Lib_CM.uvoptx │ │ │ │ │ │ │ ├── RTX_Lib_CM.uvprojx │ │ │ │ │ │ │ └── SVC_Table.S │ │ │ │ │ │ ├── HAL_CM.c │ │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ │ ├── HAL_CM0.s │ │ │ │ │ │ │ ├── HAL_CM3.s │ │ │ │ │ │ │ ├── HAL_CM4.s │ │ │ │ │ │ │ ├── RTX_Lib_CM.ewp │ │ │ │ │ │ │ ├── RTX_Lib_CM.eww │ │ │ │ │ │ │ └── SVC_Table.s │ │ │ │ │ │ ├── RTX_Config.h │ │ │ │ │ │ ├── rt_CMSIS.c │ │ │ │ │ │ ├── rt_Event.c │ │ │ │ │ │ ├── rt_Event.h │ │ │ │ │ │ ├── rt_HAL_CM.h │ │ │ │ │ │ ├── rt_List.c │ │ │ │ │ │ ├── rt_List.h │ │ │ │ │ │ ├── rt_Mailbox.c │ │ │ │ │ │ ├── rt_Mailbox.h │ │ │ │ │ │ ├── rt_MemBox.c │ │ │ │ │ │ ├── rt_MemBox.h │ │ │ │ │ │ ├── rt_Memory.c │ │ │ │ │ │ ├── rt_Memory.h │ │ │ │ │ │ ├── rt_Mutex.c │ │ │ │ │ │ ├── rt_Mutex.h │ │ │ │ │ │ ├── rt_Robin.c │ │ │ │ │ │ ├── rt_Robin.h │ │ │ │ │ │ ├── rt_Semaphore.c │ │ │ │ │ │ ├── rt_Semaphore.h │ │ │ │ │ │ ├── rt_System.c │ │ │ │ │ │ ├── rt_System.h │ │ │ │ │ │ ├── rt_Task.c │ │ │ │ │ │ ├── rt_Task.h │ │ │ │ │ │ ├── rt_Time.c │ │ │ │ │ │ ├── rt_Time.h │ │ │ │ │ │ ├── rt_Timer.c │ │ │ │ │ │ ├── rt_Timer.h │ │ │ │ │ │ └── rt_TypeDef.h │ │ │ │ │ ├── Templates/ │ │ │ │ │ │ └── RTX_Conf_CM.c │ │ │ │ │ └── UserCodeTemplates/ │ │ │ │ │ ├── MailQueue.c │ │ │ │ │ ├── MemPool.c │ │ │ │ │ ├── MsgQueue.c │ │ │ │ │ ├── Mutex.c │ │ │ │ │ ├── Semaphore.c │ │ │ │ │ ├── Thread.c │ │ │ │ │ ├── Timer.c │ │ │ │ │ ├── main.c │ │ │ │ │ └── osObjects.h │ │ │ │ └── Template/ │ │ │ │ ├── CPP/ │ │ │ │ │ ├── Mail.h │ │ │ │ │ ├── MemoryPool.h │ │ │ │ │ ├── Mutex.cpp │ │ │ │ │ ├── Mutex.h │ │ │ │ │ ├── Queue.h │ │ │ │ │ ├── RtosTimer.cpp │ │ │ │ │ ├── RtosTimer.h │ │ │ │ │ ├── Semaphore.cpp │ │ │ │ │ ├── Semaphore.h │ │ │ │ │ ├── Thread.cpp │ │ │ │ │ ├── Thread.h │ │ │ │ │ └── rtos.h │ │ │ │ ├── Hist.txt │ │ │ │ ├── Template.uvopt │ │ │ │ ├── Template.uvproj │ │ │ │ ├── cmsis_os.h │ │ │ │ ├── my_objects.h │ │ │ │ ├── os_sample.c │ │ │ │ ├── os_sample1.c │ │ │ │ ├── startup_LPC177x_8x.s │ │ │ │ └── system_LPC177x_8x.c │ │ │ ├── RTOS2/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── cmsis_os2.h │ │ │ │ │ └── os_tick.h │ │ │ │ ├── RTX/ │ │ │ │ │ ├── Config/ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ ├── RTX_Config.h │ │ │ │ │ │ └── handlers.c │ │ │ │ │ ├── Examples/ │ │ │ │ │ │ ├── Blinky/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── Blinky.c │ │ │ │ │ │ │ ├── Blinky.uvguix │ │ │ │ │ │ │ ├── Blinky.uvoptx │ │ │ │ │ │ │ ├── Blinky.uvprojx │ │ │ │ │ │ │ └── RTE/ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ ├── Compiler/ │ │ │ │ │ │ │ │ └── EventRecorderConf.h │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM3/ │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ │ │ └── system_ARMCM3.c │ │ │ │ │ │ ├── MemPool/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── MemPool.uvguix │ │ │ │ │ │ │ ├── MemPool.uvoptx │ │ │ │ │ │ │ ├── MemPool.uvprojx │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ │ ├── Compiler/ │ │ │ │ │ │ │ │ │ └── EventRecorderConf.h │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ └── ARMCM3/ │ │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ │ │ │ └── system_ARMCM3.c │ │ │ │ │ │ │ └── main.c │ │ │ │ │ │ ├── Migration/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── Blinky.c │ │ │ │ │ │ │ ├── Blinky.uvguix │ │ │ │ │ │ │ ├── Blinky.uvoptx │ │ │ │ │ │ │ ├── Blinky.uvprojx │ │ │ │ │ │ │ └── RTE/ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ ├── Compiler/ │ │ │ │ │ │ │ │ └── EventRecorderConf.h │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ └── ARMCM3/ │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ │ │ └── system_ARMCM3.c │ │ │ │ │ │ ├── MsgQueue/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── MsqQueue.uvguix │ │ │ │ │ │ │ ├── MsqQueue.uvoptx │ │ │ │ │ │ │ ├── MsqQueue.uvprojx │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ │ ├── Compiler/ │ │ │ │ │ │ │ │ │ └── EventRecorderConf.h │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ └── ARMCM3/ │ │ │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ │ │ │ └── system_ARMCM3.c │ │ │ │ │ │ │ └── main.c │ │ │ │ │ │ └── TrustZoneV8M/ │ │ │ │ │ │ ├── NoRTOS/ │ │ │ │ │ │ │ ├── ARMCM33_DSP_FP_TZ_config.txt │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── CM33_ns/ │ │ │ │ │ │ │ │ ├── CM33_ns.uvguix │ │ │ │ │ │ │ │ ├── CM33_ns.uvoptx │ │ │ │ │ │ │ │ ├── CM33_ns.uvprojx │ │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ │ ├── ARMCM33_AC6.sct │ │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ │ └── main_ns.c │ │ │ │ │ │ │ ├── CM33_s/ │ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ │ ├── CM33_s.uvguix │ │ │ │ │ │ │ │ ├── CM33_s.uvoptx │ │ │ │ │ │ │ │ ├── CM33_s.uvprojx │ │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ │ ├── interface.c │ │ │ │ │ │ │ │ ├── interface.h │ │ │ │ │ │ │ │ └── main_s.c │ │ │ │ │ │ │ ├── Debug.ini │ │ │ │ │ │ │ ├── NoRTOS.uvmpw │ │ │ │ │ │ │ └── NoRTOS.uvmpw.uvgui │ │ │ │ │ │ ├── RTOS/ │ │ │ │ │ │ │ ├── ARMCM33_DSP_FP_TZ_config.txt │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── CM33_ns/ │ │ │ │ │ │ │ │ ├── CM33_ns.uvguix │ │ │ │ │ │ │ │ ├── CM33_ns.uvoptx │ │ │ │ │ │ │ │ ├── CM33_ns.uvprojx │ │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ │ ├── ARMCM33_AC6.sct │ │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ │ └── main_ns.c │ │ │ │ │ │ │ ├── CM33_s/ │ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ │ ├── CM33_s.uvguix │ │ │ │ │ │ │ │ ├── CM33_s.uvoptx │ │ │ │ │ │ │ │ ├── CM33_s.uvprojx │ │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ │ ├── interface.c │ │ │ │ │ │ │ │ ├── interface.h │ │ │ │ │ │ │ │ ├── main_s.c │ │ │ │ │ │ │ │ └── tz_context.c │ │ │ │ │ │ │ ├── Debug.ini │ │ │ │ │ │ │ ├── RTOS.uvmpw │ │ │ │ │ │ │ └── RTOS.uvmpw.uvgui │ │ │ │ │ │ └── RTOS_Faults/ │ │ │ │ │ │ ├── ARMCM33_DSP_FP_TZ_config.txt │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ ├── CM33_ns/ │ │ │ │ │ │ │ ├── CM33_ns.uvguix │ │ │ │ │ │ │ ├── CM33_ns.uvoptx │ │ │ │ │ │ │ ├── CM33_ns.uvprojx │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ │ │ │ ├── RTX_Config.c │ │ │ │ │ │ │ │ │ └── RTX_Config.h │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ ├── ARMCM33_AC6.sct │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ └── main_ns.c │ │ │ │ │ │ ├── CM33_s/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── CM33_s.uvguix │ │ │ │ │ │ │ ├── CM33_s.uvoptx │ │ │ │ │ │ │ ├── CM33_s.uvprojx │ │ │ │ │ │ │ ├── Hardfault.c │ │ │ │ │ │ │ ├── Hardfault.h │ │ │ │ │ │ │ ├── IncidentLog_s.c │ │ │ │ │ │ │ ├── IncidentLog_s.h │ │ │ │ │ │ │ ├── RTE/ │ │ │ │ │ │ │ │ └── Device/ │ │ │ │ │ │ │ │ └── ARMCM33_DSP_FP_TZ/ │ │ │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ │ │ ├── partition_ARMCM33.h │ │ │ │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ │ │ │ ├── SysTick_s.c │ │ │ │ │ │ │ ├── SysTick_s.h │ │ │ │ │ │ │ ├── interface.c │ │ │ │ │ │ │ ├── interface.h │ │ │ │ │ │ │ ├── main_s.c │ │ │ │ │ │ │ └── tz_context.c │ │ │ │ │ │ ├── Debug.ini │ │ │ │ │ │ ├── RTOS_Faults.uvmpw │ │ │ │ │ │ └── RTOS_Faults.uvmpw.uvgui │ │ │ │ │ ├── Examples_IAR/ │ │ │ │ │ │ ├── Blinky/ │ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ │ ├── Blinky/ │ │ │ │ │ │ │ │ ├── Blinky.ewd │ │ │ │ │ │ │ │ ├── Blinky.ewp │ │ │ │ │ │ │ │ └── settings/ │ │ │ │ │ │ │ │ ├── Blinky.crun │ │ │ │ │ │ │ │ ├── Blinky.dbgdt │ │ │ │ │ │ │ │ └── Blinky.dnx │ │ │ │ │ │ │ └── Blinky.c │ │ │ │ │ │ └── MsgQueue/ │ │ │ │ │ │ ├── Abstract.txt │ │ │ │ │ │ ├── MsgQueue/ │ │ │ │ │ │ │ ├── MsgQueue.ewd │ │ │ │ │ │ │ ├── MsgQueue.ewp │ │ │ │ │ │ │ └── settings/ │ │ │ │ │ │ │ ├── MsgQueue.crun │ │ │ │ │ │ │ ├── MsgQueue.dbgdt │ │ │ │ │ │ │ └── MsgQueue.dnx │ │ │ │ │ │ └── main.c │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── rtx_def.h │ │ │ │ │ │ ├── rtx_evr.h │ │ │ │ │ │ └── rtx_os.h │ │ │ │ │ ├── Include1/ │ │ │ │ │ │ └── cmsis_os.h │ │ │ │ │ ├── Library/ │ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ │ └── MDK/ │ │ │ │ │ │ │ ├── Lint/ │ │ │ │ │ │ │ │ └── MISRA_C_2012_Config.lnt │ │ │ │ │ │ │ ├── RTX_CM.uvoptx │ │ │ │ │ │ │ └── RTX_CM.uvprojx │ │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ │ └── MDK/ │ │ │ │ │ │ │ ├── RTX_CM.uvoptx │ │ │ │ │ │ │ └── RTX_CM.uvprojx │ │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ │ └── IDE/ │ │ │ │ │ │ │ ├── RTE_Components.h │ │ │ │ │ │ │ ├── RTX_CM.ewp │ │ │ │ │ │ │ └── RTX_CM.eww │ │ │ │ │ │ ├── RTX_Config.h │ │ │ │ │ │ ├── build.py │ │ │ │ │ │ ├── cmsis_os1.c │ │ │ │ │ │ └── fetch_libs.sh │ │ │ │ │ ├── RTX5.scvd │ │ │ │ │ ├── Source/ │ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ │ ├── irq_armv6m.s │ │ │ │ │ │ │ ├── irq_armv7a.s │ │ │ │ │ │ │ └── irq_armv7m.s │ │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ │ ├── irq_armv6m.S │ │ │ │ │ │ │ ├── irq_armv7a.S │ │ │ │ │ │ │ ├── irq_armv7m.S │ │ │ │ │ │ │ ├── irq_armv8mbl.S │ │ │ │ │ │ │ └── irq_armv8mml.S │ │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ │ ├── irq_armv6m.s │ │ │ │ │ │ │ ├── irq_armv7a.s │ │ │ │ │ │ │ ├── irq_armv7m.s │ │ │ │ │ │ │ ├── irq_armv8mbl.s │ │ │ │ │ │ │ └── irq_armv8mml.s │ │ │ │ │ │ ├── rtx_core_c.h │ │ │ │ │ │ ├── rtx_core_ca.h │ │ │ │ │ │ ├── rtx_core_cm.h │ │ │ │ │ │ ├── rtx_delay.c │ │ │ │ │ │ ├── rtx_evflags.c │ │ │ │ │ │ ├── rtx_evr.c │ │ │ │ │ │ ├── rtx_kernel.c │ │ │ │ │ │ ├── rtx_lib.c │ │ │ │ │ │ ├── rtx_lib.h │ │ │ │ │ │ ├── rtx_memory.c │ │ │ │ │ │ ├── rtx_mempool.c │ │ │ │ │ │ ├── rtx_msgqueue.c │ │ │ │ │ │ ├── rtx_mutex.c │ │ │ │ │ │ ├── rtx_semaphore.c │ │ │ │ │ │ ├── rtx_system.c │ │ │ │ │ │ ├── rtx_thread.c │ │ │ │ │ │ └── rtx_timer.c │ │ │ │ │ └── Template/ │ │ │ │ │ ├── Events.c │ │ │ │ │ ├── MemPool.c │ │ │ │ │ ├── MsgQueue.c │ │ │ │ │ ├── Mutex.c │ │ │ │ │ ├── Semaphore.c │ │ │ │ │ ├── Thread.c │ │ │ │ │ ├── Timer.c │ │ │ │ │ ├── main.c │ │ │ │ │ └── svc_user.c │ │ │ │ ├── Source/ │ │ │ │ │ ├── os_systick.c │ │ │ │ │ ├── os_tick_gtim.c │ │ │ │ │ └── os_tick_ptim.c │ │ │ │ └── Template/ │ │ │ │ ├── cmsis_os.h │ │ │ │ └── cmsis_os1.c │ │ │ └── Utilities/ │ │ │ ├── ARM_Example.h │ │ │ ├── ARM_Example.svd │ │ │ ├── CMSIS-SVD.xsd │ │ │ ├── check_header.sh │ │ │ ├── check_links.sh │ │ │ ├── fetch_devtools.sh │ │ │ └── gen_pack.sh │ │ ├── Device/ │ │ │ ├── ARM/ │ │ │ │ ├── ARMCA5/ │ │ │ │ │ ├── Config/ │ │ │ │ │ │ ├── mem_ARMCA5.h │ │ │ │ │ │ └── system_ARMCA5.h │ │ │ │ │ ├── Include/ │ │ │ │ │ │ └── ARMCA5.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── AC5/ │ │ │ │ │ │ ├── ARMCA5.sct │ │ │ │ │ │ └── startup_ARMCA5.c │ │ │ │ │ ├── AC6/ │ │ │ │ │ │ ├── ARMCA5.sct │ │ │ │ │ │ └── startup_ARMCA5.c │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── ARMCA5.ld │ │ │ │ │ │ ├── ARMCA5.sct │ │ │ │ │ │ └── startup_ARMCA5.c │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ ├── ARMCA5.icf │ │ │ │ │ │ └── startup_ARMCA5.s │ │ │ │ │ ├── mmu_ARMCA5.c │ │ │ │ │ └── system_ARMCA5.c │ │ │ │ ├── ARMCA7/ │ │ │ │ │ ├── Config/ │ │ │ │ │ │ ├── mem_ARMCA7.h │ │ │ │ │ │ └── system_ARMCA7.h │ │ │ │ │ ├── Include/ │ │ │ │ │ │ └── ARMCA7.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── AC5/ │ │ │ │ │ │ ├── ARMCA7.sct │ │ │ │ │ │ └── startup_ARMCA7.c │ │ │ │ │ ├── AC6/ │ │ │ │ │ │ ├── ARMCA7.sct │ │ │ │ │ │ └── startup_ARMCA7.c │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── ARMCA7.ld │ │ │ │ │ │ └── startup_ARMCA7.c │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ ├── ARMCA7.icf │ │ │ │ │ │ └── startup_ARMCA7.s │ │ │ │ │ ├── mmu_ARMCA7.c │ │ │ │ │ └── system_ARMCA7.c │ │ │ │ ├── ARMCA9/ │ │ │ │ │ ├── Config/ │ │ │ │ │ │ ├── mem_ARMCA9.h │ │ │ │ │ │ └── system_ARMCA9.h │ │ │ │ │ ├── Include/ │ │ │ │ │ │ └── ARMCA9.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── AC5/ │ │ │ │ │ │ ├── ARMCA9.sct │ │ │ │ │ │ └── startup_ARMCA9.c │ │ │ │ │ ├── AC6/ │ │ │ │ │ │ ├── ARMCA9.sct │ │ │ │ │ │ └── startup_ARMCA9.c │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── ARMCA9.ld │ │ │ │ │ │ └── startup_ARMCA9.c │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ ├── ARMCA9.icf │ │ │ │ │ │ └── startup_ARMCA9.s │ │ │ │ │ ├── mmu_ARMCA9.c │ │ │ │ │ └── system_ARMCA9.c │ │ │ │ ├── ARMCM0/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM0.h │ │ │ │ │ │ └── system_ARMCM0.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM0_ac5.sct │ │ │ │ │ │ ├── ARMCM0_ac6.sct │ │ │ │ │ │ └── startup_ARMCM0.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM0.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM0.s │ │ │ │ │ ├── startup_ARMCM0.c │ │ │ │ │ └── system_ARMCM0.c │ │ │ │ ├── ARMCM0plus/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM0plus.h │ │ │ │ │ │ ├── ARMCM0plus_MPU.h │ │ │ │ │ │ └── system_ARMCM0plus.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM0plus_ac5.sct │ │ │ │ │ │ ├── ARMCM0plus_ac6.sct │ │ │ │ │ │ └── startup_ARMCM0plus.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM0plus.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM0plus.s │ │ │ │ │ ├── startup_ARMCM0plus.c │ │ │ │ │ └── system_ARMCM0plus.c │ │ │ │ ├── ARMCM1/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM1.h │ │ │ │ │ │ └── system_ARMCM1.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM1_ac5.sct │ │ │ │ │ │ ├── ARMCM1_ac6.sct │ │ │ │ │ │ └── startup_ARMCM1.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM1.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM1.s │ │ │ │ │ ├── startup_ARMCM1.c │ │ │ │ │ └── system_ARMCM1.c │ │ │ │ ├── ARMCM23/ │ │ │ │ │ ├── Debug/ │ │ │ │ │ │ └── ARMv8MBL.dbgconf │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM23.h │ │ │ │ │ │ ├── ARMCM23_TZ.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMCM23.h │ │ │ │ │ │ └── system_ARMCM23.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM23_ac6.sct │ │ │ │ │ │ ├── ARMCM23_ac6_s.sct │ │ │ │ │ │ └── startup_ARMCM23.S │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM23.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM23.s │ │ │ │ │ ├── startup_ARMCM23.c │ │ │ │ │ └── system_ARMCM23.c │ │ │ │ ├── ARMCM3/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM3.h │ │ │ │ │ │ └── system_ARMCM3.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM3_ac5.sct │ │ │ │ │ │ ├── ARMCM3_ac6.sct │ │ │ │ │ │ └── startup_ARMCM3.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM3.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM3.s │ │ │ │ │ ├── startup_ARMCM3.c │ │ │ │ │ └── system_ARMCM3.c │ │ │ │ ├── ARMCM33/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM33.h │ │ │ │ │ │ ├── ARMCM33_DSP_FP.h │ │ │ │ │ │ ├── ARMCM33_DSP_FP_TZ.h │ │ │ │ │ │ ├── ARMCM33_TZ.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMCM33.h │ │ │ │ │ │ └── system_ARMCM33.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM33_ac6.sct │ │ │ │ │ │ ├── ARMCM33_ac6_s.sct │ │ │ │ │ │ └── startup_ARMCM33.S │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM33.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM33.s │ │ │ │ │ ├── startup_ARMCM33.c │ │ │ │ │ └── system_ARMCM33.c │ │ │ │ ├── ARMCM35P/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM35P.h │ │ │ │ │ │ ├── ARMCM35P_DSP_FP.h │ │ │ │ │ │ ├── ARMCM35P_DSP_FP_TZ.h │ │ │ │ │ │ ├── ARMCM35P_TZ.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMCM35P.h │ │ │ │ │ │ └── system_ARMCM35P.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM35P_ac6.sct │ │ │ │ │ │ ├── ARMCM35P_ac6_s.sct │ │ │ │ │ │ └── startup_ARMCM35P.S │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM35P.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM35P.s │ │ │ │ │ ├── startup_ARMCM35P.c │ │ │ │ │ └── system_ARMCM35P.c │ │ │ │ ├── ARMCM4/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM4.h │ │ │ │ │ │ ├── ARMCM4_FP.h │ │ │ │ │ │ └── system_ARMCM4.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM4_ac5.sct │ │ │ │ │ │ ├── ARMCM4_ac6.sct │ │ │ │ │ │ └── startup_ARMCM4.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM4.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM4.s │ │ │ │ │ ├── startup_ARMCM4.c │ │ │ │ │ └── system_ARMCM4.c │ │ │ │ ├── ARMCM55/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM55.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMCM55.h │ │ │ │ │ │ └── system_ARMCM55.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM55_ac6.sct │ │ │ │ │ │ └── ARMCM55_ac6_s.sct │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ └── gcc_arm.ld │ │ │ │ │ ├── startup_ARMCM55.c │ │ │ │ │ └── system_ARMCM55.c │ │ │ │ ├── ARMCM7/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM7.h │ │ │ │ │ │ ├── ARMCM7_DP.h │ │ │ │ │ │ ├── ARMCM7_SP.h │ │ │ │ │ │ └── system_ARMCM7.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM7_ac5.sct │ │ │ │ │ │ ├── ARMCM7_ac6.sct │ │ │ │ │ │ └── startup_ARMCM7.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMCM7.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMCM7.s │ │ │ │ │ ├── startup_ARMCM7.c │ │ │ │ │ └── system_ARMCM7.c │ │ │ │ ├── ARMCM85/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMCM85.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMCM85.h │ │ │ │ │ │ └── system_ARMCM85.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMCM85_ac6.sct │ │ │ │ │ │ └── ARMCM85_ac6_s.sct │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ └── gcc_arm.ld │ │ │ │ │ ├── startup_ARMCM85.c │ │ │ │ │ └── system_ARMCM85.c │ │ │ │ ├── ARMSC000/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMSC000.h │ │ │ │ │ │ └── system_ARMSC000.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMSC000_ac5.sct │ │ │ │ │ │ ├── ARMSC000_ac6.sct │ │ │ │ │ │ └── startup_ARMSC000.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMSC000.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMSC000.s │ │ │ │ │ ├── startup_ARMSC000.c │ │ │ │ │ └── system_ARMSC000.c │ │ │ │ ├── ARMSC300/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMSC300.h │ │ │ │ │ │ └── system_ARMSC300.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMSC300_ac5.sct │ │ │ │ │ │ ├── ARMSC300_ac6.sct │ │ │ │ │ │ └── startup_ARMSC300.s │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMSC300.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMSC300.s │ │ │ │ │ ├── startup_ARMSC300.c │ │ │ │ │ └── system_ARMSC300.c │ │ │ │ ├── ARMv81MML/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMv81MML_DSP_DP_MVE_FP.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMv81MML.h │ │ │ │ │ │ └── system_ARMv81MML.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMv81MML_ac6.sct │ │ │ │ │ │ └── ARMv81MML_ac6_s.sct │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ └── gcc_arm.ld │ │ │ │ │ ├── startup_ARMv81MML.c │ │ │ │ │ └── system_ARMv81MML.c │ │ │ │ ├── ARMv8MBL/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMv8MBL.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMv8MBL.h │ │ │ │ │ │ └── system_ARMv8MBL.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMv8MBL_ac6.sct │ │ │ │ │ │ ├── ARMv8MBL_ac6_s.sct │ │ │ │ │ │ └── startup_ARMv8MBL.S │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMv8MBL.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMv8MBL.s │ │ │ │ │ ├── startup_ARMv8MBL.c │ │ │ │ │ └── system_ARMv8MBL.c │ │ │ │ ├── ARMv8MML/ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── ARMv8MML.h │ │ │ │ │ │ ├── ARMv8MML_DP.h │ │ │ │ │ │ ├── ARMv8MML_DSP.h │ │ │ │ │ │ ├── ARMv8MML_DSP_DP.h │ │ │ │ │ │ ├── ARMv8MML_DSP_SP.h │ │ │ │ │ │ ├── ARMv8MML_SP.h │ │ │ │ │ │ ├── Template/ │ │ │ │ │ │ │ └── partition_ARMv8MML.h │ │ │ │ │ │ └── system_ARMv8MML.h │ │ │ │ │ └── Source/ │ │ │ │ │ ├── ARM/ │ │ │ │ │ │ ├── ARMv8MML_ac6.sct │ │ │ │ │ │ ├── ARMv8MML_ac6_s.sct │ │ │ │ │ │ └── startup_ARMv8MML.S │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ │ └── startup_ARMv8MML.S │ │ │ │ │ ├── IAR/ │ │ │ │ │ │ └── startup_ARMv8MML.s │ │ │ │ │ ├── startup_ARMv8MML.c │ │ │ │ │ └── system_ARMv8MML.c │ │ │ │ └── SVD/ │ │ │ │ ├── ARMCM0.svd │ │ │ │ ├── ARMCM0P.svd │ │ │ │ ├── ARMCM1.svd │ │ │ │ ├── ARMCM23.svd │ │ │ │ ├── ARMCM3.svd │ │ │ │ ├── ARMCM33.svd │ │ │ │ ├── ARMCM35P.svd │ │ │ │ ├── ARMCM4.svd │ │ │ │ ├── ARMCM55.svd │ │ │ │ ├── ARMCM7.svd │ │ │ │ ├── ARMCM85.svd │ │ │ │ ├── ARMSC000.svd │ │ │ │ ├── ARMSC300.svd │ │ │ │ ├── ARMv8MBL.svd │ │ │ │ └── ARMv8MML.svd │ │ │ ├── _Template_Flash/ │ │ │ │ ├── Abstract.txt │ │ │ │ ├── FlashDev.c │ │ │ │ ├── FlashOS.h │ │ │ │ ├── FlashPrg.c │ │ │ │ ├── NewDevice.uvguix │ │ │ │ ├── NewDevice.uvoptx │ │ │ │ ├── NewDevice.uvprojx │ │ │ │ └── Target.lin │ │ │ └── _Template_Vendor/ │ │ │ ├── ReadMe.txt │ │ │ └── Vendor/ │ │ │ ├── Device/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── Device.h │ │ │ │ │ ├── Template/ │ │ │ │ │ │ └── partition_Device.h │ │ │ │ │ └── system_Device.h │ │ │ │ └── Source/ │ │ │ │ ├── ARM/ │ │ │ │ │ ├── Device_ac5.sct │ │ │ │ │ ├── Device_ac6.sct │ │ │ │ │ ├── startup_Device_ac5.s │ │ │ │ │ ├── startup_Device_ac5_noSct.s │ │ │ │ │ └── startup_Device_ac6.S │ │ │ │ ├── GCC/ │ │ │ │ │ ├── gcc_arm.ld │ │ │ │ │ └── startup_Device.S │ │ │ │ ├── IAR/ │ │ │ │ │ └── startup_Device.s │ │ │ │ ├── startup_Device.c │ │ │ │ └── system_Device.c │ │ │ └── Device_A/ │ │ │ ├── Include/ │ │ │ │ ├── Device.h │ │ │ │ ├── mem_Device.h │ │ │ │ └── system_Device.h │ │ │ └── Source/ │ │ │ ├── ARM/ │ │ │ │ ├── Device.sct │ │ │ │ └── startup_Device.c │ │ │ ├── mmu_Device.c │ │ │ └── system_Device.c │ │ ├── Jenkinsfile │ │ ├── LICENSE.txt │ │ ├── README.md │ │ ├── docker/ │ │ │ ├── dockerfile │ │ │ ├── dockerfile.gnu │ │ │ ├── getDependencies.sh │ │ │ ├── requirements.txt │ │ │ └── rtebuild/ │ │ │ ├── armcc.rtebuild │ │ │ ├── armclang.rtebuild │ │ │ ├── armclang_ltm.rtebuild │ │ │ ├── gcc.rtebuild │ │ │ └── toolchain.rtebuild │ │ └── linter.py │ └── printf/ │ ├── .gitattributes │ ├── .travis.yml │ ├── LICENSE │ ├── Makefile │ ├── README.md │ ├── codecov.yml │ ├── printf.c │ ├── printf.h │ └── test/ │ ├── catch.hpp │ └── test_suite.cpp ├── firmware.ld ├── font.c ├── font.h ├── frequencies.c ├── frequencies.h ├── function.json ├── functions.c ├── functions.h ├── fw-pack.py ├── gen.py ├── genJson.py ├── h --force-with-lease origin main ├── hardware/ │ └── dp32g030/ │ ├── aes.def │ ├── crc.def │ ├── dma.def │ ├── flash.def │ ├── gpio.def │ ├── pmu.def │ ├── portcon.def │ ├── saradc.def │ ├── spi.def │ ├── syscon.def │ └── uart.def ├── helper/ │ ├── battery.c │ ├── battery.h │ ├── boot.c │ ├── boot.h │ ├── rds.c │ └── rds.h ├── init.c ├── main.c ├── misc.c ├── misc.h ├── openocd-win/ │ ├── README.md │ ├── bin/ │ │ └── openocd │ └── openocd/ │ ├── OpenULINK/ │ │ └── ulink_firmware.hex │ ├── README.md │ ├── angie/ │ │ └── angie_bitstream.bit │ ├── bin/ │ │ └── openocd │ ├── contrib/ │ │ ├── 60-openocd.rules │ │ └── libdcc/ │ │ ├── README │ │ ├── dcc_stdio.c │ │ ├── dcc_stdio.h │ │ └── example.c │ ├── distro-info/ │ │ ├── CHANGELOG.md │ │ ├── licenses/ │ │ │ ├── autoconf-2.71/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── COPYING.EXCEPTION │ │ │ │ ├── COPYINGv3 │ │ │ │ ├── NEWS │ │ │ │ ├── README │ │ │ │ └── THANKS │ │ │ ├── automake-1.16.5/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── NEWS │ │ │ │ ├── NEWS-2.0 │ │ │ │ ├── README │ │ │ │ └── THANKS │ │ │ ├── hidapi-hidapi-0.14.0/ │ │ │ │ ├── AUTHORS.txt │ │ │ │ ├── LICENSE-bsd.txt │ │ │ │ ├── LICENSE-gpl3.txt │ │ │ │ ├── LICENSE-orig.txt │ │ │ │ ├── LICENSE.txt │ │ │ │ └── README.md │ │ │ ├── libftdi1-1.5/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING-CMAKE-SCRIPTS │ │ │ │ ├── COPYING.GPL │ │ │ │ ├── COPYING.LIB │ │ │ │ ├── LICENSE │ │ │ │ ├── README │ │ │ │ ├── README.build │ │ │ │ └── README.mingw │ │ │ ├── libiconv-1.17/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── COPYING.LIB │ │ │ │ ├── DEPENDENCIES │ │ │ │ ├── NEWS │ │ │ │ ├── README │ │ │ │ └── THANKS │ │ │ ├── libtool-2.4.7/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── NEWS │ │ │ │ ├── README │ │ │ │ └── THANKS │ │ │ ├── libusb-1.0.26/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── NEWS │ │ │ │ └── README │ │ │ ├── openocd-0.12.0/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── AUTHORS.ChangeLog │ │ │ │ ├── COPYING │ │ │ │ ├── NEWS │ │ │ │ ├── NEWS-0.10.0 │ │ │ │ ├── NEWS-0.11.0 │ │ │ │ ├── NEWS-0.12.0 │ │ │ │ ├── NEWS-0.2.0 │ │ │ │ ├── NEWS-0.3.0 │ │ │ │ ├── NEWS-0.4.0 │ │ │ │ ├── NEWS-0.5.0 │ │ │ │ ├── NEWS-0.6.0 │ │ │ │ ├── NEWS-0.7.0 │ │ │ │ ├── NEWS-0.8.0 │ │ │ │ ├── NEWS-0.9.0 │ │ │ │ ├── README │ │ │ │ ├── README.Windows │ │ │ │ ├── README.macOS │ │ │ │ ├── exceptions/ │ │ │ │ │ └── eCos-exception-2.0 │ │ │ │ ├── license-rules.txt │ │ │ │ ├── preferred/ │ │ │ │ │ ├── BSD-1-Clause │ │ │ │ │ ├── BSD-2-Clause │ │ │ │ │ ├── BSD-2-Clause-Views │ │ │ │ │ ├── BSD-3-Clause │ │ │ │ │ ├── BSD-Source-Code │ │ │ │ │ ├── GFDL-1.2 │ │ │ │ │ ├── GPL-2.0 │ │ │ │ │ ├── LGPL-2.1 │ │ │ │ │ ├── MIT │ │ │ │ │ └── gfdl-1.2.texi.readme │ │ │ │ └── stand-alone/ │ │ │ │ └── GPL-3.0 │ │ │ ├── pkg-config-0.29.2/ │ │ │ │ ├── AUTHORS │ │ │ │ ├── COPYING │ │ │ │ ├── NEWS │ │ │ │ ├── README │ │ │ │ └── README.win32 │ │ │ └── texinfo-7.0.3/ │ │ │ ├── AUTHORS │ │ │ ├── COPYING │ │ │ ├── NEWS │ │ │ ├── README │ │ │ └── README-hacking │ │ └── scripts/ │ │ ├── README-OUT.md │ │ ├── VERSION │ │ ├── application.sh │ │ ├── build.sh │ │ ├── dependencies/ │ │ │ └── openocd.sh │ │ ├── templates/ │ │ │ ├── body-github-release-liquid.md │ │ │ ├── body-jekyll-release-post-part-1-liquid.md │ │ │ └── body-jekyll-release-post-part-2-liquid.md │ │ ├── test.sh │ │ ├── tests/ │ │ │ └── run.sh │ │ └── versioning.sh │ └── scripts/ │ ├── bitsbytes.tcl │ ├── board/ │ │ ├── 8devices-lima.cfg │ │ ├── actux3.cfg │ │ ├── adapteva_parallella1.cfg │ │ ├── adsp-sc584-ezbrd.cfg │ │ ├── alphascale_asm9260_ek.cfg │ │ ├── altera_sockit.cfg │ │ ├── am3517evm.cfg │ │ ├── ampere_emag8180.cfg │ │ ├── ampere_qs_mq_1s.cfg │ │ ├── ampere_qs_mq_2s.cfg │ │ ├── arm_evaluator7t.cfg │ │ ├── arm_musca_a.cfg │ │ ├── arty_s7.cfg │ │ ├── asus-rt-n16.cfg │ │ ├── asus-rt-n66u.cfg │ │ ├── at91cap7a-stk-sdram.cfg │ │ ├── at91eb40a.cfg │ │ ├── at91rm9200-dk.cfg │ │ ├── at91rm9200-ek.cfg │ │ ├── at91sam9261-ek.cfg │ │ ├── at91sam9263-ek.cfg │ │ ├── at91sam9g20-ek.cfg │ │ ├── atmel_at91sam7s-ek.cfg │ │ ├── atmel_at91sam9260-ek.cfg │ │ ├── atmel_at91sam9rl-ek.cfg │ │ ├── atmel_sam3n_ek.cfg │ │ ├── atmel_sam3s_ek.cfg │ │ ├── atmel_sam3u_ek.cfg │ │ ├── atmel_sam3x_ek.cfg │ │ ├── atmel_sam4e_ek.cfg │ │ ├── atmel_sam4l8_xplained_pro.cfg │ │ ├── atmel_sam4s_ek.cfg │ │ ├── atmel_sam4s_xplained_pro.cfg │ │ ├── atmel_samc20_xplained_pro.cfg │ │ ├── atmel_samc21_xplained_pro.cfg │ │ ├── atmel_samd10_xplained_mini.cfg │ │ ├── atmel_samd11_xplained_pro.cfg │ │ ├── atmel_samd20_xplained_pro.cfg │ │ ├── atmel_samd21_xplained_pro.cfg │ │ ├── atmel_same70_xplained.cfg │ │ ├── atmel_samg53_xplained_pro.cfg │ │ ├── atmel_samg55_xplained_pro.cfg │ │ ├── atmel_saml21_xplained_pro.cfg │ │ ├── atmel_samr21_xplained_pro.cfg │ │ ├── atmel_samv71_xplained_ultra.cfg │ │ ├── avnet_ultrazed-eg.cfg │ │ ├── balloon3-cpu.cfg │ │ ├── bcm28155_ap.cfg │ │ ├── bemicro_cycloneiii.cfg │ │ ├── bluefield.cfg │ │ ├── bt-homehubv1.cfg │ │ ├── calao-usb-a9260.cfg │ │ ├── calao-usb-a9g20-c01.cfg │ │ ├── certuspro_evaluation.cfg │ │ ├── colibri.cfg │ │ ├── crossbow_tech_imote2.cfg │ │ ├── csb337.cfg │ │ ├── csb732.cfg │ │ ├── da850evm.cfg │ │ ├── digi_connectcore_wi-9c.cfg │ │ ├── digilent_analog_discovery.cfg │ │ ├── digilent_atlys.cfg │ │ ├── digilent_nexys_video.cfg │ │ ├── digilent_zedboard.cfg │ │ ├── diolan_lpc4350-db1.cfg │ │ ├── diolan_lpc4357-db1.cfg │ │ ├── dk-tm4c129.cfg │ │ ├── dm355evm.cfg │ │ ├── dm365evm.cfg │ │ ├── dm6446evm.cfg │ │ ├── dp_busblaster_v3.cfg │ │ ├── dp_busblaster_v4.cfg │ │ ├── dptechnics_dpt-board-v1.cfg │ │ ├── ecp5_evaluation.cfg │ │ ├── efikamx.cfg │ │ ├── efm32.cfg │ │ ├── eir.cfg │ │ ├── ek-lm3s1968.cfg │ │ ├── ek-lm3s3748.cfg │ │ ├── ek-lm3s6965.cfg │ │ ├── ek-lm3s811-revb.cfg │ │ ├── ek-lm3s811.cfg │ │ ├── ek-lm3s8962.cfg │ │ ├── ek-lm3s9b9x.cfg │ │ ├── ek-lm3s9d92.cfg │ │ ├── ek-lm4f120xl.cfg │ │ ├── ek-lm4f232.cfg │ │ ├── ek-tm4c123gxl.cfg │ │ ├── ek-tm4c1294xl.cfg │ │ ├── embedded-artists_lpc2478-32.cfg │ │ ├── emcraft_imx8m-som-bsb.cfg │ │ ├── emcraft_twr-vf6-som-bsb.cfg │ │ ├── emcraft_vf6-som.cfg │ │ ├── esp32-bridge.cfg │ │ ├── esp32-ethernet-kit-3.3v.cfg │ │ ├── esp32-wrover-kit-1.8v.cfg │ │ ├── esp32-wrover-kit-3.3v.cfg │ │ ├── esp32s2-bridge.cfg │ │ ├── esp32s2-kaluga-1.cfg │ │ ├── esp32s3-bridge.cfg │ │ ├── esp32s3-builtin.cfg │ │ ├── esp32s3-ftdi.cfg │ │ ├── ethernut3.cfg │ │ ├── evb-lan9255.cfg │ │ ├── frdm-kl25z.cfg │ │ ├── frdm-kl46z.cfg │ │ ├── fsl_imx6q_sabresd.cfg │ │ ├── gatemate_eval.cfg │ │ ├── glyn_tonga2.cfg │ │ ├── gowin_runber.cfg │ │ ├── gti/ │ │ │ └── espressobin.cfg │ │ ├── gumstix-aerocore.cfg │ │ ├── hammer.cfg │ │ ├── hilscher_nxdb500sys.cfg │ │ ├── hilscher_nxeb500hmi.cfg │ │ ├── hilscher_nxhx10.cfg │ │ ├── hilscher_nxhx50.cfg │ │ ├── hilscher_nxhx500.cfg │ │ ├── hilscher_nxsb100.cfg │ │ ├── hitex_lpc1768stick.cfg │ │ ├── hitex_lpc2929.cfg │ │ ├── hitex_stm32-performancestick.cfg │ │ ├── hitex_str9-comstick.cfg │ │ ├── iar_lpc1768.cfg │ │ ├── iar_str912_sk.cfg │ │ ├── icnova_imx53_sodimm.cfg │ │ ├── icnova_sam9g45_sodimm.cfg │ │ ├── imx27ads.cfg │ │ ├── imx27lnst.cfg │ │ ├── imx28evk.cfg │ │ ├── imx31pdk.cfg │ │ ├── imx35pdk.cfg │ │ ├── imx53-m53evk.cfg │ │ ├── imx53loco.cfg │ │ ├── imx8mp-evk.cfg │ │ ├── insignal_arndale.cfg │ │ ├── kasli.cfg │ │ ├── kc100.cfg │ │ ├── kc705.cfg │ │ ├── kcu105.cfg │ │ ├── keil_mcb1700.cfg │ │ ├── keil_mcb2140.cfg │ │ ├── kindle2.cfg │ │ ├── kontron_sl28.cfg │ │ ├── kwikstik.cfg │ │ ├── la_fonera-fon2200.cfg │ │ ├── lambdaconcept_ecpix-5.cfg │ │ ├── lemaker_hikey.cfg │ │ ├── linksys-wag200g.cfg │ │ ├── linksys-wrt54gl.cfg │ │ ├── linksys_nslu2.cfg │ │ ├── lisa-l.cfg │ │ ├── logicpd_imx27.cfg │ │ ├── lpc1850_spifi_generic.cfg │ │ ├── lpc4350_spifi_generic.cfg │ │ ├── lubbock.cfg │ │ ├── marsohod.cfg │ │ ├── marsohod2.cfg │ │ ├── marsohod3.cfg │ │ ├── mbed-lpc11u24.cfg │ │ ├── mbed-lpc1768.cfg │ │ ├── mcb1700.cfg │ │ ├── microchip_explorer16.cfg │ │ ├── microchip_sama5d27_som1_kit1.cfg │ │ ├── microchip_same51_curiosity_nano.cfg │ │ ├── microchip_same54_xplained_pro.cfg │ │ ├── microchip_saml11_xplained_pro.cfg │ │ ├── mini2440.cfg │ │ ├── mini6410.cfg │ │ ├── minispartan6.cfg │ │ ├── nds32_corvettef1.cfg │ │ ├── nds32_xc7.cfg │ │ ├── netgear-dg834v3.cfg │ │ ├── netgear-wg102.cfg │ │ ├── nordic_nrf51822_mkit.cfg │ │ ├── nordic_nrf51_dk.cfg │ │ ├── nordic_nrf52_dk.cfg │ │ ├── nordic_nrf52_ftx232.cfg │ │ ├── novena-internal-fpga.cfg │ │ ├── npcx_evb.cfg │ │ ├── numato_mimas_a7.cfg │ │ ├── numato_opsis.cfg │ │ ├── nxp_frdm-k64f.cfg │ │ ├── nxp_frdm-ls1012a.cfg │ │ ├── nxp_imx7sabre.cfg │ │ ├── nxp_lpc-link2.cfg │ │ ├── nxp_mcimx8m-evk.cfg │ │ ├── nxp_rdb-ls1046a.cfg │ │ ├── nxp_rdb-ls1088a.cfg │ │ ├── olimex_LPC2378STK.cfg │ │ ├── olimex_lpc_h2148.cfg │ │ ├── olimex_sam7_ex256.cfg │ │ ├── olimex_sam7_la2.cfg │ │ ├── olimex_sam9_l9260.cfg │ │ ├── olimex_stm32_h103.cfg │ │ ├── olimex_stm32_h107.cfg │ │ ├── olimex_stm32_h405.cfg │ │ ├── olimex_stm32_p107.cfg │ │ ├── omap2420_h4.cfg │ │ ├── openrd.cfg │ │ ├── or1k_generic.cfg │ │ ├── osk5912.cfg │ │ ├── phone_se_j100i.cfg │ │ ├── phytec_lpc3250.cfg │ │ ├── pic-p32mx.cfg │ │ ├── pico-debug.cfg │ │ ├── pipistrello.cfg │ │ ├── propox_mmnet1001.cfg │ │ ├── pxa255_sst.cfg │ │ ├── quark_d2000_refboard.cfg │ │ ├── quark_x10xx_board.cfg │ │ ├── quicklogic_quickfeather.cfg │ │ ├── radiona_ulx3s.cfg │ │ ├── redbee.cfg │ │ ├── reflexces_achilles_i-dev_kit_arria10.cfg │ │ ├── renesas_dk-s7g2.cfg │ │ ├── renesas_falcon.cfg │ │ ├── renesas_gr_peach.cfg │ │ ├── renesas_porter.cfg │ │ ├── renesas_salvator-xs.cfg │ │ ├── renesas_silk.cfg │ │ ├── renesas_stout.cfg │ │ ├── rigado_bmd300_ek.cfg │ │ ├── rpi3.cfg │ │ ├── rpi4b.cfg │ │ ├── rsc-w910.cfg │ │ ├── sayma_amc.cfg │ │ ├── sheevaplug.cfg │ │ ├── sifive-e31arty.cfg │ │ ├── sifive-e51arty.cfg │ │ ├── sifive-hifive1-revb.cfg │ │ ├── sifive-hifive1.cfg │ │ ├── smdk6410.cfg │ │ ├── snps_em_sk.cfg │ │ ├── snps_em_sk_v1.cfg │ │ ├── snps_em_sk_v2.1.cfg │ │ ├── snps_em_sk_v2.2.cfg │ │ ├── snps_hsdk.cfg │ │ ├── snps_hsdk_4xd.cfg │ │ ├── spansion_sk-fm4-176l-s6e2cc.cfg │ │ ├── spansion_sk-fm4-u120-9b560.cfg │ │ ├── spear300evb.cfg │ │ ├── spear300evb_mod.cfg │ │ ├── spear310evb20.cfg │ │ ├── spear310evb20_mod.cfg │ │ ├── spear320cpu.cfg │ │ ├── spear320cpu_mod.cfg │ │ ├── st_b-l475e-iot01a.cfg │ │ ├── st_nucleo_8l152r8.cfg │ │ ├── st_nucleo_8s208rb.cfg │ │ ├── st_nucleo_f0.cfg │ │ ├── st_nucleo_f103rb.cfg │ │ ├── st_nucleo_f3.cfg │ │ ├── st_nucleo_f4.cfg │ │ ├── st_nucleo_f7.cfg │ │ ├── st_nucleo_g0.cfg │ │ ├── st_nucleo_g4.cfg │ │ ├── st_nucleo_h743zi.cfg │ │ ├── st_nucleo_h745zi.cfg │ │ ├── st_nucleo_l073rz.cfg │ │ ├── st_nucleo_l1.cfg │ │ ├── st_nucleo_l4.cfg │ │ ├── st_nucleo_l5.cfg │ │ ├── st_nucleo_wb55.cfg │ │ ├── steval-idb007v1.cfg │ │ ├── steval-idb008v1.cfg │ │ ├── steval-idb011v1.cfg │ │ ├── steval-idb012v1.cfg │ │ ├── steval_pcc010.cfg │ │ ├── stm320518_eval.cfg │ │ ├── stm320518_eval_stlink.cfg │ │ ├── stm32100b_eval.cfg │ │ ├── stm3210b_eval.cfg │ │ ├── stm3210c_eval.cfg │ │ ├── stm3210e_eval.cfg │ │ ├── stm3220g_eval.cfg │ │ ├── stm3220g_eval_stlink.cfg │ │ ├── stm3241g_eval.cfg │ │ ├── stm3241g_eval_stlink.cfg │ │ ├── stm32429i_eval.cfg │ │ ├── stm32429i_eval_stlink.cfg │ │ ├── stm32439i_eval.cfg │ │ ├── stm32439i_eval_stlink.cfg │ │ ├── stm327x6g_eval.cfg │ │ ├── stm32f0discovery.cfg │ │ ├── stm32f103c8_blue_pill.cfg │ │ ├── stm32f334discovery.cfg │ │ ├── stm32f3discovery.cfg │ │ ├── stm32f412g-disco.cfg │ │ ├── stm32f413h-disco.cfg │ │ ├── stm32f429disc1.cfg │ │ ├── stm32f429discovery.cfg │ │ ├── stm32f469discovery.cfg │ │ ├── stm32f469i-disco.cfg │ │ ├── stm32f4discovery.cfg │ │ ├── stm32f723e-disco.cfg │ │ ├── stm32f746g-disco.cfg │ │ ├── stm32f769i-disco.cfg │ │ ├── stm32f7discovery.cfg │ │ ├── stm32h735g-disco.cfg │ │ ├── stm32h745i-disco.cfg │ │ ├── stm32h747i-disco.cfg │ │ ├── stm32h750b-disco.cfg │ │ ├── stm32h7b3i-disco.cfg │ │ ├── stm32h7x3i_eval.cfg │ │ ├── stm32h7x_dual_qspi.cfg │ │ ├── stm32l0discovery.cfg │ │ ├── stm32l476g-disco.cfg │ │ ├── stm32l496g-disco.cfg │ │ ├── stm32l4discovery.cfg │ │ ├── stm32l4p5g-disco.cfg │ │ ├── stm32l4r9i-disco.cfg │ │ ├── stm32ldiscovery.cfg │ │ ├── stm32mp13x_dk.cfg │ │ ├── stm32mp15x_dk2.cfg │ │ ├── stm32vldiscovery.cfg │ │ ├── str910-eval.cfg │ │ ├── telo.cfg │ │ ├── ti_am335xevm.cfg │ │ ├── ti_am437x_idk.cfg │ │ ├── ti_am43xx_evm.cfg │ │ ├── ti_am625_swd_native.cfg │ │ ├── ti_am625evm.cfg │ │ ├── ti_am62a7evm.cfg │ │ ├── ti_am642evm.cfg │ │ ├── ti_am654evm.cfg │ │ ├── ti_beagleboard.cfg │ │ ├── ti_beagleboard_xm.cfg │ │ ├── ti_beaglebone-base.cfg │ │ ├── ti_beaglebone.cfg │ │ ├── ti_beaglebone_black.cfg │ │ ├── ti_blaze.cfg │ │ ├── ti_cc13x0_launchpad.cfg │ │ ├── ti_cc13x2_launchpad.cfg │ │ ├── ti_cc26x0_launchpad.cfg │ │ ├── ti_cc26x2_launchpad.cfg │ │ ├── ti_cc3200_launchxl.cfg │ │ ├── ti_cc3220sf_launchpad.cfg │ │ ├── ti_cc32xx_launchpad.cfg │ │ ├── ti_dk-tm4c129.cfg │ │ ├── ti_ek-tm4c123gxl.cfg │ │ ├── ti_ek-tm4c1294xl.cfg │ │ ├── ti_j7200evm.cfg │ │ ├── ti_j721e_swd_native.cfg │ │ ├── ti_j721evm.cfg │ │ ├── ti_j721s2evm.cfg │ │ ├── ti_msp432_launchpad.cfg │ │ ├── ti_pandaboard.cfg │ │ ├── ti_pandaboard_es.cfg │ │ ├── ti_tmdx570ls20susb.cfg │ │ ├── ti_tmdx570ls31usb.cfg │ │ ├── tocoding_poplar.cfg │ │ ├── topas910.cfg │ │ ├── topasa900.cfg │ │ ├── tp-link_tl-mr3020.cfg │ │ ├── tp-link_wdr4300.cfg │ │ ├── trion_t20_bga256.cfg │ │ ├── twr-k60f120m.cfg │ │ ├── twr-k60n512.cfg │ │ ├── twr-vf65gs10.cfg │ │ ├── twr-vf65gs10_cmsisdap.cfg │ │ ├── tx25_stk5.cfg │ │ ├── tx27_stk5.cfg │ │ ├── unknown_at91sam9260.cfg │ │ ├── uptech_2410.cfg │ │ ├── vd_a53x2_dap.cfg │ │ ├── vd_a53x2_jtag.cfg │ │ ├── vd_m4_dap.cfg │ │ ├── vd_m4_jtag.cfg │ │ ├── vd_m7_jtag.cfg │ │ ├── vd_pulpissimo_jtag.cfg │ │ ├── vd_swerv_jtag.cfg │ │ ├── vd_xt8_jtag.cfg │ │ ├── verdex.cfg │ │ ├── voipac.cfg │ │ ├── voltcraft_dso-3062c.cfg │ │ ├── x300t.cfg │ │ ├── xmc-2go.cfg │ │ ├── xmc1100-boot-kit.cfg │ │ ├── xmc4200-application-kit-actuator.cfg │ │ ├── xmc4300-relax.cfg │ │ ├── xmc4500-application-kit-general.cfg │ │ ├── xmc4500-application-kit-sdram.cfg │ │ ├── xmc4500-relax.cfg │ │ ├── xmc4700-relax.cfg │ │ ├── xmc4800-relax.cfg │ │ ├── xmos_xk-xac-xa8_arm.cfg │ │ ├── xtensa-kc705-ext-dap.cfg │ │ ├── xtensa-kc705-ext.cfg │ │ ├── xtensa-kc705-onboard.cfg │ │ ├── xtensa-palladium-vdebug.cfg │ │ └── xtensa-rt685-ext.cfg │ ├── chip/ │ │ ├── atmel/ │ │ │ └── at91/ │ │ │ ├── aic.tcl │ │ │ ├── at91_pio.cfg │ │ │ ├── at91_pmc.cfg │ │ │ ├── at91_rstc.cfg │ │ │ ├── at91_wdt.cfg │ │ │ ├── at91sam7x128.tcl │ │ │ ├── at91sam7x256.tcl │ │ │ ├── at91sam9261.cfg │ │ │ ├── at91sam9261_matrix.cfg │ │ │ ├── at91sam9263.cfg │ │ │ ├── at91sam9263_matrix.cfg │ │ │ ├── at91sam9_init.cfg │ │ │ ├── at91sam9_sdramc.cfg │ │ │ ├── at91sam9_smc.cfg │ │ │ ├── hardware.cfg │ │ │ ├── pmc.tcl │ │ │ ├── rtt.tcl │ │ │ ├── sam9_smc.cfg │ │ │ └── usarts.tcl │ │ ├── st/ │ │ │ ├── spear/ │ │ │ │ ├── quirk_no_srst.tcl │ │ │ │ ├── spear3xx.tcl │ │ │ │ └── spear3xx_ddr.tcl │ │ │ └── stm32/ │ │ │ ├── stm32.tcl │ │ │ ├── stm32_rcc.tcl │ │ │ └── stm32_regs.tcl │ │ └── ti/ │ │ └── lm3s/ │ │ ├── lm3s.tcl │ │ └── lm3s_regs.tcl │ ├── cpld/ │ │ ├── altera-5m570z-cpld.cfg │ │ ├── altera-epm240.cfg │ │ ├── altera-max10.cfg │ │ ├── altera-maxii.cfg │ │ ├── altera-maxv.cfg │ │ ├── jtagspi.cfg │ │ ├── lattice-lc4032ze.cfg │ │ ├── xilinx-xc3s.cfg │ │ ├── xilinx-xc4v.cfg │ │ ├── xilinx-xc4vfx_40_60_100_140.cfg │ │ ├── xilinx-xc5v.cfg │ │ ├── xilinx-xc5vfx_100_130_200.cfg │ │ ├── xilinx-xc6s.cfg │ │ ├── xilinx-xc6v.cfg │ │ ├── xilinx-xc7.cfg │ │ ├── xilinx-xc7v.cfg │ │ ├── xilinx-xc7vh580t.cfg │ │ ├── xilinx-xc7vh870t.cfg │ │ ├── xilinx-xcf-p.cfg │ │ ├── xilinx-xcf-s.cfg │ │ ├── xilinx-xcr3256.cfg │ │ └── xilinx-xcu.cfg │ ├── cpu/ │ │ ├── arc/ │ │ │ ├── common.tcl │ │ │ ├── em.tcl │ │ │ ├── hs.tcl │ │ │ └── v2.tcl │ │ └── arm/ │ │ ├── arm7tdmi.tcl │ │ ├── arm920.tcl │ │ ├── arm946.tcl │ │ ├── arm966.tcl │ │ └── cortex_m3.tcl │ ├── fpga/ │ │ ├── altera-10m50.cfg │ │ ├── altera-arriaii.cfg │ │ ├── altera-cyclone10.cfg │ │ ├── altera-cycloneiii.cfg │ │ ├── altera-cycloneiv.cfg │ │ ├── altera-cyclonev.cfg │ │ ├── altera-ep3c10.cfg │ │ ├── efinix_titanium.cfg │ │ ├── efinix_trion.cfg │ │ ├── gatemate.cfg │ │ ├── gowin_gw1n.cfg │ │ ├── lattice_certus.cfg │ │ ├── lattice_certuspro.cfg │ │ ├── lattice_ecp2.cfg │ │ ├── lattice_ecp3.cfg │ │ ├── lattice_ecp5.cfg │ │ ├── lattice_machxo3.cfg │ │ ├── xilinx-dna.cfg │ │ └── xilinx-xadc.cfg │ ├── interface/ │ │ ├── altera-usb-blaster.cfg │ │ ├── altera-usb-blaster2.cfg │ │ ├── angie.cfg │ │ ├── arm-jtag-ew.cfg │ │ ├── ast2600-gpiod.cfg │ │ ├── at91rm9200.cfg │ │ ├── beaglebone-jtag-native.cfg │ │ ├── beaglebone-swd-native.cfg │ │ ├── buspirate.cfg │ │ ├── chameleon.cfg │ │ ├── cmsis-dap.cfg │ │ ├── dln-2-gpiod.cfg │ │ ├── dummy.cfg │ │ ├── esp_usb_bridge.cfg │ │ ├── esp_usb_jtag.cfg │ │ ├── estick.cfg │ │ ├── flashlink.cfg │ │ ├── ft232r/ │ │ │ └── radiona_ulx3s.cfg │ │ ├── ft232r.cfg │ │ ├── ftdi/ │ │ │ ├── 100ask-openjtag.cfg │ │ │ ├── ashling-opella-ld-jtag.cfg │ │ │ ├── ashling-opella-ld-swd.cfg │ │ │ ├── axm0432.cfg │ │ │ ├── c232hm.cfg │ │ │ ├── cortino.cfg │ │ │ ├── digilent-hs1.cfg │ │ │ ├── digilent-hs2.cfg │ │ │ ├── digilent_jtag_hs3.cfg │ │ │ ├── digilent_jtag_smt2.cfg │ │ │ ├── digilent_jtag_smt2_nc.cfg │ │ │ ├── dlp-usb1232h.cfg │ │ │ ├── dp_busblaster.cfg │ │ │ ├── dp_busblaster_kt-link.cfg │ │ │ ├── esp32_devkitj_v1.cfg │ │ │ ├── esp32s2_kaluga_v1.cfg │ │ │ ├── flossjtag-noeeprom.cfg │ │ │ ├── flossjtag.cfg │ │ │ ├── flyswatter.cfg │ │ │ ├── flyswatter2.cfg │ │ │ ├── ft232h-module-swd.cfg │ │ │ ├── gw16042.cfg │ │ │ ├── hie-jtag.cfg │ │ │ ├── hilscher_nxhx10_etm.cfg │ │ │ ├── hilscher_nxhx500_etm.cfg │ │ │ ├── hilscher_nxhx500_re.cfg │ │ │ ├── hilscher_nxhx50_etm.cfg │ │ │ ├── hilscher_nxhx50_re.cfg │ │ │ ├── hitex_lpc1768stick.cfg │ │ │ ├── hitex_str9-comstick.cfg │ │ │ ├── icebear.cfg │ │ │ ├── imx8mp-evk.cfg │ │ │ ├── incircuit-icprog.cfg │ │ │ ├── iotlab-usb.cfg │ │ │ ├── isodebug.cfg │ │ │ ├── jtag-lock-pick_tiny_2.cfg │ │ │ ├── jtagkey.cfg │ │ │ ├── jtagkey2.cfg │ │ │ ├── jtagkey2p.cfg │ │ │ ├── kt-link.cfg │ │ │ ├── lambdaconcept_ecpix-5.cfg │ │ │ ├── lisa-l.cfg │ │ │ ├── luminary-icdi.cfg │ │ │ ├── luminary-lm3s811.cfg │ │ │ ├── luminary.cfg │ │ │ ├── m53evk.cfg │ │ │ ├── mbftdi.cfg │ │ │ ├── minimodule-swd.cfg │ │ │ ├── minimodule.cfg │ │ │ ├── minispartan6.cfg │ │ │ ├── miniwiggler.cfg │ │ │ ├── neodb.cfg │ │ │ ├── ngxtech.cfg │ │ │ ├── olimex-arm-jtag-swd.cfg │ │ │ ├── olimex-arm-usb-ocd-h.cfg │ │ │ ├── olimex-arm-usb-ocd.cfg │ │ │ ├── olimex-arm-usb-tiny-h.cfg │ │ │ ├── olimex-jtag-tiny.cfg │ │ │ ├── oocdlink.cfg │ │ │ ├── opendous_ftdi.cfg │ │ │ ├── openocd-usb-hs.cfg │ │ │ ├── openocd-usb.cfg │ │ │ ├── openrd.cfg │ │ │ ├── pipistrello.cfg │ │ │ ├── pls_spc5.cfg │ │ │ ├── redbee-econotag.cfg │ │ │ ├── redbee-usb.cfg │ │ │ ├── rowley-cc-arm-swd.cfg │ │ │ ├── sheevaplug.cfg │ │ │ ├── signalyzer-lite.cfg │ │ │ ├── signalyzer.cfg │ │ │ ├── sipeed-rv-debugger.cfg │ │ │ ├── snps_sdp.cfg │ │ │ ├── steppenprobe.cfg │ │ │ ├── stm32-stick.cfg │ │ │ ├── swd-resistor-hack.cfg │ │ │ ├── ti-icdi.cfg │ │ │ ├── tigard.cfg │ │ │ ├── tumpa-lite.cfg │ │ │ ├── tumpa.cfg │ │ │ ├── turtelizer2-revB.cfg │ │ │ ├── turtelizer2-revC.cfg │ │ │ ├── um232h.cfg │ │ │ ├── vpaclink.cfg │ │ │ ├── xds100v2.cfg │ │ │ ├── xds100v3.cfg │ │ │ └── xt_kc705_ml605.cfg │ │ ├── imx-native.cfg │ │ ├── jlink.cfg │ │ ├── jtag_dpi.cfg │ │ ├── jtag_hat_rpi2.cfg │ │ ├── jtag_vpi.cfg │ │ ├── kitprog.cfg │ │ ├── nulink.cfg │ │ ├── opendous.cfg │ │ ├── openjtag.cfg │ │ ├── osbdm.cfg │ │ ├── parport.cfg │ │ ├── parport_dlc5.cfg │ │ ├── raspberrypi-gpio-connector.cfg │ │ ├── raspberrypi-native.cfg │ │ ├── raspberrypi2-native.cfg │ │ ├── rlink.cfg │ │ ├── rshim.cfg │ │ ├── stlink-dap.cfg │ │ ├── stlink-v1.cfg │ │ ├── stlink-v2-1.cfg │ │ ├── stlink-v2.cfg │ │ ├── stlink.cfg │ │ ├── sysfsgpio-raspberrypi.cfg │ │ ├── ti-icdi.cfg │ │ ├── ulink.cfg │ │ ├── usb-jtag.cfg │ │ ├── usbprog.cfg │ │ ├── vdebug.cfg │ │ ├── vsllink.cfg │ │ └── xds110.cfg │ ├── mem_helper.tcl │ ├── memory.tcl │ ├── mmr_helpers.tcl │ ├── target/ │ │ ├── 1986ве1т.cfg │ │ ├── adsp-sc58x.cfg │ │ ├── aduc702x.cfg │ │ ├── aducm360.cfg │ │ ├── allwinner_v3s.cfg │ │ ├── alphascale_asm9260t.cfg │ │ ├── altera_fpgasoc.cfg │ │ ├── altera_fpgasoc_arria10.cfg │ │ ├── am335x.cfg │ │ ├── am437x.cfg │ │ ├── amdm37x.cfg │ │ ├── ampere_emag.cfg │ │ ├── ampere_qs_mq.cfg │ │ ├── ar71xx.cfg │ │ ├── arm_corelink_sse200.cfg │ │ ├── armada370.cfg │ │ ├── at32ap7000.cfg │ │ ├── at91r40008.cfg │ │ ├── at91rm9200.cfg │ │ ├── at91sam3XXX.cfg │ │ ├── at91sam3ax_4x.cfg │ │ ├── at91sam3ax_8x.cfg │ │ ├── at91sam3ax_xx.cfg │ │ ├── at91sam3nXX.cfg │ │ ├── at91sam3sXX.cfg │ │ ├── at91sam3u1c.cfg │ │ ├── at91sam3u1e.cfg │ │ ├── at91sam3u2c.cfg │ │ ├── at91sam3u2e.cfg │ │ ├── at91sam3u4c.cfg │ │ ├── at91sam3u4e.cfg │ │ ├── at91sam3uxx.cfg │ │ ├── at91sam4XXX.cfg │ │ ├── at91sam4c32x.cfg │ │ ├── at91sam4cXXX.cfg │ │ ├── at91sam4lXX.cfg │ │ ├── at91sam4sXX.cfg │ │ ├── at91sam4sd32x.cfg │ │ ├── at91sam7a2.cfg │ │ ├── at91sam7se512.cfg │ │ ├── at91sam7sx.cfg │ │ ├── at91sam7x256.cfg │ │ ├── at91sam7x512.cfg │ │ ├── at91sam9.cfg │ │ ├── at91sam9260.cfg │ │ ├── at91sam9260_ext_RAM_ext_flash.cfg │ │ ├── at91sam9261.cfg │ │ ├── at91sam9263.cfg │ │ ├── at91sam9g10.cfg │ │ ├── at91sam9g20.cfg │ │ ├── at91sam9g45.cfg │ │ ├── at91sam9rl.cfg │ │ ├── at91sama5d2.cfg │ │ ├── at91samdXX.cfg │ │ ├── at91samg5x.cfg │ │ ├── atheros_ar2313.cfg │ │ ├── atheros_ar2315.cfg │ │ ├── atheros_ar9331.cfg │ │ ├── atheros_ar9344.cfg │ │ ├── atmega128.cfg │ │ ├── atmega128rfa1.cfg │ │ ├── atmega32u4.cfg │ │ ├── atsame5x.cfg │ │ ├── atsaml1x.cfg │ │ ├── atsamv.cfg │ │ ├── avr32.cfg │ │ ├── bcm2711.cfg │ │ ├── bcm281xx.cfg │ │ ├── bcm2835.cfg │ │ ├── bcm2836.cfg │ │ ├── bcm2837.cfg │ │ ├── bcm4706.cfg │ │ ├── bcm4718.cfg │ │ ├── bcm47xx.cfg │ │ ├── bcm5352e.cfg │ │ ├── bcm6348.cfg │ │ ├── bluefield.cfg │ │ ├── bluenrg-x.cfg │ │ ├── c100.cfg │ │ ├── c100config.tcl │ │ ├── c100helper.tcl │ │ ├── c100regs.tcl │ │ ├── cc2538.cfg │ │ ├── cs351x.cfg │ │ ├── davinci.cfg │ │ ├── dragonite.cfg │ │ ├── dsp56321.cfg │ │ ├── dsp568013.cfg │ │ ├── dsp568037.cfg │ │ ├── efm32.cfg │ │ ├── em357.cfg │ │ ├── em358.cfg │ │ ├── eos_s3.cfg │ │ ├── epc9301.cfg │ │ ├── esi32xx.cfg │ │ ├── esp32.cfg │ │ ├── esp32s2.cfg │ │ ├── esp32s3.cfg │ │ ├── esp_common.cfg │ │ ├── exynos5250.cfg │ │ ├── faux.cfg │ │ ├── feroceon.cfg │ │ ├── fm3.cfg │ │ ├── fm4.cfg │ │ ├── fm4_mb9bf.cfg │ │ ├── fm4_s6e2cc.cfg │ │ ├── gd32e23x.cfg │ │ ├── gd32vf103.cfg │ │ ├── gp326xxxa.cfg │ │ ├── hi3798.cfg │ │ ├── hi6220.cfg │ │ ├── hilscher_netx10.cfg │ │ ├── hilscher_netx50.cfg │ │ ├── hilscher_netx500.cfg │ │ ├── icepick.cfg │ │ ├── imx.cfg │ │ ├── imx21.cfg │ │ ├── imx25.cfg │ │ ├── imx27.cfg │ │ ├── imx28.cfg │ │ ├── imx31.cfg │ │ ├── imx35.cfg │ │ ├── imx51.cfg │ │ ├── imx53.cfg │ │ ├── imx6.cfg │ │ ├── imx6sx.cfg │ │ ├── imx6ul.cfg │ │ ├── imx7.cfg │ │ ├── imx7ulp.cfg │ │ ├── imx8m.cfg │ │ ├── imx8qm.cfg │ │ ├── infineon/ │ │ │ └── tle987x.cfg │ │ ├── is5114.cfg │ │ ├── ixp42x.cfg │ │ ├── k1921vk01t.cfg │ │ ├── k40.cfg │ │ ├── k60.cfg │ │ ├── ke0x.cfg │ │ ├── ke1xf.cfg │ │ ├── ke1xz.cfg │ │ ├── kl25.cfg │ │ ├── kl46.cfg │ │ ├── klx.cfg │ │ ├── ks869x.cfg │ │ ├── kx.cfg │ │ ├── lpc11xx.cfg │ │ ├── lpc12xx.cfg │ │ ├── lpc13xx.cfg │ │ ├── lpc17xx.cfg │ │ ├── lpc1850.cfg │ │ ├── lpc1xxx.cfg │ │ ├── lpc2103.cfg │ │ ├── lpc2124.cfg │ │ ├── lpc2129.cfg │ │ ├── lpc2148.cfg │ │ ├── lpc2294.cfg │ │ ├── lpc2378.cfg │ │ ├── lpc2460.cfg │ │ ├── lpc2478.cfg │ │ ├── lpc2900.cfg │ │ ├── lpc2xxx.cfg │ │ ├── lpc3131.cfg │ │ ├── lpc3250.cfg │ │ ├── lpc40xx.cfg │ │ ├── lpc4350.cfg │ │ ├── lpc4357.cfg │ │ ├── lpc4370.cfg │ │ ├── lpc84x.cfg │ │ ├── lpc8nxx.cfg │ │ ├── lpc8xx.cfg │ │ ├── ls1012a.cfg │ │ ├── ls1028a.cfg │ │ ├── ls1046a.cfg │ │ ├── ls1088a.cfg │ │ ├── lsch3_common.cfg │ │ ├── marvell/ │ │ │ ├── 88f3710.cfg │ │ │ ├── 88f3720.cfg │ │ │ └── 88f37x0.cfg │ │ ├── max32620.cfg │ │ ├── max32625.cfg │ │ ├── max3263x.cfg │ │ ├── mc13224v.cfg │ │ ├── mdr32f9q2i.cfg │ │ ├── nds32v5.cfg │ │ ├── ngultra.cfg │ │ ├── nhs31xx.cfg │ │ ├── npcx.cfg │ │ ├── nrf51.cfg │ │ ├── nrf52.cfg │ │ ├── nuc910.cfg │ │ ├── numicro.cfg │ │ ├── numicro_m4.cfg │ │ ├── omap2420.cfg │ │ ├── omap3530.cfg │ │ ├── omap4430.cfg │ │ ├── omap4460.cfg │ │ ├── omap5912.cfg │ │ ├── omapl138.cfg │ │ ├── or1k.cfg │ │ ├── pic32mx.cfg │ │ ├── psoc4.cfg │ │ ├── psoc5lp.cfg │ │ ├── psoc6.cfg │ │ ├── pxa255.cfg │ │ ├── pxa270.cfg │ │ ├── pxa3xx.cfg │ │ ├── qn908x.cfg │ │ ├── qualcomm_qca4531.cfg │ │ ├── quark_d20xx.cfg │ │ ├── quark_x10xx.cfg │ │ ├── readme.txt │ │ ├── renesas_r7s72100.cfg │ │ ├── renesas_rcar_gen2.cfg │ │ ├── renesas_rcar_gen3.cfg │ │ ├── renesas_rcar_reset_common.cfg │ │ ├── renesas_rz_five.cfg │ │ ├── renesas_rz_g2.cfg │ │ ├── renesas_s7g2.cfg │ │ ├── rk3308.cfg │ │ ├── rk3399.cfg │ │ ├── rp2040.cfg │ │ ├── rsl10.cfg │ │ ├── rtl872xd.cfg │ │ ├── samsung_s3c2410.cfg │ │ ├── samsung_s3c2440.cfg │ │ ├── samsung_s3c2450.cfg │ │ ├── samsung_s3c4510.cfg │ │ ├── samsung_s3c6410.cfg │ │ ├── sharp_lh79532.cfg │ │ ├── sim3x.cfg │ │ ├── smp8634.cfg │ │ ├── snps_em_sk_fpga.cfg │ │ ├── snps_hsdk.cfg │ │ ├── snps_hsdk_4xd.cfg │ │ ├── spear3xx.cfg │ │ ├── stellaris.cfg │ │ ├── stm32c0x.cfg │ │ ├── stm32f0x.cfg │ │ ├── stm32f1x.cfg │ │ ├── stm32f2x.cfg │ │ ├── stm32f3x.cfg │ │ ├── stm32f4x.cfg │ │ ├── stm32f7x.cfg │ │ ├── stm32g0x.cfg │ │ ├── stm32g4x.cfg │ │ ├── stm32h7x.cfg │ │ ├── stm32h7x_dual_bank.cfg │ │ ├── stm32l0.cfg │ │ ├── stm32l0_dual_bank.cfg │ │ ├── stm32l1.cfg │ │ ├── stm32l1x_dual_bank.cfg │ │ ├── stm32l4x.cfg │ │ ├── stm32l5x.cfg │ │ ├── stm32mp13x.cfg │ │ ├── stm32mp15x.cfg │ │ ├── stm32u5x.cfg │ │ ├── stm32w108xx.cfg │ │ ├── stm32wbx.cfg │ │ ├── stm32wlx.cfg │ │ ├── stm32x5x_common.cfg │ │ ├── stm32xl.cfg │ │ ├── stm8l.cfg │ │ ├── stm8l151x2.cfg │ │ ├── stm8l151x3.cfg │ │ ├── stm8l152.cfg │ │ ├── stm8l15xx4.cfg │ │ ├── stm8l15xx6.cfg │ │ ├── stm8l15xx8.cfg │ │ ├── stm8s.cfg │ │ ├── stm8s003.cfg │ │ ├── stm8s103.cfg │ │ ├── stm8s105.cfg │ │ ├── str710.cfg │ │ ├── str730.cfg │ │ ├── str750.cfg │ │ ├── str912.cfg │ │ ├── swj-dp.tcl │ │ ├── swm050.cfg │ │ ├── test_reset_syntax_error.cfg │ │ ├── test_syntax_error.cfg │ │ ├── ti-ar7.cfg │ │ ├── ti-cjtag.cfg │ │ ├── ti_calypso.cfg │ │ ├── ti_cc13x0.cfg │ │ ├── ti_cc13x2.cfg │ │ ├── ti_cc26x0.cfg │ │ ├── ti_cc26x2.cfg │ │ ├── ti_cc3220sf.cfg │ │ ├── ti_cc32xx.cfg │ │ ├── ti_dm355.cfg │ │ ├── ti_dm365.cfg │ │ ├── ti_dm6446.cfg │ │ ├── ti_k3.cfg │ │ ├── ti_msp432.cfg │ │ ├── ti_rm4x.cfg │ │ ├── ti_tms570.cfg │ │ ├── ti_tms570lc43xx.cfg │ │ ├── ti_tms570ls20xxx.cfg │ │ ├── ti_tms570ls3137.cfg │ │ ├── tmpa900.cfg │ │ ├── tmpa910.cfg │ │ ├── tnetc4401.cfg │ │ ├── u8500.cfg │ │ ├── vd_aarch64.cfg │ │ ├── vd_cortex_m.cfg │ │ ├── vd_riscv.cfg │ │ ├── vybrid_vf6xx.cfg │ │ ├── xilinx_zynqmp.cfg │ │ ├── xmc1xxx.cfg │ │ ├── xmc4xxx.cfg │ │ ├── xmos_xs1-xau8a-10_arm.cfg │ │ ├── xtensa-core-esp32.cfg │ │ ├── xtensa-core-esp32s2.cfg │ │ ├── xtensa-core-esp32s3.cfg │ │ ├── xtensa-core-nxp_rt600.cfg │ │ ├── xtensa-core-xt8.cfg │ │ ├── xtensa.cfg │ │ ├── zynq_7000.cfg │ │ └── к1879xб1я.cfg │ ├── test/ │ │ ├── selftest.cfg │ │ └── syntax1.cfg │ └── tools/ │ ├── firmware-recovery.tcl │ ├── memtest.tcl │ └── test_cpu_speed.tcl ├── printf_config.h ├── radio.c ├── radio.h ├── scheduler.c ├── settings.c ├── settings.h ├── sram-overlay.c ├── sram-overlay.h ├── start.S ├── ui/ │ ├── aircopy.c │ ├── aircopy.h │ ├── battery.c │ ├── battery.h │ ├── fmradio.c │ ├── fmradio.h │ ├── helper.c │ ├── helper.h │ ├── inputbox.c │ ├── inputbox.h │ ├── lock.c │ ├── lock.h │ ├── main.c │ ├── main.h │ ├── menu.c │ ├── menu.h │ ├── messenger.c │ ├── messenger.h │ ├── scanner.c │ ├── scanner.h │ ├── status.c │ ├── status.h │ ├── ui.c │ ├── ui.h │ ├── welcome.c │ └── welcome.h ├── utils/ │ ├── clean.bat │ ├── main.cpp │ ├── misc.bpf │ ├── misc.bpr │ ├── misc.res │ ├── uv-k5_small.fon │ └── uv-k5_small_bold.fon ├── uv-k5font/ │ ├── chinese_array.txt │ ├── chinese_map.txt │ ├── font-pixel-made/ │ │ ├── ark-pixel-10px-monospaced.ttc │ │ ├── ark-pixel-10px-proportional.ttc │ │ ├── ark-pixel-12px-monospaced.ttc │ │ ├── ark-pixel-12px-proportional.ttc │ │ ├── chinese.txt │ │ ├── font.py │ │ ├── pic.py │ │ └── text.py │ ├── font.cpp │ ├── font.h │ ├── font.xlsx │ ├── font_new/ │ │ ├── chinese_array.txt │ │ ├── font.cpp │ │ ├── font.h │ │ └── main.cpp │ ├── main.cpp │ ├── name.txt │ ├── name_out.txt │ ├── name_out_fina.txt │ ├── name_tmp.txt │ └── uv-k5font_full/ │ ├── chinese_array.txt │ ├── font.cpp │ ├── font.h │ ├── font.xlsx │ ├── gb2312_f.txt │ ├── main.cpp │ ├── name.txt │ ├── name_out.txt │ ├── name_out_fina.txt │ └── name_tmp.txt ├── version.c ├── version.h ├── win_make.bat ├── 写频脚本/ │ ├── picture.py │ └── uvk5_cn.py └── 输入法/ ├── PINYIN.cpp ├── PINYIN.h ├── font.c ├── font.h └── main.cpp ================================================ FILE CONTENTS ================================================ ================================================ FILE: .github/workflows/build.yml ================================================ on: #ָ workflow ¼ push: #ʱ jobs: #幤 build: #Ϊ build runs-on: ubuntu-22.04 #ʹ Ubuntu 22.04 ִ container: # image: archlinux:latest #ʹ Arch Linux steps: #幤еIJ - name: Install dependencies run: | pacman -Syyu --noconfirm \ base-devel \ arm-none-eabi-gcc \ arm-none-eabi-newlib \ git \ python-pip \ python-crcmod \ - name: Checkout #ȡ uses: actions/checkout@v4 #ʹ GitHub Actions ṩ checkout - name: safe.directory # git safe.directory run: git config --global --add safe.directory /__w/uv-k5-firmware-custom/uv-k5-firmware-custom - name: Make #ִ make run: make full #Ŀ - name: size # firmware С run: arm-none-eabi-size firmware #ʹ arm-none-eabi-size ̼С - name: Upload Artifact #ϴ̼ļ uses: actions/upload-artifact@v4 #ʹ GitHub Actions ṩ upload-artifact with: name: firmware # artifact Ϊ firmware path: LOSEHU*.bin #ϴļ·Ϊ LOSEHU*.bin ================================================ FILE: .github/workflows/docker-image.yml ================================================ on: #指定触发 workflow 的事件 workflow_dispatch: #当代码推送时触发 jobs: #定义工作流程 build: #工作流名称为 build runs-on: ubuntu-22.04 #使用 Ubuntu 22.04 环境执行 container: #定义容器 image: archlinux:latest #使用 Arch Linux 镜像 steps: #定义工作流程中的步骤 - name: Install dependencies run: | pacman -Syyu --noconfirm \ base-devel \ arm-none-eabi-gcc \ arm-none-eabi-newlib \ git \ python-pip \ python-crcmod \ zip \ lftp \ python-requests - name: Checkout #拉取代码 uses: actions/checkout@v4 #使用 GitHub Actions 提供的 checkout 动作 - name: safe.directory #设置 git 的 safe.directory 配置 run: git config --global --add safe.directory /__w/uv-k5-firmware-custom/uv-k5-firmware-custom - name: Generate #生成固件 run: | python gen.py python genJson.py - name: Create ZIP file run: | mkdir -p output zip -j output/losehu.zip ./LOSEHU*.bin ./version.json ./function.json - name: Upload ALL #上传固件文件 uses: actions/upload-artifact@v4 #使用 GitHub Actions 提供的 upload-artifact 动作 with: name: firmware_all #设置 artifact 名称为 firmware path: output/losehu.zip #上传文件路径为 LOSEHU*.bin - name: Upload files run: | echo "Uploading LOSEHU.zip to ftp" lftp -u ${{ secrets.FTP_USERNAME }},${{ secrets.FTP_PASSWORD }} ${{ secrets.FTP_SERVER }} < HM1030 0.1 HM1030 Microcontroller registers 8 32 32 read-write 0 0 SYS Registers group SYS 0x40000000 0x00000000 0x188 registers CLK_SEL Clock Select 0x00000000 read-write 0x00000002 0xFFFFFFFF SYS 系统时钟选择 0 RCHF 1 CLK_DIV 0 1 read-write DIV_CLK CLK_DIVx 0 DIV1 1 DIV2 2 DIV4 3 DIV8 4 DIV16 5 DIV32 1 3 read-write SRC_SEL SRC 0 RCHF 1 RCLF 2 XTAH 3 XTAL 4 PLL 4 3 read-write PLL_CLK SRC 0 RCHF 1 XTAH 7 1 read-write ADC ADC 时钟选择 0 DIV1 1 DIV2 2 DIV4 3 DIV8 10 2 read-write DIV_CLK_GATE Clock DIV Enable 0x00000004 read-write 0x00000000 0xFFFFFFFF DIV_EN Clock DIV Enable 0 1 read-write DEV_CLK_GATE Clock Enable 0x00000008 read-write 0x00000000 0xFFFFFFFF GPIOA GPIOA field 0 1 read-write GPIOB GPIOB field 1 1 read-write GPIOC GPIOC field 2 1 read-write IIC0 IIC0 field 4 1 read-write IIC1 IIC1 field 5 1 read-write UART0 UART0 field 6 1 read-write UART1 UART1 field 7 1 read-write UART2 UART2 field 8 1 read-write SPI0 SPI0 field 10 1 read-write SPI1 SPI1 field 11 1 read-write TIMERBASE0 TIMERBASE0 field 12 1 read-write TIMERBASE1 TIMERBASE1 field 13 1 read-write TIMERBASE2 TIMERBASE2 field 14 1 read-write TIMERPLUS0 TIMERPLUS0 field 15 1 read-write TIMERPLUS1 TIMERPLUS1 field 16 1 read-write PWMBASE0 PWMBASE0 field 17 1 read-write PWMBASE1 PWMBASE1 field 18 1 read-write PWMPLUS0 PWMPLUS0 field 20 1 read-write PWMPLUS1 PWMPLUS1 field 21 1 read-write RTC RTC field 22 1 read-write IWDT IWDT field 23 1 read-write WWDT WWDT field 24 1 read-write ADC ADC field 25 1 read-write CRC CRC field 27 1 read-write AES AES field 28 1 read-write RC_FREQ_DELTA RC Register 0x00000078 read-write 0x00000000 0xFFFFFFFF RCLF_DELTA RCLF 差值 0 10 read-write RCLF_SIG RCLF 符号 0 - 1 + 10 1 read-write RCHF_DELTA RCHF 差值 11 10 read-write RCHF_SIG RCHF 符号 0 - 1 + 31 1 read-write VREF_VOLT_DELTA RC Control Register 0x0000007C read-write 0x00000000 0xFFFFFFFF VREF_DELTA VREF 差值 0 5 read-write VREF_SIG VREF 符号 0 - 1 + 6 1 read-write CHIP_ID0 CHIP ID0 Register 0x00000080 read-write 0x00000000 0xFFFFFFFF CHIP_ID0 CHIP_ID0 0 32 read-write CHIP_ID1 CHIP ID1 Register 0x00000084 read-write 0x00000000 0xFFFFFFFF CHIP_ID1 CHIP_ID1 0 32 read-write CHIP_ID2 CHIP ID2 Register 0x00000088 read-write 0x00000000 0xFFFFFFFF CHIP_ID2 CHIP_ID2 0 32 read-write CHIP_ID3 CHIP ID3 Register 0x0000008C read-write 0x00000000 0xFFFFFFFF CHIP_ID3 CHIP_ID3 0 32 read-write RCTRIM_EN RCTRIM_EN Register 0x00000100 read-write 0x00000000 0xFFFFFFFF TIMP_SRC_XTAH_EN TIMP_SRC_XTAH_EN 0 1 read-write TIMP_SRC_RCLF_EN TIMP_SRC_RCLF_EN 1 1 read-write CMP_CFG CMP_CFG Register 0x00000120 read-write 0x00000000 0xFFFFFFFF CMP_EN CMP_EN 0 3 read-write CMP_INTEN CMP_INTEN 8 3 read-write CMP0_HYS CMP0_HYS 16 2 read-write CMP1_HYS CMP1_HYS 18 2 read-write CMP2_HYS CMP2_HYS 20 2 read-write CMP_ST CMP_ST Register 0x00000124 read-write 0x00000000 0xFFFFFFFF BIT0_CMP_OUT CMP_OUT 0 1 read-write BIT1_CMP_OUT CMP_OUT 1 1 read-write BIT2_CMP_OUT CMP_OUT 2 1 read-write BIT0_CMP_ORG_OUT CMP_OUT 8 1 read-write BIT1_CMP_ORG_OUT CMP_OUT 9 1 read-write BIT2_CMP_ORG_OUT CMP_OUT 10 1 read-write COMP0_IF_0TO1 COMP0_IF 16 1 read-write COMP0_IF_1TO0 COMP0_IF 17 1 read-write COMP1_IF_0TO1 COMP0_IF 18 1 read-write COMP1_IF_1TO0 COMP0_IF 19 1 read-write COMP2_IF_0TO1 COMP0_IF 20 1 read-write COMP2_IF_1TO0 COMP0_IF 21 1 read-write OPA_CFG OPA_CFG Register 0x00000140 read-write 0x00000000 0xFFFFFFFF CMP_EN_bit0 CMP_EN 0 1 read-write CMP_EN_bit1 CMP_EN 1 1 read-write PMU Registers group PMU 0x40000800 0x00000000 0x00000084 registers LPOW_MD 低功耗模式选择寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF STANDBY 写1，芯片进入STANDBY模式 0 1 read-write SLEEP 写1，芯片进入SLEEP模式 1 1 read-write DEEPSLEEP 写1，芯片进入DEEPSLEEP模式 2 1 read-write STOP 写1，芯片进入STOP模式 3 1 read-write LPMD_WKEN 低功耗唤醒源使能寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF RTC_ALA_WKEN 低功耗模式下，RTC_ALA唤醒使能 0 1 read-write RTC_TIM_WKEN 低功耗模式下，RTC_TIM唤醒使能 1 1 read-write IO_WKEN 低功耗模式下，IO唤醒使能 2 1 read-write LPMD_WKST 低功耗唤醒源状态寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF RTC_ALA_WKST 低功耗模式下，RTC_ALA唤醒标志 0 1 read-write RTC_TIM_WKST 低功耗模式下，RTC_TIM唤醒标志 1 1 read-write IO_WKST 低功耗模式下，IO唤醒标志 2 1 read-write CHIP_RST_ST 低功耗唤醒源标志寄存器 0x0000000C read-write 0x00000000 0xFFFFFFFF WWDT_RST_ST WWDT复位标志 0 1 read-write IWDT_RST_ST IWDT复位标志 1 1 read-write POR_RST_ST 上电复位标志 2 1 read-write SRC_CFG 时钟控制 0x00000010 read-write 0x00000003 0xFFFFFFFF RCHF_EN RCHF 使能控制位 0 1 read-write RCHF_FSEL RCHF 频率选择控制位 1 1 read-write XTAH_EN XTAH 使能控制位 2 1 read-write XTAL_EN XTAL 使能控制位 3 1 read-write RTC_CLK_SEL RTC 时钟选择 4 1 read-write TRIM_POW0 电压电流TRIM寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF TRIM_V_HP HPBG温度TRIM位 0 4 read-write TRIM_I_HP HPBG电压TRIM位 4 4 read-write TRIM_TEMPCO_HPBG HPBG电压TRIM位 8 4 read-write TRIM_POW1 电压电流TRIM寄存器 0x00000024 read-write 0x00000000 0xFFFFFFFF TRIM_TEMPCO_LPBG LPBG温度trim位 0 4 read-write TRIM_V_LP LPBG电压trim位 4 4 read-write TRIM_POW2 TRIM寄存器 0x00000028 read-write 0x00000000 0xFFFFFFFF TRIM_POW3 TRIM寄存器 0x0000002C read-write 0x00000000 0xFFFFFFFF TRIM_PD_UVLO UVLO33trim位 0 1 read-write TRIM_LPLDO LPLDO电压输出trim位 1 2 read-write TRIM_HPLDO_H HPLDO电压调整到1.264v 3 1 read-write TRIM_RCHF TRIM寄存器 0x00000030 read-write 0x00000000 0xFFFFFFFF TRIM_P RCHF_P_trim位 0 4 read-write TRIM_N RCHF_N_trim位 8 4 read-write TRIM_RCLF TRIM寄存器 0x00000034 read-write 0x00000000 0xFFFFFFFF TRIM_FINE RCLF_FINE_trim位（精调位） 0 4 read-write TRIM_CS RCLF_CS_trim位（粗调位） 8 4 read-write TRIM_OPA TRIM寄存器 0x00000038 read-write 0x00000000 0xFFFFFFFF OPA0_TRIMN OPA0的N端TRIM位 0 5 read-write OPA0_TRIMP OPA0的P端TRIM位 5 5 read-write OPA1_TRIMN OPA1的N端TRIM位 10 5 read-write OPA1_TRIMP OPA1的P端TRIM位 15 5 read-write TRIM_PLL TRIM寄存器 0x0000003C read-write 0x00000000 0xFFFFFFFF PLL_R_TRSIM PLL的R值TRIM位 0 4 read-write TRIM_LOCK TRIM锁定寄存器 0x00000080 read-write 0x00000000 0xFFFFFFFF TRIM_LOCK 写入0x55,TRIM_POW和TRIM_RC不能被改写 0 8 read-write TRIM_UNLOCK 写入0xAA,TRIM_POW和TRIM_RC能被改写 8 8 read-write DMA Registers group DMA 0x40001000 0x00000000 0x174 registers DMA_CTR DMA使能 0x00000000 read-write 0x00000000 0xFFFFFFFF DMA_EN DMA使能 0 1 read-write DMA_INTEN DMA中断使能 0x00000004 read-write 0x00000000 0xFFFFFFFF CH0_TC_INTEN 通道0传输完成中断使能寄存器 0 1 read-write CH1_TC_INTEN 通道1传输完成中断使能寄存器 1 1 read-write CH2_TC_INTEN 通道2传输完成中断使能寄存器 2 1 read-write CH3_TC_INTEN 通道3传输完成中断使能寄存器 3 1 read-write CH0_THC_INTEN 通道0传输一半完成中断使能寄存器 8 1 read-write CH1_THC_INTEN 通道1传输一半完成中断使能寄存器 9 1 read-write CH2_THC_INTEN 通道2传输一半完成中断使能寄存器 10 1 read-write CH3_THC_INTEN 通道3传输一半完成中断使能寄存器 11 1 read-write DMA_INTST DMA中断状态 0x00000008 read-write 0x00000000 0xFFFFFFFF CH0_TC_INTST 通道0传输完成中断状态寄存器 0 1 read-write CH1_TC_INTST 通道1传输完成中断状态寄存器 1 1 read-write CH2_TC_INTST 通道2传输完成中断状态寄存器 2 1 read-write CH3_TC_INTST 通道3传输完成中断状态寄存器 3 1 read-write CH0_THC_INTST 通道0传输一半完成中断状态寄存器 8 1 read-write CH1_THC_INTST 通道1传输一半完成中断状态寄存器 9 1 read-write CH2_THC_INTST 通道2传输一半完成中断状态寄存器 10 1 read-write CH3_THC_INTST 通道3传输一半完成中断状态寄存器 11 1 read-write DMA_CH0CTR DMA通道0控制寄存器 0x00000100 read-write 0x00000000 0xFFFFFFFF EN 通道使能 0 1 read-write LENTH 传输计数 1 12 read-write LOOP 循环方式 13 1 read-write PRI 通道优先级 14 2 read-write SWRED 软件请求开始传输 16 1 read-write DMA_CH0MOD DMA通道0模式寄存器 0x00000104 read-write 0x00000000 0xFFFFFFFF MSADDMOD MS测地址变化方式选择 0 1 read-write MSSIZE MS测总线传输宽度 1 2 read-write MSSEL MS测外设选择 3 3 read-write MDADDMOD MD测地址变化方式选择 8 1 read-write MDSIZE MD测总线传输宽度 9 2 read-write MDSEL MD测外设选择 13 3 read-write DMA_CH0MSADDR DMA通道0源地址寄存器 0x00000108 read-write 0x00000000 0xFFFFFFFF MSADDR MS侧地址(源地址) 0 32 read-write DMA_CH0MDADDR DMA通道0目标地址寄存器 0x0000010C read-write 0x00000000 0xFFFFFFFF MDADDR MD侧地址(目标地址) 0 1 read-write DMA_CH0ST DMA通道0状态寄存器 0x00000110 read-write 0x00000000 0xFFFFFFFF CUR_LENTH 当前已传输个数 0 12 read-write DMA_CH1CTR DMA通道1控制寄存器 0x00000120 read-write 0x00000000 0xFFFFFFFF EN 通道使能 0 1 read-write LENTH 传输计数 1 12 read-write LOOP 循环方式 13 1 read-write PRI 通道优先级 14 2 read-write SWRED 软件请求开始传输 16 1 read-write DMA_CH1MOD DMA通道1模式寄存器 0x00000124 read-write 0x00000000 0xFFFFFFFF MSADDMOD MS测地址变化方式选择 0 1 read-write MSSIZE MS测总线传输宽度 1 2 read-write MSSEL MS测外设选择 3 3 read-write MDADDMOD MD测地址变化方式选择 8 1 read-write MDSIZE MD测总线传输宽度 9 2 read-write MDSEL MD测外设选择 13 3 read-write DMA_CH1MSADDR DMA通道1源地址寄存器 0x00000128 read-write 0x00000000 0xFFFFFFFF MSADDR MS侧地址(源地址) 0 32 read-write DMA_CH1MDADDR DMA通道1目标地址寄存器 0x0000012C read-write 0x00000000 0xFFFFFFFF MDADDR MD侧地址(目标地址) 0 1 read-write DMA_CH1ST DMA通道1状态寄存器 0x00000130 read-write 0x00000000 0xFFFFFFFF CUR_LENTH 当前已传输个数 0 12 read-write DMA_CH2CTR DMA通道2控制寄存器 0x00000140 read-write 0x00000000 0xFFFFFFFF EN 通道使能 0 1 read-write LENTH 传输计数 1 12 read-write LOOP 循环方式 13 1 read-write PRI 通道优先级 14 2 read-write SWRED 软件请求开始传输 16 1 read-write DMA_CH2MOD DMA通道2模式寄存器 0x00000144 read-write 0x00000000 0xFFFFFFFF MSADDMOD MS测地址变化方式选择 0 1 read-write MSSIZE MS测总线传输宽度 1 2 read-write MSSEL MS测外设选择 3 3 read-write MDADDMOD MD测地址变化方式选择 8 1 read-write MDSIZE MD测总线传输宽度 9 2 read-write MDSEL MD测外设选择 13 3 read-write DMA_CH2MSADDR DMA通道2源地址寄存器 0x00000148 read-write 0x00000000 0xFFFFFFFF MSADDR MS侧地址(源地址) 0 32 read-write DMA_CH2MDADDR DMA通道2目标地址寄存器 0x0000014C read-write 0x00000000 0xFFFFFFFF MDADDR MD侧地址(目标地址) 0 1 read-write DMA_CH2ST DMA通道2状态寄存器 0x00000150 read-write 0x00000000 0xFFFFFFFF CUR_LENTH 当前已传输个数 0 12 read-write DMA_CH3CTR DMA通道3控制寄存器 0x00000160 read-write 0x00000000 0xFFFFFFFF EN 通道使能 0 1 read-write LENTH 传输计数 1 12 read-write LOOP 循环方式 13 1 read-write PRI 通道优先级 14 2 read-write SWRED 软件请求开始传输 16 1 read-write DMA_CH3MOD DMA通道3模式寄存器 0x00000164 read-write 0x00000000 0xFFFFFFFF MSADDMOD MS测地址变化方式选择 0 1 read-write MSSIZE MS测总线传输宽度 1 2 read-write MSSEL MS测外设选择 3 3 read-write MDADDMOD MD测地址变化方式选择 8 1 read-write MDSIZE MD测总线传输宽度 9 2 read-write MDSEL MD测外设选择 13 3 read-write DMA_CH3MSADDR DMA通道3源地址寄存器 0x00000168 read-write 0x00000000 0xFFFFFFFF MSADDR MS侧地址(源地址) 0 32 read-write DMA_CH3MDADDR DMA通道3目标地址寄存器 0x0000016C read-write 0x00000000 0xFFFFFFFF MDADDR MD侧地址(目标地址) 0 1 read-write DMA_CH3ST DMA通道3状态寄存器 0x00000170 read-write 0x00000000 0xFFFFFFFF CUR_LENTH 当前已传输个数 0 12 read-write CRC Registers group CRC 0x40003000 0x00000000 0x10 registers CRC_CR CRC控制 0x00000000 read-write 0x00000000 0xFFFFFFFF CRC_EN CRC使能 0 1 read-write INPUT_REV 输入数据是否取反 1 1 read-write INPUT_INV 输入数据翻转寄存器 2 2 read-write OUTPUT_REV 输出数据是否取反 4 1 read-write OUTPUT_INV 输出数据翻转寄存器 5 2 read-write DATA_WIDTH CRC输入数据有效位数寄存器 7 2 read-write CRC_SEL CRC算法选择寄存器 9 2 read-write CRC_IV CRC初值 0x00000004 read-write 0x00000000 0xFFFFFFFF CRC_IV CRC初值 0 32 read-write CRC_DATAIN CRC输入数据寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF CRC_DATAIN CRC输入数据寄存器 0 32 read-write CRC_DATAOUT CRC输出数据寄存器 0x0000000C read-write 0x00000000 0xFFFFFFFF CRC_DATAOUT CRC输出数据寄存器 0 32 read-write GPIOA Registers group GPIO 0x40060000 0x00000000 0x00000024 registers DATA DATA register 0x00000000 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write DIR 0 输入 1 输出 0x00000004 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTLVLTRG Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 0x00000008 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTBE Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 0x0000000C read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTRISEEN Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 0x00000010 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTEN 1 中断使能 0 中断禁止 0x00000014 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTRAWSTAT 中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 0x00000018 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTSTAT INTSTAT.PIN0 = INTRAWSTAT.PIN0 and INTEN.PIN0 0x0000001C read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write INTCLR 写1清除中断标志，只对边沿触发中断有用 0x00000020 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write GPIOB 0x40060800 GPIOC Registers group GPIO 0x40061000 0x00000000 0x00000024 registers DATA DATA register 0x00000000 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write DIR 0 输入 1 输出 0x00000004 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTLVLTRG Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 0x00000008 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTBE Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 0x0000000C read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTRISEEN Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 0x00000010 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTEN 1 中断使能 0 中断禁止 0x00000014 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTRAWSTAT 中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 0x00000018 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTSTAT INTSTAT.PIN0 = INTRAWSTAT.PIN0 and INTEN.PIN0 0x0000001C read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write INTCLR 写1清除中断标志，只对边沿触发中断有用 0x00000020 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write TIMERBASE0 Registers group TIMERBASE 0x40064000 0x00000000 0x000000038 registers TIMERBASE_EN TIMERBASE使能 0x00000000 read-write 0x00000000 0xFFFFFFFF LOW_EN TIMERBASE_LOW定时器使能寄存器 0 1 read-write HIGH_EN TIMERBASE_HIGH定时器使能寄存器 1 1 read-write TIMERBASE_DIV TIMERBASE预分频 0x00000004 read-write 0x00000000 0xFFFFFFFF DIV TIMERBASE计数时钟预分频寄存器 0 16 read-write TIMERBASE_IE TIMERBASE定时器中断使能 0x00000010 read-write 0x00000000 0xFFFFFFFF LOW_IE TIMERBASE_LOW定时器中断使能 0 1 read-write HIGH_IE TIMERBASE_HIGH定时器中断使能 1 1 read-write TIMERBASE_IF TIMERBASE定时器中断状态 0x00000014 read-write 0x00000000 0xFFFFFFFF LOW_IF TIMERBASE_LOW定时器中断状态 0 1 read-write HIGH_IF TIMERBASE_HIGH定时器中断状态 1 1 read-write HIGH_LOAD TIMERBASE_HIGH定时器目标配置寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF LOAD TIMERBASE_HIGH定时器目标配置寄存器 0 16 read-write HIGH_CNT TIMERBASE_HIGH定时器当前计数值 0x00000024 read-write 0x00000000 0xFFFFFFFF CNT TIMERBASE_HIGH定时器当前计数值 0 16 read-write LOW_LOAD TIMERBASE_LOW定时器目标配置寄存器 0x00000030 read-write 0x00000000 0xFFFFFFFF LOAD TIMERBASE_LOW定时器目标配置寄存器 0 16 read-write LOW_CNT TIMERBASE_LOW定时器当前计数值 0x00000034 read-write 0x00000000 0xFFFFFFFF CNT TIMERBASE_LOW定时器当前计数值 0 16 read-write TIMERBASE1 0x40064800 TIMERBASE2 0x40065000 TIMERPLUS0 Registers group TIMERPLUS 0x40067000 0x00000000 0x000000044 registers TIMERPLUS_EN TIMERPLUS使能 0x00000000 read-write 0x00000000 0xFFFFFFFF LOW_EN 低16bit定时器使能寄存器 0 1 read-write HIGH_EN 高16bit定时器使能寄存器 1 1 read-write TIMERPLUS_DIV TIMERPLUS预分频 0x00000004 read-write 0x00000000 0xFFFFFFFF DIV 计数时钟预分频寄存器 0 16 read-write TIMERPLUS_CTR TIMERPLUS配置寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF LOW_MODE TIMER_LOW工作模式寄存器 0 2 read-write LOW_CLKSEL TIMER_LOW计数时钟源选择 2 2 read-write LOW_EXT_SEL TIMER_LOW计数模式或输入捕获模式输入信号选择 4 1 read-write LOW_EXT_EDGE TIMER_LOW计数模式或输入捕获模式输入信号有效沿选择 5 2 read-write LOW_PO_MD TIMER_LOW周期脉冲输出使能 7 1 read-write LOW_DMA_EN DMA读取TIMER_LOW捕获值使能 8 1 read-write HIGH_MODE TIMER_HIGH工作模式寄存器 16 2 read-write HIGH_CLKSEL TIMER_HIGH计数时钟源选择 18 2 read-write HIGH_EXT_SEL TIMER_HIGH计数模式或输入捕获模式输入信号选择 20 1 read-write HIGH_EXT_EDGE TIMER_HIGH计数模式或输入捕获模式输入信号有效沿选择 21 2 read-write HIGH_PO_MD TIMER_HIGH周期脉冲输出使能 23 1 read-write HIGH_DMA_EN DMA读取TIMER_HIGH捕获值使能 24 1 read-write TIMERPLUS_IE TIMERPLUS定时器中断使能 0x00000010 read-write 0x00000000 0xFFFFFFFF LOW_TO_IF TIMERPLUS_LOW达到目标值中断使能 0 1 read-write LOW_PR_IE TIMERPLUS_LOW输入脉冲上升沿中断使能 1 1 read-write LOW_PF_IE TIMERPLUS_LOW输入脉冲下降沿中断使能 2 1 read-write HIGH_TO_IE TIMERPLUS_HIGH达到目标值中断使能 8 1 read-write HIGH_PR_IE TIMERPLUS_HIGH输入脉冲上升沿中断使能 9 1 read-write HIGH_PF_IE TIMERPLUS_HIGH输入脉冲下降沿中断使能 10 1 read-write HALL0_R_IE HALL0上升沿中断使能 16 1 read-write HALL0_F_IE HALL0下降沿中断使能 17 1 read-write HALL1_R_IE HALL1上升沿中断使能 18 1 read-write HALL1_F_IE HALL1下降沿中断使能 19 1 read-write HALL2_R_IE HALL2上升沿中断使能 20 1 read-write HALL2_F_IE HALL2下降沿中断使能 21 1 read-write TIMERPLUS_IF TIMERPLUS定时器中断状态 0x00000014 read-write 0x00000000 0xFFFFFFFF LOW_TO_IF TIMERPLUS_LOW达到目标值中断状态 0 1 read-write LOW_PR_IF TIMERPLUS_LOW输入脉冲上升沿中断状态 1 1 read-write LOW_PF_IF TIMERPLUS_LOW输入脉冲下降沿中断状态 2 1 read-write HIGH_TO_IF TIMERPLUS_HIGH达到目标值中断状态 8 1 read-write HIGH_PR_IF TIMERPLUS_HIGH输入脉冲上升沿中断状态 9 1 read-write HIGH_PF_IF TIMERPLUS_HIGH输入脉冲下降沿中断状态 10 1 read-write HALL0_R_IF HALL0上升沿中断状态 16 1 read-write HALL0_F_IF HALL0下降沿中断状态 17 1 read-write HALL1_R_IF HALL1上升沿中断状态 18 1 read-write HALL1_F_IF HALL1下降沿中断状态 19 1 read-write HALL2_R_IF HALL2上升沿中断状态 20 1 read-write HALL2_F_IF HALL2 下降沿中断状态 21 1 read-write HIGH_LOAD HIGH定时器目标配置寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF LOAD HIGH定时器目标配置寄存器 0 16 read-write HIGH_CNT HIGH定时器当前计数值 0x00000024 read-write 0x00000000 0xFFFFFFFF CNT HIGH定时器当前计数值 0 16 read-write HIGH_CVAL HIGH捕获值计数值 0x00000028 read-write 0x00000000 0xFFFFFFFF CVAL HIGH捕获值计数值 0 16 read-write LOW_LOAD LOW定时器目标配置寄存器 0x00000030 read-write 0x00000000 0xFFFFFFFF LOAD LOW定时器目标配置寄存器 0 16 read-write LOW_CNT LOW定时器当前计数值 0x00000034 read-write 0x00000000 0xFFFFFFFF CNT LOW定时器当前计数值 0 16 read-write LOW_CVAL LOW捕获值计数值 0x00000038 read-write 0x00000000 0xFFFFFFFF CNT LOW捕获值计数值 0 16 read-write HALL_VAL HALL原始信号电平 0x00000040 read-write 0x00000000 0xFFFFFFFF HALL0_VAL HALL0的原始信号电平 0 1 read-write HALL1_VAL HALL1的原始信号电平 1 1 read-write HALL2_VAL HALL2的原始信号电平 2 1 read-write TIMERPLUS1 0x40067800 RTC Registers group RTC 0x40069000 0x00000000 0x30 registers CFG 配置寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF RTC_EN RTC 使能位 0 1 read-write ALM_EN RTC 闹钟功能使能位 1 1 read-write LOAD_EN RTC加载寄存器TR和DR时间设定值 2 1 read-write IE 中断使能寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF SEC_IE 秒中断使能位 0 1 read-write MIN_IE 分钟中断使能位 1 1 read-write HOUR_IE 小时中断使能位 2 1 read-write DATE_IE 日中断使能位 3 1 read-write ALM_IE 闹钟中断使能位 4 1 read-write MS_IE 1/2秒中断使能位 5 1 read-write IF 状态寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF SEC_IF 秒中断响应 0 1 read-write MIN_IF 分钟中断响应 1 1 read-write HOUR_IF 小时中断响应 2 1 read-write DATE_IF 日中断响应 3 1 read-write ALM_IF 闹钟中断响应 4 1 read-write MS_IF 1/2秒中断响应 5 1 read-write TIME_ERR 时间设定有效标志位 8 1 read-write ALM_ERR 闹钟设定有效标志位 9 1 read-write PRE 预分频寄存器 0x00000010 read-write 0x00007fff 0xFFFFFFFF ROUND 预分频整数部分 0 20 read-write DECIMAL 预分频小数部分 20 4 read-write PERIOD 小数计算周期选择 24 1 read-write TR 时间寄存器 0x00000014 read-write 0x00000000 0xFFFFFFFF SEC 设定时间所属秒钟的个位数 0 4 read-write SEC_DEC 设定时间所属秒钟的十位数 4 3 read-write MIN 设定时间所属分钟的个位数 8 4 read-write MIN_DEC 设定时间所属分钟的十位数 12 3 read-write HOUR 设定时间所属小时的个位数 16 4 read-write HOUR_DEC 设定时间所属小时的十位数 20 2 read-write WEEK 设定时间所属星期 24 3 read-write DR 日期寄存器 0x00000018 read-write 0x00000101 0xFFFFFFFF DATE 设定时间所属日期的个位数 0 4 read-write DATE_DEC 设定时间所属日期的十位数 4 2 read-write MONTH 设定时间所属月份的个位数 8 4 read-write MONTH_DEC 设定时间所属月份的十位数 12 1 read-write YEAR 设定时间所属月份的个位数 16 4 read-write YEAR_DEC 设定时间所属月份的十位数 20 4 read-write AR 闹钟寄存器 0x0000001C read-write 0x00000000 0xFFFFFFFF SEC 闹钟时间所属秒钟的个位数 0 4 read-write SEC_DEC 闹钟时间所属秒钟的十位数 4 3 read-write MIN 闹钟时间所属分钟的个位数 8 4 read-write MIN_DEC 闹钟时间所属分钟的十位数 12 3 read-write HOUR 闹钟时间所属小时的个位数 16 4 read-write HOUR_DEC 闹钟时间所属小时的十位数 20 2 read-write WEEKDAY 闹钟时间所属星期 24 7 read-write TSTR 当前时间寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF SEC 当前时间所属秒钟的个位数 0 4 read-write SEC_DEC 当前时间所属秒钟的十位数 4 3 read-write MIN 当前时间所属分钟的个位数 8 4 read-write MIN_DEC 当前时间所属分钟的十位数 12 3 read-write HOUR 当前时间所属小时的个位数 16 4 read-write HOUR_DEC 当前时间所属小时的十位数 20 3 read-write WEEKDAY 当前时间所属星期 24 3 read-write TSDR 当前日期寄存器 0x00000024 read-write 0x00000101 0xFFFFFFFF DATE 当前时间所属的日期的个位数e 0 4 read-write DATE_DEC 当前时间所属的日期的十位数 4 2 read-write MONTH 当前时间所属的月份的个位数 8 1 read-write MONTH_DEC 当前时间所属的月份的十位数 12 1 read-write YEAR 当前时间所属的纪年的个位数 16 4 read-write YEAR_DEC 当前时间所属的纪年的十位数 20 4 read-write CNT 秒标当前计数值 0x00000028 read-write 0x0007FFFF 0xFFFFFFFF CNT_15 20bit计数位 0 20 read-write VALID 当前时间有效标志寄存器 0x0000002C read-write 0x00000000 0xFFFFFFFF CUR_VALID 当前时间有效标志位 0 1 read-write IWDT Registers group IWDT 0x4006A000 0x00000000 0x00000014 registers LOAD 初值寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF IWDTLOAD IWDT计数器的初始值配置寄存器 0 20 read-write VALUE VALUE register 0x00000004 read-only 0x00000000 0xFFFFFFFF CTRL CTRL register 0x00000008 read-write 0x00000000 0xFFFFFFFF IWDTEN IWDT启动位 0 1 read-write INTEN IWDT中断使能位 1 1 read-write IF IWDT状态位 0x0000000C read-write 0x00000000 0xFFFFFFFF IF IF field 0 1 read-write FEED 写0x55喂狗 0x00000010 read-write 0x00000000 0xFFFFFFFF FEED FEED field 0 8 read-write WWDT Registers group WWDT 0x4006A800 0x00000000 0x00000014 registers LOAD 初值寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF INT_LOAD 窗口中断比较值寄存器 0 7 read-write RST_LOAD 窗口复位比较值寄存器 8 6 read-write VALUE VALUE register 0x00000004 read-only 0x00000000 0xFFFFFFFF VALUE 计数值寄存器 0 7 read-write CTRL CTRL register 0x00000008 read-write 0x00000000 0xFFFFFFFF EN 启动位 0 1 read-write INTEN 中断使能位 1 1 read-write PRERSTINTEN 预复位中断使能位 4 1 read-write IF IWDT状态位 0x0000000C read-write 0x00000000 0xFFFFFFFF WININT 窗口中断标志位 0 1 read-write PRERSTINT 预复位中断标志位 1 1 read-write FEED 写0x55喂狗 0x00000010 read-write 0x00000000 0xFFFFFFFF FEED FEED field 0 8 read-write UART0 Registers group UART 0x4006B000 0x00000000 0x00000024 registers CTRL 控制寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF UARTEN UART使能位 0 1 read-write RXEN 接收使能位 1 1 read-write TXEN 发送使能位 2 1 read-write RXDMAEN 接收DMA传输使能 3 1 read-write TXDMAEN 发送DMA传输使能 4 1 read-write NINEBIT 9bit数据模式使能 5 1 read-write PAREN 奇偶校验位使能 6 1 read-write PARMD 奇偶校验模式选择 7 2 read-write STOPMD 发送STOP位长度选择 9 2 read-write ABRDEN 自动波特率检测使能 11 1 read-write ABRDBIT 自动波特率检测位长配置 12 2 read-write TX_DLY 发送延迟时间设置 14 3 read-write BAUD 波特率配置寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF BAUD 波特率配置数据 0 16 read-write TDR 写数据寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF TDR 写数据寄存器 0 9 read-write RDR 读数据寄存器 0x0000000C read-only 0x00000000 0xFFFFFFFF RDR 读数据寄存器 0 9 read-only IE 中断使能寄存器 0x00000010 read-write 0x00000000 0xFFFFFFFF TXDONE 全部数据发送完成中断使能 2 1 read-write PARITYE 接收数据出现奇偶校验错中断使能 3 1 read-write STOPE 接收数据出现停止位错误中断使能 4 1 read-write RXTO 接收超时中断使能 5 1 read-write RXFIFO 接收FIFO中接收的数据达到设定水位中断使能 6 1 read-write TXFIFO 发送FIFO中保存的数据达到设定水位中断使能 7 1 read-write RXFIFO_OVF 接收FIFO溢出中断使能 8 1 read-write ABRD_OVF 自动波特率检测功能计数器溢出中断使能 9 1 read-write IF 中断状态寄存器 0x00000014 read-write 0x00000000 0xFFFFFFFF TXDONE 全部数据发送完成 2 1 read-write PARITYE 接收数据出现奇偶校验错 3 1 read-write STOPE 接收数据出现停止位错误 4 1 read-write RXTO 接收超时标志 5 1 read-write RXFIFO 接收FIFO中接收到的数据达到设定水位 6 1 read-write TXFIFO 发送FIFO中保存的数据达到设定水位 7 1 read-write RXFIFO_OVF 接收FIFO溢出标志 8 1 read-write ABRD_OVF 自动波特率检测功能计数器溢出标志 9 1 read-write RXFIFO_EMPTY 接收FIFO空标志 10 1 read-only RXFIFO_FULL 接收FIFO满标志 11 1 read-only RXFIFO_HFULL 接收FIFO半满标志 12 1 read-only TXFIFO_EMPTY 发送FIFO空标志 13 1 read-only TXFIFO_FULL 发送FIFO满标志 14 1 read-only TXFIFO_HFULL 发送FIFO半满标志 15 1 read-only TXBUSY 数据发送忙标志 16 1 read-only RF_LEVEL 接收FIFO水位标志信号 17 3 read-only TF_LEVEL 发送FIFO水位标志信号 20 3 read-only FIFO FIFO控制寄存器 0x00000018 read-write 0x00000000 0xFFFFFFFF RF_LEVEL 用于RXFIFO产生中断的水位设置 0 3 read-write TF_LEVEL 用于TXFIFO产生中断的水位设置 3 3 read-write RF_CLR RXFIFO清除使能 6 1 read-write TF_CLR TXFIFO清除使能 7 1 read-write FC 流控制配置寄存器 0x0000001C read-write 0x00000000 0xFFFFFFFF CTSEN CTS流控使能 0 1 read-write RTSEN RTS流控使能 1 1 read-write CTSPOL CTS信号极性配置 2 1 read-write RTSPOL RTS信号极性配置 3 1 read-write CTS_SIGNAL 表示线上CTS状态 4 1 read-only RTS_SIGNAL 表示线上RTS状态 5 1 read-only RXTO 接收超时配置寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF RXTO 接收数据超时触发比较值 0 8 read-write UART1 0x4006B800 UART2 0x4006C000 FLASH Registers group FLASH 0x4006F000 0x00000000 0x0000002C registers CFG CFG register 0x00000000 read-write 0x00000000 0xFFFFFFFF READ_MD 读速率模式选择 0 1 read-write NVR_SEL NVR区选择 1 1 read-write MODE 操作模式配置寄存器 2 3 read-write DEEP_PD 配置FLASH进入deep_power_down模式 31 1 read-write ADDR 地址寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF ADDR 18位地址 0 14 read-write WDATA 写数据寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF START 操作启动控制位 0x00000010 read-write 0x00000000 0xFFFFFFFF START 操作启动控制位 0 1 read-write SPIF_ST 状态寄存器 0x00000014 read-write 0x00000000 0xFFFFFFFF INIT_BUSY FLASH初始化忙标志 0 1 read-write BUSY 控制器忙标志 1 1 read-write PROG_BUF_EMPTY 编程数据缓存寄存器空状态标志 2 1 read-only LOCK 操作锁控制 0x00000018 read-write 0x00000000 0xFFFFFFFF LOCK 操作锁控制 0 8 read-write UNLOCK 操作解锁控制 0x0000001C read-write 0x00000000 0xFFFFFFFF UNLOCK 操作解锁控制 0 8 read-write MASK MASK选择 0x00000020 read-write 0x00000000 0xFFFFFFFF SEL 选择 0 2 read-write LOCK 选择锁定控制 2 1 read-write ERASETIME 时间寄存器 0x00000024 read-write 0x7532A31B 0xFFFFFFFF TERASE FLASH扇区擦（全片擦）时，TERASE（TSCE）时间寄存器 0 19 read-write TRCV FLASH扇区擦（全片擦）时，TRCV时间寄存器 19 12 read-write PROGTIME 时间寄存器 0x00000028 read-write 0x001F4360 0xFFFFFFFF TPROG FLASH编程操作时的TPROG时间控制寄存器 0 11 read-write TPGS FLASH编程操作时的TPGS时间控制寄存器 11 11 read-write PORT Registers group PORT 0x400B0000 0x00000000 0x00000070C registers PORTA0_SEL PORTA 功能选择寄存器 0 0x00000000 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 4 read-write PIN1 PIN1 field 4 4 read-write PIN2 PIN2 field 8 4 read-write PIN3 PIN3 field 12 4 read-write PIN4 PIN4 field 16 4 read-write PIN5 PIN5 field 20 4 read-write PIN6 PIN6 field 24 4 read-write PIN7 PIN7 field 28 4 read-write PORTA1_SEL PORTA 功能选择寄存器 1 0x00000004 read-write 0x00000000 0xFFFFFFFF PIN8 PIN8 field 0 4 read-write PIN9 PIN9 field 4 4 read-write PIN10 PIN10 field 8 4 read-write PIN11 PIN11 field 12 4 read-write PIN12 PIN12 field 16 4 read-write PIN13 PIN13 field 20 4 read-write PIN14 PIN14 field 24 4 read-write PIN15 PIN15 field 28 4 read-write PORTB_SEL0 PORTB 功能选择寄存器 0 0x00000008 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 4 read-write PIN1 PIN1 field 4 4 read-write PIN2 PIN2 field 8 4 read-write PIN3 PIN3 field 12 4 read-write PIN4 PIN4 field 16 4 read-write PIN5 PIN5 field 20 4 read-write PIN6 PIN6 field 24 4 read-write PIN7 PIN7 field 28 4 read-write PORTB_SEL1 PORTB 功能选择寄存器 1 0x0000000C read-write 0x01001000 0xFFFFFFFF PIN8 PIN8 field 0 4 read-write PIN9 PIN9 field 4 4 read-write PIN10 PIN10 field 8 4 read-write PIN11 PIN11 field 12 4 read-write PIN12 PIN12 field 16 4 read-write PIN13 PIN13 field 20 4 read-write PIN14 PIN14 field 24 4 read-write PIN15 PIN15 field 28 4 read-write PORTC_SEL0 PORTC 功能选择寄存器 0 0x00000010 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 4 read-write PIN1 PIN1 field 4 4 read-write PIN2 PIN2 field 8 4 read-write PIN3 PIN3 field 12 4 read-write PIN4 PIN4 field 16 4 read-write PIN5 PIN5 field 20 4 read-write PIN6 PIN6 field 24 4 read-write PIN7 PIN7 field 28 4 read-write PORTA_IE PORTA Input Enable register 0 Input Disable 1 Input Enable 0x00000100 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_IE PORTB Input Enable register 0 Input Disable 1 Input Enable 0x00000104 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_IE PORTC Input Enable register 0 Input Disable 1 Input Enable 0x00000108 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PORTA_PU Pull_Up Enable register 0 Pull_Up Disable 1 Pull_Up Enable 0x00000200 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_PU Pull_Up Enable register 0 Pull_Up Disable 1 Pull_Up Enable 0x00000204 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_PU Pull_Up Enable register 0 Pull_Up Disable 1 Pull_Up Enable 0x00000208 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PORTA_PD Pull_Down Enable register 0 Pull_Down Disable 1 Pull_Down Enable 0x00000300 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_PD Pull_Down Enable register 0 Pull_Down Disable 1 Pull_Down Enable 0x00000304 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_PD Pull_Down Enable register 0 Pull_Down Disable 1 Pull_Down Enable 0x00000308 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PORTA_OD Open_Drain Enable register 0 Open_Drain Disable 1 Open_Drain Enable 0x00000400 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_OD Open_Drain Enable register 0 Open_Drain Disable 1 Open_Drain Enable 0x00000404 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_OD Open_Drain Enable register 0 Open_Drain Disable 1 Open_Drain Enable 0x00000408 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PORTA_WKE WakeUp Enable register 0 WakeUp Disable 1 WakeUp Enable 0x00000500 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_WKE WakeUp Enable register 0 WakeUp Disable 1 WakeUp Enable 0x00000504 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_WKE WakeUp Enable register 0 WakeUp Disable 1 WakeUp Enable 0x00000508 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PORT_CFG Configure register 0x00000600 read-write 0x00000000 0xFFFFFFFF PORTA_DS PORTA 驱动能力选择寄存器 0 2 read-write PORTB_DS PORTB 驱动能力选择寄存器 2 2 read-write PORTC_DS PORTC 驱动能力选择寄存器 4 2 read-write PORT_HYS PORT 输入迟滞等级选择 10 1 read-write PORTA_WK_SEL PORTA唤醒功能沿配置 0x00000700 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTB_WK_SEL PORTB唤醒功能沿配置 0x00000704 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PIN8 PIN8 field 8 1 read-write PIN9 PIN9 field 9 1 read-write PIN10 PIN10 field 10 1 read-write PIN11 PIN11 field 11 1 read-write PIN12 PIN12 field 12 1 read-write PIN13 PIN13 field 13 1 read-write PIN14 PIN14 field 14 1 read-write PIN15 PIN15 field 15 1 read-write PORTC_WK_SEL PORTC唤醒功能沿配置 0x00000708 read-write 0x00000000 0xFFFFFFFF PIN0 PIN0 field 0 1 read-write PIN1 PIN1 field 1 1 read-write PIN2 PIN2 field 2 1 read-write PIN3 PIN3 field 3 1 read-write PIN4 PIN4 field 4 1 read-write PIN5 PIN5 field 5 1 read-write PIN6 PIN6 field 6 1 read-write PIN7 PIN7 field 7 1 read-write PWMBASE0 Registers group PWMBASE 0x400B1000 0x00000000 0x00000044 registers EN PWMBASE使能寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF COUNTER_EN PWMBASE计数器使能寄存器 0 1 read-write PWMBASE_DIV PWMBASE时钟预分频寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF PWMBASE_DIV PWMBASE计数时钟预分频寄存器 0 16 read-write PWM_CON PWMBASE输出配置寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF CH0_OUT_INV PWM0CH0输出极性是否翻转寄存器 0 1 read-write CH1_OUT_INV CH1输出极性是否翻转寄存器 1 1 read-write CH2_OUT_INV CH2输出极性是否翻转寄存器 2 1 read-write CH0_OE CH0通道波形输出使能 4 1 read-write CH1_OE CH1通道波形输出使能 5 1 read-write CH2_OE CH2通道波形输出使能 6 1 read-write PWMBASE_PERIOD PWMBASE周期配置寄存器 0x0000000C read-write 0x00000000 0xFFFFFFFF PWM_PERIOD PWM输出周期配置寄存器 0 16 read-write PWMBASE_INTEN PWMBASE_INTEN register 0x00000010 read-write 0x00000000 0xFFFFFFFF CH0_COMP_IE CH0到达翻转点中断使能 0 1 read-write CH1_COMP_IE CH1到达翻转点中断使能 1 1 read-write CH2_COMP_IE CH2到达翻转点中断使能 2 1 read-write POF_IE 周期溢出中断使能 3 1 read-write PWMBASE_IF PWMBASE_IF register 0x00000014 read-write 0x00000000 0xFFFFFFFF CH0_COMP_IF CH0到达翻转点状态 0 1 read-write CH1_COMP_IF CH1到达翻转点状态 1 1 read-write CH2_COMP_IF CH2到达翻转点状态 2 1 read-write POF_IF 周期溢出中断状态 3 1 read-write PWMBASE_CNT PWMBASE当前计数值寄存器 0x00000018 read-only 0x00000000 0xFFFFFFFF PWMBASE_CNT PWMBASE计数器当前计数值寄存器 0 16 read-only PWMBASE_CH0_COMP PWMBASE通道0翻转点配置寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF CH0_COMP CH0翻转点配置寄存器 0 16 read-write PWMBASE_CH1_COMP PWMBASE通道1翻转点配置寄存器 0x00000030 read-write 0x00000000 0xFFFFFFFF CH1_COMP CH1翻转点配置寄存器 0 16 read-write PWMBASE_CH2_COMP PWMBASE通道2翻转点配置寄存器 0x00000040 read-write 0x00000000 0xFFFFFFFF CH2_COMP CH2翻转点配置寄存器 0 16 read-write PWMBASE1 0x400B1800 PWMPLUS0 Registers group PWMPLUS 0x400B4000 0x00000000 0x000000e8 registers PWMPLUS_CFG PWMPLUS配置寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF COUNTER_EN 计数器使能寄存器 0 1 read-write CNT_TYPE PWM计数器行为方式 1 1 read-write CNT_REP PWM计数器循环方式 2 1 read-write OUT_MODE PWM输出模式 3 1 read-write AUTO_RELOAD 自动装载寄存器，表示周期溢出多少次后自动装载一次周期值、比较值、死区值和TRIGGER值。 8 8 read-write PWMPLUS_GEN PWMPLUS通道波形生成寄存器 0x00000004 read-write 0x00000000 0xFFFFFFFF CH0_IDLE 原始CH0通道空闲时输出状态值 0 1 read-write CH0N_IDLE 原始CH0N通道空闲时输出状态值 1 1 read-write CH1_IDLE 原始CH1通道空闲时输出状态值 2 1 read-write CH1N_IDLE 原始CH1N通道空闲时输出状态值 3 1 read-write CH2_IDLE 原始CH2通道空闲时输出状态值 4 1 read-write CH2N_IDLE 原始CH2N通道空闲时输出状态值 5 1 read-write CH0_START 原始CH0通道开始计数时输出状态值 8 1 read-write CH1_START 原始CH1通道计数开始时输出状态值 9 1 read-write CH2_START 原始CH2通道计数开始时输出状态值 10 1 read-write CH0_OUTINV CH0通道输出状态选择 16 1 read-write CH0N_OUTINV CH0N通道输出状态选择 17 1 read-write CH1_OUTINV CH1通道输出状态选择 18 1 read-write CH1N_OUTINV CH1N通道输出状态选择 19 1 read-write CH2_OUTINV CH2通道输出状态选择 20 1 read-write CH2N_OUTINV CH2N通道输出状态选择 21 1 read-write CH0_OE CH0通道波形输出使能 24 1 read-write CH0N_OE CH0N通道波形输出使能 25 1 read-write CH1_OE CH1通道波形输出使能 26 1 read-write CH1N_OE CH1N通道波形输出使能 27 1 read-write CH2_OE CH2通道波形输出使能 28 1 read-write CH2N_OE CH2N通道波形输出使能 29 1 read-write PWMPLUS_CLKSRC PWMPLUS时钟源和分频配置寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF CNT_SRC PWMPLUS计数器计数时钟选择 0 3 read-write EXTPULSE0_EDGE Extpulse0作为计数时钟时边沿选择控制 4 1 read-write EXTPULSE1_EDGE Extpulse1作为计数时钟时边沿选择控制 5 1 read-write PREDIV 内部预分频时钟频率选择。 16 16 read-write PWMPLUS_BRAKE_CFG PWMPLUS刹车配置寄存器 0x0000000c read-write 0x00000000 0xFFFFFFFF CH0_BRAKE CH0/CH0N刹车控制选择 0 3 read-write CH1_BRAKE CH1/CH1N刹车控制选择 3 3 read-write CH2_BRAKE CH2/CH2N刹车控制选择 6 3 read-write BRAKE_LEV 刹车有效电平选择 12 3 read-write BRAKE_CH0POL 刹车时CH0输出电平选择 16 1 read-write BRAKE_CH0NPOL 刹车时CH0N输出电平选择 17 1 read-write BRAKE_CH1POL 刹车时CH1输出电平选择 18 1 read-write BRAKE_CH1NPOL 刹车时CH1N输出电平选择 19 1 read-write BRAKE_CH2POL 刹车时CH2输出电平选择 20 1 read-write BRAKE_CH2NPOL 刹车时CH2N输出电平选择 21 1 read-write BRAKE_FILLER 刹车信号数字滤波控制 24 2 read-write PWMPLUS_MASK_LEV PWMPLUS强制输出电平选择寄存器 0x00000010 read-write 0x00000000 0xFFFFFFFF CH0_MASK_LEV CH0通道屏蔽电平选择 0 1 read-write CH0N_MASK_LEV CH0N通道屏蔽电平选择 1 1 read-write CH1_MASK_LEV CH1通道屏蔽电平选择 2 1 read-write CH1N_MASK_LEV CH1N通道屏蔽电平选择 3 1 read-write CH2_MASK_LEV CH2通道屏蔽电平选择 4 1 read-write CH2N_MASK_LEV CH2N通道屏蔽电平选择 5 1 read-write PWMPLUS_PERIOD PWMPLUS计数器周期值寄存器 0x0000001C read-write 0x00000000 0xFFFFFFFF PERIOD PWMPLUS周期配置寄存器。 0 16 read-write PWMPLUS_CH0_COMP PWMPLUS通道0翻转点配置寄存器 0x00000020 read-write 0x00000000 0xFFFFFFFF CH0_COMP CH0/CH0N翻转点配置寄存器。 0 16 read-write PWMPLUS_CH1_COMP PWMPLUS通道1翻转点配置寄存器 0x00000024 read-write 0x00000000 0xFFFFFFFF CH1_COMP CH1/CH1N翻转点配置寄存器。 0 16 read-write PWMPLUS_CH2_COMP PWMPLUS通道2翻转点配置寄存器 0x00000028 read-write 0x00000000 0xFFFFFFFF CH2_COMP CH2/CH2N翻转点配置寄存器。 0 16 read-write PWMPLUS_CH0_DT PWMPLUS通道0死区长度配置寄存器 0x00000030 read-write 0x00000000 0xFFFFFFFF CH0_DT CH0/CH0N死区长度配置寄存器 0 10 read-write PWMPLUS_CH1_DT PWMPLUS通道1死区长度配置寄存器 0x00000034 read-write 0x00000000 0xFFFFFFFF CH1_DT CH1/CH1N死区长度配置寄存器 0 10 read-write PWMPLUS_CH2_DT PWMPLUS通道2死区长度配置寄存器 0x00000038 read-write 0x00000000 0xFFFFFFFF CH2_DT CH2/CH2N死区长度配置寄存器 0 10 read-write PWMPLUS_TRIG_COMP PWMPLUS内部触发比较值寄存器 0x00000040 read-write 0x00000000 0xFFFFFFFF TRIG_COMP 内部触发点配置寄存器 0 16 read-write PWMPLUS_TRIG_CFG PWMPLUS内部触发配置寄存器 0x00000044 read-write 0x00000000 0xFFFFFFFF TRIGOUT0_SEL 输出的trigger0信号功能选择 0 4 read-write PWMPLUS_IE PWMPLUS中断使能寄存器 0x00000060 read-write 0x00000000 0xFFFFFFFF UP_CH0COMP_IE 向上计数CH0到达翻转点中断使能 0 1 read-write UP_CH1COMP_IE 向上计数CH1到达翻转点中断使能 1 1 read-write UP_CH2COMP_IE 向上计数CH2到达翻转点中断使能 2 1 read-write UP_POF_IE 向上计数周期溢出中断使能 3 1 read-write UP_TRIG_IE 向上计数达到TRIGGER触发点中断使能 4 1 read-write DOWN_CH0COMP_IE 向下计数CH0到达翻转点中断使能 8 1 read-write DOWN_CH1COMP_IE 向下计数CH1到达翻转点中断使能 9 1 read-write DOWN_CH2COMP_IE 向下计数CH2到达翻转点中断使能 10 1 read-write DOWN_POF_IE 向下计数周期溢出中断使能 11 1 read-write DOWN_TRIG_IE 向下计数达到TRIGGER触发点中断使能 12 1 read-write BRAK0_IE 刹车0中断使能 16 1 read-write BRAK1_IE 刹车1中断使能 17 1 read-write BRAK2_IE 刹车2中断使能 18 1 read-write AUTORELOAD_IE 自动装载中断使能 19 1 read-write PWMPLUS_IF PWMPLUS中断状态寄存器 0x00000064 read-write 0x00000000 0xFFFFFFFF UP_CH0COMP_IF 向上计数CH0到达翻转点中断状态 0 1 read-write UP_CH1COMP_IF 向上计数CH1到达翻转点中断状态 1 1 read-write UP_CH2COMP_IF 向上计数CH2到达翻转点中断状态 2 1 read-write UP_POF_IF 向上计数周期溢出中断状态 3 1 read-write UP_TRIG_IF 向上计数达到TRIGGER触发点中断状态 4 1 read-write DOWN_CH0COMP_IF 向下计数CH0到达翻转点中断状态 8 1 read-write DOWN_CH1COMP_IF 向下计数CH1到达翻转点中断状态 9 1 read-write DOWN_CH2COMP_IF 向下计数CH2到达翻转点中断状态 10 1 read-write DOWN_POF_IF 向下计数周期溢出中断状态 11 1 read-write DOWN_TRIG_IF 向下计数达到TRIGGER触发点中断状态 12 1 read-write BRAK0_IF 刹车0中断状态 16 1 read-write BRAK1_IF 刹车1中断状态 17 1 read-write BRAK2_IF 刹车2中断状态 18 1 read-write AUTORELOAD_IF 自动装载中断状态 19 1 read-write PWMPLUS_SWLOAD PWMPLUS配置寄存器软件加载寄存器 0x00000084 read-write 0x00000000 0xFFFFFFFF SWLOAD PWM配置寄存器软件LOAD控制位 0 1 read-write PWMPLUS_MASK_EN PWMPLUS屏蔽使能控制寄存器 0x00000088 read-write 0x00000000 0xFFFFFFFF CH0_MASK_EN CH0通道屏蔽使能 0 1 read-write CH0N_MASK_EN CH0N通道屏蔽使能 1 1 read-write CH1_MASK_EN CH1通道屏蔽使能 2 1 read-write CH1N_MASK_EN CH1N通道屏蔽使能 3 1 read-write CH2_MASK_EN CH2通道屏蔽使能 4 1 read-write CH2N_MASK_EN CH2N通道屏蔽使能 5 1 read-write PWMPLUS_CNT_ST PWMPLUS计数器状态寄存器 0x000000E0 read-only 0x00000000 0xFFFFFFFF PWMPLUS_CNT PWM计数器当前计数值寄存器 0 16 read-write CNT_DIR PWM计数器当前计数方向 16 1 read-write CNT_ST PWM计数器工作状态 17 1 read-write PWMPLUS_BRAKE_ST PWMPLUS刹车状态寄存器 0x000000E4 read-write 0x00000000 0xFFFFFFFF BRAKE_ST 刹车输入信号当前状态 0 2 read-write PWMPLUS1 0x400B4800 SPI0 Registers group SPI 0x400B8000 0x00000000 0x0000001C registers CR CR register 0x00000000 read-write 0x00000000 0xFFFFFFFF SPR0 SPI波特率选择位0 0 1 read-write SPR1 SPI波特率选择位1 1 1 read-write SPR2 SPI波特率选择位2 2 1 read-write SPE SPI系统使能 3 1 read-write CPHA 时钟相位选择 4 1 read-write CPOL 时钟极性选择 5 1 read-write MSTR 主从模式选择 6 1 read-write LSB 数据传输顺序选择 7 1 read-write CPHA_DATAHOLD_S 从模式下 CPHA 为 1 时，数据保持时间配置寄存器 8 4 read-write SSN 主模式下SSN输出 12 1 read-write RXDMAEN 接收DMA控制使能位 13 1 read-write TXDMAEN 发送DMA控制使能位 14 1 read-write RF_CLR 接收FIFO清除位 15 1 read-write TF_CLR 发送FIFO清除位 16 1 read-write WDR WDR register 0x00000004 read-write 0x00000000 0xFFFFFFFF WDR 写数据寄存器 0 8 read-write RDR RDR register 0x00000008 read-write 0x00000000 0xFFFFFFFF RDR 读数据寄存器 0 8 read-only IE IE register 0x00000010 read-write 0x00000000 0xFFFFFFFF RXFIFO_OVF 接收FIFO溢出中断使能 0 1 read-write RXFIFO_FULL 接收FIFO满中断使能 1 1 read-write RXFIFO_HFULL 接收FIFO半满中断使能 2 1 read-write TXFIFO_EMPTY 发送FIFO空中断使能 3 1 read-write TXFIFO_HFULL 发送FIFO半满中断使能 4 1 read-write IF IF register 0x00000014 read-write 0x00000000 0xFFFFFFFF RXFIFO_OVF 接收FIFO溢出标志 0 1 read-write RXFIFO_FULL 接收FIFO满标志 1 1 read-write RXFIFO_HFULL 接收FIFO半满标志 2 1 read-write TXFIFO_EMPTY 发送FIFO空标志 3 1 read-write TXFIFO_HFULL 发送FIFO半满标志 4 1 read-write BUSY SPI忙标志 5 1 read-write FIFOST FIFOST register 0x00000018 read-write 0x00000000 0xFFFFFFFF RFE 接收FIFO空标志 0 1 read-only RFF 接收FIFO满标志 1 1 read-only RFHF 接收FIFO半满标志 2 1 read-only TFE 发送FIFO空标志 3 1 read-only TFF 发送FIFO满标志 4 1 read-only TFHF 发送FIFO半满标志 5 1 read-only RF_LEVEL 接收FIFO水位状态 6 3 read-only TF_LEVEL 发送FIFO水位状态 9 3 read-only SPI1 0x400B8800 IIC0 Registers group IIC 0x400B9000 0x00000000 0x00000038 registers CCFG 通用配置寄存器 0x00000000 read-write 0x0000010C 0xFFFFFFFF EN IIC 总线使能 0 1 read-write MODE 模式控制 1 1 read-write HS High-speed mode。 2 1 read-write DNF ReceiveSDA、SCL数字噪声滤波 3 4 read-write CST CST register 0x00000004 read-only 0x00000006 0xFFFFFFFF BUSY 总线忙状态 0 1 read-only SCL IICSCL状态 1 1 read-only SDA IICSDA状态 2 1 read-only SLV_ACTIVE Slave活跃状态 8 1 read-only SLV_RD Slave读状态 9 1 read-only SLV_WR Slave写状态 10 1 read-only SLV_STRETCH_BUSY SlaveClockStretching忙状态 11 1 read-only SLV_RXDT Slave接收到的数据类型 12 2 read-only CTRANS CTRANS register 0x00000008 read-write 0x00000000 0xFFFFFFFF TX_ACK 发送 ACK/NACK 0 1 read-write RX_ACK 接收到的ACK/NACK 1 1 read-only TXD_CLR 发送数据寄存器清空 2 1 write RXDATA RXDATA register 0x0000000C read-only 0x00000000 0xFFFFFFFF RXDATA 接收数据寄存器 0 8 read-only TXDATA TXDATA register 0x00000010 read-write 0x00000000 0xFFFFFFFF TXDATA 发送数据寄存器 0 8 read-write IE IE register 0x00000014 read-write 0x00000001 0xFFFFFFFF RXOVF 接收数据寄存器溢出中断使能 2 1 read-write TXF 发送数据结束中断使能 3 1 read-write RXF 接收数据结束中断使能 4 1 read-write SLV_STA Slave检测到START中断使能 8 1 read-write SLV_STO Slave检测到STOP中断使能 9 1 read-write AL Master仲裁丢失总线中断使能 16 1 read-write MLTO Master SCL LOW 超时中断使能 17 1 read-write IF IF register 0x00000018 read-write 0x00000001 0xFFFFFFFF TXE 发送数据寄存器空 0 1 read-write RXNE 接收数据寄存器非空 1 1 read-write RXOVF 接收数据寄存器溢出 2 1 read-write TXF 发送数据结束 3 1 read-write RXF 接收数据结束 4 1 read-write SLV_STA Slave检测到START 8 1 read-write SLV_STO Slave检测到STOP 9 1 read-write AL Master仲裁丢失总线 16 1 read-write MLTO Master SCL LOW 超时 17 1 read-write MCTRL MCTRL register 0x00000020 read-write 0x00000000 0xFFFFFFFF STA 写1，产生START 0 1 read-write RD 写1，接收数据到RXDATA中 1 1 read-write WR 写1，发送TXDATA中数据 2 1 read-write STO 写1,产生STOP， 3 1 read-write MSPC MSPC register 0x00000024 read-write 0x00034080 0xFFFFFFFF SCL_LOW SCL时钟低电平时间配置 0 8 read-write SCL_HI SCL时钟高电平时间配置 8 8 read-write CPD 时钟预分频，详见SCL_HI和SCL_LOW描述 16 8 read-write DAT_HD SDA数据保持时间配置 24 8 read-write SCTRL SCTRL register 0x00000030 read-write 0x00000000 0xFFFFFFFF ADMD slave地址模式控制 0 1 read-write MCDE Master Code Detect Enable 1 1 read-write STRETCH Clock stretching使能控制 2 1 read-write ASDS Stretching 后数据建立时间自适应使能 3 1 read-write SADDR SADDR register 0x00000034 read-write 0x00000000 0xFFFFFFFF ADDR0 地址 0 1 read-write ADDR7_1 地址[7:1] 1 7 read-write ADDR9_8 地址[9:8] 8 2 read-write MASK_ADDR0 Slave 对应地址位掩码 16 1 read-write MASK_ADDR7_1 Slave 对应地址位掩码 17 7 read-write IIC1 0x400B9800 ADC Registers group ADC 0x400BA000 0x00000000 0x000000F8 registers CTRL CTRL register 0x00000000 read-write 0x00000000 0xFFFFFFFF CH0 通道0选中 0 1 read-write CH1 通道1选中 1 1 read-write CH2 通道2选中 2 1 read-write CH3 通道3选中 3 1 read-write CH4 通道4选中 4 1 read-write CH5 通道5选中 5 1 read-write CH6 通道6选中 6 1 read-write CH7 通道7选中 7 1 read-write CH8 通道8选中 8 1 read-write CH9 通道9选中 9 1 read-write CH10 通道10选中 10 1 read-write CH11 通道11选中 11 1 read-write CH12 通道12选中 12 1 read-write CH13 通道13选中 13 1 read-write CH14 通道14选中 14 1 read-write CH15 通道15选中 15 1 read-write AVG 一次启动 ADC 采样取平均次数配置寄存器 16 2 read-write CONT ADC 采样工作模式 18 1 read-write SMPL_SETUP 外部采样时钟下采样建立时间 19 3 read-write ADC_MEM_MODE ADC 数据存储方式选择 22 1 read-write ADC_SMPL_CLK ADC采样模式选择 23 1 read-write IN_SMPL_WIN ADC 内部采样时钟方式采样窗口设置 24 3 read-write ADC_EN ADC使能位 27 1 read-write ADC_TRIG ADC触发源选择 28 1 read-write DMA_EN DMA读取FIFO使能 29 1 read-write START START register 0x00000004 read-write 0x00000000 0xFFFFFFFF START 启动信号 0 1 read-write BUSY 忙信号 1 1 read-only SOFT_RESET 软复位使能 2 1 read-write FIFOCLR FIFO清除使能 3 1 read-write IE IE register 0x00000008 read-write 0x00000000 0xFFFFFFFF CH0_EOC 通道0转换完成中断使能 0 1 read-write CH1_EOC 通道1转换完成中断使能 1 1 read-write CH2_EOC 通道2转换完成中断使能 2 1 read-write CH3_EOC 通道3转换完成中断使能 3 1 read-write CH4_EOC 通道4转换完成中断使能 4 1 read-write CH5_EOC 通道5转换完成中断使能 5 1 read-write CH6_EOC 通道6转换完成中断使能 6 1 read-write CH7_EOC 通道7转换完成中断使能 7 1 read-write CH8_EOC 通道8转换完成中断使能 8 1 read-write CH9_EOC 通道9转换完成中断使能 9 1 read-write CH10_EOC 通道10转换完成中断使能 10 1 read-write CH11_EOC 通道11转换完成中断使能 11 1 read-write CH12_EOC 通道12转换完成中断使能 12 1 read-write CH13_EOC 通道13转换完成中断使能 13 1 read-write CH14_EOC 通道14转换完成中断使能 14 1 read-write CH15_EOC 通道15转换完成中断使能 15 1 read-write FIFO_FULL FIFO满中断使能 16 1 read-write FIFO_HFULL FIFO半满中断使能 17 1 read-write FIFO_OVF FIFO溢出中断使能 18 1 read-write IF IF register 0x0000000C read-write 0x00000000 0xFFFFFFFF CH0_EOC 通道0转换完成中断状态 0 1 read-write CH1_EOC 通道1转换完成中断状态 1 1 read-write CH2_EOC 通道2转换完成中断状态 2 1 read-write CH3_EOC 通道3转换完成中断状态 3 1 read-write CH4_EOC 通道4转换完成中断状态 4 1 read-write CH5_EOC 通道5转换完成中断状态 5 1 read-write CH6_EOC 通道6转换完成中断状态 6 1 read-write CH7_EOC 通道7转换完成中断状态 7 1 read-write CH8_EOC 通道8转换完成中断状态 8 1 read-write CH9_EOC 通道9转换完成中断状态 9 1 read-write CH10_EOC 通道10转换完成中断状态 10 1 read-write CH11_EOC 通道11转换完成中断状态 11 1 read-write CH12_EOC 通道12转换完成中断状态 12 1 read-write CH13_EOC 通道13转换完成中断状态 13 1 read-write CH14_EOC 通道14转换完成中断状态 14 1 read-write CH15_EOC 通道15转换完成中断状态 15 1 read-write FIFO_FULL FIFO满中断状态 16 1 read-write FIFO_HFULL FIFO半满中断状态 17 1 read-write FIFO_OVF FIFO溢出中断状态 18 1 read-write CH0_STATE CH0_STATE register 0x00000010 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH0_DATA CH0_DATA register 0x00000014 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH1_STATE CH1_STATE register 0x00000018 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH1_DATA CH1_DATA register 0x0000001C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH2_STATE CH2_STATE register 0x00000020 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH2_DATA CH2_DATA register 0x00000024 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH3_STATE CH3_STATE register 0x00000028 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH3_DATA CH3_DATA register 0x0000002C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH4_STATE CH4_STATE register 0x00000030 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH4_DATA CH4_DATA register 0x00000034 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH5_STATE CH5_STATE register 0x00000038 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH5_DATA CH5_DATA register 0x0000003C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH6_STATE CH6_STATE register 0x00000040 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH6_DATA CH6_DATA register 0x00000044 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH7_STATE CH7_STATE register 0x00000048 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH7_DATA CH7_DATA register 0x0000004C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH8_STATE CH8_STATE register 0x00000050 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH8_DATA CH8_DATA register 0x00000054 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH9_STATE CH9_STATE register 0x00000058 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH9_DATA CH9_DATA register 0x0000005C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH10_STATE CH10_STATE register 0x00000060 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH10_DATA CH10_DATA register 0x00000064 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH11_STATE CH11_STATE register 0x00000068 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH11_DATA CH11_DATA register 0x0000006C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH12_STATE CH12_STATE register 0x00000070 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH12_DATA CH12_DATA register 0x00000074 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH13_STATE CH13_STATE register 0x00000078 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH13_DATA CH13_DATA register 0x0000007C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH14_STATE CH14_STATE register 0x00000080 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH14_DATA CH14_DATA register 0x00000084 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only CH15_STATE CH15_STATE register 0x00000088 read-only 0x00000000 0xFFFFFFFF EOC 转换完成标志 0 1 read-only OVF 溢出标志 1 1 read-only CH15_DATA CH15_DATA register 0x0000008C read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only FIFO_STATE FIFO_STATE register 0x000000A0 read-only 0x00000000 0xFFFFFFFF FULL 满标志 0 1 read-only HFULL 半满标志 1 1 read-write EMPTY 空标志 2 1 read-write OVF 溢出标志 3 1 read-write LEVEL 水位 4 4 read-write FIFO_DATA FIFO_DATA register 0x000000A4 read-only 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-only NUM 通道编号 12 4 read-only EXTTRIG_SEL 外部信号触发ADC选择寄存器 0x000000B0 read-write 0x00000000 0xFFFFFFFF DATA 通道12bit数据 0 12 read-write ADC_CALIB_OFFSET ADC_CALIB_OFFSET register 0x000000F0 read-write 0x00000000 0xFFFFFFFF OFFSET ADC数据校准的OFFSET值 0 8 read-write OFFSET_VALID OFFSET数据是否有效 16 1 read-write ADC_CALIB_KD ADC_CALIB_KD register 0x000000F4 read-write 0x00000000 0xFFFFFFFF KD ADC数据校准K值的小数部分 0 10 read-write VALID KD数据是否有效 16 1 read-write AES Registers group AES 0x400BD000 0x00000000 0x00000030 registers CR 控制寄存器 0x00000000 read-write 0x00000000 0xFFFFFFFF EN 使能信号 0 1 read-write DATATYPE 数据类型选择 1 2 read-write MODE 模式选择 3 2 read-write CHMOD 链接模式选择 5 2 read-write CCFC 计算完成标志清除 7 1 read-write ERRC 错误标志清除 8 1 read-write SR 状态寄存器 0x00000004 read-only 0x00000000 0xFFFFFFFF CCF 计算完成标志 0 1 read-only RDERR 读取错误标志 1 1 read-only WRERR 写入错误标志 2 1 read-only DINR 输入数据寄存器 0x00000008 read-write 0x00000000 0xFFFFFFFF DINR 输入数据寄存器 0 32 read-write DOUTR 输出数据寄存器 0x0000000C read-only 0x00000000 0xFFFFFFFF DOUTR 数据输出寄存器 0 32 read-only KEYR0 密钥寄存器0 0x00000010 read-write 0x00000000 0xFFFFFFFF KEYR 密钥寄存器[31:0] 0 32 read-write KEYR1 密钥寄存器1 0x00000014 read-write 0x00000000 0xFFFFFFFF KEYR 密钥寄存器[63:32] 0 32 read-write KEYR2 密钥寄存器2 0x00000018 read-write 0x00000000 0xFFFFFFFF KEYR 密钥寄存器[95:64] 0 32 read-write KEYR3 密钥寄存器3 0x0000001C read-write 0x00000000 0xFFFFFFFF KEYR 密钥寄存器[127:96] 0 32 read-write IVR0 加密起始点寄存器0 0x00000020 read-write 0x00000000 0xFFFFFFFF IVR 初始化向量寄存器[31：0] 0 1 read-write IVR1 加密起始点寄存器1 0x00000024 read-write 0x00000000 0xFFFFFFFF IVR 初始化向量寄存器[63:32] 0 1 read-write IVR2 加密起始点寄存器2 0x00000028 read-write 0x00000000 0xFFFFFFFF IVR 初始化向量寄存器[95:64] 0 1 read-write IVR3 加密起始点寄存器3 0x0000002C read-write 0x00000000 0xFFFFFFFF IVR 初始化向量寄存器（MSB IVR [127：96]） 0 1 read-write ================================================ FILE: Dockerfile ================================================ FROM --platform=amd64 archlinux:latest RUN pacman -Syyu base-devel --noconfirm RUN pacman -Syyu arm-none-eabi-gcc --noconfirm RUN pacman -Syyu arm-none-eabi-newlib --noconfirm RUN pacman -Syyu git --noconfirm RUN pacman -Syyu python-pip --noconfirm RUN pacman -Syyu python-crcmod --noconfirm WORKDIR /app COPY . . RUN git submodule update --init --recursive #RUN make && cp firmware* compiled-firmware/ ================================================ FILE: Dockerfile_cn ================================================ # 使用指定平台和最新的 Arch Linux 镜像 FROM --platform=amd64 archlinux:latest # 更换镜像源为更快的服务器，并更新系统和安装必要的软件包 RUN echo 'Server = http://mirrors.ustc.edu.cn/archlinux/$repo/os/$arch' > /etc/pacman.d/mirrorlist RUN pacman -Syyu --noconfirm RUN pacman -S --noconfirm --needed base-devel arm-none-eabi-gcc arm-none-eabi-newlib git python-pip python-crcmod RUN pacman -Scc --noconfirm # 设置工作目录 WORKDIR /app # 复制当前目录内容到工作目录 COPY . . # 初始化并更新子模块 RUN git submodule update --init --recursive # 如果需要编译固件，取消注释以下行 # RUN make && cp firmware* compiled-firmware/ ================================================ FILE: Doxyfile ================================================ OUTPUT_DIRECTORY = docs GENERATE_LATEX = NO GENERATE_RTF = NO GENERATE_MAN = NO OPTIMIZE_OUTPUT_FOR_C = YES HAVE_DOT = YES EXTRACT_ALL = YES EXTRACT_PRIVATE = YES EXTRACT_STATIC = YES CALL_GRAPH = YES CALLER_GRAPH = YES DISABLE_INDEX = YES GENERATE_TREEVIEW = YES RECURSIVE = YES COLLABORATION_GRAPH = YES GRAPHICAL_HIERARCHY = YES DOT_MULTI_TARGETS = YES ================================================ FILE: LICENSE ================================================ Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: Makefile ================================================ # compile options (see README.md for descriptions) # 0 = disable # 1 = enable # ---- COMPILER/LINKER OPTIONS ---- ENABLE_CLANG ?= 0 ENABLE_SWD ?= 1 ENABLE_OVERLAY ?= 0 ENABLE_LTO ?= 1 # ---- STOCK QUANSHENG FERATURES ---- ENABLE_UART ?= 1 ENABLE_AIRCOPY ?= 0 ENABLE_FMRADIO = 0 ENABLE_NOAA ?= 0 ENABLE_VOICE ?= 0 ENABLE_VOX ?= 1 ENABLE_ALARM ?= 0 ENABLE_TX1750 ?= 0 ENABLE_PWRON_PASSWORD ?= 0 ENABLE_DTMF_CALLING ?= 1 ENABLE_FLASHLIGHT ?= 1 ENABLE_BOOTLOADER ?= 0 # ---- CUSTOM MODS ---- ENABLE_BIG_FREQ ?= 1 ENABLE_KEEP_MEM_NAME ?= 1 ENABLE_WIDE_RX ?= 1 ENABLE_TX_WHEN_AM ?= 0 ENABLE_F_CAL_MENU ?= 0 ENABLE_CTCSS_TAIL_PHASE_SHIFT ?= 0 ENABLE_BOOT_BEEPS ?= 0 ENABLE_SHOW_CHARGE_LEVEL ?= 0 ENABLE_REVERSE_BAT_SYMBOL ?= 0 ENABLE_NO_CODE_SCAN_TIMEOUT ?= 1 ENABLE_AM_FIX ?= 1 ENABLE_SQUELCH_MORE_SENSITIVE ?= 1 ENABLE_FASTER_CHANNEL_SCAN ?= 1 ENABLE_RSSI_BAR ?= 1 ENABLE_COPY_CHAN_TO_VFO ?= 1 ENABLE_SPECTRUM = 0 ENABLE_REDUCE_LOW_MID_TX_POWER?= 0 ENABLE_BYP_RAW_DEMODULATORS ?= 0 ENABLE_BLMIN_TMP_OFF ?= 0 ENABLE_SCAN_RANGES ?= 1 ENABLE_MDC1200 = 0 ENABLE_MDC1200_SHOW_OP_ARG = 0 ENABLE_MDC1200_SIDE_BEEP = 0 ENABLE_MDC1200_CONTACT = 0 ENABLE_MDC1200_EDIT = 0 ENABLE_UART_RW_BK_REGS ?= 0 ENABLE_AUDIO_BAR_DEFAULT ?= 0 ENABLE_EEPROM_TYPE = 0 ENABLE_CHINESE_FULL = 0 ENABLE_ENGLISH =0 ENABLE_DOCK ?= 0 ENABLE_CUSTOM_SIDEFUNCTIONS ?= 1 ENABLE_SIDEFUNCTIONS_SEND ?= 1 ENABLE_BLOCK ?= 0 ENABLE_PINYIN =0 ENABLE_TURN ?=1 # ---- DEBUGGING ---- ENABLE_AM_FIX_SHOW_DATA ?= 0 ENABLE_AGC_SHOW_DATA ?= 0 ENABLE_TIMER ?= 0 VSCODE_DEBUG = 0 ENABLE_WARNING ?= 1 ENABLE_MESSENGER = 0 ENABLE_MESSENGER_DELIVERY_NOTIFICATION = 0 ENABLE_MESSENGER_NOTIFICATION = 0 ENABLE_4732 =0 ENABLE_4732SSB =0 ENABLE_DOPPLER =0 ############################################################# PACKED_FILE_SUFFIX = LOSEHU132 ifeq ($(ENABLE_PINYIN),1) ENABLE_CHINESE_FULL=4 endif ifeq ($(ENABLE_DOPPLER),1) ENABLE_SPECTRUM=1 endif ifeq ($(ENABLE_CHINESE_FULL),0) ifeq ($(ENABLE_ENGLISH),1) $(info E) PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)E endif endif ifeq ($(ENABLE_CHINESE_FULL),4) ifeq ($(ENABLE_ENGLISH),1) $(info EK) PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)EK else ifeq ($(ENABLE_PINYIN),1) $(info H) PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)H else $(info K) PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)K endif endif ifeq ($(ENABLE_4732),1) ENABLE_FMRADIO=0 PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)S $(info SI4732) endif ifeq ($(ENABLE_FMRADIO),1) ENABLE_4732=0 endif CFLAGS = ifeq ($(ENABLE_MDC1200),0) ENABLE_MDC1200_SHOW_OP_ARG = 0 ENABLE_MDC1200_SIDE_BEEP = 0 ENABLE_MDC1200_CONTACT = 0 ENABLE_MDC1200_EDIT =0 endif OPENOCD = C:/OpenOCD-20240916-0.12.0/bin/openocd.exe TARGET = firmware ifeq ($(ENABLE_CLANG),1) # GCC's linker, ld, doesn't understand LLVM's generated bytecode ENABLE_LTO := 0 endif ifeq ($(ENABLE_LTO),1) # can't have LTO and OVERLAY enabled at same time ENABLE_OVERLAY := 0 endif BSP_DEFINITIONS := $(wildcard hardware/*/*.def) BSP_HEADERS := $(patsubst hardware/%,bsp/%,$(BSP_DEFINITIONS)) BSP_HEADERS := $(patsubst %.def,%.h,$(BSP_HEADERS)) OBJS = # Startup files OBJS += start.o OBJS += init.o OBJS += app/messenger.o ifeq ($(ENABLE_MESSENGER),1) OBJS += ui/messenger.o endif ifeq ($(ENABLE_OVERLAY),1) OBJS += sram-overlay.o endif OBJS += external/printf/printf.o ifeq ($(ENABLE_TIMER),1) OBJS += driver/rtc.o endif ifeq ($(ENABLE_DOPPLER),1) OBJS += driver/rtc.o endif ifeq ($(ENABLE_MDC1200),1) OBJS += app/mdc1200.o endif ifeq ($(ENABLE_DOPPLER),1) OBJS += app/doppler.o endif # Drivers OBJS += driver/adc.o ifeq ($(ENABLE_UART),1) OBJS += driver/aes.o endif OBJS += driver/backlight.o ifeq ($(ENABLE_FMRADIO),1) OBJS += driver/bk1080.o endif OBJS += driver/bk4819.o ifeq ($(filter $(ENABLE_AIRCOPY) $(ENABLE_UART),1),1) OBJS += driver/crc.o endif OBJS += driver/eeprom.o ifeq ($(ENABLE_OVERLAY),1) OBJS += driver/flash.o endif ifeq ($(ENABLE_4732),1) OBJS += app/si.o OBJS += driver/si473x.o OBJS += helper/rds.o OBJS += app/spectrum.o endif OBJS += driver/gpio.o OBJS += driver/i2c.o OBJS += driver/keyboard.o OBJS += driver/spi.o OBJS += driver/st7565.o OBJS += driver/system.o OBJS += driver/systick.o ifeq ($(ENABLE_UART),1) OBJS += driver/uart.o endif # Main OBJS += app/action.o ifeq ($(ENABLE_AIRCOPY),1) OBJS += app/aircopy.o endif OBJS += app/app.o OBJS += app/chFrScanner.o OBJS += app/common.o OBJS += app/dtmf.o ifeq ($(ENABLE_FLASHLIGHT),1) OBJS += app/flashlight.o endif ifeq ($(ENABLE_FMRADIO),1) OBJS += app/fm.o endif OBJS += app/generic.o OBJS += app/main.o OBJS += app/menu.o ifeq ($(ENABLE_SPECTRUM), 1) OBJS += app/spectrum.o endif OBJS += app/scanner.o ifeq ($(ENABLE_UART),1) OBJS += app/uart.o endif ifeq ($(ENABLE_AM_FIX), 1) OBJS += am_fix.o endif OBJS += audio.o OBJS += bitmaps.o OBJS += board.o OBJS += dcs.o OBJS += font.o OBJS += frequencies.o OBJS += functions.o OBJS += helper/battery.o OBJS += helper/boot.o OBJS += misc.o OBJS += radio.o OBJS += scheduler.o OBJS += settings.o ifeq ($(ENABLE_AIRCOPY),1) OBJS += ui/aircopy.o endif OBJS += ui/battery.o ifeq ($(ENABLE_FMRADIO),1) OBJS += ui/fmradio.o endif OBJS += ui/helper.o OBJS += ui/inputbox.o ifeq ($(ENABLE_PWRON_PASSWORD),1) OBJS += ui/lock.o endif OBJS += ui/main.o OBJS += ui/menu.o OBJS += ui/scanner.o OBJS += ui/status.o OBJS += ui/ui.o OBJS += ui/welcome.o OBJS += version.o OBJS += main.o ifeq ($(OS), Windows_NT) # windows TOP := $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) RM = del /Q FixPath = $(subst /,\,$1) WHERE = where NULL_OUTPUT = nul else # unix TOP := $(shell pwd) RM = rm -f FixPath = $1 WHERE = which NULL_OUTPUT = /dev/null endif AS = arm-none-eabi-gcc LD = arm-none-eabi-gcc ifeq ($(ENABLE_CLANG),0) CC = arm-none-eabi-gcc # Use GCC's linker to avoid undefined symbol errors # LD += arm-none-eabi-gcc else # May need to adjust this to match your system CC = clang --sysroot=/usr/arm-none-eabi --target=arm-none-eabi # Bloats binaries to 512MB # LD = ld.lld endif OBJCOPY = arm-none-eabi-objcopy SIZE = arm-none-eabi-size AUTHOR_STRING ?= LOSEHU # the user might not have/want git installed # can set own version string here (max 7 chars) ifneq (, $(shell $(WHERE) git)) VERSION_STRING ?= $(shell git describe --tags --exact-match 2>$(NULL_OUTPUT)) ifeq (, $(VERSION_STRING)) VERSION_STRING := $(shell git rev-parse --short HEAD) endif endif # If there is still no VERSION_STRING we need to make one. # It is needed for the firmware packing script ifeq (, $(VERSION_STRING)) VERSION_STRING := NOGIT endif #VERSION_STRING := 230930b ASFLAGS = -c -mcpu=cortex-m0 ifeq ($(ENABLE_OVERLAY),1) ASFLAGS += -DENABLE_OVERLAY endif ifeq ($(ENABLE_CLANG),0) CFLAGS += -Os -Wall -Wno-error -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c2x -MMD -w #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c99 -MMD #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=gnu99 -MMD #CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=gnu11 -MMD else # Oz needed to make it fit on flash CFLAGS += -Oz -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c2x -MMD endif ifeq ($(ENABLE_LTO),1) CFLAGS += -flto=auto else # We get most of the space savings if LTO creates problems CFLAGS += -ffunction-sections -fdata-sections endif # May cause unhelpful build failures #CFLAGS += -Wpadded # catch any and all warnings CFLAGS += -Wextra #CFLAGS += -Wpedantic # 设置PACKED_FILE_SUFFIX，根据ENABLE_CHINESE_FULL的值设置不同的后缀 CFLAGS += -DENABLE_EEPROM_TYPE=$(ENABLE_EEPROM_TYPE) CFLAGS += -DENABLE_CHINESE_FULL=$(ENABLE_CHINESE_FULL) CFLAGS += -DPACKED_FILE_SUFFIX=\"$(PACKED_FILE_SUFFIX)\" CFLAGS += -DPRINTF_INCLUDE_CONFIG_H CFLAGS += -DAUTHOR_STRING=\"$(AUTHOR_STRING)\" -DVERSION_STRING=\"$(VERSION_STRING)\" ifeq ($(ENABLE_MDC1200_EDIT),1) CFLAGS += -DENABLE_MDC1200_EDIT endif ifeq ($(ENABLE_SPECTRUM),1) CFLAGS += -DENABLE_SPECTRUM endif ifeq ($(ENABLE_MDC1200),1) CFLAGS += -DENABLE_MDC1200 endif ifeq ($(ENABLE_BOOTLOADER),1) CFLAGS += -DENABLE_BOOTLOADER endif ifeq ($(VSCODE_DEBUG),1) CFLAGS += -DVSCODE_DEBUG endif ifeq ($(ENABLE_WARNING),1) CFLAGS += -DENABLE_WARNING endif ifeq ($(ENABLE_DOCK),1) CFLAGS += -DENABLE_DOCK endif ifeq ($(ENABLE_ENGLISH),1) CFLAGS += -DENABLE_ENGLISH endif ifeq ($(ENABLE_PINYIN),1) CFLAGS += -DENABLE_PINYIN endif ifeq ($(ENABLE_TURN),1) CFLAGS += -DENABLE_TURN endif ifeq ($(ENABLE_BLOCK),1) CFLAGS += -DENABLE_BLOCK endif ifeq ($(ENABLE_MESSENGER),1) CFLAGS += -DENABLE_MESSENGER endif ifeq ($(ENABLE_DOPPLER),1) CFLAGS += -DENABLE_DOPPLER endif ifeq ($(ENABLE_4732),1) CFLAGS += -DENABLE_4732 endif ifeq ($(ENABLE_4732SSB),1) CFLAGS += -DENABLE_4732SSB endif ifeq ($(ENABLE_MESSENGER_DELIVERY_NOTIFICATION),1) CFLAGS += -DENABLE_MESSENGER_DELIVERY_NOTIFICATION endif ifeq ($(ENABLE_MESSENGER_NOTIFICATION),1) CFLAGS += -DENABLE_MESSENGER_NOTIFICATION endif #ifeq ($(ENABLE_CHINESE_FULL),4) ifeq ($(ENABLE_CUSTOM_SIDEFUNCTIONS),1) CFLAGS += -DENABLE_CUSTOM_SIDEFUNCTIONS endif ifeq ($(ENABLE_SIDEFUNCTIONS_SEND),1) CFLAGS += -DENABLE_SIDEFUNCTIONS_SEND endif #endif ifeq ($(ENABLE_TIMER),1) CFLAGS += -DENABLE_TIMER endif ifeq ($(ENABLE_MDC1200_CONTACT),1) CFLAGS += -DENABLE_MDC1200_CONTACT endif ifeq ($(ENABLE_AUDIO_BAR_DEFAULT),1) CFLAGS += -DENABLE_AUDIO_BAR_DEFAULT endif ifeq ($(ENABLE_CHINESE_FULL),4) ifeq ($(ENABLE_EEPROM_4M),1) CFLAGS += -DENABLE_EEPROM_4M endif endif ifeq ($(ENABLE_MDC1200_SHOW_OP_ARG),1) CFLAGS += -DENABLE_MDC1200_SHOW_OP_ARG endif ifeq ($(ENABLE_MDC1200_SIDE_BEEP),1) CFLAGS += -DENABLE_MDC1200_SIDE_BEEP endif ifeq ($(ENABLE_SWD),1) CFLAGS += -DENABLE_SWD endif ifeq ($(ENABLE_OVERLAY),1) CFLAGS += -DENABLE_OVERLAY endif ifeq ($(ENABLE_AIRCOPY),1) CFLAGS += -DENABLE_AIRCOPY endif ifeq ($(ENABLE_FMRADIO),1) CFLAGS += -DENABLE_FMRADIO endif ifeq ($(ENABLE_UART),1) CFLAGS += -DENABLE_UART endif ifeq ($(ENABLE_UART_RW_BK_REGS),1) CFLAGS += -DENABLE_UART_RW_BK_REGS endif ifeq ($(ENABLE_BIG_FREQ),1) CFLAGS += -DENABLE_BIG_FREQ endif ifeq ($(ENABLE_NOAA),1) CFLAGS += -DENABLE_NOAA endif ifeq ($(ENABLE_VOICE),1) CFLAGS += -DENABLE_VOICE endif ifeq ($(ENABLE_VOX),1) CFLAGS += -DENABLE_VOX endif ifeq ($(ENABLE_ALARM),1) CFLAGS += -DENABLE_ALARM endif ifeq ($(ENABLE_TX1750),1) CFLAGS += -DENABLE_TX1750 endif ifeq ($(ENABLE_PWRON_PASSWORD),1) CFLAGS += -DENABLE_PWRON_PASSWORD endif ifeq ($(ENABLE_KEEP_MEM_NAME),1) CFLAGS += -DENABLE_KEEP_MEM_NAME endif ifeq ($(ENABLE_WIDE_RX),1) CFLAGS += -DENABLE_WIDE_RX endif ifeq ($(ENABLE_TX_WHEN_AM),1) CFLAGS += -DENABLE_TX_WHEN_AM endif ifeq ($(ENABLE_F_CAL_MENU),1) CFLAGS += -DENABLE_F_CAL_MENU endif ifeq ($(ENABLE_CTCSS_TAIL_PHASE_SHIFT),1) CFLAGS += -DENABLE_CTCSS_TAIL_PHASE_SHIFT endif ifeq ($(ENABLE_BOOT_BEEPS),1) CFLAGS += -DENABLE_BOOT_BEEPS endif ifeq ($(ENABLE_SHOW_CHARGE_LEVEL),1) CFLAGS += -DENABLE_SHOW_CHARGE_LEVEL endif ifeq ($(ENABLE_REVERSE_BAT_SYMBOL),1) CFLAGS += -DENABLE_REVERSE_BAT_SYMBOL endif ifeq ($(ENABLE_NO_CODE_SCAN_TIMEOUT),1) CFLAGS += -DENABLE_NO_CODE_SCAN_TIMEOUT endif ifeq ($(ENABLE_AM_FIX),1) CFLAGS += -DENABLE_AM_FIX endif ifeq ($(ENABLE_AM_FIX_SHOW_DATA),1) CFLAGS += -DENABLE_AM_FIX_SHOW_DATA endif ifeq ($(ENABLE_SQUELCH_MORE_SENSITIVE),1) CFLAGS += -DENABLE_SQUELCH_MORE_SENSITIVE endif ifeq ($(ENABLE_FASTER_CHANNEL_SCAN),1) CFLAGS += -DENABLE_FASTER_CHANNEL_SCAN endif ifeq ($(ENABLE_BACKLIGHT_ON_RX),1) CFLAGS += -DENABLE_BACKLIGHT_ON_RX endif ifeq ($(ENABLE_RSSI_BAR),1) CFLAGS += -DENABLE_RSSI_BAR endif ifeq ($(ENABLE_AUDIO_BAR),1) CFLAGS += -DENABLE_AUDIO_BAR endif ifeq ($(ENABLE_COPY_CHAN_TO_VFO),1) CFLAGS += -DENABLE_COPY_CHAN_TO_VFO endif ifeq ($(ENABLE_SINGLE_VFO_CHAN),1) CFLAGS += -DENABLE_SINGLE_VFO_CHAN endif ifeq ($(ENABLE_BAND_SCOPE),1) CFLAGS += -DENABLE_BAND_SCOPE endif ifeq ($(ENABLE_REDUCE_LOW_MID_TX_POWER),1) CFLAGS += -DENABLE_REDUCE_LOW_MID_TX_POWER endif ifeq ($(ENABLE_BYP_RAW_DEMODULATORS),1) CFLAGS += -DENABLE_BYP_RAW_DEMODULATORS endif ifeq ($(ENABLE_SCAN_RANGES),1) CFLAGS += -DENABLE_SCAN_RANGES endif ifeq ($(ENABLE_DTMF_CALLING),1) CFLAGS += -DENABLE_DTMF_CALLING endif ifeq ($(ENABLE_AGC_SHOW_DATA),1) CFLAGS += -DENABLE_AGC_SHOW_DATA endif ifeq ($(ENABLE_FLASHLIGHT),1) CFLAGS += -DENABLE_FLASHLIGHT endif LDFLAGS = LDFLAGS += -z noexecstack -mcpu=cortex-m0 -nostartfiles -Wl,-T,firmware.ld -Wl,--gc-sections # Use newlib-nano instead of newlib LDFLAGS += --specs=nano.specs ifeq ($(VSCODE_DEBUG),1) ASFLAGS += -g CFLAGS += -g LDFLAGS += -g endif INC = INC += -I $(TOP) INC += -I $(TOP)/external/CMSIS_5/CMSIS/Core/Include/ INC += -I $(TOP)/external/CMSIS_5/Device/ARM/ARMCM0/Include LIBS = DEPS = $(OBJS:.o=.d) ifneq (, $(shell $(WHERE) python)) MY_PYTHON := python else ifneq (, $(shell $(WHERE) python3)) MY_PYTHON := python3 endif ifdef MY_PYTHON HAS_CRCMOD := $(shell $(MY_PYTHON) -c "import crcmod" 2>&1) endif full: $(RM) *.bin $(MAKE) build ENABLE_CHINESE_FULL=0 ENABLE_ENGLISH=1 ENABLE_FMRADIO=1 ENABLE_MESSENGER=1 ENABLE_MESSENGER_DELIVERY_NOTIFICATION=1 ENABLE_MESSENGER_NOTIFICATION=1 ENABLE_SPECTRUM=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1 $(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_ENGLISH=1 ENABLE_DOPPLER=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1 $(MAKE) build ENABLE_CHINESE_FULL=0 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1 $(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_DOPPLER=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1 $(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_DOPPLER=1 ENABLE_PINYIN=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 $(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_PINYIN=1 ENABLE_4732=1 ENABLE_4732SSB=1 ENABLE_SPECTRUM=1 test: $(RM) *.bin $(MAKE) build ENABLE_CHINESE_FULL=0 ENABLE_MDC1200=0 ENABLE_MDC1200_EDIT=0 ENABLE_MDC1200_CONTACT=0 ENABLE_FMRADIO=0 ENABLE_MESSENGER=1 ENABLE_MESSENGER_DELIVERY_NOTIFICATION=1 ENABLE_MESSENGER_NOTIFICATION=1 VSCODE_DEBUG=1 build:clean $(TARGET) @$(OBJCOPY) -O binary $(TARGET) $(TARGET).bin ifndef MY_PYTHON $(info ) $(info ) else ifneq (,$(HAS_CRCMOD)) $(info ) $(info !!!!!!!! run: pip install crcmod) $(info ) else -$(MY_PYTHON) fw-pack.py $(TARGET).bin $(AUTHOR_STRING) $(PACKED_FILE_SUFFIX).bin endif $(SIZE) $(TARGET) all: $(MAKE) build $(MAKE) flash debug: $(OPENOCD) -c "bindto 0.0.0.0" -f interface/stlink.cfg -f dp32g030.cfg flash: $(OPENOCD) -c "bindto 0.0.0.0" -f interface/stlink.cfg -f dp32g030.cfg -c "write_image firmware.bin 0; shutdown;" version.o: .FORCE $(TARGET): $(OBJS) @$(LD) $(LDFLAGS) $^ -o $@ $(LIBS) bsp/dp32g030/%.h: hardware/dp32g030/%.def %.o: %.c | $(BSP_HEADERS) @$(CC) $(CFLAGS) $(INC) -c $< -o $@ %.o: %.S @$(AS) $(ASFLAGS) $< -o $@ .FORCE: -include $(DEPS) CUSCANSHU ?= NUL CUSTOMNAME ?= NUL full_all: $(MAKE) build_all $(CUSCANSHU) CUSTOMNAME="$(CUSTOMNAME)" build_all: clean $(TARGET) $(OBJCOPY) -O binary $(TARGET) $(TARGET).bin ifndef MY_PYTHON else ifneq (,$(HAS_CRCMOD)) $(info ) $(info !!!!!!!! run: pip install crcmod) $(info ) else -$(MY_PYTHON) fw-pack.py $(TARGET).bin $(AUTHOR_STRING) $(CUSTOMNAME).bin endif $(SIZE) $(TARGET) clean: @$(RM) $(call FixPath, $(TARGET).bin $(PACKED_FILE_SUFFIX).bin $(TARGET) ) ifeq ($(OS), Windows_NT) # Windows 系统 @call del_win.bat else # 类 Unix 系统（Linux, macOS, 等） chmod +x del_linux.sh sh ./del_linux.sh endif ================================================ FILE: README.md ================================================ **Read this in other languages: [English](./README_en.md), [中文](./README.md).** **语言版本: [English](./README_en.md), [中文](./README.md).** # [K5Web]( https://k5.vicicode.com/) * 支持在线固件功能编译，无需安装编译环境！！ * 多普勒卫星、开机图片文字、SI4732 SSB补丁的写频方式！ * 支持**创意工坊**，注册后登录可上传自定义固件和开机图片！！！ 请访问：[K5Web]( https://k5.vicicode.com/) # [自定义引导](https://github.com/losehu/uv-k5-bootloader-custom) * 通过创立一个引导程序加载进RAM实现固件切换 * 可切换任意固件 * 目前仅适用于4Mib的EEPROM，通过修改代码可轻松拓展至其他大小EEPROM # [独立的多普勒卫星固件](https://github.com/losehu/uv-k5-firmware-custom/tree/doppler) * 可以独立解算最多40个卫星的角度，高度，速度，距离，频偏 * 需要扩容2Mit及以上的EEprom * 可以显示卫星位置，带方位图 # [更大固件系统](https://github.com/losehu/uv-k5-system-custom/) * 可以让UVK5加载超过64KB大小的固件，最高512MB * 更大的固件可以在一个固件中实现所有功能！！！ * 开发中。。。敬请期待 # 版本说明 * 目前分为如下几个版本：**LOSEHUxxx**、**LOSEHUxxxK**、**LOSEHUxxxH**、**LOSEHUxxxE**、**LOSEHUxxxEK**、**LOSEHUxxxHS** * | 版本 | 语言 | EEPROM 需求 | MDC1200 | 多普勒模式 | 频谱 | 收音机 | 中文信道名 | 自定义开机中文字符 | 开机图片 | 中文输入法 | 短信 | |--------------|------|-------------|---------|------------|------|--------|------------|--------------------|----------|------------|------| | LOSEHUxxx | 中文 | 无需扩容 | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | | LOSEHUxxxK | 中文 | 1Mib 以上 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | LOSEHUxxxH | 中文 | 2Mib 以上 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | | LOSEHUxxxHS | 中文 | 2Mib 以上 | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | | LOSEHUxxxE | 英文 | 无需扩容 | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | | LOSEHUxxxEK | 英文 | 1Mib 以上 | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ### 说明： - ✅ 表示支持该功能 - ❌ 表示不支持该功能 - 表格中的“收音机”功能在 LOSEHUxxxHS 版本中特指 SI4732 收音机 # 多功能的K5/6固件 该固件基于多个开源固件修改合并，拥有最多样性的功能 * **更大容量的Eeprom芯片** * **自动多普勒频移** * **自定义开机图** * **SI4732支持** * **中/英文支持** * **中文输入法** * **GB2312中文界面、信道** * **频谱图** * **MDC1200信令、联系人** * **短信** * **信号强度指示器（ S表 ）** * **一键扫频** * **收音机** * **AM 修复** * **SSB 解调** # 操作说明(必读！！) | 按键 | 功能 | |----------------------------|------------------------------------------------------| | 🐤 **主界面下** | | | **单按`上/下`** | 调整频率（步长为菜单1项`步进频率`） | | **单按`数字`** | 在频率模式下快捷输入频率 | | **单按`*`** | 输入要发送的DTMF(`A、B、C、D、*、#`对应`M、上、下、*、F`键侧键1退格,按PPT键发送) | | **长按`F`** | 锁定键盘 | | **长按`M`** | 切换调制模式 | | **长按`*`** | 信道模式下是搜索列表,多次长按可切换(列表1/2/全部)，频率模式下,从当前频率开始搜索 | | **长按`0`/`F+0`** | 打开/关闭收音机(或SI4732) | | **长按`1`/`F+1`** | 在信道模式下将当前信道复制到另一个VFO | | **长按`2`/`F+2`** | 切换A/B通道 | | **长按`3`/`F+3`** | 切换频率/信道 | | **长按`4`/`F+4`** | 一键对频 | | **长按`5`** | 信道模式下切换搜索列表 | | **长按`5`** | 频率模式下设置搜索频率范围(从通道A到通道B频率),按*键开始搜索 | | **`F+5`** | 频谱 | | **长按`6`/`F+6`** | 切换发射功率 | | **长按`7`/`F+7`** | 声控发射开关 | | **长按`8`/`F+8`** | 一键倒频 | | **长按`9`/`F+9`** | 一键即呼 | | **`F+M`** | 打开短信 | | **`F+UP`** | 按键音开关 | | **`F+Down`** | 自动多普勒 | | **`F+EXIT`** | 菜单上下颠倒 | | **`F+*`** | 扫描(数字/模拟)亚音 | | **短按`侧键1`** | 监听 | | **长按`侧键1`** | DTMF解码开关 | | **短按`侧键2`** | 设置宽窄带 | | **长按`侧键2`** | 手电筒 | | **宽窄带、DTMF解码、切换FM/AM/USB** | 集成至自定义的 **侧键与M** | | 🎤 **SI4732收音机** | | | **短按`侧键1`、短按`侧键2`** | SSB模式下更改bfo | | **短按`5`** | 输入频率，**短按`*`** 小数点 , **短按`MENU`** 确认 | | **短按`0`** | 切换模式(AM/FM/SSB)，**短按`F`** 切换LSB/USB | | **短按`1`**、**短按`7`** | 切换步进频率 | | **短按`4`** | 切换显示信号强度 | | **短按`6`** | 切换带宽 | | **短按`2`**、**短按`8`** | 切换ATT | | **短按`3`**、**短按`9`** | 上下搜索 ，**短按`EXIT`** 停止搜索 | | 🔑 **多普勒模式** | | | **短按`5`** | 输入时间，**短按`*`** 小数点 , **短按`MENU`** 确认 | | **短按`MENU`** | 切换参数，上下调节 | | **短按`PPT`** | 发射 | | **短按`侧键1`** | 开启监听 | # EEPROM分布说明 | EEPROM地址 | 描述 | |----------------------------------------|-----------------------------------------------------------| | 😭 **通用** | 版本号：LOSEHUxxx | | 0X01D00~0x02000 | 基本不变 | | 0X01D00 ~ 0X01E00
0X1F90 ~ 0X01FF0 | **MDC1200**-22个MDC联系人
每个联系人占用16B，前2B为MDC ID，后14B为联系人名 | | 0X01FFF | **MDC1200**-MDC联系人数量 | | 0x01FFD~0x01FFE | **MDC1200**-MDC ID | | 0x01FF8~0x01FFC | 侧键功能 | | 0x01FFD~0x01FFE | **MDC1200**-MDC ID | | 😱 **扩容版(K、H)** | 版本号：LOSEHUxxxK、LOSEHUxxxH | | 0x02000~0x02012 | 开机字符1 | | 0x02012~0x02024 | 开机字符2 | | 0x02024~0x02025 | 开机字符1、2的长度 | | 0x02080~0x02480 | 开机画面，长度128（宽）*64/8=1024=0x400 | | 0x01FFD~0x01FFE | **MDC1200**-MDC ID | | 0x02480~0x0255C | gFontBigDigits，长度11*20=220=0XDC | | 0x0255C~0x0267C | gFont3x5，长度96*3=288=0X120 | | 0x0267C~0x028B0 | gFontSmall，长度96*6=564=0X234 | | 0x028B0~0x02B96 | 菜单编码，长度53*14=742=0X2E6 | | 0x02BA0~0x02BA9 | **多普勒**-卫星名称,首字符在前,最多9个英文，最后一个为'\0' | | 0x02BAA~0x02BAF | **多普勒**-开始过境时间的年份十位个位、月、日、时、分、秒 | | 0x02BB0~0x2BB5 | **多普勒**-离境时间的年份十位个位、月、日、时、分、秒 | | 0x02BB6~0x02BB7 | **多普勒**-总过境时间（秒），低位在前，高位在后 | | 0x02BB8~0x02BB9 | **多普勒**-手台的发射亚音，低位在前，高位在后 | | 0x02BBA~0x02BBB | **多普勒**-手台的接收亚音，低位在前，高位在后 | | 0x02C00~0x02C64 | **多普勒**-CTCSS_Options,长度50*2=100=0x64 | | 0x02C64~0x02D34 | **多普勒**-DCS_Options,长度104*2=208=0xD0 | | 0x02BBC~0X02BBF | **多普勒**-开始过境时间与2000年1月1日UNIX时间戳的差,低位在前，高位在后 | | 0X02BC0~0X02BC5 | **多普勒**-当前时间的年份十位个位、月、日、时、分、秒 | | 0x02E00~0x1E1E6 | GB2312中文字库,共6763*11*12/8=111590=0x1B3E6 | | 0x1E200~0x20000(MAX) | **多普勒**-第2*n（偶数）秒卫星数据，每秒8B,包括上下行频率/10，低位在前，高位在后 | | 😰 **2Mib扩容版（H）** | 版本号：LOSEHUxxxH | | 0x20000~0x26B00 | **中文输入法**-拼音索引、对应字数、字的起始地址 | | 0x26B00~0x2A330 | **中文输入法**-拼音汉字表 | | 0x3C228~0x40000 | **SI4732**-patch，长度为0x3DD8，用于SI4732的固件升级 | | 0x3C210~0x3C21C | **SI4732**FM、AM、SSB频率、模式 | [多普勒EEPROM分布说明](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/doc/多普勒eeprom详细说明.txt) # 用户功能自定义 你可以通过启用/禁用各种编译选项来定制固件 | 编译选项 | 描述 | |----------------------------------------|-------------------------------------------------------------------------------| | 🧰 **泉盛基本功能** | [Quansheng Basic Functions](https://github.com/egzumer/uv-k5-firmware-custom) | | ENABLE_UART | 串口，没有这个,你就不能通过PC配置无线电！ | | ENABLE_AIRCOPY | AirCopy无线复制 | | ENABLE_FMRADIO | 收音机功能 | | ENABLE_NOAA | NOAA功能 (只有在美国有用) | | ENABLE_VOICE | 语音播报 | | ENABLE_VOX | VOX声控发射 | | ENABLE_ALARM | TX 警报 | | ENABLE_PWRON_PASSWORD | 开机密码 | | ENABLE_DTMF_CALLING | DTMF拨号功能，呼叫发起，呼叫接收，群组通话，联系人列表等 | | ENABLE_FLASHLIGHT | 启用顶部手电筒LED灯（开启，闪烁，SOS） | | ⌚ **自定义模组** | | | ENABLE_BIG_FREQ | 大号字体的频率显示（类似官方泉盛固件） | | ENABLE_KEEP_MEM_NAME | 在重新保存内存频道时保持频道名称 | | ENABLE_WIDE_RX | 全频18MHz至1300MHz接收（尽管前端/功率放大器未设计用于整个范围） | | ENABLE_TX_WHEN_AM | 当RX设置为AM时允许TX（始终为FM） | | ENABLE_F_CAL_MENU | 启用收音机的隐藏频率校准菜单 | | ENABLE_CTCSS_TAIL_PHASE_SHIFT | 使用标准CTCSS尾部相移，而不是QS独有的55Hz音调方法 | | ENABLE_BOOT_BEEPS | 在启动时为用户提供音频反馈，指示音量旋钮的位置 | | ENABLE_SHOW_CHARGE_LEVEL | 在收音机充电时显示电池充电水平 | | ENABLE_REVERSE_BAT_SYMBOL | 在状态栏上镜像电池符号（正极在右侧） | | ENABLE_NO_CODE_SCAN_TIMEOUT | 禁用32秒CTCSS/DCS扫描超时（按退出按钮而不是等待超时结束扫描 | | ENABLE_AM_FIX | 在AM模式下动态调整前端增益，以帮助防止AM解调器饱和，暂时忽略屏幕上的RSSI级别 | | ENABLE_SQUELCH_MORE_SENSITIVE | 将静噪电平稍微调敏感一些 | | ENABLE_FASTER_CHANNEL_SCAN | 增加频道扫描速度，但静噪调敏度也增加了 | | ENABLE_RSSI_BAR | 启用以dBm/Sn为单位的RSSI条形图水平，取代小天线符号 | | ENABLE_AUDIO_BAR | 发送时显示音频条级别 | | ENABLE_COPY_CHAN_TO_VFO | 将当前频道设置复制到频率模式。在频道模式下长按 `1 BAND` | | ENABLE_SPECTRUM | fagci 频谱分析仪，`F` + `5 NOAA`激活 | | ENABLE_REDUCE_LOW_MID_TX_POWER | 使中等和低功率设置更低 | | ENABLE_BYP_RAW_DEMODULATORS | 额外的BYP（旁路？）和RAW解调选项，被证明并不十分有用，但如果你想实验的话，它是存在的 | | ENABLE_SCAN_RANGES | 频率扫描的扫描范围模式 | | ENABLE_BLOCK | EEPROM上锁 | | ENABLE_WARNING | BEEP提示音 | | ENABLE_CUSTOM_SIDEFUNCTIONS | 自定义侧键功能 | | ENABLE_SIDEFUNCTIONS_SEND | 自定义侧键功能（侧键发射功能） | | ENABLE_AUDIO_BAR_DEFAULT | 默认语音条样式 | | 📡 **自动多普勒** | [Automatic Doppler](https://github.com/losehu/uv-k5-firmware-custom) | | ENABLE_DOPPLER | 自动多普勒功能 | | 📧 **短信** | [SMS](https://github.com/joaquimorg/uv-k5-firmware-custom) | | ENABLE_MESSENGER | 发送和接收短文本消息（按键 = `F` + `MENU`） | | ENABLE_MESSENGER_DELIVERY_NOTIFICATION | 如果收到消息，则向发送方发送通知 | | ENABLE_MESSENGER_NOTIFICATION | 在收到消息时播放声音 | | 📱 **MDC1200** | [MDC1200](https://github.com/OneOfEleven/uv-k5-firmware-custom) | | ENABLE_MDC1200 | MDC1200发送功能 | | ENABLE_MDC1200_SHOW_OP_ARG | MDC显示首尾音参数 | | ENABLE_MDC1200_SIDE_BEEP | MDC侧音 | | ENABLE_MDC1200_CONTACT | MDC联系人 | | 🎛️ **DOCK** | [DOCK](https://github.com/nicsure/QuanshengDock) | | ENABLE_DOCK | 允许通过电脑控制手台，无屏幕显示！ | | 🚫 **调试** | | | ENABLE_AM_FIX_SHOW_DATA | 显示AM修复的调试数据 | | ENABLE_AGC_SHOW_DATA | 显示ACG参数 | | ENABLE_UART_RW_BK_REGS | 添加了两个额外的命令，允许读取和写入BK4819寄存器 | | ⚠️ **编译选项** | | | ENABLE_CLANG | 实验性质，使用clang而不是gcc构建（如果启用此选项，LTO将被禁用） | | ENABLE_SWD | 使用CPU的SWD端口，调试/编程时需要 | | ENABLE_OVERLAY | CPU FLASH相关内容，不需要 | | ENABLE_LTO | 减小编译固件的大小，但可能会破坏EEPROM读取（启用后OVERLAY将被禁用） | # 打赏 如果这个项目对您有帮助,可以考虑赞助来支持开发工作。 这是：[打赏名单](https://losehu.github.io/payment-codes/#%E6%94%B6%E6%AC%BE%E7%A0%81) 非常感谢各位的支持！！！ 打赏码： [![打赏码](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/payment/show.png)](https://losehu.github.io/payment-codes/) ## Star History [![Star History Chart](https://api.star-history.com/svg?repos=losehu/uv-k5-firmware-custom&type=Date)](https://star-history.com/#losehu/uv-k5-firmware-custom&Date) ================================================ FILE: README_en.md ================================================ **Read this in other languages: [English](./README_en.md), [中文](./README.md).** **语言版本: [English](./README_en.md), [中文](./README.md).** # [K5Web]( https://k5.vicicode.com/) * Supports online firmware functionality compilation, no need to install the compilation environment!! * Doppler satellite, boot image text, SI4732 SSB patch frequency writing method! * Supports **Workshop**, register and log in to upload custom firmware and boot images!!! Please visit: [K5Web]( https://k5.vicicode.com/) # [Custom Bootloader](https://github.com/losehu/uv-k5-bootloader-custom) * Achieves firmware switching by creating a bootloader loaded into RAM * Can switch any firmware * Currently only applicable to 4Mib EEPROM, can be easily expanded to other EEPROM sizes by modifying the code # [Standalone Doppler Satellite Firmware](https://github.com/losehu/uv-k5-firmware-custom/tree/doppler) * Can independently calculate up to 40 satellites’ angles, altitudes, speeds, distances, and frequency offsets * Requires expansion of 2Mit or larger EEPROM * Can display satellite positions with azimuth map # [Larger Firmware System](https://github.com/losehu/uv-k5-system-custom/) * Allows UVK5 to load firmware larger than 64KB, up to 512MB * A larger firmware can implement all functions in a single firmware!!! * In development... Stay tuned # Version Description * The current versions are: **LOSEHUxxx**, **LOSEHUxxxK**, **LOSEHUxxxH**, **LOSEHUxxxE**, **LOSEHUxxxEK**, **LOSEHUxxxHS** * | Version | Language | EEPROM Requirement | MDC1200 | Doppler Mode | Spectrum | Radio | Chinese Channel Name | Custom Boot Image | Boot Image | Chinese Input Method | SMS | |---------------|----------|---------------------|---------|--------------|----------|-------|----------------------|-------------------|------------|----------------------|-----| | LOSEHUxxx | Chinese | No expansion needed | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | | LOSEHUxxxK | Chinese | 1Mib or above | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | | LOSEHUxxxH | Chinese | 2Mib or above | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | | LOSEHUxxxHS | Chinese | 2Mib or above | ❌ | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | | LOSEHUxxxE | English | No expansion needed | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | | LOSEHUxxxEK | English | 1Mib or above | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | ❌ | ### Explanation: - ✅ means the feature is supported - ❌ means the feature is not supported - The "Radio" feature in the LOSEHUxxxHS version specifically refers to the SI4732 radio # Multi-functional K5/6 Firmware This firmware is based on modifications and merges of multiple open-source firmware, featuring the most diverse functions: * **Larger EEPROM capacity** * **Automatic Doppler frequency shift** * Custom boot logo * **SI4732 support** * **Chinese/English support** * **Chinese input method** * **GB2312 Chinese interface, channels** * **Spectrum graph** * **MDC1200 signaling, contacts** * **SMS** * **Signal strength indicator (S meter)** * **One-touch frequency scanning** * **Radio receiver** * **AM fix** * **SSB demodulation** # Operating Instructions (Mandatory Reading!!) | Key | Function | |-----------------|----------------------------------------------------------------------------------------------------------------------------------------------------------| | 🐤 **Main Interface** | | | **Single Press `Up/Down`** | Adjust frequency (step size is set by menu item `Step Frequency`) | | **Single Press `Number`** | Quickly input frequency in frequency mode | | **Single Press `*`** | Input DTMF to be sent (`A, B, C, D, *, #` correspond to `M, Up, Down, *, F` respectively. Side Key 1 acts as backspace, press PTT key to send) | | **Long Press `F`** | Keyboard Lock | | **Long Press `M`** | Switch modulation mode | | **Long Press `*`** | In channel mode, activates search list, multiple long presses toggle between lists (1/2/All). In frequency mode, initiates search from current frequency | | **Long Press `0`/`F+0`** | Open/Close radio receiver(OR SI4732) | | **Long Press `1`/`F+1`** | In channel mode, copies current channel to another VFO | | **Long Press `2`/`F+2`** | Switch between A/B channels | | **Long Press `3`/`F+3`** | Switch between frequency/channel | | **Long Press `4`/`F+4`** | One-touch frequency alignment | | **Long Press `5`** | In channel mode, toggles search list | | **Long Press `5`** | In frequency mode, sets search frequency range (from channel A to channel B frequency), press * key to start search | | **`F+5`** | Spectrum | | **Long Press `6`/`F+6`** | Switch transmit power | | **Long Press `7`/`F+7`** | Voice-activated transmission switch | | **Long Press `8`/`F+8`** | One-touch reverse frequency | | **Long Press `9`/`F+9`** | One-touch call | | **`F+M`** | Open SMS | | **`F+UP`** | Key tone switch | | **`F+Down`** | Automatic Doppler shift | | **`F+EXIT`** | Inverts menu navigation (Up/Down) | | **`F+*`** | Scan (Digital/Analog) sub-audio | | **Short Press Side Key 1** | Monitor | | **Long Press Side Key 1** | DTMF decoding switch | | **Short Press Side Key 2** | Set wide/narrow band | | **Long Press Side Key 2** | Flashlight | |**Wide/Narrow Band, DTMF decoding, FM/AM/USB Switching**| Integrated into custom **Side Key and M** | | 🎤 **SI4732 Radio** | | | **Short press `Side Key 1`, Short press `Side Key 2`** | Change BFO in SSB mode | | **Short press `5`** | Enter frequency, **short press `*`** for decimal point, **short press `MENU`** to confirm | | **Short press `0`** | Switch mode (AM/FM/SSB), **short press `F`** to switch LSB/USB | | **Short press `1`, Short press `7`** | Change step frequency | | **Short press `4`** | Toggle signal strength display | | **Short press `6`** | Change bandwidth | | **Short press `2`, Short press `8`** | Toggle ATT | | **Short press `3`, Short press `9`** | Search up/down, **short press `EXIT`** to stop search | | 🔑 **Doppler Mode** | | | **Short press `5`** | Enter time, **short press `*`** for decimal point, **short press `MENU`** to confirm | | **Short press `MENU`** | Toggle parameters, adjust up/down | | **Short press `PPT`** | Transmit | | **Short press `Side Key 1`** | Enable listening | | # Eeprom Layout Explanation | Eeprom Address | Description | |----------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------| | 😭 **General** | Version: LOSEHUxxx | | 0X01D00~0x02000 | Rarely changed | | 0X01D00 ~ 0X01E00
0X1F90 ~ 0X01FF0 | **MDC1200** - 22 MDC contacts
Each contact occupies 16B, with the first 2B being MDC ID and the next 14B being contact name | | 0X01FFF | **MDC1200** - Number of MDC contacts | | 0x01FFD~0x01FFE | **MDC1200** - MDC ID | | 0x01FF8~0x01FFC | Side key functions | | 0x01FFD~0x01FFE | **MDC1200** - MDC ID | | 😱 **Expanded Version (K, H)** | Version: LOSEHUxxxK, LOSEHUxxxH | | 0x02000~0x02012 | Boot character 1 | | 0x02012~0x02024 | Boot character 2 | | 0x02024~0x02025 | Length of boot characters 1 and 2 | | 0x02080~0x02480 | Boot screen, length 128 (width) * 64/8 = 1024 = 0x400 | | 0x01FFD~0x01FFE | **MDC1200** - MDC ID | | 0x02480~0x0255C | gFontBigDigits, length 11 * 20 = 220 = 0XDC | | 0x0255C~0x0267C | gFont3x5, length 96 * 3 = 288 = 0X120 | | 0x0267C~0x028B0 | gFontSmall, length 96 * 6 = 564 = 0X234 | | 0x028B0~0x02B96 | Menu encoding, length 53 * 14 = 742 = 0X2E6 | | 0x02BA0~0x02BA9 | **Doppler** - Satellite names, with the first character first, up to 9 English characters, the last one being '\0' | | 0x02BAA~0x02BAF | **Doppler** - Year (tens and units), month, day, hour, minute, and second of start transit time | | 0x02BB0~0x2BB5 | **Doppler** - Year (tens and units), month, day, hour, minute, and second of departure time | | 0x02BB6~0x02BB7 | **Doppler** - Total transit time (seconds), with the low byte first and the high byte second | | 0x02BB8~0x02BB9 | **Doppler** - Transmitter sub-audio, with the low byte first and the high byte second | | 0x02BBA~0x02BBB | **Doppler** - Receiver sub-audio, with the low byte first and the high byte second | | 0x02C00~0x02C64 | **Doppler** - CTCSS_Options, length 50 * 2 = 100 = 0x64 | | 0x02C64~0x02D34 | **Doppler** - DCS_Options, length 104 * 2 = 208 = 0xD0 | | 0x02BBC~0X02BBF | **Doppler** - Difference between start transit time and UNIX timestamp of January 1, 2000, with the low byte first and the high byte second | | 0X02BC0~0X02BC5 | **Doppler** - Year (tens and units), month, day, hour, minute, and second of current time | | 0x02E00~0x1E1E6 | GB2312 Chinese font library, total 6763 * 11 * 12/8 = 111590 = 0x1B3E6 | | 0x1E200~0x20000(MAX) | **Doppler** - 2*n (even) second satellite data, 8B per second, including uplink/downlink frequency/10, with the low byte first and the high byte second | | 😰 **2Mib Expanded Version (H)** | Version: LOSEHUxxxH | | 0x20000~0x26B00 | **Chinese Input Method** - Pinyin index, corresponding number of characters, starting address of characters | | 0x26B00~0X2A330 | **Chinese Input Method** - Pinyin Chinese character table | | 0x3C228~0x40000 | **SI4732**-patch，Length 0x3DD8，used to update SI4732 firmware | | 0x3C210~0x3C21C | **SI4732**FM、AM、SSB Freq、Mode | [Doppler Eeprom Layout Explanation](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/doc/多普勒eeprom详细说明.txt) # Examples

# User Function Customization You can customize the firmware by enabling/disabling various compilation options. | Compilation Option | Description | |----------------------------------------|---------------------------------------------------------------------------------------------------------------------------------| | 🧰 **Quansheng Basic Functions** | [Quansheng Basic Functions](https://github.com/egzumer/uv-k5-firmware-custom) | | ENABLE_UART | UART, without this, you cannot configure the radio via PC! | | ENABLE_AIRCOPY | AirCopy wireless copy | | ENABLE_FMRADIO | FM radio function | | ENABLE_NOAA | NOAA function (only useful in the US) | | ENABLE_VOICE | Voice broadcast | | ENABLE_VOX | VOX voice-controlled transmission | | ENABLE_ALARM | TX alarm | | ENABLE_PWRON_PASSWORD | Boot password | | ENABLE_DTMF_CALLING | DTMF dialing function, call initiation, call reception, group call, contact list, etc. | | ENABLE_FLASHLIGHT | Enable top flashlight LED light (on, blink, SOS) | | ⌚ **Custom Module** | | | ENABLE_BIG_FREQ | Large font frequency display (similar to official Quansheng firmware) | | ENABLE_KEEP_MEM_NAME | Keep channel name when saving memory channel | | ENABLE_WIDE_RX | Receive full range from 18MHz to 1300MHz (although the front end/power amplifier is not designed for the entire range) | | ENABLE_TX_WHEN_AM | Allow TX when RX is set to AM (always FM) | | ENABLE_F_CAL_MENU | Enable hidden frequency calibration menu for radio | | ENABLE_CTCSS_TAIL_PHASE_SHIFT | Use standard CTCSS tail phase shift instead of the unique QS 55Hz tone method | | ENABLE_BOOT_BEEPS | Provide audio feedback for users at startup, indicating the position of the volume knob | | ENABLE_SHOW_CHARGE_LEVEL | Display battery charge level while radio is charging | | ENABLE_REVERSE_BAT_SYMBOL | Mirror battery symbol in status bar (positive pole on right) | | ENABLE_NO_CODE_SCAN_TIMEOUT | Disable 32-second CTCSS/DCS scan timeout (exit button instead of waiting for timeout to end scan) | | ENABLE_AM_FIX | Dynamically adjust front-end gain in AM mode to help prevent AM demodulator saturation, temporarily ignore RSSI level on screen | | ENABLE_SQUELCH_MORE_SENSITIVE | Slightly increase squelch sensitivity | | ENABLE_FASTER_CHANNEL_SCAN | Increase channel scan speed, but also increase squelch sensitivity | | ENABLE_RSSI_BAR | Enable RSSI bar graph level in dBm/Sn units, instead of small antenna symbol | | ENABLE_AUDIO_BAR | Display audio bar level while transmitting | | ENABLE_COPY_CHAN_TO_VFO | Copy current channel setting to frequency mode. Long press `1 BAND` in channel mode | | ENABLE_SPECTRUM | Spectrum analyzer, activated by `F` + `5 NOAA` | | ENABLE_REDUCE_LOW_MID_TX_POWER | Reduce mid and low power settings even lower | | ENABLE_BYP_RAW_DEMODULATORS | Additional BYP (bypass?) and RAW demodulation options, proven not very useful, but available if you want to experiment | | ENABLE_SCAN_RANGES | Scan range mode for frequency scanning | | ENABLE_BLOCK | EEPROM lock | | ENABLE_WARNING | Beep prompt | | ENABLE_CUSTOM_SIDEFUNCTIONS | Custom side key function | | ENABLE_SIDEFUNCTIONS_SEND | Custom side key function (side key transmit function) | | ENABLE_AUDIO_BAR_DEFAULT | Default audio bar style | | 📡 **Automatic Doppler** | [Automatic Doppler](https://github.com/losehu/uv-k5-firmware-custom) | | ENABLE_DOPPLER | Automatic Doppler function | | 📧 **SMS** | [SMS](https://github.com/joaquimorg/uv-k5-firmware-custom) | | ENABLE_MESSENGER | Send and receive short text messages (button = `F` + `MENU`) | | ENABLE_MESSENGER_DELIVERY_NOTIFICATION | Send notification to sender if message received | | ENABLE_MESSENGER_NOTIFICATION | Play sound when message received | | 📱 **MDC1200** | [MDC1200](https://github.com/OneOfEleven/uv-k5-firmware-custom) | | ENABLE_MDC1200 | MDC1200 transmission function | | ENABLE_MDC1200_SHOW_OP_ARG | MDC display head/tail parameter | | ENABLE_MDC1200_SIDE_BEEP | MDC side tone | | ENABLE_MDC1200_CONTACT | MDC contact | | 🎛️ **DOCK** | [DOCK](https://github.com/nicsure/QuanshengDock) | | ENABLE_DOCK | Allow control of the radio via PC, no screen display! | | 🚫 **Debug** | | | ENABLE_AM_FIX_SHOW_DATA | Display debug data for AM fix | | ENABLE_AGC_SHOW_DATA | Display ACG parameters | | ENABLE_UART_RW_BK_REGS | Added two extra commands to read and write BK4819 registers | | ⚠️ **Compilation Options** | | | ENABLE_CLANG | Experimental, build with clang instead of gcc (if this option is enabled, LTO will be disabled) | | ENABLE_SWD | Use the CPU's SWD port, required for debugging/programming | | ENABLE_OVERLAY | CPU FLASH-related content, not needed | | ENABLE_LTO | Reduce the size of the compiled firmware, but may break EEPROM reading (OVERLAY will be disabled after enabling) | # Donations If this project has been helpful to you, consider sponsoring to support development work. [Donation List](https://losehu.github.io/payment-codes/#%E6%94%B6%E6%AC%BE%E7%A0%81) Thank you very much for your support!!! Donation Codes: [![Donation Codes](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/payment/show.png)](https://losehu.github.io/payment-codes/) ## Star History [![Star History Chart](https://api.star-history.com/svg?repos=losehu/uv-k5-firmware-custom&type=Date)](https://star-history.com/#losehu/uv-k5-firmware-custom&Date) ================================================ FILE: am_fix.c ================================================ /* Copyright 2023 OneOfEleven * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ // code to 'try' and reduce the AM demodulator saturation problem // // that is until someone works out how to properly configure the BK chip ! #include #include "am_fix.h" #include "app/main.h" #include "board.h" #include "driver/bk4819.h" //#include "external/printf/printf.h" #include "frequencies.h" #include "functions.h" #include "misc.h" #include "settings.h" #ifdef ENABLE_AGC_SHOW_DATA #include "ui/main.h" #endif #ifdef ENABLE_AM_FIX typedef struct { uint16_t reg_val; int8_t gain_dB; } __attribute__((packed)) t_gain_table; // REG_10 AGC gain table // // <15:10> ??? // // <9:8> = LNA Gain Short // 3 = 0dB < original value // 2 = -19dB // was -11 // 1 = -24dB // was -16 // 0 = -28dB // was -19 // // <7:5> = LNA Gain // 7 = 0dB // 6 = -2dB // 5 = -4dB < original value // 4 = -6dB // 3 = -9dB // 2 = -14dB // 1 = -19dB // 0 = -24dB // // <4:3> = MIXER Gain // 3 = 0dB < original value // 2 = -3dB // 1 = -6dB // 0 = -8dB // // <2:0> = PGA Gain // 7 = 0dB // 6 = -3dB < original value // 5 = -6dB // 4 = -9dB // 3 = -15dB // 2 = -21dB // 1 = -27dB // 0 = -33dB // front end register dB values // // these values need to be accurate for the code to properly/reliably switch // between table entries when adjusting the front end registers. // // these 4 tables need a measuring/calibration update // //// static const int16_t lna_short_dB[] = { -19, -16, -11, 0}; // was (but wrong) // static const int16_t lna_short_dB[] = { (-28), (-24), (-19), 0}; // corrected'ish // static const int16_t lna_dB[] = { (-24), (-19), (-14), ( -9), (-6), (-4), (-2), 0}; // static const int16_t mixer_dB[] = { ( -8), ( -6), ( -3), 0}; // static const int16_t pga_dB[] = { (-33), (-27), (-21), (-15), (-9), (-6), (-3), 0}; // lookup table is hugely easier than writing code to do the same // #define LOOKUP_TABLE 1 #if LOOKUP_TABLE static const t_gain_table gain_table[] = { {0x03BE, -7}, // 0 .. 3 5 3 6 .. 0dB -4dB 0dB -3dB .. -7dB original {0x0000,-93}, // 1 .. 0 0 0 0 .. -28dB -24dB -8dB -33dB .. -93dB {0x0008,-91}, // 2 .. 0 0 1 0 .. -28dB -24dB -6dB -33dB .. -91dB {0x0010,-88}, // 3 .. 0 0 2 0 .. -28dB -24dB -3dB -33dB .. -88dB {0x0001,-87}, // 4 .. 0 0 0 1 .. -28dB -24dB -8dB -27dB .. -87dB {0x0009,-85}, // 5 .. 0 0 1 1 .. -28dB -24dB -6dB -27dB .. -85dB {0x0011,-82}, // 6 .. 0 0 2 1 .. -28dB -24dB -3dB -27dB .. -82dB {0x0002,-81}, // 7 .. 0 0 0 2 .. -28dB -24dB -8dB -21dB .. -81dB {0x000A,-79}, // 8 .. 0 0 1 2 .. -28dB -24dB -6dB -21dB .. -79dB {0x0012,-76}, // 9 .. 0 0 2 2 .. -28dB -24dB -3dB -21dB .. -76dB {0x0003,-75}, // 10 .. 0 0 0 3 .. -28dB -24dB -8dB -15dB .. -75dB {0x000B,-73}, // 11 .. 0 0 1 3 .. -28dB -24dB -6dB -15dB .. -73dB {0x0013,-70}, // 12 .. 0 0 2 3 .. -28dB -24dB -3dB -15dB .. -70dB {0x0004,-69}, // 13 .. 0 0 0 4 .. -28dB -24dB -8dB -9dB .. -69dB {0x000C,-67}, // 14 .. 0 0 1 4 .. -28dB -24dB -6dB -9dB .. -67dB {0x000D,-64}, // 15 .. 0 0 1 5 .. -28dB -24dB -6dB -6dB .. -64dB {0x001C,-61}, // 16 .. 0 0 3 4 .. -28dB -24dB 0dB - 9dB .. -61dB {0x001D,-58}, // 17 .. 0 0 3 5 .. -28dB -24dB 0dB -6dB .. -58dB {0x001E,-55}, // 18 .. 0 0 3 6 .. -28dB -24dB 0dB -3dB .. -55dB {0x001F,-52}, // 19 .. 0 0 3 7 .. -28dB -24dB 0dB 0dB .. -52dB {0x003E,-50}, // 20 .. 0 1 3 6 .. -28dB -19dB 0dB -3dB .. -50dB {0x003F,-47}, // 21 .. 0 1 3 7 .. -28dB -19dB 0dB 0dB .. -47dB {0x005E,-45}, // 22 .. 0 2 3 6 .. -28dB -14dB 0dB -3dB .. -45dB {0x005F,-42}, // 23 .. 0 2 3 7 .. -28dB -14dB 0dB 0dB .. -42dB {0x007E,-40}, // 24 .. 0 3 3 6 .. -28dB -9dB 0dB -3dB .. -40dB {0x007F,-37}, // 25 .. 0 3 3 7 .. -28dB -9dB 0dB 0dB .. -37dB {0x009F,-34}, // 26 .. 0 4 3 7 .. -28dB -6dB 0dB 0dB .. -34dB {0x00BF,-32}, // 27 .. 0 5 3 7 .. -28dB -4dB 0dB 0dB .. -32dB {0x00DF,-30}, // 28 .. 0 6 3 7 .. -28dB -2dB 0dB 0dB .. -30dB {0x00FF,-28}, // 29 .. 0 7 3 7 .. -28dB 0dB 0dB 0dB .. -28dB {0x01DF,-26}, // 30 .. 1 6 3 7 .. -24dB -2dB 0dB 0dB .. -26dB {0x01FF,-24}, // 31 .. 1 7 3 7 .. -24dB 0dB 0dB 0dB .. -24dB {0x02BF,-23}, // 32 .. 2 5 3 7 .. -19dB -4dB 0dB 0dB .. -23dB {0x02DF,-21}, // 33 .. 2 6 3 7 .. -19dB -2dB 0dB -0dB .. -21dB {0x02FF,-19}, // 34 .. 2 7 3 7 .. -19dB 0dB 0dB 0dB .. -19dB {0x035E,-17}, // 35 .. 3 2 3 6 .. 0dB -14dB 0dB -3dB .. -17dB {0x035F,-14}, // 36 .. 3 2 3 7 .. 0dB -14dB 0dB 0dB .. -14dB {0x037E,-12}, // 37 .. 3 3 3 6 .. 0dB -9dB 0dB -3dB .. -12dB {0x037F,-9}, // 38 .. 3 3 3 7 .. 0dB -9dB 0dB 0dB .. -9dB {0x038F,-6}, // 39 .. 3 4 3 7 .. 0dB - 6dB 0dB 0dB .. -6dB {0x03BF,-4}, // 40 .. 3 5 3 7 .. 0dB -4dB 0dB 0dB .. -4dB {0x03DF,-2}, // 41 .. 3 6 3 7 .. 0dB - 2dB 0dB 0dB .. -2dB {0x03FF,0} // 42 .. 3 7 3 7 .. 0dB 0dB 0dB 0dB .. 0dB }; const uint8_t gain_table_size = ARRAY_SIZE(gain_table); #else t_gain_table gain_table[100] = {{0x03BE, -7}}; //original uint8_t gain_table_size = 0; void CreateTable() { typedef union { struct { uint8_t pgaIdx:3; uint8_t mixerIdx:2; uint8_t lnaIdx:3; uint8_t lnaSIdx:2; }; uint16_t __raw; } GainData; static const int8_t lna_short_dB[] = {-28, -24, -19, 0}; // corrected'ish static const int8_t lna_dB[] = {-24, -19, -14, -9, -6, -4, -2, 0}; static const int8_t mixer_dB[] = { -8, -6, -3, 0}; static const int8_t pga_dB[] = {-33, -27, -21, -15, -9, -6, -3, 0}; unsigned i; for (uint8_t lnaSIdx = 0; lnaSIdx < ARRAY_SIZE(lna_short_dB); lnaSIdx++) { for (uint8_t lnaIdx = 0; lnaIdx < ARRAY_SIZE(lna_dB); lnaIdx++) { for (uint8_t mixerIdx = 0; mixerIdx < ARRAY_SIZE(mixer_dB); mixerIdx++) { for (uint8_t pgaIdx = 0; pgaIdx < ARRAY_SIZE(pga_dB); pgaIdx++) { int16_t db = lna_short_dB[lnaSIdx] + lna_dB[lnaIdx] + mixer_dB[mixerIdx] + pga_dB[pgaIdx]; GainData gainData = {{ pgaIdx, mixerIdx, lnaIdx, lnaSIdx, }}; for (i = 1; i < ARRAY_SIZE(gain_table); i++) { t_gain_table * gain = &gain_table[i]; if (db == gain->gain_dB) break; if (db > gain->gain_dB) continue; if (db < gain->gain_dB) { if(gain->gain_dB) memmove(gain + 1, gain, 100 - i); gain->gain_dB = db; gain->reg_val = gainData.__raw; break; } gain->gain_dB = db; gain->reg_val = gainData.__raw; break; } } } } } gain_table_size = i+1; } #endif #ifdef ENABLE_AM_FIX_SHOW_DATA // display update rate static const unsigned int display_update_rate = 250 / 10; // max 250ms display update rate unsigned int counter = 0; #endif unsigned int gain_table_index[2] = {0, 0}; // used simply to detect a changed gain setting unsigned int gain_table_index_prev[2] = {0, 0}; // holds the previous RSSI level .. we do an average of old + new RSSI reading int16_t prev_rssi[2] = {0, 0}; // to help reduce gain hunting, peak hold count down tick unsigned int hold_counter[2] = {0, 0}; // -89dBm, any higher and the AM demodulator starts to saturate/clip/distort const int16_t desired_rssi = (-89 + 160) * 2; int8_t currentGainDiff; bool enabled = true; void AM_fix_init(void) { // called at boot-up for (int i = 0; i < 2; i++) { gain_table_index[i] = 0; // re-start with original QS setting } #if !LOOKUP_TABLE CreateTable(); #endif } void AM_fix_reset(const unsigned vfo) { // reset the AM fixer upper if (vfo > 1) return; #ifdef ENABLE_AM_FIX_SHOW_DATA counter = 0; #endif prev_rssi[vfo] = 0; hold_counter[vfo] = 0; gain_table_index_prev[vfo] = 0; } // adjust the RX gain to try and prevent the AM demodulator from // saturating/overloading/clipping (distorted AM audio) // // we're actually doing the BK4819's job for it here, but as the chip // won't/don't do it for itself, we're left to bodging it ourself by // playing with the RF front end gain setting // void AM_fix_10ms(const unsigned vfo) { if(!gSetting_AM_fix || !enabled || vfo > 1 ) return; switch (gCurrentFunction) { case FUNCTION_TRANSMIT: case FUNCTION_BAND_SCOPE: case FUNCTION_POWER_SAVE: #ifdef ENABLE_AM_FIX_SHOW_DATA counter = display_update_rate; // queue up a display update as soon as we switch to RX mode #endif return; default: break; } #ifdef ENABLE_AM_FIX_SHOW_DATA if (counter > 0) { if (++counter >= display_update_rate) { // trigger a display update counter = 0; gUpdateDisplay = true; } } #endif static uint32_t lastFreq[2]; if(gEeprom.VfoInfo[vfo].pRX->Frequency != lastFreq[vfo]) { lastFreq[vfo] = gEeprom.VfoInfo[vfo].pRX->Frequency; AM_fix_reset(vfo); } int16_t rssi; { // sample the current RSSI level // average it with the previous rssi (a bit of noise/spike immunity) const int16_t new_rssi = BK4819_GetRSSI(); rssi = (prev_rssi[vfo] > 0) ? (prev_rssi[vfo] + new_rssi) / 2 : new_rssi; prev_rssi[vfo] = new_rssi; } #ifdef ENABLE_AM_FIX_SHOW_DATA { static int16_t lastRssi; if (lastRssi != rssi) { // rssi changed lastRssi = rssi; if (counter == 0) { counter = 1; gUpdateDisplay = true; // trigger a display update } } } #endif // automatically adjust the RF RX gain // update the gain hold counter if (hold_counter[vfo] > 0) hold_counter[vfo]--; // dB difference between actual and desired RSSI level int16_t diff_dB = (rssi - desired_rssi) / 2; if (diff_dB > 0) { // decrease gain unsigned int index = gain_table_index[vfo]; // current position we're at if (diff_dB >= 10) { // jump immediately to a new gain setting // this greatly speeds up initial gain reduction (but reduces noise/spike immunity) const int16_t desired_gain_dB = (int16_t)gain_table[index].gain_dB - diff_dB + 8; // get no closer than 8dB (bit of noise/spike immunity) // scan the table to see what index to jump straight too while (index > 1) if (gain_table[--index].gain_dB <= desired_gain_dB) break; } else { // incrementally reduce the gain .. taking it slow improves noise/spike immunity if (index > 1) index--; // slow step-by-step gain reduction } index = MAX(1u, index); if (gain_table_index[vfo] != index) { gain_table_index[vfo] = index; hold_counter[vfo] = 30; // 300ms hold } } if (diff_dB >= -6) // 6dB hysterisis (help reduce gain hunting) hold_counter[vfo] = 30; // 300ms hold if (hold_counter[vfo] == 0) { // hold has been released, we're free to increase gain const unsigned int index = gain_table_index[vfo] + 1; // move up to next gain index gain_table_index[vfo] = MIN(index, gain_table_size - 1u); } { // apply the new settings to the front end registers const unsigned int index = gain_table_index[vfo]; // remember the new table index gain_table_index_prev[vfo] = index; currentGainDiff = gain_table[0].gain_dB - gain_table[index].gain_dB; BK4819_WriteRegister(BK4819_REG_13, gain_table[index].reg_val); #ifdef ENABLE_AGC_SHOW_DATA UI_MAIN_PrintAGC(true); #endif } #ifdef ENABLE_AM_FIX_SHOW_DATA if (counter == 0) { counter = 1; gUpdateDisplay = true; } #endif } #ifdef ENABLE_AM_FIX_SHOW_DATA void AM_fix_print_data(const unsigned vfo, char *s) { if (s != NULL && vfo < ARRAY_SIZE(gain_table_index)) { const unsigned int index = gain_table_index[vfo]; sprintf(s, "%2u %4ddB %3u", index, gain_table[index].gain_dB, prev_rssi[vfo]); counter = 0; } } #endif int8_t AM_fix_get_gain_diff() { return currentGainDiff; } void AM_fix_enable(bool on) { enabled = on; } #endif ================================================ FILE: am_fix.h ================================================ /* Copyright 2023 OneOfEleven * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef AM_FIXH #include #include #ifdef ENABLE_AM_FIX void AM_fix_init(void); void AM_fix_reset(const unsigned vfo); void AM_fix_10ms(const unsigned vfo); #ifdef ENABLE_AM_FIX_SHOW_DATA void AM_fix_print_data(const unsigned vfo, char *s); #endif int8_t AM_fix_get_gain_diff(); void AM_fix_enable(bool on); #endif #endif ================================================ FILE: app/action.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ # include #include "app/generic.h" #include #ifdef ENABLE_FLASHLIGHT #include "app/flashlight.h" #endif #include "app/action.h" #include "app/app.h" #include "app/chFrScanner.h" #include "app/common.h" #include "app/dtmf.h" #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/scanner.h" #include "audio.h" #include "bsp/dp32g030/gpio.h" #ifdef ENABLE_FMRADIO #include "driver/bk1080.h" #endif #include "driver/bk4819.h" #include "driver/gpio.h" #include "driver/backlight.h" #include "functions.h" #include "misc.h" #include "settings.h" #include "ui/inputbox.h" #include "ui/ui.h" #if defined(ENABLE_FMRADIO) static void ACTION_Scan_FM(bool bRestart); #endif #if defined(ENABLE_ALARM) || defined(ENABLE_TX1750) static void ACTION_AlarmOr1750(bool b1750); inline static void ACTION_Alarm() { ACTION_AlarmOr1750(false); } inline static void ACTION_1750() { ACTION_AlarmOr1750(true); }; #endif inline static void ACTION_ScanRestart() { ACTION_Scan(true); }; void (*action_opt_table[])(void) = { [ACTION_OPT_NONE] = &FUNCTION_NOP, [ACTION_OPT_POWER] = &ACTION_Power, [ACTION_OPT_MONITOR] = &ACTION_Monitor, [ACTION_OPT_SCAN] = &ACTION_ScanRestart, [ACTION_OPT_KEYLOCK] = &COMMON_KeypadLockToggle, [ACTION_OPT_A_B] = &COMMON_SwitchVFOs, [ACTION_OPT_VFO_MR] = &COMMON_SwitchVFOMode, [ACTION_OPT_SWITCH_DEMODUL] = &ACTION_SwitchDemodul, #ifdef ENABLE_FLASHLIGHT [ACTION_OPT_FLASHLIGHT] = &ACTION_FlashLight, #else [ACTION_OPT_FLASHLIGHT] = &FUNCTION_NOP, #endif #ifdef ENABLE_VOX [ACTION_OPT_VOX] = &ACTION_Vox, #else [ACTION_OPT_VOX] = &FUNCTION_NOP, #endif #ifdef ENABLE_FMRADIO [ACTION_OPT_FM] = &ACTION_FM, #else [ACTION_OPT_FM] = &FUNCTION_NOP, #endif #ifdef ENABLE_ALARM [ACTION_OPT_ALARM] = &ACTION_Alarm, #else [ACTION_OPT_ALARM] = &FUNCTION_NOP, #endif #ifdef ENABLE_TX1750 [ACTION_OPT_1750] = &ACTION_1750, #else [ACTION_OPT_1750] = &FUNCTION_NOP, #endif #ifdef ENABLE_BLMIN_TMP_OFF [ACTION_OPT_BLMIN_TMP_OFF] = &ACTION_BlminTmpOff, #else [ACTION_OPT_BLMIN_TMP_OFF] = &FUNCTION_NOP, #endif [ACTION_OPT_D_DCD] = &ACTION_D_DCD, [ACTION_OPT_WIDTH] = &ACTION_WIDTH, #ifdef ENABLE_SIDEFUNCTIONS_SEND [ACTION_OPT_SEND_CURRENT] = &ACTION_SEND_CURRENT, [ACTION_OPT_SEND_OTHER] = &ACTION_SEND_OTHER #endif }; static_assert(ARRAY_SIZE(action_opt_table) == ACTION_OPT_LEN); void ACTION_Power(void) { if (++gTxVfo->OUTPUT_POWER > OUTPUT_POWER_HIGH) gTxVfo->OUTPUT_POWER = OUTPUT_POWER_LOW; gRequestSaveChannel = 1; gRequestDisplayScreen = gScreenToDisplay; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_POWER; #endif } void ACTION_Monitor(void) { if (gCurrentFunction != FUNCTION_MONITOR) { // enable the monitor RADIO_SelectVfos(); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gIsNoaaMode) gNoaaChannel = gRxVfo->CHANNEL_SAVE - NOAA_CHANNEL_FIRST; #endif RADIO_SetupRegisters(true); APP_StartListening(FUNCTION_MONITOR); return; } gMonitor = false; if (gScanStateDir != SCAN_OFF) { gScanPauseDelayIn_10ms = scan_pause_delay_in_1_10ms; gScheduleScanListen = false; gScanPauseMode = true; } #ifdef ENABLE_NOAA if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode) { gNOAA_Countdown_10ms = NOAA_countdown_10ms; gScheduleNOAA = false; } #endif RADIO_SetupRegisters(true); #ifdef ENABLE_FMRADIO if (gFmRadioMode) { FM_Start(); gRequestDisplayScreen = DISPLAY_FM; } else #endif gRequestDisplayScreen = gScreenToDisplay; } void ACTION_Scan(bool bRestart) { (void) bRestart; #ifdef ENABLE_FMRADIO if (gFmRadioMode) { ACTION_Scan_FM(bRestart); return; } #endif if (SCANNER_IsScanning()) { return; } // not scanning gMonitor = false; #ifdef ENABLE_DTMF_CALLING DTMF_clear_RX(); #endif gDTMF_RX_live_timeout = 0; memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live)); RADIO_SelectVfos(); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) { return; } #endif GUI_SelectNextDisplay(DISPLAY_MAIN); if (gScanStateDir != SCAN_OFF) { // already scanning if (!IS_MR_CHANNEL(gNextMrChannel)) { CHFRSCANNER_Stop(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif return; } // channel mode. Keep scanning but toggle between scan lists gEeprom.SCAN_LIST_DEFAULT = (gEeprom.SCAN_LIST_DEFAULT + 1) % 3; // jump to the next channel CHFRSCANNER_Start(false, gScanStateDir); gScanPauseDelayIn_10ms = 1; gScheduleScanListen = false; } else { // start scanning CHFRSCANNER_Start(true, SCAN_FWD); #ifdef ENABLE_VOICE AUDIO_SetVoiceID(0, VOICE_ID_SCANNING_BEGIN); AUDIO_PlaySingleVoice(true); #endif // clear the other vfo's rssi level (to hide the antenna symbol) gVFO_RSSI_bar_level[(gEeprom.RX_VFO + 1) & 1U] = 0; // let the user see DW is not active gDualWatchActive = false; } gUpdateStatus = true; } void ACTION_SwitchDemodul(void) { gRequestSaveChannel = 1; gTxVfo->Modulation++; if (gTxVfo->Modulation == MODULATION_UKNOWN) gTxVfo->Modulation = MODULATION_FM; } void ACTION_Handle(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (gScreenToDisplay == DISPLAY_MAIN && gDTMF_InputMode) { // entering DTMF code gPttWasReleased = true; if (Key != KEY_SIDE1 || bKeyHeld || !bKeyPressed) { return; } // side1 btn pressed gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; gRequestDisplayScreen = DISPLAY_MAIN; if (gDTMF_InputBox_Index <= 0) { // turn off DTMF input box if no codes left gDTMF_InputMode = false; return; } // DTMF codes are in the input box gDTMF_InputBox[--gDTMF_InputBox_Index] = '-'; // delete one code #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif return; } enum ACTION_OPT_t funcShort = ACTION_OPT_NONE; enum ACTION_OPT_t funcLong = ACTION_OPT_NONE; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS switch(Key) { case KEY_SIDE1: funcShort = gEeprom.KEY_1_SHORT_PRESS_ACTION; funcLong = gEeprom.KEY_1_LONG_PRESS_ACTION; break; case KEY_SIDE2: funcShort = gEeprom.KEY_2_SHORT_PRESS_ACTION; funcLong = gEeprom.KEY_2_LONG_PRESS_ACTION; break; case KEY_MENU: funcLong = gEeprom.KEY_M_LONG_PRESS_ACTION; break; default: break; } #else switch (Key) { case KEY_SIDE1: funcShort = ACTION_OPT_MONITOR;//gEeprom.KEY_1_SHORT_PRESS_ACTION; funcLong = ACTION_OPT_D_DCD;//gEeprom.KEY_1_LONG_PRESS_ACTION; break; case KEY_SIDE2: funcShort = ACTION_OPT_WIDTH;// gEeprom.KEY_2_SHORT_PRESS_ACTION; funcLong = ACTION_OPT_FLASHLIGHT; break; case KEY_MENU: funcLong = ACTION_OPT_SWITCH_DEMODUL;//gEeprom.KEY_M_LONG_PRESS_ACTION; break; default: break; } #endif if (!bKeyHeld && bKeyPressed) // button pushed { return; } // held or released beyond this point if (!(bKeyHeld && !bKeyPressed)) // don't beep on released after hold gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; if (bKeyHeld || bKeyPressed) // held { funcShort = funcLong; #ifdef ENABLE_SIDEFUNCTIONS_SEND if(funcShort == ACTION_OPT_SEND_CURRENT || funcShort == ACTION_OPT_SEND_OTHER){ gFlagLastVfo = gEeprom.TX_VFO; gEeprom.TX_VFO = funcShort == ACTION_OPT_SEND_CURRENT ? gFlagLastVfo : !gFlagLastVfo; gFlagReconfigureVfos = true; gFlagStopTX = true; GENERIC_Key_PTT(bKeyPressed); } #endif if (!bKeyPressed) //ignore release if held return; } // held or released after short press beyond this point action_opt_table[funcShort](); // switch (funcShort) // { // default: // case ACTION_OPT_WIDTH: // gTxVfo->CHANNEL_BANDWIDTH=!gTxVfo->CHANNEL_BANDWIDTH; // gRequestSaveChannel = 1; // break; // case ACTION_OPT_NONE: // break; // // case ACTION_OPT_POWER: // ACTION_Power(); // break; // case ACTION_OPT_MONITOR: // ACTION_Monitor(); // break; // case ACTION_OPT_SCAN: // ACTION_Scan(true); // break; // // case ACTION_OPT_KEYLOCK: // COMMON_KeypadLockToggle(); // break; // case ACTION_OPT_A_B: // COMMON_SwitchVFOs(); // break; // case ACTION_OPT_VFO_MR: // COMMON_SwitchVFOMode(); // break; // case ACTION_OPT_SWITCH_DEMODUL: // ACTION_SwitchDemodul(); // break; //#ifdef ENABLE_FLASHLIGHT // case ACTION_OPT_FLASHLIGHT: // ACTION_FlashLight(); //#endif // break; //#ifdef ENABLE_VOX // case ACTION_OPT_VOX: // ACTION_Vox(); //#endif // break; //#ifdef ENABLE_FMRADIO // case ACTION_OPT_FM: // ACTION_FM(); //#endif // break; //#ifdef ENABLE_ALARM // case ACTION_OPT_ALARM: // ACTION_AlarmOr1750(false); // break; //#endif // case ACTION_OPT_1750: //#if defined(ENABLE_TX1750) // ACTION_AlarmOr1750(true); // break; //#endif //#ifdef ENABLE_DTMF_CALLING // case ACTION_OPT_D_DCD: // gTxVfo->DTMF_DECODING_ENABLE = !gTxVfo->DTMF_DECODING_ENABLE; // DTMF_clear_RX(); // gRequestSaveChannel = 1; // break; // //#endif //#ifdef ENABLE_BLMIN_TMP_OFF // case ACTION_OPT_BLMIN_TMP_OFF: // ACTION_BlminTmpOff(); // break; //#endif // } } #ifdef ENABLE_FMRADIO void ACTION_FM(void) { if (gCurrentFunction != FUNCTION_TRANSMIT && gCurrentFunction != FUNCTION_MONITOR) { gInputBoxIndex = 0; if (gFmRadioMode) { FM_TurnOff(); gFlagReconfigureVfos = true; gRequestDisplayScreen = DISPLAY_MAIN; #ifdef ENABLE_VOX gVoxResumeCountdown = 80; #endif return; } gMonitor = false; RADIO_SelectVfos(); RADIO_SetupRegisters(true); FM_Start(); gRequestDisplayScreen = DISPLAY_FM; } } static void ACTION_Scan_FM(bool bRestart) { if (FUNCTION_IsRx()) return; GUI_SelectNextDisplay(DISPLAY_FM); gMonitor = false; if (gFM_ScanState != FM_SCAN_OFF) { FM_PlayAndUpdate(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif return; } uint16_t freq; if (bRestart) { gFM_AutoScan = true; gFM_ChannelPosition = 0; FM_EraseChannels(); freq = gEeprom.FM_LowerLimit; } else { gFM_AutoScan = false; gFM_ChannelPosition = 0; freq = gEeprom.FM_FrequencyPlaying; } BK1080_GetFrequencyDeviation(freq); FM_Tune(freq, 1, bRestart); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_BEGIN; #endif } #endif #if defined(ENABLE_ALARM) || defined(ENABLE_TX1750) static void ACTION_AlarmOr1750(const bool b1750) { #if defined(ENABLE_ALARM) const AlarmState_t alarm_mode = (gEeprom.ALARM_MODE == ALARM_MODE_TONE) ? ALARM_STATE_TXALARM : ALARM_STATE_SITE_ALARM; gAlarmRunningCounter = 0; #endif #if defined(ENABLE_ALARM) && defined(ENABLE_TX1750) gAlarmState = b1750 ? ALARM_STATE_TX1750 : alarm_mode; #elif defined(ENABLE_ALARM) gAlarmState = alarm_mode; #else gAlarmState = ALARM_STATE_TX1750; #endif (void)b1750; gInputBoxIndex = 0; gFlagPrepareTX = gAlarmState != ALARM_STATE_OFF; if (gScreenToDisplay != DISPLAY_MENU) // 1of11 .. don't close the menu gRequestDisplayScreen = DISPLAY_MAIN; } #endif #ifdef ENABLE_VOX void ACTION_Vox(void) { gEeprom.VOX_SWITCH = !gEeprom.VOX_SWITCH; gRequestSaveSettings = true; gFlagReconfigureVfos = true; gUpdateStatus = true; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_VOX; #endif } #endif #ifdef ENABLE_BLMIN_TMP_OFF void ACTION_BlminTmpOff(void) { if(++gEeprom.BACKLIGHT_MIN_STAT == BLMIN_STAT_UNKNOWN) { gEeprom.BACKLIGHT_MIN_STAT = BLMIN_STAT_ON; BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MIN); } else { BACKLIGHT_SetBrightness(0); } } #endif void ACTION_WIDTH(void) { gRequestSaveChannel = 1; gTxVfo->CHANNEL_BANDWIDTH = !gTxVfo->CHANNEL_BANDWIDTH; } void ACTION_D_DCD(void) { gRequestSaveChannel = 1; gTxVfo->DTMF_DECODING_ENABLE = !gTxVfo->DTMF_DECODING_ENABLE; DTMF_clear_RX(); } #ifdef ENABLE_SIDEFUNCTIONS_SEND void ACTION_SEND_CURRENT(void){return;} void ACTION_SEND_OTHER(void){return;} #endif ================================================ FILE: app/action.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_ACTION_H #define APP_ACTION_H #include "driver/keyboard.h" //static void ACTION_FlashLight(void) void ACTION_Power(void); void ACTION_Monitor(void); void ACTION_Scan(bool bRestart); #ifdef ENABLE_VOX void ACTION_Vox(void); #endif #ifdef ENABLE_FMRADIO void ACTION_FM(void); #endif void ACTION_SwitchDemodul(void); void ACTION_SwitchWidth(void); void ACTION_SwitchDTMFDecode(void); #ifdef ENABLE_BLMIN_TMP_OFF void ACTION_BlminTmpOff(void); #endif void ACTION_D_DCD(void); void ACTION_WIDTH(void); void ACTION_Handle(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); #ifdef ENABLE_SIDEFUNCTIONS_SEND void ACTION_SEND_CURRENT(void); void ACTION_SEND_OTHER(void); #endif #endif ================================================ FILE: app/aircopy.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifdef ENABLE_AIRCOPY #include "app/aircopy.h" #include "audio.h" #include "driver/bk4819.h" #include "driver/crc.h" #include "driver/eeprom.h" #include "frequencies.h" #include "misc.h" #include "radio.h" #include "ui/helper.h" #include "ui/inputbox.h" #include "ui/ui.h" static const uint16_t Obfuscation[8] = { 0x6C16, 0xE614, 0x912E, 0x400D, 0x3521, 0x40D5, 0x0313, 0x80E9 }; AIRCOPY_State_t gAircopyState; uint16_t gAirCopyBlockNumber; uint16_t gErrorsDuringAirCopy; uint8_t gAirCopyIsSendMode; uint16_t g_FSK_Buffer[36]; bool AIRCOPY_SendMessage(void) { static uint8_t gAircopySendCountdown = 1; if (gAircopyState != AIRCOPY_TRANSFER) { return 1; } if (--gAircopySendCountdown) { return 1; } g_FSK_Buffer[1] = (gAirCopyBlockNumber & 0x3FF) << 6; EEPROM_ReadBuffer(g_FSK_Buffer[1], &g_FSK_Buffer[2], 64); g_FSK_Buffer[34] = CRC_Calculate(&g_FSK_Buffer[1], 2 + 64); for (unsigned int i = 0; i < 34; i++) { g_FSK_Buffer[i + 1] ^= Obfuscation[i % 8]; } if (++gAirCopyBlockNumber >= 0x78) { gAircopyState = AIRCOPY_COMPLETE; } RADIO_SetTxParameters(); BK4819_SendFSKData(g_FSK_Buffer); BK4819_SetupPowerAmplifier(0, 0); BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, false); gAircopySendCountdown = 30; return 0; } void AIRCOPY_StorePacket(void) { if (gFSKWriteIndex < 36) { return; } gFSKWriteIndex = 0; gUpdateDisplay = true; uint16_t Status = BK4819_ReadRegister(BK4819_REG_0B); BK4819_PrepareFSKReceive(); // Doc says bit 4 should be 1 = CRC OK, 0 = CRC FAIL, but original firmware checks for FAIL. if ((Status & 0x0010U) != 0 || g_FSK_Buffer[0] != 0xABCD || g_FSK_Buffer[35] != 0xDCBA) { gErrorsDuringAirCopy++; return; } for (unsigned int i = 0; i < 34; i++) { g_FSK_Buffer[i + 1] ^= Obfuscation[i % 8]; } uint16_t CRC = CRC_Calculate(&g_FSK_Buffer[1], 2 + 64); if (g_FSK_Buffer[34] != CRC) { gErrorsDuringAirCopy++; return; } uint16_t Offset = g_FSK_Buffer[1]; if (Offset >= 0x1E00) { gErrorsDuringAirCopy++; return; } const uint16_t *pData = &g_FSK_Buffer[2]; for (unsigned int i = 0; i < 8; i++) { EEPROM_WriteBuffer(Offset, pData,8); pData += 4; Offset += 8; } if (Offset == 0x1E00) { gAircopyState = AIRCOPY_COMPLETE; } gAirCopyBlockNumber++; } static void AIRCOPY_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) { return; } INPUTBOX_Append(Key); gRequestDisplayScreen = DISPLAY_AIRCOPY; if (gInputBoxIndex < 6) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif return; } gInputBoxIndex = 0; uint32_t Frequency = StrToUL(INPUTBOX_GetAscii()) * 100; for (unsigned int i = 0; i < BAND_N_ELEM; i++) { if (Frequency < frequencyBandTable[i].lower || Frequency >= frequencyBandTable[i].upper) { continue; } if (TX_freq_check(Frequency)) { continue; } #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif Frequency = FREQUENCY_RoundToStep(Frequency, gRxVfo->StepFrequency); gRxVfo->Band = i; gRxVfo->freq_config_RX.Frequency = Frequency; gRxVfo->freq_config_TX.Frequency = Frequency; RADIO_ConfigureSquelchAndOutputPower(gRxVfo); gCurrentVfo = gRxVfo; RADIO_SetupRegisters(true); BK4819_SetupAircopy(); BK4819_ResetFSK(); return; } gRequestDisplayScreen = DISPLAY_AIRCOPY; } static void AIRCOPY_Key_EXIT(bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) { return; } if (gInputBoxIndex == 0) { gFSKWriteIndex = 0; gAirCopyBlockNumber = 0; gInputBoxIndex = 0; gErrorsDuringAirCopy = 0; gAirCopyIsSendMode = 0; BK4819_PrepareFSKReceive(); gAircopyState = AIRCOPY_TRANSFER; } else { gInputBox[--gInputBoxIndex] = 10; } gRequestDisplayScreen = DISPLAY_AIRCOPY; } static void AIRCOPY_Key_MENU(bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) { return; } gFSKWriteIndex = 0; gAirCopyBlockNumber = 0; gInputBoxIndex = 0; gAirCopyIsSendMode = 1; g_FSK_Buffer[0] = 0xABCD; g_FSK_Buffer[1] = 0; g_FSK_Buffer[35] = 0xDCBA; GUI_DisplayScreen(); gAircopyState = AIRCOPY_TRANSFER; } void AIRCOPY_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { switch (Key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: AIRCOPY_Key_DIGITS(Key, bKeyPressed, bKeyHeld); break; case KEY_MENU: AIRCOPY_Key_MENU(bKeyPressed, bKeyHeld); break; case KEY_EXIT: AIRCOPY_Key_EXIT(bKeyPressed, bKeyHeld); break; default: break; } } #endif ================================================ FILE: app/aircopy.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_AIRCOPY_H #define APP_AIRCOPY_H #ifdef ENABLE_AIRCOPY #include "driver/keyboard.h" enum AIRCOPY_State_t { AIRCOPY_READY = 0, AIRCOPY_TRANSFER, AIRCOPY_COMPLETE }; typedef enum AIRCOPY_State_t AIRCOPY_State_t; extern AIRCOPY_State_t gAircopyState; extern uint16_t gAirCopyBlockNumber; extern uint16_t gErrorsDuringAirCopy; extern uint8_t gAirCopyIsSendMode; extern uint16_t g_FSK_Buffer[36]; bool AIRCOPY_SendMessage(void); void AIRCOPY_StorePacket(void); void AIRCOPY_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); #endif #endif ================================================ FILE: app/app.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "assert.h" #ifdef ENABLE_FLASHLIGHT #include "app/flashlight.h" #endif #include #include #include #include "mdc1200.h" #include "app/action.h" #ifdef ENABLE_AIRCOPY #include "app/aircopy.h" #endif #include "app/app.h" #include "app/chFrScanner.h" #include "app/dtmf.h" #include "driver/uart.h" #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/generic.h" #include "app/main.h" #include "app/menu.h" #include "app/scanner.h" #ifdef ENABLE_UART #include "app/uart.h" #endif #include "ARMCM0.h" #include "audio.h" #include "board.h" #include "bsp/dp32g030/gpio.h" #include "driver/backlight.h" #ifdef ENABLE_FMRADIO #include "driver/bk1080.h" #endif #include "driver/bk4819.h" #include "driver/gpio.h" #include "driver/keyboard.h" #include "driver/st7565.h" #include "driver/system.h" #include "am_fix.h" #include "dtmf.h" //#include "external/printf/printf.h" #include "frequencies.h" #include "functions.h" #include "helper/battery.h" #include "misc.h" #include "radio.h" #include "settings.h" #if defined(ENABLE_OVERLAY) #include "sram-overlay.h" #endif #ifdef ENABLE_MESSENGER #include "app/messenger.h" #endif #ifdef ENABLE_DOPPLER #include "app/doppler.h" #endif #include "ui/battery.h" #include "ui/inputbox.h" #include "ui/main.h" #include "ui/menu.h" #include "ui/status.h" #include "ui/ui.h" #include "messenger.h" #ifdef ENABLE_MESSENGER_NOTIFICATION bool gPlayMSGRing = false; uint8_t gPlayMSGRingCount = 0; #endif static bool flagSaveVfo; static bool flagSaveSettings; static bool flagSaveChannel; static void ProcessKey(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); void (*ProcessKeysFunctions[])(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) = { [DISPLAY_MAIN] = &MAIN_ProcessKeys, [DISPLAY_MENU] = &MENU_ProcessKeys, [DISPLAY_SCANNER] = &SCANNER_ProcessKeys, #ifdef ENABLE_FMRADIO [DISPLAY_FM] = &FM_ProcessKeys, #endif #ifdef ENABLE_MESSENGER [DISPLAY_MSG] = &MSG_ProcessKeys, #endif #ifdef ENABLE_AIRCOPY [DISPLAY_AIRCOPY] = &AIRCOPY_ProcessKeys, #endif }; static_assert(ARRAY_SIZE(ProcessKeysFunctions) == DISPLAY_N_ELEM); static void CheckForIncoming(void) { if (!g_SquelchLost) return; // squelch is closed // squelch is open if (gScanStateDir == SCAN_OFF) { // not RF scanning if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF) { // dual watch is disabled #ifdef ENABLE_NOAA if (gIsNoaaMode) { gNOAA_Countdown_10ms = NOAA_countdown_3_10ms; gScheduleNOAA = false; } #endif if (gCurrentFunction != FUNCTION_INCOMING) { FUNCTION_Select(FUNCTION_INCOMING); //gUpdateDisplay = true; } return; } // dual watch is enabled and we're RX'ing a signal if (gRxReceptionMode != RX_MODE_NONE) { if (gCurrentFunction != FUNCTION_INCOMING) { FUNCTION_Select(FUNCTION_INCOMING); //gUpdateDisplay = true; } return; } gDualWatchCountdown_10ms = dual_watch_count_after_rx_10ms; gScheduleDualWatch = false; // let the user see DW is not active gDualWatchActive = false; gUpdateStatus = true; } else { // RF scanning if (gRxReceptionMode != RX_MODE_NONE) { if (gCurrentFunction != FUNCTION_INCOMING) { FUNCTION_Select(FUNCTION_INCOMING); //gUpdateDisplay = true; } return; } gScanPauseDelayIn_10ms = scan_pause_delay_in_3_10ms; gScheduleScanListen = false; } gRxReceptionMode = RX_MODE_DETECTED; if (gCurrentFunction != FUNCTION_INCOMING) { FUNCTION_Select(FUNCTION_INCOMING); //gUpdateDisplay = true; } } static void HandleIncoming(void) { if (!g_SquelchLost) { // squelch is closed #ifdef ENABLE_DTMF_CALLING if (gDTMF_RX_index > 0) DTMF_clear_RX(); #endif if (gCurrentFunction != FUNCTION_FOREGROUND) { FUNCTION_Select(FUNCTION_FOREGROUND); //OK gUpdateDisplay = true; } return; } bool bFlag = (gScanStateDir == SCAN_OFF && gCurrentCodeType == CODE_TYPE_OFF); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gNOAACountdown_10ms > 0) { gNOAACountdown_10ms = 0; bFlag = true; } #endif if (g_CTCSS_Lost && gCurrentCodeType == CODE_TYPE_CONTINUOUS_TONE) { bFlag = true; gFoundCTCSS = false; } if (g_CDCSS_Lost && gCDCSSCodeType == CDCSS_POSITIVE_CODE && (gCurrentCodeType == CODE_TYPE_DIGITAL || gCurrentCodeType == CODE_TYPE_REVERSE_DIGITAL)) { gFoundCDCSS = false; } else if (!bFlag) return; #ifdef ENABLE_DTMF_CALLING if (gScanStateDir == SCAN_OFF && (gRxVfo->DTMF_DECODING_ENABLE || gSetting_KILLED)) { // DTMF DCD is enabled DTMF_HandleRequest(); if (gDTMF_CallState == DTMF_CALL_STATE_NONE) { if (gRxReceptionMode != RX_MODE_DETECTED) { return; } gDualWatchCountdown_10ms = dual_watch_count_after_1_10ms; gScheduleDualWatch = false; gRxReceptionMode = RX_MODE_LISTENING; // let the user see DW is not active gDualWatchActive = false; gUpdateStatus = true; gUpdateDisplay = true; return; } } #endif APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE); } static void HandleReceive(void) { #define END_OF_RX_MODE_SKIP 0 #define END_OF_RX_MODE_END 1 #define END_OF_RX_MODE_TTE 2 uint8_t Mode = END_OF_RX_MODE_SKIP; if (gFlagTailToneEliminationComplete) { Mode = END_OF_RX_MODE_END; goto Skip; } if (gScanStateDir != SCAN_OFF && IS_FREQ_CHANNEL(gNextMrChannel)) { // we are scanning in the frequency mode if (g_SquelchLost) return; Mode = END_OF_RX_MODE_END; goto Skip; } switch (gCurrentCodeType) { default: case CODE_TYPE_OFF: break; case CODE_TYPE_CONTINUOUS_TONE: if (gFoundCTCSS && gFoundCTCSSCountdown_10ms == 0) { gFoundCTCSS = false; gFoundCDCSS = false; Mode = END_OF_RX_MODE_END; goto Skip; } break; case CODE_TYPE_DIGITAL: case CODE_TYPE_REVERSE_DIGITAL: if (gFoundCDCSS && gFoundCDCSSCountdown_10ms == 0) { gFoundCTCSS = false; gFoundCDCSS = false; Mode = END_OF_RX_MODE_END; goto Skip; } break; } if (g_SquelchLost) { #ifdef ENABLE_NOAA if (!gEndOfRxDetectedMaybe && !IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) #else if (!gEndOfRxDetectedMaybe) #endif { switch (gCurrentCodeType) { case CODE_TYPE_OFF: if (gEeprom.SQUELCH_LEVEL) { if (g_CxCSS_TAIL_Found) { Mode = END_OF_RX_MODE_TTE; g_CxCSS_TAIL_Found = false; } } break; case CODE_TYPE_CONTINUOUS_TONE: if (g_CTCSS_Lost) { gFoundCTCSS = false; } else if (!gFoundCTCSS) { gFoundCTCSS = true; gFoundCTCSSCountdown_10ms = 100; // 1 sec } if (g_CxCSS_TAIL_Found) { Mode = END_OF_RX_MODE_TTE; g_CxCSS_TAIL_Found = false; } break; case CODE_TYPE_DIGITAL: case CODE_TYPE_REVERSE_DIGITAL: if (g_CDCSS_Lost && gCDCSSCodeType == CDCSS_POSITIVE_CODE) { gFoundCDCSS = false; } else if (!gFoundCDCSS) { gFoundCDCSS = true; gFoundCDCSSCountdown_10ms = 100; // 1 sec } if (g_CxCSS_TAIL_Found) { if (BK4819_GetCTCType() == 1) Mode = END_OF_RX_MODE_TTE; g_CxCSS_TAIL_Found = false; } break; } } } else Mode = END_OF_RX_MODE_END; if (!gEndOfRxDetectedMaybe && Mode == END_OF_RX_MODE_SKIP && gNextTimeslice40ms && gEeprom.TAIL_TONE_ELIMINATION && (gCurrentCodeType == CODE_TYPE_DIGITAL || gCurrentCodeType == CODE_TYPE_REVERSE_DIGITAL) && BK4819_GetCTCType() == 1) Mode = END_OF_RX_MODE_TTE; else gNextTimeslice40ms = false; Skip: switch (Mode) { case END_OF_RX_MODE_SKIP: break; case END_OF_RX_MODE_END: RADIO_SetupRegisters(true); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) gNOAACountdown_10ms = 300; // 3 sec #endif gUpdateDisplay = true; if (gScanStateDir != SCAN_OFF) { switch (gEeprom.SCAN_RESUME_MODE) { case SCAN_RESUME_TO: break; case SCAN_RESUME_CO: gScanPauseDelayIn_10ms = scan_pause_delay_in_7_10ms; gScheduleScanListen = false; break; case SCAN_RESUME_SE: CHFRSCANNER_Stop(); break; } } break; case END_OF_RX_MODE_TTE: if (gEeprom.TAIL_TONE_ELIMINATION) { AUDIO_AudioPathOff(); gTailToneEliminationCountdown_10ms = 20; gFlagTailToneEliminationComplete = false; gEndOfRxDetectedMaybe = true; gEnableSpeaker = false; } break; } } static void HandlePowerSave() { if (!gRxIdleMode) { CheckForIncoming(); } } static void (*HandleFunction_fn_table[])(void) = { [FUNCTION_FOREGROUND] = &CheckForIncoming, [FUNCTION_TRANSMIT] = &FUNCTION_NOP, [FUNCTION_MONITOR] = &FUNCTION_NOP, [FUNCTION_INCOMING] = &HandleIncoming, [FUNCTION_RECEIVE] = &HandleReceive, [FUNCTION_POWER_SAVE] = &HandlePowerSave, [FUNCTION_BAND_SCOPE] = &FUNCTION_NOP, }; static_assert(ARRAY_SIZE(HandleFunction_fn_table) == FUNCTION_N_ELEM); static void HandleFunction(void) { HandleFunction_fn_table[gCurrentFunction](); } void APP_StartListening(FUNCTION_Type_t function) { const unsigned int vfo = gEeprom.RX_VFO; // const unsigned int chan = gRxVfo->CHANNEL_SAVE; #ifdef ENABLE_DTMF_CALLING if (gSetting_KILLED) return; #endif #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Init(0, false); #endif // clear the other vfo's rssi level (to hide the antenna symbol) gVFO_RSSI_bar_level[!vfo] = 0; AUDIO_AudioPathOn(); gEnableSpeaker = true; BACKLIGHT_TurnOn(); if (gScanStateDir != SCAN_OFF) CHFRSCANNER_Found(); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gIsNoaaMode) { gRxVfo->CHANNEL_SAVE = gNoaaChannel + NOAA_CHANNEL_FIRST; gRxVfo->pRX->Frequency = NoaaFrequencyTable[gNoaaChannel]; gRxVfo->pTX->Frequency = NoaaFrequencyTable[gNoaaChannel]; gEeprom.ScreenChannel[vfo] = gRxVfo->CHANNEL_SAVE; gNOAA_Countdown_10ms = 500; // 5 sec gScheduleNOAA = false; } #endif if (gScanStateDir == SCAN_OFF && gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) { // not scanning, dual watch is enabled gDualWatchCountdown_10ms = dual_watch_count_after_2_10ms; gScheduleDualWatch = false; // when crossband is active only the main VFO should be used for TX if (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF) gRxVfoIsActive = true; // let the user see DW is not active gDualWatchActive = false; gUpdateStatus = true; } BK4819_WriteRegister(BK4819_REG_48, (11u << 12) | // ??? .. 0 to 15, doesn't seem to make any difference (0u << 10) | // AF Rx Gain-1 (gEeprom.VOLUME_GAIN << 4) | // AF Rx Gain-2 (gEeprom.DAC_GAIN << 0)); // AF DAC Gain (after Gain-1 and Gain-2) #ifdef ENABLE_VOICE if (gVoiceWriteIndex == 0) // AM/FM RX mode will be set when the voice has finished #endif RADIO_SetModulation(gRxVfo->Modulation); // no need, set it now FUNCTION_Select(function); #ifdef ENABLE_FMRADIO if (function == FUNCTION_MONITOR || gFmRadioMode) #else if (function == FUNCTION_MONITOR) #endif { // squelch is disabled if (gScreenToDisplay != DISPLAY_MENU) // 1of11 .. don't close the menu GUI_SelectNextDisplay(DISPLAY_MAIN); } else gUpdateDisplay = true; gUpdateStatus = true; } uint32_t APP_SetFreqByStepAndLimits(VFO_Info_t *pInfo, int8_t direction, uint32_t lower, uint32_t upper) { uint32_t Frequency = FREQUENCY_RoundToStep(pInfo->freq_config_RX.Frequency + (direction * pInfo->StepFrequency), pInfo->StepFrequency); if (Frequency >= upper) Frequency = lower; else if (Frequency < lower) Frequency = FREQUENCY_RoundToStep(upper - pInfo->StepFrequency, pInfo->StepFrequency); return Frequency; } uint32_t APP_SetFrequencyByStep(VFO_Info_t *pInfo, int8_t direction) { return APP_SetFreqByStepAndLimits(pInfo, direction, frequencyBandTable[pInfo->Band].lower, frequencyBandTable[pInfo->Band].upper); } #ifdef ENABLE_NOAA static void NOAA_IncreaseChannel(void) { if (++gNoaaChannel > 9) gNoaaChannel = 0; } #endif static void DualwatchAlternate(void) { #ifdef ENABLE_NOAA if (gIsNoaaMode) { if (!IS_NOAA_CHANNEL(gEeprom.ScreenChannel[0]) || !IS_NOAA_CHANNEL(gEeprom.ScreenChannel[1])) gEeprom.RX_VFO = (gEeprom.RX_VFO + 1) & 1; else gEeprom.RX_VFO = 0; gRxVfo = &gEeprom.VfoInfo[gEeprom.RX_VFO]; if (IS_NOAA_CHANNEL(gEeprom.VfoInfo[0].CHANNEL_SAVE)) NOAA_IncreaseChannel(); } else #endif { // toggle between VFO's gEeprom.RX_VFO = !gEeprom.RX_VFO; gRxVfo = &gEeprom.VfoInfo[gEeprom.RX_VFO]; if (!gDualWatchActive) { // let the user see DW is active gDualWatchActive = true; gUpdateStatus = true; } } RADIO_SetupRegisters(false); #ifdef ENABLE_NOAA gDualWatchCountdown_10ms = gIsNoaaMode ? dual_watch_count_noaa_10ms : dual_watch_count_toggle_10ms; #else gDualWatchCountdown_10ms = dual_watch_count_toggle_10ms; #endif } static void CheckRadioInterrupts(void) { if (SCANNER_IsScanning()) return; while (BK4819_ReadRegister(BK4819_REG_0C) & 1u) { // BK chip interrupt request // clear interrupts BK4819_WriteRegister(BK4819_REG_02, 0); // fetch interrupt status bits union { struct { uint16_t __UNUSED: 1; uint16_t fskRxSync: 1; uint16_t sqlLost: 1; uint16_t sqlFound: 1; uint16_t voxLost: 1; uint16_t voxFound: 1; uint16_t ctcssLost: 1; uint16_t ctcssFound: 1; uint16_t cdcssLost: 1; uint16_t cdcssFound: 1; uint16_t cssTailFound: 1; uint16_t dtmf5ToneFound: 1; uint16_t fskFifoAlmostFull: 1; uint16_t fskRxFinied: 1; uint16_t fskFifoAlmostEmpty: 1; uint16_t fskTxFinied: 1; }; uint16_t __raw; } interrupts; interrupts.__raw = BK4819_ReadRegister(BK4819_REG_02); // 0 = no phase shift // 1 = 120deg phase shift // 2 = 180deg phase shift // 3 = 240deg phase shift // const uint8_t ctcss_shift = BK4819_GetCTCShift(); // if (ctcss_shift > 0) // g_CTCSS_Lost = true; if (interrupts.dtmf5ToneFound) { const char c = DTMF_GetCharacter(BK4819_GetDTMF_5TONE_Code()); // save the RX'ed DTMF character if (c != 0xff) { if (gCurrentFunction != FUNCTION_TRANSMIT) { if (gSetting_live_DTMF_decoder) { size_t len = strlen(gDTMF_RX_live); if (len >= sizeof(gDTMF_RX_live) - 1) { // make room memmove(&gDTMF_RX_live[0], &gDTMF_RX_live[1], sizeof(gDTMF_RX_live) - 1); len--; } gDTMF_RX_live[len++] = c; gDTMF_RX_live[len] = 0; gDTMF_RX_live_timeout = DTMF_RX_live_timeout_500ms; // time till we delete it gUpdateDisplay = true; } #ifdef ENABLE_DTMF_CALLING if (gRxVfo->DTMF_DECODING_ENABLE || gSetting_KILLED) { if (gDTMF_RX_index >= sizeof(gDTMF_RX) - 1) { // make room memmove(&gDTMF_RX[0], &gDTMF_RX[1], sizeof(gDTMF_RX) - 1); gDTMF_RX_index--; } gDTMF_RX[gDTMF_RX_index++] = c; gDTMF_RX[gDTMF_RX_index] = 0; gDTMF_RX_timeout = DTMF_RX_timeout_500ms; // time till we delete it gDTMF_RX_pending = true; SYSTEM_DelayMs(3);//fix DTMF not reply@Yurisu DTMF_HandleRequest(); } #endif } } } if (interrupts.cssTailFound) g_CxCSS_TAIL_Found = true; if (interrupts.cdcssLost) { g_CDCSS_Lost = true; gCDCSSCodeType = BK4819_GetCDCSSCodeType(); } if (interrupts.cdcssFound) g_CDCSS_Lost = false; if (interrupts.ctcssLost) g_CTCSS_Lost = true; if (interrupts.ctcssFound) g_CTCSS_Lost = false; #ifdef ENABLE_VOX if (interrupts.voxLost) { g_VOX_Lost = true; gVoxPauseCountdown = 10; if (gEeprom.VOX_SWITCH) { if (gCurrentFunction == FUNCTION_POWER_SAVE && !gRxIdleMode) { gPowerSave_10ms = power_save2_10ms; gPowerSaveCountdownExpired = 0; } if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF && (gScheduleDualWatch || gDualWatchCountdown_10ms < dual_watch_count_after_vox_10ms)) { gDualWatchCountdown_10ms = dual_watch_count_after_vox_10ms; gScheduleDualWatch = false; // let the user see DW is not active gDualWatchActive = false; gUpdateStatus = true; } } } if (interrupts.voxFound) { g_VOX_Lost = false; gVoxPauseCountdown = 0; } #endif if (interrupts.sqlLost) { g_SquelchLost = true; BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, true); } if (interrupts.sqlFound) { g_SquelchLost = false; BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, false); } #ifdef ENABLE_AIRCOPY if (interrupts.fskFifoAlmostFull && gScreenToDisplay == DISPLAY_AIRCOPY && gAircopyState == AIRCOPY_TRANSFER && gAirCopyIsSendMode == 0) { for (unsigned int i = 0; i < 4; i++) { g_FSK_Buffer[gFSKWriteIndex++] = BK4819_ReadRegister(BK4819_REG_5F); } AIRCOPY_StorePacket(); } #endif //ok #if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200) solve_sign(interrupts.__raw); #endif } } void APP_EndTransmission(bool inmediately) { // back to RX mode RADIO_SendEndOfTransmission(); if (gMonitor) { //turn the monitor back on gFlagReconfigureVfos = true; } if (inmediately || gEeprom.REPEATER_TAIL_TONE_ELIMINATION == 0) { FUNCTION_Select(FUNCTION_FOREGROUND);//OK } else { gRTTECountdown_10ms = gEeprom.REPEATER_TAIL_TONE_ELIMINATION * 10; } } #ifdef ENABLE_VOX static void HandleVox(void) { #ifdef ENABLE_DTMF_CALLING if (gSetting_KILLED) return; #endif if (gVoxResumeCountdown == 0) { if (gVoxPauseCountdown) return; } else { g_VOX_Lost = false; gVoxPauseCountdown = 0; } #ifdef ENABLE_FMRADIO if (gFmRadioMode) return; #endif if (gCurrentFunction == FUNCTION_RECEIVE || gCurrentFunction == FUNCTION_MONITOR) return; if (gScanStateDir != SCAN_OFF) return; if (gVOX_NoiseDetected) { if (g_VOX_Lost) gVoxStopCountdown_10ms = vox_stop_count_down_10ms; else if (gVoxStopCountdown_10ms == 0) gVOX_NoiseDetected = false; if (gCurrentFunction == FUNCTION_TRANSMIT && !gPttIsPressed && !gVOX_NoiseDetected) { APP_EndTransmission(false); gUpdateStatus = true; gUpdateDisplay = true; } return; } if (g_VOX_Lost) { gVOX_NoiseDetected = true; if (gCurrentFunction == FUNCTION_POWER_SAVE) FUNCTION_Select(FUNCTION_FOREGROUND); //OK if (gCurrentFunction != FUNCTION_TRANSMIT && !SerialConfigInProgress()) { #ifdef ENABLE_DTMF_CALLING gDTMF_ReplyState = DTMF_REPLY_NONE; #endif RADIO_PrepareTX(); gUpdateDisplay = true; } } } #endif void APP_Update(void) { #ifdef ENABLE_VOICE if (gFlagPlayQueuedVoice) { AUDIO_PlayQueuedVoice(); gFlagPlayQueuedVoice = false; } #endif if (gCurrentFunction == FUNCTION_TRANSMIT && (gTxTimeoutReached || SerialConfigInProgress())) { // transmitter timed out or must de-key gTxTimeoutReached = false; APP_EndTransmission(true); #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_880HZ_60MS_TRIPLE_BEEP); #endif RADIO_SetVfoState(VFO_STATE_TIMEOUT); GUI_DisplayScreen(); } if (gReducedService) return; if (gCurrentFunction != FUNCTION_TRANSMIT) HandleFunction(); #ifdef ENABLE_FMRADIO // if (gFmRadioCountdown_500ms > 0) if (gFmRadioMode && gFmRadioCountdown_500ms > 0) // 1of11 return; #endif #ifdef ENABLE_VOICE if (!SCANNER_IsScanning() && gScanStateDir != SCAN_OFF && gScheduleScanListen && !gPttIsPressed && gVoiceWriteIndex == 0) #else if (!SCANNER_IsScanning() && gScanStateDir != SCAN_OFF && gScheduleScanListen && !gPttIsPressed) #endif { // scanning CHFRSCANNER_ContinueScanning(); } #ifdef ENABLE_NOAA #ifdef ENABLE_VOICE if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode && gScheduleNOAA && gVoiceWriteIndex == 0) #else if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode && gScheduleNOAA) #endif { NOAA_IncreaseChannel(); RADIO_SetupRegisters(false); gNOAA_Countdown_10ms = 7; // 70ms gScheduleNOAA = false; } #endif // toggle between the VFO's if dual watch is enabled if (!SCANNER_IsScanning() && gEeprom.DUAL_WATCH != DUAL_WATCH_OFF && gScheduleDualWatch && gScanStateDir == SCAN_OFF && !gPttIsPressed && gCurrentFunction != FUNCTION_POWER_SAVE #ifdef ENABLE_VOICE && gVoiceWriteIndex == 0 #endif #ifdef ENABLE_FMRADIO && !gFmRadioMode #endif #ifdef ENABLE_DTMF_CALLING && gDTMF_CallState == DTMF_CALL_STATE_NONE #endif ) { DualwatchAlternate(); // toggle between the two VFO's if (gRxVfoIsActive && gScreenToDisplay == DISPLAY_MAIN) { GUI_SelectNextDisplay(DISPLAY_MAIN); } gRxVfoIsActive = false; gScanPauseMode = false; gRxReceptionMode = RX_MODE_NONE; gScheduleDualWatch = false; } #ifdef ENABLE_FMRADIO if (gScheduleFM && gFM_ScanState != FM_SCAN_OFF && !FUNCTION_IsRx()) { // switch to FM radio mode FM_Play(); gScheduleFM = false; } #endif #ifdef ENABLE_VOX if (gEeprom.VOX_SWITCH) HandleVox(); #endif if (gSchedulePowerSave) { if (gPttIsPressed || gKeyBeingHeld || gEeprom.BATTERY_SAVE == 0 || gScanStateDir != SCAN_OFF || gCssBackgroundScan || gScreenToDisplay != DISPLAY_MAIN #ifdef ENABLE_FMRADIO || gFmRadioMode #endif #ifdef ENABLE_DTMF_CALLING || gDTMF_CallState != DTMF_CALL_STATE_NONE #endif #ifdef ENABLE_NOAA || (gIsNoaaMode && (IS_NOAA_CHANNEL(gEeprom.ScreenChannel[0]) || IS_NOAA_CHANNEL(gEeprom.ScreenChannel[1]))) #endif ) { gBatterySaveCountdown_10ms = battery_save_count_10ms; } else { FUNCTION_Select(FUNCTION_POWER_SAVE); } gSchedulePowerSave = false; } if (gPowerSaveCountdownExpired && gCurrentFunction == FUNCTION_POWER_SAVE #ifdef ENABLE_VOICE && gVoiceWriteIndex == 0 #endif ) { static bool goToSleep; // wake up, enable RX then go back to sleep if (gRxIdleMode) { BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable(); #ifdef ENABLE_VOX if (gEeprom.VOX_SWITCH) BK4819_EnableVox(gEeprom.VOX1_THRESHOLD, gEeprom.VOX0_THRESHOLD); #endif if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF && gScanStateDir == SCAN_OFF && !gCssBackgroundScan) { // dual watch mode, toggle between the two VFO's DualwatchAlternate(); goToSleep = false; } FUNCTION_Init(); gPowerSave_10ms = power_save1_10ms; // come back here in a bit gRxIdleMode = false; // RX is awake } else if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF || gScanStateDir != SCAN_OFF || gCssBackgroundScan || goToSleep) { // dual watch mode off or scanning or rssi update request // go back to sleep gPowerSave_10ms = gEeprom.BATTERY_SAVE * 10; gRxIdleMode = true; goToSleep = false; BK4819_DisableVox(); BK4819_Sleep(); BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, false); // Authentic device checked removed } else { // toggle between the two VFO's DualwatchAlternate(); gPowerSave_10ms = power_save1_10ms; goToSleep = true; } gPowerSaveCountdownExpired = false; } } // called every 10ms static void CheckKeys(void) { #ifdef ENABLE_DTMF_CALLING if(gSetting_KILLED){ return; } #endif #ifdef ENABLE_AIRCOPY if (gScreenToDisplay == DISPLAY_AIRCOPY && gAircopyState != AIRCOPY_READY){ return; } #endif // -------------------- PTT ------------------------ if (gPttIsPressed) { if (GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT) || SerialConfigInProgress()) { // PTT released or serial comms config in progress if (++gPttDebounceCounter >= 3 || SerialConfigInProgress()) // 30ms { // stop transmitting ProcessKey(KEY_PTT, false, false); gPttIsPressed = false; if (gKeyReading1 != KEY_INVALID) gPttWasReleased = true; } } else gPttDebounceCounter = 0; } else if (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT) && !SerialConfigInProgress()) { // PTT pressed if (++gPttDebounceCounter >= 3) // 30ms { // start transmitting boot_counter_10ms = 0; gPttDebounceCounter = 0; gPttIsPressed = true; ProcessKey(KEY_PTT, true, false); } } else gPttDebounceCounter = 0; // --------------------- OTHER KEYS ---------------------------- // scan the hardware keys KEY_Code_t Key = KEYBOARD_Poll(); if (Key != KEY_INVALID) // any key pressed boot_counter_10ms = 0; // cancel boot screen/beeps if any key pressed if (gKeyReading0 != Key) // new key pressed { if (gKeyReading0 != KEY_INVALID && Key != KEY_INVALID) ProcessKey(gKeyReading1, false, gKeyBeingHeld); // key pressed without releasing previous key gKeyReading0 = Key; gDebounceCounter = 0; return; } gDebounceCounter++; if (gDebounceCounter == key_debounce_10ms) // debounced new key pressed { if (Key == KEY_INVALID) //all non PTT keys released { if (gKeyReading1 != KEY_INVALID) // some button was pressed before { ProcessKey(gKeyReading1, false, gKeyBeingHeld); // process last button released event gKeyReading1 = KEY_INVALID; } } else // process new key pressed { gKeyReading1 = Key; ProcessKey(Key, true, false); } gKeyBeingHeld = false; return; } if (gDebounceCounter < key_repeat_delay_10ms || Key == KEY_INVALID) // the button is not held long enough for repeat yet, or not really pressed return; if (gDebounceCounter == key_repeat_delay_10ms) //initial key repeat with longer delay { if (Key != KEY_PTT) { gKeyBeingHeld = true; ProcessKey(Key, true, true); // key held event } } else //subsequent fast key repeats { if (Key == KEY_UP || Key == KEY_DOWN) // fast key repeats for up/down buttons { gKeyBeingHeld = true; if ((gDebounceCounter % key_repeat_10ms) == 0) ProcessKey(Key, true, true); // key held event } if (gDebounceCounter < 0xFFFF) return; gDebounceCounter = key_repeat_delay_10ms + 1; } } void APP_TimeSlice10ms(void) { gNextTimeslice = false; gFlashLightBlinkCounter++; #ifdef ENABLE_MESSENGER keyTickCounter++; #endif #ifdef ENABLE_BOOT_BEEPS if (boot_counter_10ms > 0 && (boot_counter_10ms % 25) == 0) { AUDIO_PlayBeep(BEEP_880HZ_40MS_OPTIONAL); } #endif #ifdef ENABLE_AM_FIX if (gRxVfo->Modulation == MODULATION_AM) { AM_fix_10ms(gEeprom.RX_VFO); } #endif #ifdef ENABLE_UART if (UART_IsCommandAvailable()) { __disable_irq(); UART_HandleCommand(); __enable_irq(); } #endif if (gReducedService) return; if (gCurrentFunction != FUNCTION_POWER_SAVE || !gRxIdleMode) CheckRadioInterrupts(); if (gCurrentFunction == FUNCTION_TRANSMIT) { // transmitting //#ifdef ENABLE_AUDIO_BAR if ((gFlashLightBlinkCounter % (150 / 10)) == 0) // once every 150ms UI_DisplayAudioBar(); //#endif } if (gUpdateDisplay) { gUpdateDisplay = false; GUI_DisplayScreen(); } if (gUpdateStatus) UI_DisplayStatus(); // Skipping authentic device checks #ifdef ENABLE_FMRADIO if (gFmRadioMode && gFmRadioCountdown_500ms > 0) // 1of11 return; #endif #ifdef ENABLE_FLASHLIGHT // FlashlightTimeSlice(); #endif #ifdef ENABLE_VOX if (gVoxResumeCountdown > 0) gVoxResumeCountdown--; if (gVoxPauseCountdown > 0) gVoxPauseCountdown--; #endif if (gCurrentFunction == FUNCTION_TRANSMIT) { #ifdef ENABLE_ALARM if (gAlarmState == ALARM_STATE_TXALARM || gAlarmState == ALARM_STATE_SITE_ALARM) { uint16_t Tone; gAlarmRunningCounter++; gAlarmToneCounter++; Tone = 500 + (gAlarmToneCounter * 25); if (Tone > 1500) { Tone = 500; gAlarmToneCounter = 0; } BK4819_SetScrambleFrequencyControlWord(Tone); if (gEeprom.ALARM_MODE == ALARM_MODE_TONE && gAlarmRunningCounter == 512) { gAlarmRunningCounter = 0; if (gAlarmState == ALARM_STATE_TXALARM) { gAlarmState = ALARM_STATE_SITE_ALARM; if(gEeprom.TAIL_TONE_ELIMINATION) RADIO_SendCssTail(); BK4819_SetupPowerAmplifier(0, 0); BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, false); BK4819_Enable_AfDac_DiscMode_TxDsp(); BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, false); GUI_DisplayScreen(); } else { gAlarmState = ALARM_STATE_TXALARM; GUI_DisplayScreen(); BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, true); RADIO_SetTxParameters(); BK4819_TransmitTone(true, 500); SYSTEM_DelayMs(2); AUDIO_AudioPathOn(); gEnableSpeaker = true; gAlarmToneCounter = 0; } } } #endif // repeater tail tone elimination if (gRTTECountdown_10ms > 0) { if (--gRTTECountdown_10ms == 0) { FUNCTION_Select(FUNCTION_FOREGROUND); //OK gUpdateStatus = true; gUpdateDisplay = true; } } } #ifdef ENABLE_FMRADIO if (gFmRadioMode && gFM_RestoreCountdown_10ms > 0) { if (--gFM_RestoreCountdown_10ms == 0) { // switch back to FM radio mode FM_Start(); GUI_SelectNextDisplay(DISPLAY_FM); } } #endif SCANNER_TimeSlice10ms(); #ifdef ENABLE_AIRCOPY if (gScreenToDisplay == DISPLAY_AIRCOPY && gAircopyState == AIRCOPY_TRANSFER && gAirCopyIsSendMode == 1) { if (!AIRCOPY_SendMessage()) { GUI_DisplayScreen(); } } #endif CheckKeys(); } void cancelUserInputModes(void) { if (gDTMF_InputMode || gDTMF_InputBox_Index > 0) { DTMF_clear_input_box(); gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; gRequestDisplayScreen = DISPLAY_MAIN; gUpdateDisplay = true; } if (gWasFKeyPressed || gKeyInputCountdown > 0 || gInputBoxIndex > 0) { gWasFKeyPressed = false; gInputBoxIndex = 0; gKeyInputCountdown = 0; gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; gUpdateStatus = true; gUpdateDisplay = true; } } // this is called once every 500ms void APP_TimeSlice500ms(void) { gNextTimeslice_500ms = false; bool exit_menu = false; #ifdef ENABLE_MESSENGER_NOTIFICATION if (gPlayMSGRing) { gPlayMSGRingCount = 5; gPlayMSGRing = false; } if (gPlayMSGRingCount > 0) { AUDIO_PlayBeep(BEEP_880HZ_200MS); gPlayMSGRingCount--; } #endif #ifdef ENABLE_MESSENGER if (hasNewMessage > 0) { if (hasNewMessage == 1) { hasNewMessage = 2; } else if (hasNewMessage == 2) { hasNewMessage = 1; } } #endif // Skipped authentic device check if (gKeypadLocked > 0) if (--gKeypadLocked == 0) gUpdateDisplay = true; if (gKeyInputCountdown > 0) { if (--gKeyInputCountdown == 0) { cancelUserInputModes(); if (gBeepToPlay != BEEP_NONE) { #ifdef ENABLE_WARNING AUDIO_PlayBeep(gBeepToPlay); #endif gBeepToPlay = BEEP_NONE; } } } if (gDTMF_RX_live_timeout > 0) { #ifdef ENABLE_RSSI_BAR if (center_line == CENTER_LINE_DTMF_DEC || center_line == CENTER_LINE_NONE) // wait till the center line is free for us to use before timing out #endif { if (--gDTMF_RX_live_timeout == 0) { if (gDTMF_RX_live[0] != 0) { memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live)); gUpdateDisplay = true; } } } } if (gMenuCountdown > 0) if (--gMenuCountdown == 0) exit_menu = (gScreenToDisplay == DISPLAY_MENU); // exit menu mode #ifdef ENABLE_DTMF_CALLING if (gDTMF_RX_timeout > 0) if (--gDTMF_RX_timeout == 0) DTMF_clear_RX(); #endif #ifdef ENABLE_MDC1200 if (mdc1200_rx_ready_tick_500ms > 0) { if (--mdc1200_rx_ready_tick_500ms == 0) { if (center_line == CENTER_LINE_MDC1200) center_line = CENTER_LINE_NONE; gUpdateDisplay = true; } } #endif #ifdef ENABLE_FMRADIO if (gFmRadioCountdown_500ms > 0) { gFmRadioCountdown_500ms--; if (gFmRadioMode) // 1of11 return; } #endif if (gBacklightCountdown_500ms > 0 && !gAskToSave && !gCssBackgroundScan // don't turn off backlight if user is in backlight menu option && !(gScreenToDisplay == DISPLAY_MENU && (UI_MENU_GetCurrentMenuId() == MENU_ABR || UI_MENU_GetCurrentMenuId() == MENU_ABR_MAX)) && --gBacklightCountdown_500ms == 0 && gEeprom.BACKLIGHT_TIME < (ARRAY_SIZE(gSubMenu_BACKLIGHT) - 1) ) { BACKLIGHT_TurnOff(); } if (gReducedService) { BOARD_ADC_GetBatteryInfo(&gBatteryCurrentVoltage, &gBatteryCurrent); if (gBatteryCurrent > 500 || gBatteryCalibration[3] < gBatteryCurrentVoltage) { #ifdef ENABLE_OVERLAY overlay_FLASH_RebootToBootloader(); #else NVIC_SystemReset(); #endif } return; } gBatteryCheckCounter++; // Skipped authentic device check if (gCurrentFunction != FUNCTION_TRANSMIT) { if ((gBatteryCheckCounter & 1) == 0) { BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[gBatteryVoltageIndex++], &gBatteryCurrent); if (gBatteryVoltageIndex > 3) gBatteryVoltageIndex = 0; BATTERY_GetReadings(true); } } // regular display updates (once every 2 sec) - if need be if ((gBatteryCheckCounter & 3) == 0) { if (gChargingWithTypeC) gUpdateStatus = true; #ifdef ENABLE_SHOW_CHARGE_LEVEL if (gChargingWithTypeC) gUpdateDisplay = true; #endif } if (!gCssBackgroundScan && gScanStateDir == SCAN_OFF && !SCANNER_IsScanning() #ifdef ENABLE_FMRADIO && (gFM_ScanState == FM_SCAN_OFF || gAskToSave) #endif #ifdef ENABLE_AIRCOPY && gScreenToDisplay != DISPLAY_AIRCOPY #endif ) { if (exit_menu) { gMenuCountdown = 0; if (gEeprom.BACKLIGHT_TIME == 0) { BACKLIGHT_TurnOff(); } #ifdef ENABLE_WARNING if (gInputBoxIndex > 0 || gDTMF_InputMode) { AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); } #endif /* if (SCANNER_IsScanning()) { BK4819_StopScan(); RADIO_ConfigureChannel(0, VFO_CONFIGURE_RELOAD); RADIO_ConfigureChannel(1, VFO_CONFIGURE_RELOAD); RADIO_SetupRegisters(true); } */ DTMF_clear_input_box(); gWasFKeyPressed = false; gInputBoxIndex = 0; gAskToSave = false; gAskToDelete = false; gUpdateStatus = true; gUpdateDisplay = true; GUI_DisplayType_t disp = DISPLAY_INVALID; #ifdef ENABLE_FMRADIO if (gFmRadioMode && ! FUNCTION_IsRx()) { disp = DISPLAY_FM; } #endif if (disp == DISPLAY_INVALID #ifdef ENABLE_NO_CODE_SCAN_TIMEOUT && !SCANNER_IsScanning() #endif ) { disp = DISPLAY_MAIN; } if (disp != DISPLAY_INVALID) { GUI_SelectNextDisplay(disp); } } } if (!gPttIsPressed && gVFOStateResumeCountdown_500ms > 0 && --gVFOStateResumeCountdown_500ms == 0) { RADIO_SetVfoState(VFO_STATE_NORMAL); #ifdef ENABLE_FMRADIO if (gFmRadioMode && !FUNCTION_IsRx()) { // switch back to FM radio mode FM_Start(); GUI_SelectNextDisplay(DISPLAY_FM); } #endif } BATTERY_TimeSlice500ms(); SCANNER_TimeSlice500ms(); UI_MAIN_TimeSlice500ms(); #ifdef ENABLE_DTMF_CALLING if (gCurrentFunction != FUNCTION_TRANSMIT) { if (gDTMF_DecodeRingCountdown_500ms > 0) { // make "ring-ring" sound gDTMF_DecodeRingCountdown_500ms--; #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_880HZ_200MS); #endif } } else { gDTMF_DecodeRingCountdown_500ms = 0; } if (gDTMF_CallState != DTMF_CALL_STATE_NONE && gCurrentFunction != FUNCTION_TRANSMIT && gCurrentFunction != FUNCTION_RECEIVE && gDTMF_auto_reset_time_500ms > 0 && --gDTMF_auto_reset_time_500ms == 0) { gUpdateDisplay = true; if (gDTMF_CallState == DTMF_CALL_STATE_RECEIVED && gEeprom.DTMF_auto_reset_time >= DTMF_HOLD_MAX) { gDTMF_CallState = DTMF_CALL_STATE_RECEIVED_STAY; // keep message on-screen till a key is pressed } else { gDTMF_CallState = DTMF_CALL_STATE_NONE; } } if (gDTMF_IsTx && gDTMF_TxStopCountdown_500ms > 0 && --gDTMF_TxStopCountdown_500ms == 0) { gDTMF_IsTx = false; gUpdateDisplay = true; } #endif #ifdef ENABLE_TURN if(turn_flag && !gWasFKeyPressed){ turn_flag = 0; } #endif } #if defined(ENABLE_ALARM) || defined(ENABLE_TX1750) static void ALARM_Off(void) { AUDIO_AudioPathOff(); gEnableSpeaker = false; if (gAlarmState == ALARM_STATE_TXALARM || gAlarmState == ALARM_STATE_TX1750) { APP_EndTransmission(false); //OK } gAlarmState = ALARM_STATE_OFF; #ifdef ENABLE_VOX gVoxResumeCountdown = 80; #endif SYSTEM_DelayMs(5); RADIO_SetupRegisters(true); if (gScreenToDisplay != DISPLAY_MENU) // 1of11 .. don't close the menu gRequestDisplayScreen = DISPLAY_MAIN; } #endif static void ProcessKey(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (Key == KEY_EXIT && !BACKLIGHT_IsOn() && gEeprom.BACKLIGHT_TIME > 0) { // just turn the light on for now so the user can see what's what BACKLIGHT_TurnOn(); gBeepToPlay = BEEP_NONE; return; } if (gCurrentFunction == FUNCTION_POWER_SAVE) FUNCTION_Select(FUNCTION_FOREGROUND); //OK gBatterySaveCountdown_10ms = battery_save_count_10ms; if (!bKeyPressed) // key released { if (flagSaveVfo) { SETTINGS_SaveVfoIndices(); flagSaveVfo = false; } if (flagSaveSettings) { SETTINGS_SaveSettings(); flagSaveSettings = false; } #ifdef ENABLE_FMRADIO if (gFlagSaveFM) { SETTINGS_SaveFM(); gFlagSaveFM = false; } #endif if (flagSaveChannel) { SETTINGS_SaveChannel(gTxVfo->CHANNEL_SAVE, gEeprom.TX_VFO, gTxVfo, flagSaveChannel); flagSaveChannel = false; if (!SCANNER_IsScanning() && gVfoConfigureMode == VFO_CONFIGURE_NONE) // gVfoConfigureMode is so as we don't wipe out previously setting this variable elsewhere gVfoConfigureMode = VFO_CONFIGURE; } #ifdef ENABLE_SIDEFUNCTIONS_SEND if (gFlagStopTX) { gFlagStopTX = false; APP_EndTransmission(true); RADIO_SetupRegisters(true); GUI_SelectNextDisplay(DISPLAY_MAIN); gEeprom.TX_VFO = gFlagLastVfo; gFlagReconfigureVfos = true; gUpdateDisplay = true; return; } #endif } else // key pressed or held { // const uint8_t s = BACKLIGHT_ON_TR_TXRX; const int m = UI_MENU_GetCurrentMenuId(); if ( //not when PTT and the backlight shouldn't turn on on TX /* !(Key == KEY_PTT && s != BACKLIGHT_ON_TR_TX && s != BACKLIGHT_ON_TR_TXRX) // not in the backlight menu &&*/ !(gScreenToDisplay == DISPLAY_MENU && (m == MENU_ABR || m == MENU_ABR_MAX)) ) { BACKLIGHT_TurnOn(); } if (Key == KEY_EXIT && bKeyHeld) { // exit key held pressed // clear the live DTMF decoder if (gDTMF_RX_live[0] != 0) { memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live)); gDTMF_RX_live_timeout = 0; gUpdateDisplay = true; } // cancel user input cancelUserInputModes(); if (gMonitor) ACTION_Monitor(); //turn off the monitor #ifdef ENABLE_SCAN_RANGES gScanRangeStart = 0; #endif } if (gScreenToDisplay == DISPLAY_MENU) // 1of11 gMenuCountdown = menu_timeout_500ms; #ifdef ENABLE_DTMF_CALLING if (gDTMF_DecodeRingCountdown_500ms > 0) { // cancel the ringing gDTMF_DecodeRingCountdown_500ms = 0; #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL); #endif if (Key != KEY_PTT) { gPttWasReleased = true; return; } } #endif } bool lowBatPopup = gLowBattery && !gLowBatteryConfirmed && gScreenToDisplay == DISPLAY_MAIN; if ((gEeprom.KEY_LOCK || lowBatPopup) && gCurrentFunction != FUNCTION_TRANSMIT && Key != KEY_PTT) { // keyboard is locked or low battery popup // close low battery popup if (Key == KEY_EXIT && bKeyPressed && lowBatPopup) { gLowBatteryConfirmed = true; gUpdateDisplay = true; #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL); #endif return; } if (Key == KEY_F) { // function/key-lock key if (!bKeyPressed) return; if (!bKeyHeld) { // keypad is locked, tell the user #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); #endif gKeypadLocked = 4; // 2 seconds gUpdateDisplay = true; return; } } // KEY_MENU has a special treatment here, because we want to pass hold event to ACTION_Handle // but we don't want it to complain when initial press happens // we want to react on realese instead // KEY_MENU has a special treatment here, because we want to pass hold event to ACTION_Handle // but we don't want it to complain when initial press happens // we want to react on realese instead #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS else if (Key != KEY_SIDE1 && Key != KEY_SIDE2 && // pass side buttons !(Key == KEY_MENU && bKeyHeld && gEeprom.KEY_M_LONG_PRESS_ACTION == ACTION_OPT_KEYLOCK)) // pass KEY_MENU held #else else if (Key != KEY_SIDE1 && Key != KEY_SIDE2) // pass KEY_MENU held #endif { // keypad is locked, tell the user #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); #endif gKeypadLocked = 4; // 2 seconds gUpdateDisplay = true; return; } } if (Key <= KEY_9 || Key == KEY_F) { if (gScanStateDir != SCAN_OFF || gCssBackgroundScan) { // FREQ/CTCSS/DCS scanning #ifdef ENABLE_WARNING if (bKeyPressed && !bKeyHeld) AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); #endif return; } } bool bFlag = false; if (Key == KEY_PTT) { // if(gEeprom.KEY_LOCK) // { // gKeypadLocked = 4; // 2 seconds // return; // } if (gPttWasPressed) { bFlag = bKeyHeld; if (!bKeyPressed) { bFlag = true; gPttWasPressed = false; } } } else if (gPttWasReleased) { if (bKeyHeld) bFlag = true; if (!bKeyPressed) { bFlag = true; gPttWasReleased = false; } } if (gWasFKeyPressed && (Key == KEY_PTT || Key == KEY_EXIT || Key == KEY_SIDE1 || Key == KEY_SIDE2)) { // cancel the F-key gWasFKeyPressed = false; gUpdateStatus = true; } if (bFlag) { goto Skip; } if (gCurrentFunction == FUNCTION_TRANSMIT) { #if defined(ENABLE_ALARM) || defined(ENABLE_TX1750) if (gAlarmState == ALARM_STATE_OFF) #endif { char Code; if (Key == KEY_PTT) { GENERIC_Key_PTT(bKeyPressed); goto Skip; } if (Key == KEY_SIDE2) { // transmit 1750Hz tone Code = 0xFE; } else { Code = DTMF_GetCharacter(Key - KEY_0); if (Code == 0xFF) goto Skip; // transmit DTMF keys } if (!bKeyPressed || bKeyHeld) { if (!bKeyPressed) { AUDIO_AudioPathOff(); gEnableSpeaker = false; BK4819_ExitDTMF_TX(false); if (gCurrentVfo->SCRAMBLING_TYPE == 0 || !gSetting_ScrambleEnable) BK4819_DisableScramble(); else BK4819_EnableScramble(gCurrentVfo->SCRAMBLING_TYPE - 1); } } else { if (gEeprom.DTMF_SIDE_TONE) { // user will here the DTMF tones in speaker AUDIO_AudioPathOn(); gEnableSpeaker = true; } BK4819_DisableScramble(); if (Code == 0xFE) BK4819_TransmitTone(gEeprom.DTMF_SIDE_TONE, 1750); else BK4819_PlayDTMFEx(gEeprom.DTMF_SIDE_TONE, Code); } } #if defined(ENABLE_ALARM) || defined(ENABLE_TX1750) else if ((!bKeyHeld && bKeyPressed) || (gAlarmState == ALARM_STATE_TX1750 && bKeyHeld && !bKeyPressed)) { ALARM_Off(); if (Key == KEY_PTT) gPttWasPressed = true; else if (!bKeyHeld) gPttWasReleased = true; } #endif } else if (Key != KEY_SIDE1 && Key != KEY_SIDE2 && gScreenToDisplay != DISPLAY_INVALID) { ProcessKeysFunctions[gScreenToDisplay](Key, bKeyPressed, bKeyHeld); } else if (!SCANNER_IsScanning() #ifdef ENABLE_AIRCOPY && gScreenToDisplay != DISPLAY_AIRCOPY #endif ) { ACTION_Handle(Key, bKeyPressed, bKeyHeld); } else if (!bKeyHeld && bKeyPressed) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } Skip: if (gBeepToPlay != BEEP_NONE) { #ifdef ENABLE_WARNING AUDIO_PlayBeep(gBeepToPlay); #endif gBeepToPlay = BEEP_NONE; } if (gFlagAcceptSetting) { gMenuCountdown = menu_timeout_500ms; MENU_AcceptSetting(); gFlagRefreshSetting = true; gFlagAcceptSetting = false; } if (gRequestSaveSettings) { if (!bKeyHeld) SETTINGS_SaveSettings(); else flagSaveSettings = 1; gRequestSaveSettings = false; gUpdateStatus = true; } #ifdef ENABLE_FMRADIO if (gRequestSaveFM) { gRequestSaveFM = false; if (!bKeyHeld) SETTINGS_SaveFM(); else gFlagSaveFM = true; } #endif if (gRequestSaveVFO) { gRequestSaveVFO = false; if (!bKeyHeld) SETTINGS_SaveVfoIndices(); else flagSaveVfo = true; } if (gRequestSaveChannel > 0) { if (!bKeyHeld)// TODO: remove the gRequestSaveChannel, why use global variable for that?? { SETTINGS_SaveChannel(gTxVfo->CHANNEL_SAVE, gEeprom.TX_VFO, gTxVfo, gRequestSaveChannel); if (!SCANNER_IsScanning() && gVfoConfigureMode == VFO_CONFIGURE_NONE) // gVfoConfigureMode is so as we don't wipe out previously setting this variable elsewhere gVfoConfigureMode = VFO_CONFIGURE; } else {// this is probably so settings are not saved when up/down button is held and save is postponed to btn release flagSaveChannel = gRequestSaveChannel; if (gRequestDisplayScreen == DISPLAY_INVALID) gRequestDisplayScreen = DISPLAY_MAIN; } gRequestSaveChannel = 0; } if (gVfoConfigureMode != VFO_CONFIGURE_NONE) { if (gFlagResetVfos) { RADIO_ConfigureChannel(0, gVfoConfigureMode); RADIO_ConfigureChannel(1, gVfoConfigureMode); } else RADIO_ConfigureChannel(gEeprom.TX_VFO, gVfoConfigureMode); if (gRequestDisplayScreen == DISPLAY_INVALID) gRequestDisplayScreen = DISPLAY_MAIN; gFlagReconfigureVfos = true; gVfoConfigureMode = VFO_CONFIGURE_NONE; gFlagResetVfos = false; } if (gFlagReconfigureVfos) { RADIO_SelectVfos(); #ifdef ENABLE_NOAA RADIO_ConfigureNOAA(); #endif RADIO_SetupRegisters(true); #ifdef ENABLE_DTMF_CALLING gDTMF_auto_reset_time_500ms = 0; gDTMF_CallState = DTMF_CALL_STATE_NONE; gDTMF_TxStopCountdown_500ms = 0; gDTMF_IsTx = false; #endif gVFO_RSSI_bar_level[0] = 0; gVFO_RSSI_bar_level[1] = 0; gFlagReconfigureVfos = false; if (gMonitor) ACTION_Monitor(); // 1of11 } if (gFlagRefreshSetting) { gFlagRefreshSetting = false; gMenuCountdown = menu_timeout_500ms; MENU_ShowCurrentSetting(); } if (gFlagPrepareTX) { RADIO_PrepareTX(); gFlagPrepareTX = false; } #ifdef ENABLE_VOICE if (gAnotherVoiceID != VOICE_ID_INVALID) { if (gAnotherVoiceID < 76) AUDIO_SetVoiceID(0, gAnotherVoiceID); AUDIO_PlaySingleVoice(false); gAnotherVoiceID = VOICE_ID_INVALID; } #endif GUI_SelectNextDisplay(gRequestDisplayScreen); gRequestDisplayScreen = DISPLAY_INVALID; gUpdateDisplay = true; } ================================================ FILE: app/app.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_APP_H #define APP_APP_H #include #include "functions.h" #include "frequencies.h" #include "radio.h" #ifdef ENABLE_MESSENGER_NOTIFICATION extern bool gPlayMSGRing; #endif void APP_EndTransmission(bool inmediately); void APP_StartListening(FUNCTION_Type_t function); uint32_t APP_SetFreqByStepAndLimits(VFO_Info_t *pInfo, int8_t direction, uint32_t lower, uint32_t upper); uint32_t APP_SetFrequencyByStep(VFO_Info_t *pInfo, int8_t direction); void APP_Update(void); void APP_TimeSlice10ms(void); void APP_TimeSlice500ms(void); #endif ================================================ FILE: app/chFrScanner.c ================================================ #include "app/app.h" #include "app/chFrScanner.h" #include "functions.h" #include "misc.h" #include "settings.h" int8_t gScanStateDir; bool gScanKeepResult; bool gScanPauseMode; #ifdef ENABLE_SCAN_RANGES uint32_t gScanRangeStart; uint32_t gScanRangeStop; #endif typedef enum { SCAN_NEXT_CHAN_SCANLIST1 = 0, SCAN_NEXT_CHAN_SCANLIST2, SCAN_NEXT_CHAN_DUAL_WATCH, SCAN_NEXT_CHAN_MR, SCAN_NEXT_NUM } scan_next_chan_t; scan_next_chan_t currentScanList; uint32_t initialFrqOrChan; uint8_t initialCROSS_BAND_RX_TX; uint32_t lastFoundFrqOrChan; static void NextFreqChannel(void); static void NextMemChannel(void); void CHFRSCANNER_Start(const bool storeBackupSettings, const int8_t scan_direction) { if (storeBackupSettings) { initialCROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX; gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF; gScanKeepResult = false; } RADIO_SelectVfos(); gNextMrChannel = gRxVfo->CHANNEL_SAVE; currentScanList = SCAN_NEXT_CHAN_SCANLIST1; gScanStateDir = scan_direction; if (IS_MR_CHANNEL(gNextMrChannel)) { // channel mode if (storeBackupSettings) { initialFrqOrChan = gRxVfo->CHANNEL_SAVE; lastFoundFrqOrChan = initialFrqOrChan; } NextMemChannel(); } else { // frequency mode if (storeBackupSettings) { initialFrqOrChan = gRxVfo->freq_config_RX.Frequency; lastFoundFrqOrChan = initialFrqOrChan; } NextFreqChannel(); } gScanPauseDelayIn_10ms = scan_pause_delay_in_2_10ms; gScheduleScanListen = false; gRxReceptionMode = RX_MODE_NONE; gScanPauseMode = false; } void CHFRSCANNER_ContinueScanning(void) { if (IS_FREQ_CHANNEL(gNextMrChannel)) { if (gCurrentFunction == FUNCTION_INCOMING) APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE); else NextFreqChannel(); // switch to next frequency } else { if (gCurrentCodeType == CODE_TYPE_OFF && gCurrentFunction == FUNCTION_INCOMING) APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE); else NextMemChannel(); // switch to next channel } gScanPauseMode = false; gRxReceptionMode = RX_MODE_NONE; gScheduleScanListen = false; } void CHFRSCANNER_Found(void) { switch (gEeprom.SCAN_RESUME_MODE) { case SCAN_RESUME_TO: if (!gScanPauseMode) { gScanPauseDelayIn_10ms = scan_pause_delay_in_1_10ms; gScheduleScanListen = false; gScanPauseMode = true; } break; case SCAN_RESUME_CO: case SCAN_RESUME_SE: gScanPauseDelayIn_10ms = 0; gScheduleScanListen = false; break; } if (IS_MR_CHANNEL(gRxVfo->CHANNEL_SAVE)) { //memory scan lastFoundFrqOrChan = gRxVfo->CHANNEL_SAVE; } else { // frequency scan lastFoundFrqOrChan = gRxVfo->freq_config_RX.Frequency; } gScanKeepResult = true; } void CHFRSCANNER_Stop(void) { if (initialCROSS_BAND_RX_TX != CROSS_BAND_OFF) { gEeprom.CROSS_BAND_RX_TX = initialCROSS_BAND_RX_TX; initialCROSS_BAND_RX_TX = CROSS_BAND_OFF; } gScanStateDir = SCAN_OFF; const uint32_t chFr = gScanKeepResult ? lastFoundFrqOrChan : initialFrqOrChan; const bool channelChanged = chFr != initialFrqOrChan; if (IS_MR_CHANNEL(gNextMrChannel)) { gEeprom.MrChannel[gEeprom.RX_VFO] = chFr; gEeprom.ScreenChannel[gEeprom.RX_VFO] = chFr; RADIO_ConfigureChannel(gEeprom.RX_VFO, VFO_CONFIGURE_RELOAD); if (channelChanged) { SETTINGS_SaveVfoIndices(); gUpdateStatus = true; } } else { gRxVfo->freq_config_RX.Frequency = chFr; RADIO_ApplyOffset(gRxVfo); RADIO_ConfigureSquelchAndOutputPower(gRxVfo); if (channelChanged) { SETTINGS_SaveChannel(gRxVfo->CHANNEL_SAVE, gEeprom.RX_VFO, gRxVfo, 1); } } RADIO_SetupRegisters(true); gUpdateDisplay = true; } static void NextFreqChannel(void) { #ifdef ENABLE_SCAN_RANGES if(gScanRangeStart) { gRxVfo->freq_config_RX.Frequency = APP_SetFreqByStepAndLimits(gRxVfo, gScanStateDir, gScanRangeStart, gScanRangeStop); } else #endif gRxVfo->freq_config_RX.Frequency = APP_SetFrequencyByStep(gRxVfo, gScanStateDir); RADIO_ApplyOffset(gRxVfo); RADIO_ConfigureSquelchAndOutputPower(gRxVfo); RADIO_SetupRegisters(true); #ifdef ENABLE_FASTER_CHANNEL_SCAN gScanPauseDelayIn_10ms = 9; // 90ms #else gScanPauseDelayIn_10ms = scan_pause_delay_in_6_10ms; #endif gUpdateDisplay = true; } static void NextMemChannel(void) { static unsigned int prev_mr_chan = 0; const bool enabled = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCAN_LIST_ENABLED[gEeprom.SCAN_LIST_DEFAULT] : true; const int chan1 = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCANLIST_PRIORITY_CH1[gEeprom.SCAN_LIST_DEFAULT] : -1; const int chan2 = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCANLIST_PRIORITY_CH2[gEeprom.SCAN_LIST_DEFAULT] : -1; const unsigned int prev_chan = gNextMrChannel; unsigned int chan = 0; if (enabled) { switch (currentScanList) { case SCAN_NEXT_CHAN_SCANLIST1: prev_mr_chan = gNextMrChannel; if (chan1 >= 0) { if (RADIO_CheckValidChannel(chan1, false, 0)) { currentScanList = SCAN_NEXT_CHAN_SCANLIST1; gNextMrChannel = chan1; break; } } [[fallthrough]]; case SCAN_NEXT_CHAN_SCANLIST2: if (chan2 >= 0) { if (RADIO_CheckValidChannel(chan2, false, 0)) { currentScanList = SCAN_NEXT_CHAN_SCANLIST2; gNextMrChannel = chan2; break; } } [[fallthrough]]; // this bit doesn't yet work if the other VFO is a frequency case SCAN_NEXT_CHAN_DUAL_WATCH: // dual watch is enabled - include the other VFO in the scan // if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) // { // chan = (gEeprom.RX_VFO + 1) & 1u; // chan = gEeprom.ScreenChannel[chan]; // if (IS_MR_CHANNEL(chan)) // { // currentScanList = SCAN_NEXT_CHAN_DUAL_WATCH; // gNextMrChannel = chan; // break; // } // } default: case SCAN_NEXT_CHAN_MR: currentScanList = SCAN_NEXT_CHAN_MR; gNextMrChannel = prev_mr_chan; chan = 0xff; break; } } if (!enabled || chan == 0xff) { chan = RADIO_FindNextChannel(gNextMrChannel + gScanStateDir, gScanStateDir, (gEeprom.SCAN_LIST_DEFAULT < 2) ? true : false, gEeprom.SCAN_LIST_DEFAULT); if (chan == 0xFF) { // no valid channel found chan = MR_CHANNEL_FIRST; } gNextMrChannel = chan; } if (gNextMrChannel != prev_chan) { gEeprom.MrChannel[gEeprom.RX_VFO] = gNextMrChannel; gEeprom.ScreenChannel[gEeprom.RX_VFO] = gNextMrChannel; RADIO_ConfigureChannel(gEeprom.RX_VFO, VFO_CONFIGURE_RELOAD); RADIO_SetupRegisters(true); gUpdateDisplay = true; } #ifdef ENABLE_FASTER_CHANNEL_SCAN gScanPauseDelayIn_10ms = 9; // 90ms .. <= ~60ms it misses signals (squelch response and/or PLL lock time) ? #else gScanPauseDelayIn_10ms = scan_pause_delay_in_3_10ms; #endif if (enabled) if (++currentScanList >= SCAN_NEXT_NUM) currentScanList = SCAN_NEXT_CHAN_SCANLIST1; // back round we go } ================================================ FILE: app/chFrScanner.h ================================================ #ifndef APP_CHFRSCANNER_H #define APP_CHFRSCANNER_H #include #include // scan direction, if not equal SCAN_OFF indicates // that we are in a process of scanning channels/frequencies extern int8_t gScanStateDir; extern bool gScanKeepResult; extern bool gScanPauseMode; #ifdef ENABLE_SCAN_RANGES extern uint32_t gScanRangeStart; extern uint32_t gScanRangeStop; #endif void CHFRSCANNER_Found(void); void CHFRSCANNER_Stop(void); void CHFRSCANNER_Start(const bool storeBackupSettings, const int8_t scan_direction); void CHFRSCANNER_ContinueScanning(void); #endif ================================================ FILE: app/common.c ================================================ #include "app/chFrScanner.h" #include "audio.h" #include "functions.h" #include "misc.h" #include "settings.h" #include "ui/ui.h" void COMMON_KeypadLockToggle() { if (gScreenToDisplay != DISPLAY_MENU && gCurrentFunction != FUNCTION_TRANSMIT) { // toggle the keyboad lock #ifdef ENABLE_VOICE gAnotherVoiceID = gEeprom.KEY_LOCK ? VOICE_ID_UNLOCK : VOICE_ID_LOCK; #endif gEeprom.KEY_LOCK = !gEeprom.KEY_LOCK; //按键锁定禁止发射 取消 // RADIO_SetVfoState(VFO_STATE_NORMAL); gRequestSaveSettings = true; } } void COMMON_SwitchVFOs() { #ifdef ENABLE_SCAN_RANGES gScanRangeStart = 0; #endif gEeprom.TX_VFO ^= 1; if (gEeprom.CROSS_BAND_RX_TX != CROSS_BAND_OFF) gEeprom.CROSS_BAND_RX_TX = gEeprom.TX_VFO + 1; if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) gEeprom.DUAL_WATCH = gEeprom.TX_VFO + 1; gRequestSaveSettings = 1; gFlagReconfigureVfos = true; gScheduleDualWatch = true; gRequestDisplayScreen = DISPLAY_MAIN; } void COMMON_SwitchVFOMode() { #ifdef ENABLE_NOAA if (gEeprom.VFO_OPEN && !IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) #else if (gEeprom.VFO_OPEN) #endif { if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) { // swap to frequency mode gEeprom.ScreenChannel[gEeprom.TX_VFO] = gEeprom.FreqChannel[gEeprom.TX_VFO]; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_FREQUENCY_MODE; #endif gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; return; } uint8_t Channel = RADIO_FindNextChannel(gEeprom.MrChannel[gEeprom.TX_VFO], 1, false, 0); if (Channel != 0xFF) { // swap to channel mode gEeprom.ScreenChannel[gEeprom.TX_VFO] = Channel; #ifdef ENABLE_VOICE AUDIO_SetVoiceID(0, VOICE_ID_CHANNEL_MODE); AUDIO_SetDigitVoice(1, Channel + 1); gAnotherVoiceID = (VOICE_ID_t)0xFE; #endif gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; return; } } } ================================================ FILE: app/common.h ================================================ #ifndef APP_COMMON_H #define APP_COMMON_H #include "functions.h" #include "settings.h" #include "ui/ui.h" void COMMON_KeypadLockToggle(); void COMMON_SwitchVFOs(); void COMMON_SwitchVFOMode(); #endif ================================================ FILE: app/doppler.c ================================================ #include "doppler.h" #include "string.h" #include "driver/eeprom.h" #include "bsp/dp32g030/rtc.h" #include "ui/helper.h" struct satellite_t satellite; struct satellite_d satellite_data; bool DOPPLER_FLAG = true; //0x02BA0~0x2BA9 10B,卫星名称,首字符在前,最多9个英文，最后一个为'\0' // // //0x2BAA 1B,开始过境时间的年份的十位个位，0~99，如:2024即为24 //0x2BAB 1B,开始过境时间的月份，1~12 //0x2BAC 1B,开始过境时间的日期，1~31 //0x2BAD 1B,开始过境时间的时，0~23 //0x2BAE 1B,开始过境时间的分，0~59 //0x2BAF 1B,开始过境时间的秒，0~59 // //0x2BB0 1B,离境时间的年份的十位个位，0~99，如:2077即为77 //0x2BB1 1B,离境时间的月份，1~12 //0x2BB2 1B,离境时间的日期，1~31 //0x2BB3 1B,离境时间的时，0~23 //0x2BB4 1B,离境时间的分，0~59 //0x2BB5 1B,离境时间的秒，0~59 // //0x2BB6~0x2BB7 2B，总的过境时间（秒），高位在前，低位在后 // //0x2BB8~0x2BB9 2B，手台的发射亚音 //0x2BBA~0x2BBB 2B，手台的接收亚音 #include void uint16_to_uint8_array(uint16_t value, uint8_t array[2]) { array[0] = value & 0xFF; // 获取低8位 array[1] = (value >> 8) & 0xFF; // 获取高8位 } void INIT_DOPPLER_DATA() { memset(&satellite, 0, sizeof(satellite)); EEPROM_ReadBuffer(0x02BA0, &satellite, sizeof(satellite)); if (satellite.name[9] != 0 || !(satellite.name[0] >= 32 && satellite.name[0] <= 126) ) { DOPPLER_FLAG = 0; return; } for (int i = strlen(satellite.name); i < 10; i++) if (satellite.name[i] != 0) { DOPPLER_FLAG = 0; return; } } // 判断是否是闰年 int is_leap_year(int year) { return (year % 4 == 0 && year % 100 != 0) || (year % 400 == 0); } // 计算某个月的天数 int days_in_month(int year, int month) { int days[] = {31, 28 + is_leap_year(year), 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; return days[month - 1]; } int32_t UNIX_TIME(uint8_t time2[6]) { // 2000 年 1 月 1 日的年、月、日、时、分、秒 int32_t seconds = 0; // 计算年份之间的秒数差 for (int year = 0; year < time2[0]; year++) { seconds += (is_leap_year(year) + 365) * 24 * 3600; } // 计算当年之内的秒数差 for (int month = 1; month < time2[1]; month++) { seconds += days_in_month(time2[0], month) * 24 * 3600; } // 计算当月之内的秒数差 seconds += (time2[2] - 1) * 24 * 3600; seconds += time2[3] * 3600; seconds += time2[4] * 60; seconds += time2[5]; return seconds; } void READ_DATA(int32_t time_diff, int32_t time_diff1) { int32_t n = -time_diff; if (time_diff <= 0 && time_diff1 >= 0)//正在过境 { if ((n & 0x01) != 0)return; n = n >> 1; } else n = 0; EEPROM_ReadBuffer(0x1E200 + (n << 3), &satellite_data, sizeof(satellite_data)); // AZ（-180~180，两位浮点，度）2B,EI（-180~180，两位浮点，度）2B,上行频率/10（正整数hz）4B、下行频率/10(正整数hz)4B、距离（两位浮点，km）3B： // 第1B~2B:AZ的数字部分，只有正，低位在前高位在后， // 低1~8位为AZ整数部分，8bit（0~180） // 低9~16位为AZ浮点部分，8bit（0~99） // 如：-179.85，那么为10110011（179）01010101（85） // // 第3B~4B:EI的数字部分,与AZ同理 // 第5B:AZ,EI的符号，低位在前高位在后，前4bit为AZ符号，后4bit为EI符号 // 4bit为0XA时表示正，0XC表示负 // 第6B~9B:上行频率/10,只有正,如:438.5MHZ，那么为438,500,00，都是低位在前，高位在后 // 第10B~13B:下行频率/10,只有正,如:144.5MHZ，那么为144,500,00，都是低位在前，高位在后 // 第14B~15B:距离整数部分，只有正，如：6748.85，那么为6748 // 第16B:距离浮点部分*100,只有正，如：6748.85，那么为85 } ================================================ FILE: app/doppler.h ================================================ #ifndef _DOPPLER_ #define _DOPPLER_ #include "stdint.h" #include "stdbool.h" struct satellite_t { char name[10]; uint8_t start_time[6]; uint8_t end_time[6]; uint16_t sum_time; uint16_t SEND_CTCSS; uint16_t RECV_CTCSS; uint32_t START_TIME_UNIX; }; struct satellite_d { uint32_t UPLink; uint32_t DownLink; }; void READ_DATA(int32_t time_diff, int32_t time_diff1); void INIT_DOPPLER_DATA(); int32_t UNIX_TIME(uint8_t time2[6]); extern struct satellite_d satellite_data; extern bool DOPPLER_FLAG; extern struct satellite_t satellite; #endif ================================================ FILE: app/dtmf.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifdef ENABLE_DOPPLER #include "app/doppler.h" #endif #include "app/messenger.h" #include #include // NULL #include "app/chFrScanner.h" #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/scanner.h" #include "bsp/dp32g030/gpio.h" #include "audio.h" #include "driver/bk4819.h" #include "driver/eeprom.h" #include "driver/gpio.h" #include "driver/system.h" #include "dtmf.h" #include "external/printf/printf.h" #include "misc.h" #include "settings.h" #include "ui/ui.h" char gDTMF_String[15]; char gDTMF_InputBox[15]; uint8_t gDTMF_InputBox_Index = 0; bool gDTMF_InputMode = false; uint8_t gDTMF_PreviousIndex = 0; char gDTMF_RX_live[20]; uint8_t gDTMF_RX_live_timeout = 0; #ifdef ENABLE_DTMF_CALLING char gDTMF_RX[17]; uint8_t gDTMF_RX_index = 0; uint8_t gDTMF_RX_timeout = 0; bool gDTMF_RX_pending = false; bool gIsDtmfContactValid; char gDTMF_ID[4]; char gDTMF_Caller[4]; char gDTMF_Callee[4]; DTMF_State_t gDTMF_State; uint8_t gDTMF_DecodeRingCountdown_500ms; uint8_t gDTMF_chosen_contact; uint8_t gDTMF_auto_reset_time_500ms; DTMF_CallState_t gDTMF_CallState; DTMF_CallMode_t gDTMF_CallMode; bool gDTMF_IsTx; uint8_t gDTMF_TxStopCountdown_500ms; bool gDTMF_IsGroupCall; #endif DTMF_ReplyState_t gDTMF_ReplyState; #ifdef ENABLE_DTMF_CALLING void DTMF_clear_RX(void) { gDTMF_RX_timeout = 0; gDTMF_RX_index = 0; gDTMF_RX_pending = false; memset(gDTMF_RX, 0, sizeof(gDTMF_RX)); } #endif bool DTMF_ValidateCodes(char *pCode, const unsigned int size) { unsigned int i; if (pCode[0] == 0xFF || pCode[0] == 0) return false; for (i = 0; i < size; i++) { if (pCode[i] == 0xFF || pCode[i] == 0) { pCode[i] = 0; break; } if ((pCode[i] < '0' || pCode[i] > '9') && (pCode[i] < 'A' || pCode[i] > 'D') && pCode[i] != '*' && pCode[i] != '#') return false; } return true; } #ifdef ENABLE_DTMF_CALLING bool DTMF_GetContact(const int Index, char *pContact) { if (Index < 0 || Index >= MAX_DTMF_CONTACTS || pContact == NULL) { return false; } EEPROM_ReadBuffer(0x1C00 + (Index * 16), pContact, 16); #if ENABLE_CHINESE_FULL == 4 return pContact[0] != 0xff; #else // check whether the first character is printable or not return (pContact[0] >= ' ' && pContact[0] < 127); #endif } bool DTMF_FindContact(const char *pContact, char *pResult) { pResult[0] = 0; for (unsigned int i = 0; i < MAX_DTMF_CONTACTS; i++) { char Contact[16]; if (!DTMF_GetContact(i, Contact)) { return false; } if (memcmp(pContact, Contact + 8, 3) == 0) { memcpy(pResult, Contact, 8); pResult[8] = 0; return true; } } return false; } #endif char DTMF_GetCharacter(const unsigned int code) { switch (code) { case KEY_0: return '0'; case KEY_1: return '1'; case KEY_2: return '2'; case KEY_3: return '3'; case KEY_4: return '4'; case KEY_5: return '5'; case KEY_6: return '6'; case KEY_7: return '7'; case KEY_8: return '8'; case KEY_9: return '9'; case KEY_MENU: return 'A'; case KEY_UP: return 'B'; case KEY_DOWN: return 'C'; case KEY_EXIT: return 'D'; case KEY_STAR: return '*'; case KEY_F: return '#'; default: return 0xff; } } #ifdef ENABLE_DTMF_CALLING static bool CompareMessage(const char *pMsg, const char *pTemplate, const unsigned int size, const bool bCheckGroup) { unsigned int i; for (i = 0; i < size; i++) { if (pMsg[i] != pTemplate[i]) { if (!bCheckGroup || pMsg[i] != gEeprom.DTMF_GROUP_CALL_CODE) return false; gDTMF_IsGroupCall = true; } } return true; } DTMF_CallMode_t DTMF_CheckGroupCall(const char *pMsg, const unsigned int size) { unsigned int i; for (i = 0; i < size; i++) if (pMsg[i] == gEeprom.DTMF_GROUP_CALL_CODE) break; return (i < size) ? DTMF_CALL_MODE_GROUP : DTMF_CALL_MODE_NOT_GROUP; } #endif void DTMF_clear_input_box(void) { memset(gDTMF_InputBox, 0, sizeof(gDTMF_InputBox)); gDTMF_InputBox_Index = 0; gDTMF_InputMode = false; gPttWasReleased = false; } void DTMF_Append(const char code) { if (gDTMF_InputBox_Index == 0) { memset(gDTMF_InputBox, '-', sizeof(gDTMF_InputBox) - 1); gDTMF_InputBox[sizeof(gDTMF_InputBox) - 1] = 0; } if (gDTMF_InputBox_Index < (sizeof(gDTMF_InputBox) - 1)) gDTMF_InputBox[gDTMF_InputBox_Index++] = code; } #ifdef ENABLE_DTMF_CALLING void DTMF_HandleRequest(void) { // proccess the RX'ed DTMF characters char String[21]; unsigned int Offset; if (!gDTMF_RX_pending) return; // nothing new received if (gScanStateDir != SCAN_OFF || gCssBackgroundScan) { // we're busy scanning DTMF_clear_RX(); return; } if (!gRxVfo->DTMF_DECODING_ENABLE && !gSetting_KILLED) { // D-DCD is disabled or we're alive DTMF_clear_RX(); return; } gDTMF_RX_pending = false; if (gDTMF_RX_index >= 9) { // look for the KILL code sprintf(String, "%s%c%s", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, gEeprom.KILL_CODE); Offset = gDTMF_RX_index - strlen(String); if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true)) { // bugger if (gEeprom.PERMIT_REMOTE_KILL) { gSetting_KILLED = true; // oooerr ! DTMF_clear_RX(); SETTINGS_SaveSettings(); gDTMF_ReplyState = DTMF_REPLY_AB; #ifdef ENABLE_FMRADIO if (gFmRadioMode) { FM_TurnOff(); GUI_SelectNextDisplay(DISPLAY_MAIN); } #endif } else { gDTMF_ReplyState = DTMF_REPLY_NONE; } gDTMF_CallState = DTMF_CALL_STATE_NONE; gUpdateDisplay = true; gUpdateStatus = true; return; } } if (gDTMF_RX_index >= 9) { // look for the REVIVE code sprintf(String, "%s%c%s", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, gEeprom.REVIVE_CODE); Offset = gDTMF_RX_index - strlen(String); if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true)) { // shit, we're back ! gSetting_KILLED = false; DTMF_clear_RX(); SETTINGS_SaveSettings(); gDTMF_ReplyState = DTMF_REPLY_AB; gDTMF_CallState = DTMF_CALL_STATE_NONE; gUpdateDisplay = true; gUpdateStatus = true; return; } } if (gDTMF_RX_index >= 2) { // look for ACK reply char *pPrintStr = "AB"; Offset = gDTMF_RX_index - strlen(pPrintStr); if (CompareMessage(gDTMF_RX + Offset, pPrintStr, strlen(pPrintStr), true)) { // ends with "AB" if (gDTMF_ReplyState != DTMF_REPLY_NONE) // 1of11 // if (gDTMF_CallState != DTMF_CALL_STATE_NONE) // 1of11 // if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT) // 1of11 { gDTMF_State = DTMF_STATE_TX_SUCC; DTMF_clear_RX(); gUpdateDisplay = true; return; } } } if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT && gDTMF_CallMode == DTMF_CALL_MODE_NOT_GROUP && gDTMF_RX_index >= 9) { // waiting for a reply sprintf(String, "%s%c%s", gDTMF_String, gEeprom.DTMF_SEPARATE_CODE, "AAAAA"); Offset = gDTMF_RX_index - strlen(String); if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), false)) { // we got a response gDTMF_State = DTMF_STATE_CALL_OUT_RSP; DTMF_clear_RX(); gUpdateDisplay = true; } } if (gSetting_KILLED || gDTMF_CallState != DTMF_CALL_STATE_NONE) { // we've been killed or expecting a reply return; } if (gDTMF_RX_index >= 7) { // see if we're being called gDTMF_IsGroupCall = false; sprintf(String, "%s%c", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE); Offset = gDTMF_RX_index - strlen(String) - 3; if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true)) { // it's for us ! gDTMF_CallState = DTMF_CALL_STATE_RECEIVED; memset(gDTMF_Callee, 0, sizeof(gDTMF_Callee)); memset(gDTMF_Caller, 0, sizeof(gDTMF_Caller)); memcpy(gDTMF_Callee, gDTMF_RX + Offset + 0, 3); memcpy(gDTMF_Caller, gDTMF_RX + Offset + 4, 3); DTMF_clear_RX(); gUpdateDisplay = true; switch (gEeprom.DTMF_DECODE_RESPONSE) { case DTMF_DEC_RESPONSE_BOTH: gDTMF_DecodeRingCountdown_500ms = DTMF_decode_ring_countdown_500ms; [[fallthrough]]; case DTMF_DEC_RESPONSE_REPLY: gDTMF_ReplyState = DTMF_REPLY_AAAAA; break; case DTMF_DEC_RESPONSE_RING: gDTMF_DecodeRingCountdown_500ms = DTMF_decode_ring_countdown_500ms; break; default: case DTMF_DEC_RESPONSE_NONE: gDTMF_DecodeRingCountdown_500ms = 0; gDTMF_ReplyState = DTMF_REPLY_NONE; break; } if (gDTMF_IsGroupCall) gDTMF_ReplyState = DTMF_REPLY_NONE; } } } #endif bool DTMF_Reply() { uint16_t Delay; #ifdef ENABLE_DTMF_CALLING char String[23]; #endif const char *pString = NULL; switch (gDTMF_ReplyState) { case DTMF_REPLY_ANI: #ifdef ENABLE_DTMF_CALLING if (gDTMF_CallMode != DTMF_CALL_MODE_DTMF) { // append our ID code onto the end of the DTMF code to send sprintf(String, "%s%c%s", gDTMF_String, gEeprom.DTMF_SEPARATE_CODE, gEeprom.ANI_DTMF_ID); pString = String; } else #endif { pString = gDTMF_String; } break; #ifdef ENABLE_DTMF_CALLING case DTMF_REPLY_AB: pString = "AB"; break; case DTMF_REPLY_AAAAA: sprintf(String, "%s%c%s", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, "AAAAA"); pString = String; break; #endif default: case DTMF_REPLY_NONE: if ( #ifdef ENABLE_DTMF_CALLING gDTMF_CallState != DTMF_CALL_STATE_NONE || #endif gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_APOLLO || gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_OFF || gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_TX_DOWN) { gDTMF_ReplyState = DTMF_REPLY_NONE; return false; } // send TX-UP DTMF pString = gEeprom.DTMF_UP_CODE; break; } gDTMF_ReplyState = DTMF_REPLY_NONE; if (pString == NULL) return false; Delay = (gEeprom.DTMF_PRELOAD_TIME < 200) ? 200 : gEeprom.DTMF_PRELOAD_TIME; if (gEeprom.DTMF_SIDE_TONE) { // the user will also hear the transmitted tones AUDIO_AudioPathOn(); gEnableSpeaker = true; } SYSTEM_DelayMs(Delay); BK4819_EnterDTMF_TX(gEeprom.DTMF_SIDE_TONE); BK4819_PlayDTMFString( pString, 1, gEeprom.DTMF_FIRST_CODE_PERSIST_TIME, gEeprom.DTMF_HASH_CODE_PERSIST_TIME, gEeprom.DTMF_CODE_PERSIST_TIME, gEeprom.DTMF_CODE_INTERVAL_TIME); AUDIO_AudioPathOff(); gEnableSpeaker = false; BK4819_ExitDTMF_TX(false); return true; } void DTMF_SendEndOfTransmission(void) { #ifdef ENABLE_MESSENGER if(!stop_mdc_flag) { #endif if (gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_APOLLO) { BK4819_PlaySingleTone(2475, 250, 28, gEeprom.DTMF_SIDE_TONE); } else if ((gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_TX_DOWN || gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_BOTH) #ifdef ENABLE_DTMF_CALLING && gDTMF_CallState == DTMF_CALL_STATE_NONE #endif ) { // end-of-tx if (gEeprom.DTMF_SIDE_TONE) { AUDIO_AudioPathOn(); gEnableSpeaker = true; SYSTEM_DelayMs(60); } BK4819_EnterDTMF_TX(gEeprom.DTMF_SIDE_TONE); BK4819_PlayDTMFString( gEeprom.DTMF_DOWN_CODE, 0, gEeprom.DTMF_FIRST_CODE_PERSIST_TIME, gEeprom.DTMF_HASH_CODE_PERSIST_TIME, gEeprom.DTMF_CODE_PERSIST_TIME, gEeprom.DTMF_CODE_INTERVAL_TIME); AUDIO_AudioPathOff(); gEnableSpeaker = false; } #ifdef ENABLE_MESSENGER } #endif BK4819_ExitDTMF_TX(true); } ================================================ FILE: app/dtmf.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DTMF_H #define DTMF_H #include #include #define MAX_DTMF_CONTACTS 16 enum DTMF_State_t { DTMF_STATE_0 = 0, DTMF_STATE_TX_SUCC, DTMF_STATE_CALL_OUT_RSP }; typedef enum DTMF_State_t DTMF_State_t; enum DTMF_CallState_t { DTMF_CALL_STATE_NONE = 0, DTMF_CALL_STATE_CALL_OUT, DTMF_CALL_STATE_RECEIVED, DTMF_CALL_STATE_RECEIVED_STAY }; enum DTMF_DecodeResponse_t { DTMF_DEC_RESPONSE_NONE = 0, DTMF_DEC_RESPONSE_RING, DTMF_DEC_RESPONSE_REPLY, DTMF_DEC_RESPONSE_BOTH }; typedef enum DTMF_CallState_t DTMF_CallState_t; enum DTMF_ReplyState_t { DTMF_REPLY_NONE = 0, DTMF_REPLY_ANI, DTMF_REPLY_AB, DTMF_REPLY_AAAAA }; typedef enum DTMF_ReplyState_t DTMF_ReplyState_t; enum DTMF_CallMode_t { DTMF_CALL_MODE_NOT_GROUP = 0, DTMF_CALL_MODE_GROUP, DTMF_CALL_MODE_DTMF }; enum { // seconds DTMF_HOLD_MIN = 5, DTMF_HOLD_MAX = 60 }; typedef enum DTMF_CallMode_t DTMF_CallMode_t; extern char gDTMF_String[15]; extern char gDTMF_InputBox[15]; extern uint8_t gDTMF_InputBox_Index; extern bool gDTMF_InputMode; extern uint8_t gDTMF_PreviousIndex; extern char gDTMF_RX_live[20]; extern uint8_t gDTMF_RX_live_timeout; #ifdef ENABLE_DTMF_CALLING extern char gDTMF_RX[17]; extern uint8_t gDTMF_RX_index; extern uint8_t gDTMF_RX_timeout; extern bool gDTMF_RX_pending; extern bool gIsDtmfContactValid; extern char gDTMF_ID[4]; extern char gDTMF_Caller[4]; extern char gDTMF_Callee[4]; extern DTMF_State_t gDTMF_State; extern uint8_t gDTMF_DecodeRingCountdown_500ms; extern uint8_t gDTMF_chosen_contact; extern uint8_t gDTMF_auto_reset_time_500ms; extern DTMF_CallState_t gDTMF_CallState; extern DTMF_CallMode_t gDTMF_CallMode; extern bool gDTMF_IsTx; extern uint8_t gDTMF_TxStopCountdown_500ms; #endif extern DTMF_ReplyState_t gDTMF_ReplyState; bool DTMF_ValidateCodes(char *pCode, const unsigned int size); char DTMF_GetCharacter(const unsigned int code); void DTMF_clear_input_box(void); void DTMF_Append(const char vode); bool DTMF_Reply(); void DTMF_SendEndOfTransmission(void); #ifdef ENABLE_DTMF_CALLING void DTMF_clear_RX(void); DTMF_CallMode_t DTMF_CheckGroupCall(const char *pDTMF, const unsigned int size); bool DTMF_GetContact(const int Index, char *pContact); bool DTMF_FindContact(const char *pContact, char *pResult); void DTMF_HandleRequest(void); #endif #endif ================================================ FILE: app/flashlight.c ================================================ #ifdef ENABLE_FLASHLIGHT #include "driver/gpio.h" #include "bsp/dp32g030/gpio.h" #include "flashlight.h" enum FlashlightMode_t gFlashLightState; void FlashlightTimeSlice() { if (gFlashLightState == FLASHLIGHT_BLINK && (gFlashLightBlinkCounter & 15u) == 0) { GPIO_FlipBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); return; } if (gFlashLightState == FLASHLIGHT_SOS) { const uint16_t u = 15; static uint8_t c; static uint16_t next; if (gFlashLightBlinkCounter - next > 7 * u) { c = 0; next = gFlashLightBlinkCounter + 1; return; } if (gFlashLightBlinkCounter == next) { if (c==0) { GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); } else { GPIO_FlipBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); } if (c >= 18) { next = gFlashLightBlinkCounter + 7 * u; c = 0; } else if(c==7 || c==9 || c==11) { next = gFlashLightBlinkCounter + 3 * u; } else { next = gFlashLightBlinkCounter + u; } c++; } } } void ACTION_FlashLight(void) { if(gFlashLightState) { GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); gFlashLightState=0; }else { GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); gFlashLightState=1; } // switch (gFlashLightState) { // case FLASHLIGHT_OFF: // gFlashLightState++; // GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); // break; // case FLASHLIGHT_ON: //// case FLASHLIGHT_BLINK: // gFlashLightState++; // break; //// case FLASHLIGHT_SOS: // default: // gFlashLightState = 0; // GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT); // } } #endif ================================================ FILE: app/flashlight.h ================================================ #ifndef APP_FLASHLIGHT_H #define APP_FLASHLIGHT_H #ifdef ENABLE_FLASHLIGHT #include enum FlashlightMode_t { FLASHLIGHT_OFF = 0, FLASHLIGHT_ON, FLASHLIGHT_BLINK, FLASHLIGHT_SOS }; extern enum FlashlightMode_t gFlashLightState; extern volatile uint16_t gFlashLightBlinkCounter; void FlashlightTimeSlice(void); void ACTION_FlashLight(void); #endif #endif ================================================ FILE: app/fm.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifdef ENABLE_FMRADIO #include #include "app/action.h" #include "app/fm.h" #include "app/generic.h" #include "audio.h" #include "bsp/dp32g030/gpio.h" #include "driver/bk1080.h" #include "driver/eeprom.h" #include "driver/gpio.h" #include "functions.h" #include "misc.h" #include "settings.h" #include "ui/inputbox.h" #include "ui/ui.h" #ifndef ARRAY_SIZE #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) #endif uint16_t gFM_Channels[20]; bool gFmRadioMode; uint8_t gFmRadioCountdown_500ms; volatile uint16_t gFmPlayCountdown_10ms; volatile int8_t gFM_ScanState; bool gFM_AutoScan; uint8_t gFM_ChannelPosition; bool gFM_FoundFrequency; bool gFM_AutoScan; uint16_t gFM_RestoreCountdown_10ms; const uint8_t BUTTON_STATE_PRESSED = 1 << 0; const uint8_t BUTTON_STATE_HELD = 1 << 1; const uint8_t BUTTON_EVENT_PRESSED = BUTTON_STATE_PRESSED; const uint8_t BUTTON_EVENT_HELD = BUTTON_STATE_PRESSED | BUTTON_STATE_HELD; const uint8_t BUTTON_EVENT_SHORT = 0; const uint8_t BUTTON_EVENT_LONG = BUTTON_STATE_HELD; static void Key_FUNC(KEY_Code_t Key, uint8_t state); bool FM_CheckValidChannel(uint8_t Channel) { return (Channel < ARRAY_SIZE(gFM_Channels) && (gFM_Channels[Channel] >= 640 && gFM_Channels[Channel] < 1080)); } uint8_t FM_FindNextChannel(uint8_t Channel, uint8_t Direction) { unsigned int i; for (i = 0; i < ARRAY_SIZE(gFM_Channels); i++) { if (Channel == 0xFF) Channel = ARRAY_SIZE(gFM_Channels) - 1; else if (Channel >= ARRAY_SIZE(gFM_Channels)) Channel = 0; if (FM_CheckValidChannel(Channel)) return Channel; Channel += Direction; } return 0xFF; } int FM_ConfigureChannelState(void) { gEeprom.FM_FrequencyPlaying = gEeprom.FM_SelectedFrequency; if (gEeprom.FM_IsMrMode) { const uint8_t Channel = FM_FindNextChannel(gEeprom.FM_SelectedChannel, FM_CHANNEL_UP); if (Channel == 0xFF) { gEeprom.FM_IsMrMode = false; return -1; } gEeprom.FM_SelectedChannel = Channel; gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel]; } return 0; } void FM_TurnOff(void) { gFmRadioMode = false; gFM_ScanState = FM_SCAN_OFF; gFM_RestoreCountdown_10ms = 0; AUDIO_AudioPathOff(); gEnableSpeaker = false; BK1080_Init(0, false); gUpdateStatus = true; } void FM_EraseChannels(void) { unsigned int i; uint8_t Template[8]; memset(Template, 0xFF, sizeof(Template)); for (i = 0; i < 5; i++) EEPROM_WriteBuffer(0x0E40 + (i * 8), Template,8); memset(gFM_Channels, 0xFF, sizeof(gFM_Channels)); } void FM_Tune(uint16_t Frequency, int8_t Step, bool bFlag) { AUDIO_AudioPathOff(); gEnableSpeaker = false; gFmPlayCountdown_10ms = (gFM_ScanState == FM_SCAN_OFF) ? fm_play_countdown_noscan_10ms : fm_play_countdown_scan_10ms; gScheduleFM = false; gFM_FoundFrequency = false; gAskToSave = false; gAskToDelete = false; gEeprom.FM_FrequencyPlaying = Frequency; if (!bFlag) { Frequency += Step; if (Frequency < gEeprom.FM_LowerLimit) Frequency = gEeprom.FM_UpperLimit; else if (Frequency > gEeprom.FM_UpperLimit) Frequency = gEeprom.FM_LowerLimit; gEeprom.FM_FrequencyPlaying = Frequency; } gFM_ScanState = Step; BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); } void FM_PlayAndUpdate(void) { gFM_ScanState = FM_SCAN_OFF; if (gFM_AutoScan) { gEeprom.FM_IsMrMode = true; gEeprom.FM_SelectedChannel = 0; } FM_ConfigureChannelState(); BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); SETTINGS_SaveFM(); gFmPlayCountdown_10ms = 0; gScheduleFM = false; gAskToSave = false; AUDIO_AudioPathOn(); gEnableSpeaker = true; } int FM_CheckFrequencyLock(uint16_t Frequency, uint16_t LowerLimit) { int ret = -1; const uint16_t Test2 = BK1080_ReadRegister(BK1080_REG_07); // This is supposed to be a signed value, but above function is unsigned const uint16_t Deviation = BK1080_REG_07_GET_FREQD(Test2); if (BK1080_REG_07_GET_SNR(Test2) <= 2){ goto Bail; } const uint16_t Status = BK1080_ReadRegister(BK1080_REG_10); if ((Status & BK1080_REG_10_MASK_AFCRL) != BK1080_REG_10_AFCRL_NOT_RAILED || BK1080_REG_10_GET_RSSI(Status) < 10) { goto Bail; } //if (Deviation > -281 && Deviation < 280) if (Deviation >= 280 && Deviation <= 3815) { goto Bail; } // not BLE(less than or equal) if (Frequency > LowerLimit && (Frequency - BK1080_BaseFrequency) == 1) { if (BK1080_FrequencyDeviation & 0x800 || (BK1080_FrequencyDeviation < 20)) goto Bail; } // not BLT(less than) if (Frequency >= LowerLimit && (BK1080_BaseFrequency - Frequency) == 1) { if ((BK1080_FrequencyDeviation & 0x800) == 0 || (BK1080_FrequencyDeviation > 4075)) goto Bail; } ret = 0; Bail: BK1080_FrequencyDeviation = Deviation; BK1080_BaseFrequency = Frequency; return ret; } static void Key_DIGITS(KEY_Code_t Key, uint8_t state) { enum { STATE_FREQ_MODE, STATE_MR_MODE, STATE_SAVE }; if (state == BUTTON_EVENT_SHORT && !gWasFKeyPressed) { uint8_t State; if (gAskToDelete) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (gAskToSave) { State = STATE_SAVE; } else { if (gFM_ScanState != FM_SCAN_OFF) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } State = gEeprom.FM_IsMrMode ? STATE_MR_MODE : STATE_FREQ_MODE; } INPUTBOX_Append(Key); gRequestDisplayScreen = DISPLAY_FM; if (State == STATE_FREQ_MODE) { if (gInputBoxIndex == 1) { if (gInputBox[0] > 1) { gInputBox[1] = gInputBox[0]; gInputBox[0] = 0; gInputBoxIndex = 2; } } else if (gInputBoxIndex > 3) { uint32_t Frequency; gInputBoxIndex = 0; Frequency = StrToUL(INPUTBOX_GetAscii()); if (Frequency < gEeprom.FM_LowerLimit || gEeprom.FM_UpperLimit < Frequency) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; gRequestDisplayScreen = DISPLAY_FM; return; } gEeprom.FM_SelectedFrequency = (uint16_t)Frequency; #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gEeprom.FM_FrequencyPlaying = gEeprom.FM_SelectedFrequency; BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); gRequestSaveFM = true; return; } } else if (gInputBoxIndex == 2) { uint8_t Channel; gInputBoxIndex = 0; Channel = ((gInputBox[0] * 10) + gInputBox[1]) - 1; if (State == STATE_MR_MODE) { if (FM_CheckValidChannel(Channel)) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gEeprom.FM_SelectedChannel = Channel; gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel]; BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); gRequestSaveFM = true; return; } } else if (Channel < 20) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gRequestDisplayScreen = DISPLAY_FM; gInputBoxIndex = 0; gFM_ChannelPosition = Channel; return; } gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif } else Key_FUNC(Key, state); } static void Key_FUNC(KEY_Code_t Key, uint8_t state) { if (state == BUTTON_EVENT_SHORT || state == BUTTON_EVENT_HELD) { bool autoScan = gWasFKeyPressed || (state == BUTTON_EVENT_HELD); gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; gWasFKeyPressed = false; gUpdateStatus = true; gRequestDisplayScreen = DISPLAY_FM; switch (Key) { case KEY_0: ACTION_FM(); break; case KEY_3: gEeprom.FM_IsMrMode = !gEeprom.FM_IsMrMode; if (!FM_ConfigureChannelState()) { BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); gRequestSaveFM = true; } else gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; case KEY_STAR: ACTION_Scan(autoScan); break; default: gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; } } } static void Key_EXIT(uint8_t state) { if (state != BUTTON_EVENT_SHORT) return; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; if (gFM_ScanState == FM_SCAN_OFF) { if (gInputBoxIndex == 0) { if (!gAskToSave && !gAskToDelete) { ACTION_FM(); return; } gAskToSave = false; gAskToDelete = false; } else { gInputBox[--gInputBoxIndex] = 10; if (gInputBoxIndex) { if (gInputBoxIndex != 1) { gRequestDisplayScreen = DISPLAY_FM; return; } if (gInputBox[0] != 0) { gRequestDisplayScreen = DISPLAY_FM; return; } } gInputBoxIndex = 0; } #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif } else { FM_PlayAndUpdate(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif } gRequestDisplayScreen = DISPLAY_FM; } static void Key_MENU(uint8_t state) { if (state != BUTTON_EVENT_SHORT) return; gRequestDisplayScreen = DISPLAY_FM; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; if (gFM_ScanState == FM_SCAN_OFF) { if (!gEeprom.FM_IsMrMode) { if (gAskToSave) { gFM_Channels[gFM_ChannelPosition] = gEeprom.FM_FrequencyPlaying; gRequestSaveFM = true; } gAskToSave = !gAskToSave; } else { if (gAskToDelete) { gFM_Channels[gEeprom.FM_SelectedChannel] = 0xFFFF; FM_ConfigureChannelState(); BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); gRequestSaveFM = true; } gAskToDelete = !gAskToDelete; } } else { if (gFM_AutoScan || !gFM_FoundFrequency) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; gInputBoxIndex = 0; return; } if (gAskToSave) { gFM_Channels[gFM_ChannelPosition] = gEeprom.FM_FrequencyPlaying; gRequestSaveFM = true; } gAskToSave = !gAskToSave; } } static void Key_UP_DOWN(uint8_t state, int8_t Step) { if (state == BUTTON_EVENT_PRESSED) { if (gInputBoxIndex) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; } else if (gInputBoxIndex || state!=BUTTON_EVENT_HELD) { return; } if (gAskToSave) { gRequestDisplayScreen = DISPLAY_FM; gFM_ChannelPosition = NUMBER_AddWithWraparound(gFM_ChannelPosition, Step, 0, 19); return; } if (gFM_ScanState != FM_SCAN_OFF) { if (gFM_AutoScan) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } FM_Tune(gEeprom.FM_FrequencyPlaying, Step, false); gRequestDisplayScreen = DISPLAY_FM; return; } if (gEeprom.FM_IsMrMode) { const uint8_t Channel = FM_FindNextChannel(gEeprom.FM_SelectedChannel + Step, Step); if (Channel == 0xFF || gEeprom.FM_SelectedChannel == Channel) goto Bail; gEeprom.FM_SelectedChannel = Channel; gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel]; } else { uint16_t Frequency = gEeprom.FM_SelectedFrequency + Step; if (Frequency < gEeprom.FM_LowerLimit) Frequency = gEeprom.FM_UpperLimit; else if (Frequency > gEeprom.FM_UpperLimit) Frequency = gEeprom.FM_LowerLimit; gEeprom.FM_FrequencyPlaying = Frequency; gEeprom.FM_SelectedFrequency = gEeprom.FM_FrequencyPlaying; } gRequestSaveFM = true; Bail: BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying); gRequestDisplayScreen = DISPLAY_FM; } void FM_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { uint8_t state = bKeyPressed + 2 * bKeyHeld; switch (Key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: Key_DIGITS(Key, state); break; case KEY_STAR: Key_FUNC(Key, state); break; case KEY_MENU: Key_MENU(state); break; case KEY_UP: Key_UP_DOWN(state, 1); break; case KEY_DOWN: Key_UP_DOWN(state, -1); break;; case KEY_EXIT: Key_EXIT(state); break; case KEY_F: GENERIC_Key_F(bKeyPressed, bKeyHeld); break; case KEY_PTT: GENERIC_Key_PTT(bKeyPressed); break; default: if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; } } void FM_Play(void) { if (!FM_CheckFrequencyLock(gEeprom.FM_FrequencyPlaying, gEeprom.FM_LowerLimit)) { if (!gFM_AutoScan) { gFmPlayCountdown_10ms = 0; gFM_FoundFrequency = true; if (!gEeprom.FM_IsMrMode) gEeprom.FM_SelectedFrequency = gEeprom.FM_FrequencyPlaying; AUDIO_AudioPathOn(); gEnableSpeaker = true; GUI_SelectNextDisplay(DISPLAY_FM); return; } if (gFM_ChannelPosition < 20) gFM_Channels[gFM_ChannelPosition++] = gEeprom.FM_FrequencyPlaying; if (gFM_ChannelPosition >= 20) { FM_PlayAndUpdate(); GUI_SelectNextDisplay(DISPLAY_FM); return; } } if (gFM_AutoScan && gEeprom.FM_FrequencyPlaying >= gEeprom.FM_UpperLimit) FM_PlayAndUpdate(); else FM_Tune(gEeprom.FM_FrequencyPlaying, gFM_ScanState, false); GUI_SelectNextDisplay(DISPLAY_FM); } void FM_Start(void) { gDualWatchActive = false; gFmRadioMode = true; gFM_ScanState = FM_SCAN_OFF; gFM_RestoreCountdown_10ms = 0; BK1080_Init(gEeprom.FM_FrequencyPlaying, true); AUDIO_AudioPathOn(); gEnableSpeaker = true; gUpdateStatus = true; } #endif ================================================ FILE: app/fm.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_FM_H #define APP_FM_H #ifdef ENABLE_FMRADIO #include "driver/keyboard.h" #define FM_CHANNEL_UP 0x01 #define FM_CHANNEL_DOWN 0xFF enum { FM_SCAN_OFF = 0U, }; extern bool FM_EXIT_FLAG; extern uint16_t gFM_Channels[20]; extern bool gFmRadioMode; extern uint8_t gFmRadioCountdown_500ms; extern volatile uint16_t gFmPlayCountdown_10ms; extern volatile int8_t gFM_ScanState; extern uint8_t gFM_ChannelPosition; // Doubts about whether this should be signed or not extern uint16_t gFM_FrequencyDeviation; extern bool gFM_FoundFrequency; extern bool gFM_AutoScan; extern uint16_t gFM_RestoreCountdown_10ms; bool FM_CheckValidChannel(uint8_t Channel); uint8_t FM_FindNextChannel(uint8_t Channel, uint8_t Direction); int FM_ConfigureChannelState(void); void FM_TurnOff(void); void FM_EraseChannels(void); void FM_Tune(uint16_t Frequency, int8_t Step, bool bFlag); void FM_PlayAndUpdate(void); int FM_CheckFrequencyLock(uint16_t Frequency, uint16_t LowerLimit); void FM_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); void FM_Play(void); void FM_Start(void); #endif #endif ================================================ FILE: app/generic.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "app/app.h" #include "app/chFrScanner.h" #include "app/common.h" #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/generic.h" #include "app/menu.h" #include "app/scanner.h" #include "audio.h" #include "driver/keyboard.h" #include "dtmf.h" #include "external/printf/printf.h" #include "functions.h" #include "misc.h" #include "settings.h" #include "ui/inputbox.h" #include "ui/ui.h" #ifdef ENABLE_TURN bool turn_flag = 0; #endif void GENERIC_Key_F(bool bKeyPressed, bool bKeyHeld) { if (gInputBoxIndex > 0) { if (!bKeyHeld && bKeyPressed) // short pressed gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (bKeyHeld || !bKeyPressed) // held or released { if (bKeyHeld || bKeyPressed) // held or pressed (cannot be held and not pressed I guess, so it checks only if HELD?) { if (!bKeyHeld) // won't ever pass return; if (!bKeyPressed) // won't ever pass return; COMMON_KeypadLockToggle(); } else // released { #ifdef ENABLE_FMRADIO if ((gFmRadioMode || gScreenToDisplay != DISPLAY_MAIN) && gScreenToDisplay != DISPLAY_FM) return; #else if (gScreenToDisplay != DISPLAY_MAIN) return; #endif gWasFKeyPressed = !gWasFKeyPressed; // toggle F function #ifdef ENABLE_TURN turn_flag = gWasFKeyPressed; #endif if (gWasFKeyPressed) gKeyInputCountdown = key_input_timeout_500ms; #ifdef ENABLE_VOICE if (!gWasFKeyPressed) gAnotherVoiceID = VOICE_ID_CANCEL; #endif gUpdateStatus = true; } } else // short pressed { #ifdef ENABLE_FMRADIO if (gScreenToDisplay != DISPLAY_FM) #endif { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; return; } #ifdef ENABLE_FMRADIO if (gFM_ScanState == FM_SCAN_OFF) // not scanning { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; return; } #endif gBeepToPlay = BEEP_440HZ_500MS; gPttWasReleased = true; } } void GENERIC_Key_PTT(bool bKeyPressed) { gInputBoxIndex = 0; if (!bKeyPressed || SerialConfigInProgress()) { // PTT released if (gCurrentFunction == FUNCTION_TRANSMIT) { // we are transmitting .. stop APP_EndTransmission(SerialConfigInProgress()); #ifdef ENABLE_VOX gVOX_NoiseDetected = false; #endif RADIO_SetVfoState(VFO_STATE_NORMAL); if (gScreenToDisplay != DISPLAY_MENU) // 1of11 .. don't close the menu gRequestDisplayScreen = DISPLAY_MAIN; } return; } // PTT pressed if (SCANNER_IsScanning()) { // CTCSS/CDCSS scanning .. stop SCANNER_Stop(); goto cancel_tx; } if (gScanStateDir != SCAN_OFF) { // frequency/channel scanning . .stop CHFRSCANNER_Stop(); goto cancel_tx; } #ifdef ENABLE_FMRADIO if (gFM_ScanState != FM_SCAN_OFF) { // FM radio is scanning .. stop FM_PlayAndUpdate(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif gRequestDisplayScreen = DISPLAY_FM; goto cancel_tx; } #endif #ifdef ENABLE_FMRADIO if (gScreenToDisplay == DISPLAY_FM) goto start_tx; // listening to the FM radio .. start TX'ing #endif if (gCurrentFunction == FUNCTION_TRANSMIT && gRTTECountdown_10ms == 0) { // already transmitting gInputBoxIndex = 0; return; } if (gScreenToDisplay != DISPLAY_MENU) // 1of11 .. don't close the menu gRequestDisplayScreen = DISPLAY_MAIN; if (!gDTMF_InputMode && gDTMF_InputBox_Index == 0) goto start_tx; // wasn't entering a DTMF code .. start TX'ing (maybe) // was entering a DTMF string if (gDTMF_InputBox_Index > 0 || gDTMF_PreviousIndex > 0) { // going to transmit a DTMF string if (gDTMF_InputBox_Index == 0 && gDTMF_PreviousIndex > 0) gDTMF_InputBox_Index = gDTMF_PreviousIndex; // use the previous DTMF string if (gDTMF_InputBox_Index < sizeof(gDTMF_InputBox)) gDTMF_InputBox[gDTMF_InputBox_Index] = 0; // NULL term the string #ifdef ENABLE_DTMF_CALLING // append our DTMF ID to the inputted DTMF code - // IF the user inputted code is exactly 3 digits long and D-DCD is enabled if (gDTMF_InputBox_Index == 3 && gTxVfo->DTMF_DECODING_ENABLE > 0) gDTMF_CallMode = DTMF_CheckGroupCall(gDTMF_InputBox, 3); else gDTMF_CallMode = DTMF_CALL_MODE_DTMF; gDTMF_State = DTMF_STATE_0; #endif // remember the DTMF string gDTMF_PreviousIndex = gDTMF_InputBox_Index; strcpy(gDTMF_String, gDTMF_InputBox); gDTMF_ReplyState = DTMF_REPLY_ANI; } DTMF_clear_input_box(); start_tx: // request start TX gFlagPrepareTX = true; goto done; cancel_tx: if (gPttIsPressed) { gPttWasPressed = true; } done: gPttDebounceCounter = 0; if (gScreenToDisplay != DISPLAY_MENU #ifdef ENABLE_FMRADIO && gRequestDisplayScreen != DISPLAY_FM #endif ) { // 1of11 .. don't close the menu gRequestDisplayScreen = DISPLAY_MAIN; } gUpdateStatus = true; gUpdateDisplay = true; } ================================================ FILE: app/generic.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_GENERIC_H #define APP_GENERIC_H #include void GENERIC_Key_F(bool bKeyPressed, bool bKeyHeld); void GENERIC_Key_PTT(bool bKeyPressed); extern bool turn_flag; #endif ================================================ FILE: app/main.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "app/action.h" #include "app/app.h" #include "app/chFrScanner.h" #include "app/common.h" #include "chinese.h" #ifdef ENABLE_4732 #include "app/si.h" #endif #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/generic.h" #include "app/main.h" #include "app/scanner.h" #ifdef ENABLE_SPECTRUM #include "app/spectrum.h" #endif #include "audio.h" #include "board.h" #include "driver/bk4819.h" #include "dtmf.h" #include "frequencies.h" #include "misc.h" #include "radio.h" #include "settings.h" #include "ui/inputbox.h" #include "ui/ui.h" #include #ifdef ENABLE_MESSENGER #include "app/messenger.h" #endif #ifdef ENABLE_DOPPLER #include "app/doppler.h" #endif void toggle_chan_scanlist(void) { // toggle the selected channels scanlist setting if (SCANNER_IsScanning()) return; if (!IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) { #ifdef ENABLE_SCAN_RANGES gScanRangeStart = gScanRangeStart ? 0 : gTxVfo->pRX->Frequency; gScanRangeStop = gEeprom.VfoInfo[!gEeprom.TX_VFO].freq_config_RX.Frequency; if(gScanRangeStart > gScanRangeStop) SWAP(gScanRangeStart, gScanRangeStop); #endif return; } if (gTxVfo->SCANLIST1_PARTICIPATION ^ gTxVfo->SCANLIST2_PARTICIPATION) { gTxVfo->SCANLIST2_PARTICIPATION = gTxVfo->SCANLIST1_PARTICIPATION; } else { gTxVfo->SCANLIST1_PARTICIPATION = !gTxVfo->SCANLIST1_PARTICIPATION; } SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true); gVfoConfigureMode = VFO_CONFIGURE; gFlagResetVfos = true; } static void processFKeyFunction(const KEY_Code_t Key, const bool beep) { uint8_t Vfo = gEeprom.TX_VFO; if (gScreenToDisplay == DISPLAY_MENU) { // if (beep) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; switch (Key) { case KEY_0: #ifdef ENABLE_FMRADIO ACTION_FM(); #endif #ifdef ENABLE_4732 SI4732_Main(); #endif break; case KEY_1: if (!IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) { gWasFKeyPressed = false; gUpdateStatus = true; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; #ifdef ENABLE_COPY_CHAN_TO_VFO if (!gEeprom.VFO_OPEN || gCssBackgroundScan) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (gScanStateDir != SCAN_OFF) { if (gCurrentFunction != FUNCTION_INCOMING || gRxReceptionMode == RX_MODE_NONE || gScanPauseDelayIn_10ms == 0) { // scan is running (not paused) return; } } const uint8_t vfo = gEeprom.TX_VFO; if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo])) { // copy channel to VFO, then swap to the VFO gEeprom.ScreenChannel[vfo] = FREQ_CHANNEL_FIRST + gEeprom.VfoInfo[vfo].Band; gEeprom.VfoInfo[vfo].CHANNEL_SAVE = gEeprom.ScreenChannel[vfo]; RADIO_SelectVfos(); RADIO_ApplyOffset(gRxVfo); RADIO_ConfigureSquelchAndOutputPower(gRxVfo); RADIO_SetupRegisters(true); //SETTINGS_SaveChannel(channel, gEeprom.RX_VFO, gRxVfo, 1); gUpdateDisplay = true; } #endif return; } #ifdef ENABLE_WIDE_RX if(gTxVfo->Band == BAND7_470MHz && gTxVfo->pRX->Frequency < _1GHz_in_KHz) { gTxVfo->pRX->Frequency = _1GHz_in_KHz; return; } #endif gTxVfo->Band += 1; if (gTxVfo->Band == BAND5_350MHz && gSetting_F_LOCK != F_LOCK_NONE) { // skip if not enabled gTxVfo->Band += 1; } else if (gTxVfo->Band >= BAND_N_ELEM) { // go arround if overflowed gTxVfo->Band = BAND1_50MHz; } gEeprom.ScreenChannel[Vfo] = FREQ_CHANNEL_FIRST + gTxVfo->Band; gEeprom.FreqChannel[Vfo] = FREQ_CHANNEL_FIRST + gTxVfo->Band; gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gRequestDisplayScreen = DISPLAY_MAIN; if (beep) gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; break; case KEY_2: COMMON_SwitchVFOs(); if (beep) gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; break; case KEY_3: COMMON_SwitchVFOMode(); if (beep) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; case KEY_4: gWasFKeyPressed = false; gBackup_CROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX; gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF; gUpdateStatus = true; if (beep) gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; SCANNER_Start(false); gRequestDisplayScreen = DISPLAY_SCANNER; break; case KEY_5: if (beep) { #ifdef ENABLE_NOAA if (!IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) { gEeprom.ScreenChannel[Vfo] = gEeprom.NoaaChannel[gEeprom.TX_VFO]; } else { gEeprom.ScreenChannel[Vfo] = gEeprom.FreqChannel[gEeprom.TX_VFO]; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_FREQUENCY_MODE; #endif } gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; #elif defined(ENABLE_SPECTRUM) #ifdef ENABLE_DOPPLER DOPPLER_MODE=0; #endif APP_RunSpectrum(); gRequestDisplayScreen = DISPLAY_MAIN; #endif } else { #ifdef ENABLE_VOX toggle_chan_scanlist(); #endif } break; case KEY_6: ACTION_Power(); break; case KEY_7: #ifdef ENABLE_VOX ACTION_Vox(); #else toggle_chan_scanlist(); #endif break; case KEY_8: gTxVfo->FrequencyReverse = ++gTxVfo->FrequencyReverse % 3; gRequestSaveChannel = 1; break; case KEY_9: if (RADIO_CheckValidChannel(gEeprom.CHAN_1_CALL, false, 0)) { gEeprom.MrChannel[Vfo] = gEeprom.CHAN_1_CALL; gEeprom.ScreenChannel[Vfo] = gEeprom.CHAN_1_CALL; #ifdef ENABLE_VOICE AUDIO_SetVoiceID(0, VOICE_ID_CHANNEL_MODE); AUDIO_SetDigitVoice(1, gEeprom.CHAN_1_CALL + 1); gAnotherVoiceID = (VOICE_ID_t)0xFE; #endif gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; break; } if (beep) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; default: gUpdateStatus = true; gWasFKeyPressed = false; if (beep) gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; break; } } static void MAIN_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld) { // key held down if (bKeyPressed) { if (gScreenToDisplay == DISPLAY_MAIN) { if (gInputBoxIndex > 0) { // delete any inputted chars gInputBoxIndex = 0; gRequestDisplayScreen = DISPLAY_MAIN; } gWasFKeyPressed = false; gUpdateStatus = true; processFKeyFunction(Key, false); } } return; } if (bKeyPressed) { // key is pressed gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; // beep when key is pressed return; // don't use the key till it's released } if (!gWasFKeyPressed) { // F-key wasn't pressed const uint8_t Vfo = gEeprom.TX_VFO; gKeyInputCountdown = key_input_timeout_500ms; INPUTBOX_Append(Key); gRequestDisplayScreen = DISPLAY_MAIN; if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) { // user is entering channel number if (gInputBoxIndex != 3) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gRequestDisplayScreen = DISPLAY_MAIN; return; } gInputBoxIndex = 0; const uint16_t Channel = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1; if (!RADIO_CheckValidChannel(Channel, false, 0)) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gEeprom.MrChannel[Vfo] = (uint8_t) Channel; gEeprom.ScreenChannel[Vfo] = (uint8_t) Channel; gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; return; } // #ifdef ENABLE_NOAA // if (!IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) // #endif if (IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) { // user is entering a frequency #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif bool isGigaF = gTxVfo->pRX->Frequency >= _1GHz_in_KHz; if (gInputBoxIndex < 6 + isGigaF) { return; } gInputBoxIndex = 0; uint32_t Frequency = StrToUL(INPUTBOX_GetAscii()) * 100; // clamp the frequency entered to some valid value if (Frequency < frequencyBandTable[0].lower) { Frequency = frequencyBandTable[0].lower; } else if (Frequency >= BX4819_band1.upper && Frequency < BX4819_band2.lower) { const uint32_t center = (BX4819_band1.upper + BX4819_band2.lower) / 2; Frequency = (Frequency < center) ? BX4819_band1.upper : BX4819_band2.lower; } else if (Frequency > frequencyBandTable[BAND_N_ELEM - 1].upper) { Frequency = frequencyBandTable[BAND_N_ELEM - 1].upper; } const FREQUENCY_Band_t band = FREQUENCY_GetBand(Frequency); if (gTxVfo->Band != band) { gTxVfo->Band = band; gEeprom.ScreenChannel[Vfo] = band + FREQ_CHANNEL_FIRST; gEeprom.FreqChannel[Vfo] = band + FREQ_CHANNEL_FIRST; SETTINGS_SaveVfoIndices(); RADIO_ConfigureChannel(Vfo, VFO_CONFIGURE_RELOAD); } Frequency = FREQUENCY_RoundToStep(Frequency, gTxVfo->StepFrequency); if (Frequency >= BX4819_band1.upper && Frequency < BX4819_band2.lower) { // clamp the frequency to the limit const uint32_t center = (BX4819_band1.upper + BX4819_band2.lower) / 2; Frequency = (Frequency < center) ? BX4819_band1.upper - gTxVfo->StepFrequency : BX4819_band2.lower; } gTxVfo->freq_config_RX.Frequency = Frequency; gRequestSaveChannel = 1; return; } #ifdef ENABLE_NOAA else if (IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) { // user is entering NOAA channel if (gInputBoxIndex != 2) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gRequestDisplayScreen = DISPLAY_MAIN; return; } gInputBoxIndex = 0; uint8_t Channel = (gInputBox[0] * 10) + gInputBox[1]; if (Channel >= 1 && Channel <= ARRAY_SIZE(NoaaFrequencyTable)) { Channel += NOAA_CHANNEL_FIRST; #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gEeprom.NoaaChannel[Vfo] = Channel; gEeprom.ScreenChannel[Vfo] = Channel; gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; return; } } #endif gRequestDisplayScreen = DISPLAY_MAIN; gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gWasFKeyPressed = false; gUpdateStatus = true; processFKeyFunction(Key, true); } static void MAIN_Key_EXIT(bool bKeyPressed, bool bKeyHeld) { #include "app/menu.h" #ifdef ENABLE_TURN if (turn_flag) { turn_flag = false; key_dir *= -1; gRequestSaveSettings = true; return; } #endif if (!bKeyHeld && bKeyPressed) { // exit key pressed gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; #ifdef ENABLE_DTMF_CALLING if (gDTMF_CallState != DTMF_CALL_STATE_NONE && gCurrentFunction != FUNCTION_TRANSMIT) { // clear CALL mode being displayed gDTMF_CallState = DTMF_CALL_STATE_NONE; gUpdateDisplay = true; return; } #endif #ifdef ENABLE_FMRADIO if (!gFmRadioMode) #endif { if (gScanStateDir == SCAN_OFF) { if (gInputBoxIndex == 0) return; gInputBox[--gInputBoxIndex] = 10; gKeyInputCountdown = key_input_timeout_500ms; #ifdef ENABLE_VOICE if (gInputBoxIndex == 0) gAnotherVoiceID = VOICE_ID_CANCEL; #endif } else { gScanKeepResult = false; CHFRSCANNER_Stop(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif } gRequestDisplayScreen = DISPLAY_MAIN; return; } #ifdef ENABLE_FMRADIO ACTION_FM(); #endif return; } if (bKeyHeld && bKeyPressed) { // exit key held down if (gInputBoxIndex > 0 || gDTMF_InputBox_Index > 0 || gDTMF_InputMode) { // cancel key input mode (channel/frequency entry) DTMF_clear_input_box(); memset(gDTMF_String, 0, sizeof(gDTMF_String)); gInputBoxIndex = 0; gRequestDisplayScreen = DISPLAY_MAIN; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; } } } static void MAIN_Key_MENU(const bool bKeyPressed, const bool bKeyHeld) { if (bKeyPressed && !bKeyHeld) // menu key pressed gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; if (bKeyHeld) { // menu key held down (long press) if (bKeyPressed) { // long press MENU key gWasFKeyPressed = false; if (gScreenToDisplay == DISPLAY_MAIN) { if (gInputBoxIndex > 0) { // delete any inputted chars gInputBoxIndex = 0; gRequestDisplayScreen = DISPLAY_MAIN; } gWasFKeyPressed = false; gUpdateStatus = true; ACTION_Handle(KEY_MENU, bKeyPressed, bKeyHeld); } } return; } if (!bKeyPressed && !gDTMF_InputMode) { // menu key released #ifdef ENABLE_MESSENGER if (gWasFKeyPressed) { hasNewMessage = 0; gRequestDisplayScreen = DISPLAY_MSG; return; } #endif const bool bFlag = !gInputBoxIndex; gInputBoxIndex = 0; if (bFlag) { if (gScanStateDir != SCAN_OFF) { CHFRSCANNER_Stop(); return; } gFlagRefreshSetting = true; gRequestDisplayScreen = DISPLAY_MENU; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_MENU; #endif } else { gRequestDisplayScreen = DISPLAY_MAIN; } } } static void MAIN_Key_STAR(bool bKeyPressed, bool bKeyHeld) { if (gCurrentFunction == FUNCTION_TRANSMIT) return; if (gInputBoxIndex) { if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (bKeyHeld && !gWasFKeyPressed) // long press { if (!bKeyPressed) // released return; ACTION_Scan(false);// toggle scanning gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; return; } if (bKeyPressed) // just pressed { return; } // just released if (!gWasFKeyPressed) // pressed without the F-key { if (gScanStateDir == SCAN_OFF #ifdef ENABLE_NOAA && !IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE) #endif #ifdef ENABLE_SCAN_RANGES && gScanRangeStart == 0 #endif ) { // start entering a DTMF string gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; memcpy(gDTMF_InputBox, gDTMF_String, MIN(sizeof(gDTMF_InputBox), sizeof(gDTMF_String) - 1)); gDTMF_InputBox_Index = 0; gDTMF_InputMode = true; gKeyInputCountdown = key_input_timeout_500ms; gRequestDisplayScreen = DISPLAY_MAIN; } else gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } else { // with the F-key gWasFKeyPressed = false; #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } #endif // scan the CTCSS/DCS code gBackup_CROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX; gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF; SCANNER_Start(true); gRequestDisplayScreen = DISPLAY_SCANNER; } gPttWasReleased = true; gUpdateStatus = true; } static void MAIN_Key_UP_DOWN(bool bKeyPressed, bool bKeyHeld, int8_t Direction) { uint8_t Channel = gEeprom.ScreenChannel[gEeprom.TX_VFO]; if (gWasFKeyPressed) { gWasFKeyPressed = false; if (Direction == 1) { gEeprom.BEEP_CONTROL = !gEeprom.BEEP_CONTROL; gRequestSaveSettings = 1; } #ifdef ENABLE_DOPPLER if (Direction==-1) { if (!DOPPLER_FLAG) { BACKLIGHT_TurnOn(); UI_DisplayClear(); #ifndef ENABLE_ENGLISH //ȡ UI_PrintStringSmall("\xD0\xB4\xC8\xEB\xCA\xFD\xBE\xDD:", 0, 127, 2); #else UI_PrintStringSmall("GET DATA:", 0, 127, 2); #endif UI_PrintStringSmall("k5.vicicode.com", 0, 127, 4); ST7565_BlitFullScreen(); uint8_t cnt_i = 200; while (cnt_i) { SYSTEM_DelayMs(10); cnt_i--; } }else{ #ifdef ENABLE_DOPPLER DOPPLER_MODE=1; #endif APP_RunSpectrum(); gRequestDisplayScreen = DISPLAY_MAIN; } } #endif return; } if (bKeyHeld || !bKeyPressed) { // key held or released if (gInputBoxIndex > 0) return; // leave if input box active if (!bKeyPressed) { if (!bKeyHeld || IS_FREQ_CHANNEL(Channel)) return; // if released long button press and not in freq mode #ifdef ENABLE_VOICE AUDIO_SetDigitVoice(0, gTxVfo->CHANNEL_SAVE + 1); // say channel number gAnotherVoiceID = (VOICE_ID_t)0xFE; #endif return; } } else { if (gInputBoxIndex > 0) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; } if (gScanStateDir == SCAN_OFF) { #ifdef ENABLE_NOAA if (!IS_NOAA_CHANNEL(Channel)) #endif { uint8_t Next; if (IS_FREQ_CHANNEL(Channel)) { // step/down in frequency const uint32_t frequency = APP_SetFrequencyByStep(gTxVfo, Direction); if (RX_freq_check(frequency) < 0) { // frequency not allowed gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gTxVfo->freq_config_RX.Frequency = frequency; BK4819_SetFrequency(frequency); BK4819_RX_TurnOn(); gRequestSaveChannel = 1; return; } Next = RADIO_FindNextChannel(Channel + Direction, Direction, false, 0); if (Next == 0xFF) return; if (Channel == Next) return; gEeprom.MrChannel[gEeprom.TX_VFO] = Next; gEeprom.ScreenChannel[gEeprom.TX_VFO] = Next; if (!bKeyHeld) { #ifdef ENABLE_VOICE AUDIO_SetDigitVoice(0, Next + 1); gAnotherVoiceID = (VOICE_ID_t)0xFE; #endif } } #ifdef ENABLE_NOAA else { Channel = NOAA_CHANNEL_FIRST + NUMBER_AddWithWraparound(gEeprom.ScreenChannel[gEeprom.TX_VFO] - NOAA_CHANNEL_FIRST, Direction, 0, 9); gEeprom.NoaaChannel[gEeprom.TX_VFO] = Channel; gEeprom.ScreenChannel[gEeprom.TX_VFO] = Channel; } #endif gRequestSaveVFO = true; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; return; } // jump to the next channel CHFRSCANNER_Start(false, Direction); gScanPauseDelayIn_10ms = 1; gScheduleScanListen = false; gPttWasReleased = true; } void MAIN_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (bKeyPressed) last_rx_vfo = -1; #ifdef ENABLE_FMRADIO if (gFmRadioMode && Key != KEY_PTT && Key != KEY_EXIT) { if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } #endif if (gDTMF_InputMode && bKeyPressed && !bKeyHeld) { const char Character = DTMF_GetCharacter(Key); if (Character != 0xFF) { // add key to DTMF string DTMF_Append(Character); gKeyInputCountdown = key_input_timeout_500ms; gRequestDisplayScreen = DISPLAY_MAIN; gPttWasReleased = true; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; return; } } // TODO: ??? // if (Key > KEY_PTT) // { // Key = KEY_SIDE2; // what's this doing ??? // } switch (Key) { case KEY_0...KEY_9: MAIN_Key_DIGITS(Key, bKeyPressed, bKeyHeld); break; case KEY_MENU: MAIN_Key_MENU(bKeyPressed, bKeyHeld); break; case KEY_UP: MAIN_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1); break; case KEY_DOWN: MAIN_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1); break; case KEY_EXIT: MAIN_Key_EXIT(bKeyPressed, bKeyHeld); break; case KEY_STAR: MAIN_Key_STAR(bKeyPressed, bKeyHeld); break; case KEY_F: GENERIC_Key_F(bKeyPressed, bKeyHeld); break; case KEY_PTT: GENERIC_Key_PTT(bKeyPressed); break; default: if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; } } ================================================ FILE: app/main.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_MAIN_H #define APP_MAIN_H #include "driver/keyboard.h" void MAIN_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); #endif ================================================ FILE: app/mdc1200.c ================================================ #include "driver/bk4819.h" #include "driver/crc.h" #include "driver/uart.h" #include "mdc1200.h" #include "misc.h" #include #include "driver/eeprom.h" const uint8_t mdc1200_pre_amble[] = {0x00, 0x00, 0x00}; const uint8_t mdc1200_sync[5] = {0x07, 0x09, 0x2a, 0x44, 0x6f}; const uint8_t mdc1200_sync_suc_xor[5] = {0xfb, 0x72, 0x40, 0x99, 0xa7}; void error_correction(void *data) { // can correct up to 3 or 4 corrupted bits (I think) int i; uint8_t shift_reg; uint8_t syn; uint8_t *data8 = (uint8_t *) data; for (i = 0, shift_reg = 0, syn = 0; i < MDC1200_FEC_K; i++) { const uint8_t bi = data8[i]; int bit_num; for (bit_num = 0; bit_num < 8; bit_num++) { uint8_t b; unsigned int k = 0; shift_reg = (shift_reg << 1) | ((bi >> bit_num) & 1u); b = ((shift_reg >> 6) ^ (shift_reg >> 5) ^ (shift_reg >> 2) ^ (shift_reg >> 0)) & 1u; syn = (syn << 1) | (((b ^ (data8[i + MDC1200_FEC_K] >> bit_num)) & 1u) ? 1u : 0u); if (syn & 0x80) k++; if (syn & 0x20) k++; if (syn & 0x04) k++; if (syn & 0x02) k++; if (k >= 3) { // correct a bit error int ii = i; int bn = bit_num - 7; if (bn < 0) { bn += 8; ii--; } if (ii >= 0) data8[ii] ^= 1u << bn; // fix a bit syn ^= 0xA6; // 10100110 } } } } bool decode_data(void *data) { uint16_t crc1; uint16_t crc2; uint8_t *data8 = (uint8_t *) data; { // de-interleave unsigned int i; unsigned int k; unsigned int m; uint8_t deinterleaved[(MDC1200_FEC_K * 2) * 8]; // temp individual bit storage // interleave order // 0, 16, 32, 48, 64, 80, 96, // 1, 17, 33, 49, 65, 81, 97, // 2, 18, 34, 50, 66, 82, 98, // 3, 19, 35, 51, 67, 83, 99, // 4, 20, 36, 52, 68, 84, 100, // 5, 21, 37, 53, 69, 85, 101, // 6, 22, 38, 54, 70, 86, 102, // 7, 23, 39, 55, 71, 87, 103, // 8, 24, 40, 56, 72, 88, 104, // 9, 25, 41, 57, 73, 89, 105, // 10, 26, 42, 58, 74, 90, 106, // 11, 27, 43, 59, 75, 91, 107, // 12, 28, 44, 60, 76, 92, 108, // 13, 29, 45, 61, 77, 93, 109, // 14, 30, 46, 62, 78, 94, 110, // 15, 31, 47, 63, 79, 95, 111 // de-interleave the received bits for (i = 0, k = 0; i < 16; i++) { for (m = 0; m < MDC1200_FEC_K; m++) { const unsigned int n = (m * 16) + i; deinterleaved[k++] = (data8[n >> 3] >> ((7 - n) & 7u)) & 1u; } } // copy the de-interleaved bits back into the data buffer for (i = 0, m = 0; i < (MDC1200_FEC_K * 2); i++) { unsigned int k; uint8_t b = 0; for (k = 0; k < 8; k++) if (deinterleaved[m++]) b |= 1u << k; data8[i] = b; } } // try to correct the odd corrupted bit error_correction(data); // rx'ed de-interleaved data (min 14 bytes) looks like this .. // // OP ARG ID CRC STATUS FEC bits // 01 80 1234 2E3E 00 6580A862DD8808 crc1 = compute_crc(data, 4); crc2 = ((uint16_t) data8[5] << 8) | (data8[4] << 0); return (crc1 == crc2) ? true : false; } // ********************************************************** // TX void xor_modulation(void *data, const unsigned int size) { // exclusive-or succesive bits - the entire packet unsigned int i; uint8_t *data8 = (uint8_t *) data; uint8_t prev_bit = 0; for (i = 0; i < size; i++) { int bit_num; uint8_t in = data8[i]; uint8_t out = 0; for (bit_num = 7; bit_num >= 0; bit_num--) { const uint8_t new_bit = (in >> bit_num) & 1u; if (new_bit != prev_bit) out |= 1u << bit_num; // previous bit and new bit are different - send a '1' prev_bit = new_bit; } data8[i] = out ^ 0xff; } } uint8_t *encode_data(void *data) { // R=1/2 K=7 convolutional coder // // OP ARG ID CRC STATUS FEC bits // 01 80 1234 2E3E 00 6580A862DD8808 // // 1. reverse the bit order for each byte of the first 7 bytes (to undo the reversal performed for display, above) // 2. feed those bits into a shift register which is preloaded with all zeros // 3. for each bit, calculate the modulo-2 sum: bit(n-0) + bit(n-2) + bit(n-5) + bit(n-6) // 4. then for each byte of resulting output, again reverse those bits to generate the values shown above uint8_t *data8 = (uint8_t *) data; { // add the FEC bits to the end of the data unsigned int i; uint8_t shift_reg = 0; for (i = 0; i < MDC1200_FEC_K; i++) { unsigned int bit_num; const uint8_t bi = data8[i]; uint8_t bo = 0; for (bit_num = 0; bit_num < 8; bit_num++) { shift_reg = (shift_reg << 1) | ((bi >> bit_num) & 1u); bo |= (((shift_reg >> 6) ^ (shift_reg >> 5) ^ (shift_reg >> 2) ^ (shift_reg >> 0)) & 1u) << bit_num; } data8[MDC1200_FEC_K + i] = bo; } } { // interleave the bits unsigned int i; unsigned int k; uint8_t interleaved[(MDC1200_FEC_K * 2) * 8]; // temp individual bit storage // interleave order // 0, 16, 32, 48, 64, 80, 96, // 1, 17, 33, 49, 65, 81, 97, // 2, 18, 34, 50, 66, 82, 98, // 3, 19, 35, 51, 67, 83, 99, // 4, 20, 36, 52, 68, 84, 100, // 5, 21, 37, 53, 69, 85, 101, // 6, 22, 38, 54, 70, 86, 102, // 7, 23, 39, 55, 71, 87, 103, // 8, 24, 40, 56, 72, 88, 104, // 9, 25, 41, 57, 73, 89, 105, // 10, 26, 42, 58, 74, 90, 106, // 11, 27, 43, 59, 75, 91, 107, // 12, 28, 44, 60, 76, 92, 108, // 13, 29, 45, 61, 77, 93, 109, // 14, 30, 46, 62, 78, 94, 110, // 15, 31, 47, 63, 79, 95, 111 // bit interleaver for (i = 0, k = 0; i < (MDC1200_FEC_K * 2); i++) { unsigned int bit_num; const uint8_t b = data8[i]; for (bit_num = 0; bit_num < 8; bit_num++) { interleaved[k] = (b >> bit_num) & 1u; k += 16; if (k >= sizeof(interleaved)) k -= sizeof(interleaved) - 1; } } // copy the interleaved bits back to the data buffer for (i = 0, k = 0; i < (MDC1200_FEC_K * 2); i++) { int bit_num; uint8_t b = 0; for (bit_num = 7; bit_num >= 0; bit_num--) if (interleaved[k++]) b |= 1u << bit_num; data8[i] = b; } } return data8 + (MDC1200_FEC_K * 2); } unsigned int MDC1200_encode_single_packet(void *data, const uint8_t op, const uint8_t arg, const uint16_t unit_id) { unsigned int size; uint16_t crc; uint8_t *p = (uint8_t *) data; memcpy(p, mdc1200_pre_amble, sizeof(mdc1200_pre_amble)); p += sizeof(mdc1200_pre_amble); memcpy(p, mdc1200_sync, sizeof(mdc1200_sync)); p += sizeof(mdc1200_sync); p[0] = op; p[1] = arg; p[2] = (unit_id >> 8) & 0x00ff; p[3] = (unit_id >> 0) & 0x00ff; crc = compute_crc(p, 4); p[4] = (crc >> 0) & 0x00ff; p[5] = (crc >> 8) & 0x00ff; p[6] = 0; // unknown field (00 for PTTIDs, 76 for STS and MSG) p = encode_data(p); size = (unsigned int) (p - (uint8_t *) data); xor_modulation(data, size); return size; } struct { uint8_t bit; uint8_t prev_bit; uint8_t xor_bit; uint64_t shift_reg; unsigned int bit_count; unsigned int stage; bool inverted_sync; unsigned int data_index; uint8_t data[40]; } rx; void MDC1200_reset_rx(void) { memset(&rx, 0, sizeof(rx)); } bool MDC1200_process_rx_data( const void *buffer, const unsigned int size, //const bool inverted, uint8_t *op, uint8_t *arg, uint16_t *unit_id) { const uint8_t *buffer8 = (const uint8_t *) buffer; unsigned int index; // 04 8D BF 66 58 sync // FB 72 40 99 A7 inverted sync // // 04 8D BF 66 58 40 C4 B0 32 BA F9 33 18 35 08 83 F6 0C 36 .. 80 87 20 23 2C AE 22 10 26 0F 02 A4 08 24 // 04 8D BF 66 58 45 DB 03 07 BC FA 35 2E 33 0E 83 0E 83 69 .. 86 92 02 05 28 AC 26 34 22 0B 02 0B 02 4E memset(&rx, 0, sizeof(rx)); for (index = 0; index < size; index++) { int bit; const uint8_t rx_byte = buffer8[index]; for (bit = 7; bit >= 0; bit--) { unsigned int i; rx.prev_bit = rx.bit; rx.bit = (rx_byte >> bit) & 1u; rx.xor_bit = (rx.xor_bit ^ rx.bit) & 1u; // toggle our bit if the rx bit is high rx.shift_reg = (rx.shift_reg << 1) | rx.xor_bit; rx.bit_count++; // ********* if (rx.stage == 0) { // looking for the 40-bit sync pattern const unsigned int sync_bit_ok_threshold = 32; if (rx.bit_count >= 40) { // 40-bit sync pattern uint64_t sync_nor = 0x07092a446fu; // normal uint64_t sync_inv = 0xffffffffffu ^ sync_nor; // bit inverted sync_nor ^= rx.shift_reg; sync_inv ^= rx.shift_reg; unsigned int nor_count = 0; unsigned int inv_count = 0; for (i = 40; i > 0; i--, sync_nor >>= 1, sync_inv >>= 1) { nor_count += sync_nor & 1u; inv_count += sync_inv & 1u; } nor_count = 40 - nor_count; inv_count = 40 - inv_count; if (nor_count >= sync_bit_ok_threshold || inv_count >= sync_bit_ok_threshold) { // good enough rx.inverted_sync = (inv_count > nor_count) ? true : false; rx.data_index = 0; rx.bit_count = 0; rx.stage = 1; } } continue; } if (rx.bit_count < 8) continue; rx.bit_count = 0; rx.data[rx.data_index++] = rx.shift_reg & 0xff; // save the last 8 bits if (rx.data_index < (MDC1200_FEC_K * 2)) continue; if (!decode_data(rx.data)) { MDC1200_reset_rx(); continue; } // extract the info from the packet *op = rx.data[0]; *arg = rx.data[1]; *unit_id = ((uint16_t) rx.data[2] << 8) | (rx.data[3] << 0); // reset the detector MDC1200_reset_rx(); return true; } } MDC1200_reset_rx(); return false; } uint8_t mdc1200_rx_buffer[5 + (MDC1200_FEC_K * 2)]; unsigned int mdc1200_rx_buffer_index = 0; uint8_t mdc1200_op; uint8_t mdc1200_arg; uint16_t mdc1200_unit_id; uint8_t mdc1200_rx_ready_tick_500ms; void MDC1200_init(void) { // memcpy(mdc1200_sync_suc_xor, mdc1200_sync, sizeof(mdc1200_sync)); // xor_modulation(mdc1200_sync_suc_xor, sizeof(mdc1200_sync_suc_xor)); MDC1200_reset_rx(); } uint16_t extractHex(const char *str) { uint16_t result = 0; while (*str) { char c = *str++; if (c >= '0' && c <= '9') { result = (result << 4) | (c - '0'); } else if (c >= 'A' && c <= 'F') { result = (result << 4) | (c - 'A' + 10); } else { continue; // 遇到非十六进制字符，停止解析 } } return result; } #ifdef ENABLE_MDC1200_CONTACT uint8_t contact_num=0; //uint16_t MDC_ADD[6] = {0x1D00, 0x1D40, 0x1D80,0x1DC0,0X1F90,0X1FD0};//SHIT ADDRESS COMBINE :( void mdc1200_update_contact_num() { EEPROM_ReadBuffer(MDC_NUM_ADD, (uint8_t *)&contact_num, 1); if(contact_num>MAX_CONTACT_NUM)contact_num=0; } bool mdc1200_contact_find(uint16_t mdc_id, char *contact) { mdc1200_update_contact_num(); uint16_t add = 0x1D00; for (uint8_t i = 0; i < contact_num; i++) { uint8_t read_once[16]={0}; EEPROM_ReadBuffer(add , read_once, 16); if (mdc_id == (uint16_t) (read_once[1] | (read_once[0] << 8))) { for (int j = 0; j < 14; ++j) { if(read_once[2+j]<' '||read_once[2+j]>'~') return false; } memcpy(contact,read_once+2,14); return true; } add+=16; if(add==0x1E00)add=0X1F90; } return false; } #endif ================================================ FILE: app/mdc1200.h ================================================ #ifndef MDC1200H #define MDC1200H #include #include #define MDC1200_FEC_K 7 // R=1/2 K=7 convolutional coder // 0x00 (0x81) emergency alarm // 0x20 (0x00) emergency alarm ack // // 0x01 (0x80) is PTT ID // 0x01 (0x00) is POST ID // 0x11 (0x8A) is REMOTE MONITOR // 0x22 (0x06) is STATUS REQ // 0x2B (0x0C) is RADIO ENABLE // 0x2B (0x00) is RADIO DISABLE // 0x35 (0x89) is CALL ALERT // 0x46 (0xXX) is STS XX // 0x47 (0xXX) is MSG XX // // 0x63 (0x85) is RADIO CHECK // 0x30 (0x00) is RADIO CHECK ack // // * CALL ALERT [Double packet - 2 codewords, 1234 places call to 5678] // 3589 5678 830D 1234 [Spectra, Astro Saber "PAGE", Maxtrac "CA" w/Ack Expected=Y] // 3589 5678 810D 1234 [Maxtrac "CA" w/Ack Expected=N] // // * VOICE SELECTIVE CALL [Double packet - 2 codewords, 1234 places call to 5678] // 3589 5678 8205 1234 [Spectra "CALL"] // 3589 5678 8015 1234 [Maxtrac "SC", Astro Saber "CALL"] // // * CALL ALERT ACKNOWLEDGE [Double packet - 2 codewords, 5678 acks the call from 1234] // 3589 1234 A000 5678 // // * SIMPLE STATUS [unit 1234 transmits status number X] // 460X 1234 // // * STATUS ACKNOWLEDGE // 2300 1234 // // * STATUS REQUEST [i.e. unit 5678 report your last status] // 2206 5678 // // * STATUS RESPONSE [from target 5678 when interrogated] // 060X 5678 // // * INBOUND MESSAGE // 470X 1234 [ack expected] // 070X 1234 [ack not expected CDM1550] // // * INBOUND MESSAGE ACKNOWLEDGE // 2300 1234 // // * REMOTE MONITOR [No MDC response from target unless it has PTT ID] // 118A 5678 [118A per KA6SQG] // // * SELECTIVE RADIO INHIBIT [Fixed end inhibits target 5678] // 2B00 5678 // // * SELECTIVE RADIO INHIBIT ACKNOWLEDGE [5678 acks the inhibit] // 0B00 5678 // // * SELECTIVE RADIO INHIBIT CANCEL [Fixed end enables target 5678] // 2B0C 5678 // // * SELECTIVE RADIO INHIBIT CANCEL [5678 acks the enable] // 0B0C 5678 // // * REQUEST TO TALK [Unit 1234 asks fixed end for permission to PTT] // 4001 1234 [CDM1550 dedicated button] // 4101 1234 [CDM1550 slaved to mic PTT] // // * REQUEST TO TALK ACKNOWLEDGE // 2300 1234 [general ack - not same as permission to PTT] enum mdc1200_op_code_e { MDC1200_OP_CODE_PTT_ID = 0x01, MDC1200_OP_CODE_POST_ID = 0x01, MDC1200_OP_CODE_REMOTE_MONITOR = 0x11, MDC1200_OP_CODE_STATUS_REQ = 0x22, MDC1200_OP_CODE_RADIO_ENABLE = 0x2B, MDC1200_OP_CODE_RADIO_DISABLE = 0x2B, MDC1200_OP_CODE_CALL_ALERT = 0x35, MDC1200_OP_CODE_STS_XX = 0x46, MDC1200_OP_CODE_MSG_XX = 0x47, MDC1200_OP_CODE_RADIO_CHECK = 0x63 }; typedef enum mdc1200_op_code_e mdc1200_op_code_t; extern const uint8_t mdc1200_sync[5]; extern const uint8_t mdc1200_sync_suc_xor[5]; extern uint8_t mdc1200_op; extern uint8_t mdc1200_arg; extern uint16_t mdc1200_unit_id; bool mdc1200_contact_find(uint16_t mdc_id, char *contact); extern uint8_t mdc1200_rx_buffer[5 + (MDC1200_FEC_K * 2)]; extern unsigned int mdc1200_rx_buffer_index; bool MDC1200_process_rx_data(const void *buffer, const unsigned int size, uint8_t *op, uint8_t *arg, uint16_t *unit_id); extern uint8_t mdc1200_rx_ready_tick_500ms; unsigned int MDC1200_encode_single_packet(void *data, const uint8_t op, const uint8_t arg, const uint16_t unit_id); void MDC1200_reset_rx(void); void MDC1200_init(void); uint16_t extractHex(const char *str); //extern uint16_t MDC_ADD[6]; #define MDC_NUM_ADD 0X1FFF #define MAX_CONTACT_NUM 21 extern uint8_t contact_num; #endif ================================================ FILE: app/menu.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "app/mdc1200.h" #include #include "driver/uart.h" #include "ui/helper.h" #if !defined(ENABLE_OVERLAY) #include "ARMCM0.h" #endif #include "app/dtmf.h" #include "app/generic.h" #include "app/menu.h" #include "app/scanner.h" #include "audio.h" #include "board.h" #include "bsp/dp32g030/gpio.h" #include "driver/backlight.h" #include "driver/bk4819.h" #include "driver/eeprom.h" #include "driver/gpio.h" #include "driver/keyboard.h" #include "frequencies.h" #include "helper/battery.h" #include "misc.h" #include "settings.h" #if defined(ENABLE_OVERLAY) #include "sram-overlay.h" #endif #include "ui/inputbox.h" #include "ui/menu.h" #include "ui/menu.h" #include "ui/ui.h" #ifndef ARRAY_SIZE #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) #endif //uint8_t gUnlockAllTxConfCnt; #ifdef ENABLE_F_CAL_MENU void writeXtalFreqCal(const int32_t value, const bool update_eeprom) { BK4819_WriteRegister(BK4819_REG_3B, 22656 + value); if (update_eeprom) { struct { int16_t BK4819_XtalFreqLow; uint16_t EEPROM_1F8A; uint16_t EEPROM_1F8C; uint8_t VOLUME_GAIN; uint8_t DAC_GAIN; } __attribute__((packed)) misc; gEeprom.BK4819_XTAL_FREQ_LOW = value; // radio 1 .. 04 00 46 00 50 00 2C 0E // radio 2 .. 05 00 46 00 50 00 2C 0E // EEPROM_ReadBuffer(0x1F88, &misc, 8); misc.BK4819_XtalFreqLow = value; EEPROM_WriteBuffer(0x1F88, &misc,8); } } #endif void MENU_StartCssScan(void) { SCANNER_Start(true); gUpdateStatus = true; gCssBackgroundScan = true; gRequestDisplayScreen = DISPLAY_MENU; } #ifdef ENABLE_PINYIN void PINYIN_SOLVE(uint32_t tmp) { if (INPUT_STAGE == 0) { INPUT_STAGE = 1; } uint8_t tmp_PINYIN_SEARCH_INDEX = PINYIN_SEARCH_INDEX; uint8_t tmp_PINYIN_SEARCH_NUM = PINYIN_SEARCH_NUM; uint8_t tmp_PINYIN_SEARCH_FOUND = PINYIN_SEARCH_FOUND; PINYIN_SEARCH_INDEX = sear_pinyin_code(PINYIN_CODE, &PINYIN_SEARCH_NUM, &PINYIN_SEARCH_FOUND); if (PINYIN_SEARCH_INDEX == 255 && PINYIN_SEARCH_FOUND == 0) { PINYIN_CODE = tmp; PINYIN_CODE_INDEX *= 10; PINYIN_SEARCH_INDEX = tmp_PINYIN_SEARCH_INDEX; PINYIN_SEARCH_NUM = tmp_PINYIN_SEARCH_NUM; PINYIN_SEARCH_FOUND = tmp_PINYIN_SEARCH_FOUND; if (PINYIN_CODE_INDEX == 100000)INPUT_STAGE = 0; } if (INPUT_STAGE) { //Ҫѡƴ if (PINYIN_SEARCH_FOUND) { if (PINYIN_SEARCH_INDEX != 255) { //ȷʵƴ PINYIN_NOW_INDEX = PINYIN_SEARCH_INDEX; PINYIN_NOW_NUM = PINYIN_SEARCH_NUM; PINYIN_SEARCH_MODE = 1; } } else { //ûƴϵбѡ // PINYIN_SEARCH_MODE = 2; // PINYIN_NOW_INDEX = PINYIN_SEARCH_INDEX; // PINYIN_NOW_NUM = PINYIN_SEARCH_NUM; // PINYIN_START_INDEX = PINYIN_NOW_INDEX; // // for (int i = PINYIN_START_INDEX; i < 214; ++i) { // uint8_t tmp[4]; // uint32_t tmp_code; // EEPROM_ReadBuffer(128 * i + 0x20000, tmp, 4); // tmp_code = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24; // if (judge_belong(PINYIN_CODE, tmp_code)) { // PINYIN_END_INDEX = i; // } else break; // } } } } #endif void MENU_CssScanFound(void) { if (gScanCssResultType == CODE_TYPE_DIGITAL || gScanCssResultType == CODE_TYPE_REVERSE_DIGITAL) { gMenuCursor = UI_MENU_GetMenuIdx(MENU_R_DCS); } else if (gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) { gMenuCursor = UI_MENU_GetMenuIdx(MENU_R_CTCS); } MENU_ShowCurrentSetting(); gUpdateStatus = true; gUpdateDisplay = true; } void MENU_StopCssScan(void) { gCssBackgroundScan = false; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif gUpdateDisplay = true; gUpdateStatus = true; } int MENU_GetLimits(uint8_t menu_id, int32_t *pMin, int32_t *pMax) { switch (menu_id) { case MENU_SQL: *pMin = 0; *pMax = 9; break; case MENU_STEP: *pMin = 0; *pMax = STEP_N_ELEM - 1; break; case MENU_ABR: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_BACKLIGHT) - 1; break; // case MENU_ABR_MIN: // *pMin = 0; // *pMax = 9; // break; case MENU_ABR_MAX: *pMin = 1; *pMax = 10; break; case MENU_F_LOCK: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_F_LOCK) - 1; break; case MENU_MDF: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_MDF) - 1; break; // case MENU_TXP: // *pMin = 0; // *pMax = ARRAY_SIZE(gSubMenu_TXP) - 1; // break; case MENU_SFT_D: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_SFT_D) - 1; break; case MENU_TDR: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_RXMode) - 1; break; #ifdef ENABLE_VOICE case MENU_VOICE: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_VOICE) - 1; break; #endif case MENU_SC_REV: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_SC_REV) - 1; break; case MENU_ROGER: *pMin = 0; #ifndef ENABLE_MDC1200 *pMax = 1; #else *pMax = ARRAY_SIZE(gSubMenu_ROGER) - 1; #endif break; #if ENABLE_CHINESE_FULL == 4 case MENU_PONMSG: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_PONMSG) - 1; break; #endif case MENU_R_DCS: case MENU_T_DCS: *pMin = 0; *pMax = 208; //*pMax = (104 * 2); break; case MENU_R_CTCS: case MENU_T_CTCS: *pMin = 0; *pMax = 50; break; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_W_N: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_W_N) - 1; break; #endif #ifdef ENABLE_ALARM case MENU_AL_MOD: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_AL_MOD) - 1; break; #endif case MENU_RESET: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_RESET) - 1; break; case MENU_COMPAND: // case MENU_ABR_ON_TX_RX: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_RX_TX) - 1; break; #ifdef ENABLE_AM_FIX_TEST1 case MENU_AM_FIX_TEST1: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_AM_fix_test1) - 1; break; #endif #ifdef ENABLE_AM_FIX case MENU_AM_FIX: #endif //#ifdef ENABLE_AUDIO_BAR //case MENU_MIC_BAR: //#endif case MENU_BCL: // case MENU_BEEP: //case MENU_AUTOLK: //case MENU_S_ADD1: //case MENU_S_ADD2: case MENU_STE: case MENU_D_ST: #ifdef ENABLE_DTMF_CALLING #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_D_DCD: #endif #endif case MENU_D_LIVE_DEC: #ifdef ENABLE_NOAA case MENU_NOAA_S: #endif // case MENU_350TX: // case MENU_200TX: // case MENU_500TX: // case MENU_350EN: // case MENU_SCREN: // *pMin = 0; // *pMax = ARRAY_SIZE(gSubMenu_OFF_ON) - 1; // break; *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_OFF_ON) - 1; break; // case MENU_AM: // *pMin = 0; // *pMax = ARRAY_SIZE(gModulationStr) - 1; // break; case MENU_SCR: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_SCRAMBLER) - 1; break; case MENU_TOT: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_TOT) - 1; break; #ifdef ENABLE_VOX //case MENU_VOX: #endif case MENU_RP_STE: *pMin = 0; *pMax = 10; break; case MENU_MEM_CH: case MENU_1_CALL: case MENU_DEL_CH: case MENU_MEM_NAME: *pMin = 0; *pMax = MR_CHANNEL_LAST; break; case MENU_SLIST1: case MENU_SLIST2: *pMin = -1; *pMax = MR_CHANNEL_LAST; break; case MENU_SAVE: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_SAVE) - 1; break; case MENU_MIC: *pMin = 0; *pMax = 4; break; case MENU_S_LIST: *pMin = 0; *pMax = 2; break; #ifdef ENABLE_DTMF_CALLING case MENU_D_RSP: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_D_RSP) - 1; break; #endif case MENU_PTT_ID: *pMin = 0; *pMax = ARRAY_SIZE(gSubMenu_PTT_ID) - 1; break; // case MENU_BAT_TXT: // *pMin = 0; // *pMax = ARRAY_SIZE(gSubMenu_BAT_TXT) - 1; // break; #ifdef ENABLE_DTMF_CALLING case MENU_D_HOLD: *pMin = 5; *pMax = 60; break; #endif case MENU_D_PRE: *pMin = 3; *pMax = 99; break; #ifdef ENABLE_DTMF_CALLING case MENU_D_LIST: *pMin = 1; *pMax = 16; break; #endif #ifdef ENABLE_F_CAL_MENU case MENU_F_CALI: *pMin = -50; *pMax = +50; break; #endif case MENU_BATCAL: *pMin = 1600; *pMax = 2200; break; case MENU_BATTYP: *pMin = 0; *pMax = 1; break; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_F1SHRT: case MENU_F2SHRT: *pMin = 0; #ifdef ENABLE_SIDEFUNCTIONS_SEND *pMax = gSubMenu_SIDEFUNCTIONS_size-3; #else *pMax =gSubMenu_SIDEFUNCTIONS_size-1; #endif break; case MENU_F1LONG: case MENU_F2LONG: case MENU_MLONG: *pMin = 0; *pMax = gSubMenu_SIDEFUNCTIONS_size-1; break; #endif default: return -1; } return 0; } void MENU_AcceptSetting(void) { int32_t Min; int32_t Max; FREQ_Config_t *pConfig = &gTxVfo->freq_config_RX; if (!MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) { if (gSubMenuSelection < Min) gSubMenuSelection = Min; else if (gSubMenuSelection > Max) gSubMenuSelection = Max; } char a = gSubMenuSelection;//UART_Send(a,1); UART_Send((uint8_t *) &a, 1); switch (UI_MENU_GetCurrentMenuId()) { default: return; case MENU_SQL: gEeprom.SQUELCH_LEVEL = gSubMenuSelection; gVfoConfigureMode = VFO_CONFIGURE; break; case MENU_STEP: gTxVfo->STEP_SETTING = FREQUENCY_GetStepIdxFromSortedIdx(gSubMenuSelection); if (IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) { gRequestSaveChannel = 1; return; } return; // case MENU_TXP: // gTxVfo->OUTPUT_POWER = gSubMenuSelection; // gRequestSaveChannel = 1; // return; case MENU_T_DCS: pConfig = &gTxVfo->freq_config_TX; // Fallthrough case MENU_R_DCS: { if (gSubMenuSelection == 0) { if (pConfig->CodeType == CODE_TYPE_CONTINUOUS_TONE) { return; } pConfig->Code = 0; pConfig->CodeType = CODE_TYPE_OFF; } else if (gSubMenuSelection < 105) { pConfig->CodeType = CODE_TYPE_DIGITAL; pConfig->Code = gSubMenuSelection - 1; } else { pConfig->CodeType = CODE_TYPE_REVERSE_DIGITAL; pConfig->Code = gSubMenuSelection - 105; } gRequestSaveChannel = 1; return; } case MENU_T_CTCS: pConfig = &gTxVfo->freq_config_TX; [[fallthrough]]; case MENU_R_CTCS: { if (gSubMenuSelection == 0) { if (pConfig->CodeType != CODE_TYPE_CONTINUOUS_TONE) { return; } pConfig->Code = 0; pConfig->CodeType = CODE_TYPE_OFF; } else { pConfig->Code = gSubMenuSelection - 1; pConfig->CodeType = CODE_TYPE_CONTINUOUS_TONE; } gRequestSaveChannel = 1; return; } case MENU_SFT_D: gTxVfo->TX_OFFSET_FREQUENCY_DIRECTION = gSubMenuSelection; gRequestSaveChannel = 1; return; case MENU_OFFSET: gTxVfo->TX_OFFSET_FREQUENCY = gSubMenuSelection; gRequestSaveChannel = 1; return; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_W_N: gTxVfo->CHANNEL_BANDWIDTH = gSubMenuSelection; gRequestSaveChannel = 1; return; #endif case MENU_SCR: gTxVfo->SCRAMBLING_TYPE = gSubMenuSelection; #if 0 if (gSubMenuSelection > 0 && gSetting_ScrambleEnable) BK4819_EnableScramble(gSubMenuSelection - 1); else BK4819_DisableScramble(); #endif gRequestSaveChannel = 1; return; case MENU_BCL: gTxVfo->BUSY_CHANNEL_LOCK = gSubMenuSelection; gRequestSaveChannel = 1; return; case MENU_MEM_CH: gTxVfo->CHANNEL_SAVE = gSubMenuSelection; #if 0 gEeprom.MrChannel[0] = gSubMenuSelection; #else gEeprom.MrChannel[gEeprom.TX_VFO] = gSubMenuSelection; #endif gRequestSaveChannel = 2; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gFlagResetVfos = true; return; #ifdef ENABLE_MDC1200 case MENU_MDC_ID: #ifdef ENABLE_MDC1200_EDIT gEeprom.MDC1200_ID=extractHex(edit); #endif return; #endif case MENU_MEM_NAME: //뷨 // trailing trim for (int i = MAX_EDIT_INDEX - 1; i >= 0; i--) { if (edit[i] != ' ' && edit[i] != '_' && edit[i] != 0x00 && edit[i] != 0xff) break; edit[i] = 0; } SETTINGS_SaveChannelName(gSubMenuSelection, edit); return; case MENU_SAVE: gEeprom.BATTERY_SAVE = gSubMenuSelection; break; #ifdef ENABLE_VOX // case MENU_VOX: // gEeprom.VOX_SWITCH = gSubMenuSelection != 0; // if (gEeprom.VOX_SWITCH) // gEeprom.VOX_LEVEL = gSubMenuSelection - 1; // SETTINGS_LoadCalibration(); // gFlagReconfigureVfos = true; // gUpdateStatus = true; // break; #endif case MENU_ABR: gEeprom.BACKLIGHT_TIME = gSubMenuSelection; break; // case MENU_ABR_MIN: // gEeprom.BACKLIGHT_MIN = gSubMenuSelection; // gEeprom.BACKLIGHT_MAX = MAX(gSubMenuSelection + 1 , gEeprom.BACKLIGHT_MAX); // break; case MENU_ABR_MAX: gEeprom.BACKLIGHT_MAX = gSubMenuSelection; break; // case MENU_ABR_ON_TX_RX: // gSetting_backlight_on_tx_rx = gSubMenuSelection; // break; case MENU_TDR: gEeprom.DUAL_WATCH = (gEeprom.TX_VFO + 1) * (gSubMenuSelection & 1); gEeprom.CROSS_BAND_RX_TX = (gEeprom.TX_VFO + 1) * ((gSubMenuSelection & 2) > 0); gFlagReconfigureVfos = true; gUpdateStatus = true; break; // case MENU_BEEP: // gEeprom.BEEP_CONTROL = gSubMenuSelection; // break; case MENU_TOT: gEeprom.TX_TIMEOUT_TIMER = gSubMenuSelection; break; #ifdef ENABLE_VOICE case MENU_VOICE: gEeprom.VOICE_PROMPT = gSubMenuSelection; gUpdateStatus = true; break; #endif case MENU_SC_REV: gEeprom.SCAN_RESUME_MODE = gSubMenuSelection; break; case MENU_MDF: gEeprom.CHANNEL_DISPLAY_MODE = gSubMenuSelection; break; // case MENU_AUTOLK: // gEeprom.AUTO_KEYPAD_LOCK = gSubMenuSelection; // gKeyLockCountdown = 30; // break; // case MENU_S_ADD1: // gTxVfo->SCANLIST1_PARTICIPATION = gSubMenuSelection; // SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true); // gVfoConfigureMode = VFO_CONFIGURE; // gFlagResetVfos = true; // return; // case MENU_S_ADD2: // gTxVfo->SCANLIST2_PARTICIPATION = gSubMenuSelection; // SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true); // gVfoConfigureMode = VFO_CONFIGURE; // gFlagResetVfos = true; // return; case MENU_STE: gEeprom.TAIL_TONE_ELIMINATION = gSubMenuSelection; break; case MENU_RP_STE: gEeprom.REPEATER_TAIL_TONE_ELIMINATION = gSubMenuSelection; break; case MENU_MIC: gEeprom.MIC_SENSITIVITY = gSubMenuSelection; SETTINGS_LoadCalibration(); gFlagReconfigureVfos = true; break; //#ifdef ENABLE_AUDIO_BAR // case MENU_MIC_BAR: // gSetting_mic_bar = gSubMenuSelection; // break; //#endif case MENU_COMPAND: gTxVfo->Compander = gSubMenuSelection; SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true); gVfoConfigureMode = VFO_CONFIGURE; gFlagResetVfos = true; // gRequestSaveChannel = 1; return; case MENU_1_CALL: gEeprom.CHAN_1_CALL = gSubMenuSelection; break; case MENU_S_LIST: gEeprom.SCAN_LIST_DEFAULT = gSubMenuSelection; break; #ifdef ENABLE_ALARM case MENU_AL_MOD: gEeprom.ALARM_MODE = gSubMenuSelection; break; #endif case MENU_D_ST: gEeprom.DTMF_SIDE_TONE = gSubMenuSelection; break; #ifdef ENABLE_DTMF_CALLING case MENU_D_RSP: gEeprom.DTMF_DECODE_RESPONSE = gSubMenuSelection; break; case MENU_D_HOLD: gEeprom.DTMF_auto_reset_time = gSubMenuSelection; break; #endif case MENU_D_PRE: gEeprom.DTMF_PRELOAD_TIME = gSubMenuSelection * 10; break; case MENU_PTT_ID: gTxVfo->DTMF_PTT_ID_TX_MODE = gSubMenuSelection; gRequestSaveChannel = 1; return; // case MENU_BAT_TXT: // gSetting_battery_text = gSubMenuSelection; // break; #ifdef ENABLE_DTMF_CALLING #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_D_DCD: gTxVfo->DTMF_DECODING_ENABLE = gSubMenuSelection; DTMF_clear_RX(); gRequestSaveChannel = 1; return; #endif #endif case MENU_D_LIVE_DEC: gSetting_live_DTMF_decoder = gSubMenuSelection; gDTMF_RX_live_timeout = 0; memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live)); if (!gSetting_live_DTMF_decoder) BK4819_DisableDTMF(); gFlagReconfigureVfos = true; gUpdateStatus = true; break; #ifdef ENABLE_DTMF_CALLING case MENU_D_LIST: gDTMF_chosen_contact = gSubMenuSelection - 1; if (gIsDtmfContactValid) { GUI_SelectNextDisplay(DISPLAY_MAIN); gDTMF_InputMode = true; gDTMF_InputBox_Index = 3; memcpy(gDTMF_InputBox, gDTMF_ID, 4); gRequestDisplayScreen = DISPLAY_INVALID; } return; #endif #if ENABLE_CHINESE_FULL == 4 case MENU_PONMSG: gEeprom.POWER_ON_DISPLAY_MODE = gSubMenuSelection; break; #endif case MENU_ROGER: gEeprom.ROGER = gSubMenuSelection; break; // case MENU_AM: // gTxVfo->Modulation = gSubMenuSelection; // gRequestSaveChannel = 1; // return; #ifdef ENABLE_AM_FIX case MENU_AM_FIX: gSetting_AM_fix = gSubMenuSelection; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gFlagResetVfos = true; break; #endif #ifdef ENABLE_AM_FIX_TEST1 case MENU_AM_FIX_TEST1: gSetting_AM_fix_test1 = gSubMenuSelection; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gFlagResetVfos = true; break; #endif #ifdef ENABLE_NOAA case MENU_NOAA_S: gEeprom.NOAA_AUTO_SCAN = gSubMenuSelection; gFlagReconfigureVfos = true; break; #endif case MENU_DEL_CH: SETTINGS_UpdateChannel(gSubMenuSelection, NULL, false); gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gFlagResetVfos = true; return; case MENU_RESET: SETTINGS_FactoryReset(gSubMenuSelection); return; // case MENU_350TX: // gSetting_350TX = gSubMenuSelection; // break; case MENU_F_LOCK: { // if(gSubMenuSelection == F_LOCK_NONE) { // select 10 times to enable // gUnlockAllTxConfCnt++; // if(gUnlockAllTxConfCnt < 10) // return; // } // else // gUnlockAllTxConfCnt = 0; gSetting_F_LOCK = gSubMenuSelection; break; } // case MENU_200TX: // gSetting_200TX = gSubMenuSelection; // break; // // case MENU_500TX: // gSetting_500TX = gSubMenuSelection; // break; // case MENU_350EN: // gSetting_350EN = gSubMenuSelection; // gVfoConfigureMode = VFO_CONFIGURE_RELOAD; // gFlagResetVfos = true; // break; // case MENU_SCREN: // gSetting_ScrambleEnable = gSubMenuSelection; // gFlagReconfigureVfos = true; // break; #ifdef ENABLE_F_CAL_MENU case MENU_F_CALI: writeXtalFreqCal(gSubMenuSelection, true); return; #endif case MENU_BATCAL: { // voltages are averages between discharge curves of 1600 and 2200 mAh // gBatteryCalibration[0] = (520ul * gSubMenuSelection) / 760; // 5.20V empty, blinking above this value, reduced functionality below // gBatteryCalibration[1] = (689ul * gSubMenuSelection) / 760; // 6.89V, ~5%, 1 bars above this value // gBatteryCalibration[2] = (724ul * gSubMenuSelection) / 760; // 7.24V, ~17%, 2 bars above this value gBatteryCalibration[3] = gSubMenuSelection; // 7.6V, ~29%, 3 bars above this value // gBatteryCalibration[4] = (771ul * gSubMenuSelection) / 760; // 7.71V, ~65%, 4 bars above this value // gBatteryCalibration[5] = 2300; SETTINGS_SaveBatteryCalibration(gBatteryCalibration); return; } case MENU_BATTYP: gEeprom.BATTERY_TYPE = gSubMenuSelection; break; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_F1SHRT: case MENU_F1LONG: case MENU_F2SHRT: case MENU_F2LONG: case MENU_MLONG: { uint8_t * fun[]= { &gEeprom.KEY_1_SHORT_PRESS_ACTION, &gEeprom.KEY_1_LONG_PRESS_ACTION, &gEeprom.KEY_2_SHORT_PRESS_ACTION, &gEeprom.KEY_2_LONG_PRESS_ACTION, &gEeprom.KEY_M_LONG_PRESS_ACTION}; *fun[UI_MENU_GetCurrentMenuId()-MENU_F1SHRT] = gSubMenu_SIDEFUNCTIONS[gSubMenuSelection].id; } break; #endif } gRequestSaveSettings = true; } static void MENU_ClampSelection(int8_t Direction) { int32_t Min; int32_t Max; if (!MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) { int32_t Selection = gSubMenuSelection; if (Selection < Min) Selection = Min; else if (Selection > Max) Selection = Max; gSubMenuSelection = NUMBER_AddWithWraparound(Selection, Direction, Min, Max); } } void MENU_ShowCurrentSetting(void) { switch (UI_MENU_GetCurrentMenuId()) { case MENU_SQL: gSubMenuSelection = gEeprom.SQUELCH_LEVEL; break; case MENU_STEP: gSubMenuSelection = FREQUENCY_GetSortedIdxFromStepIdx(gTxVfo->STEP_SETTING); break; // case MENU_TXP: // gSubMenuSelection = gTxVfo->OUTPUT_POWER; // break; case MENU_RESET: gSubMenuSelection = 0; break; case MENU_R_DCS: case MENU_R_CTCS: { DCS_CodeType_t type = gTxVfo->freq_config_RX.CodeType; uint8_t code = gTxVfo->freq_config_RX.Code; int menuid = UI_MENU_GetCurrentMenuId(); if (gScanUseCssResult) { gScanUseCssResult = false; type = gScanCssResultType; code = gScanCssResultCode; } if ((menuid == MENU_R_CTCS) ^ (type == CODE_TYPE_CONTINUOUS_TONE)) { //not the same type gSubMenuSelection = 0; break; } switch (type) { case CODE_TYPE_CONTINUOUS_TONE: case CODE_TYPE_DIGITAL: gSubMenuSelection = code + 1; break; case CODE_TYPE_REVERSE_DIGITAL: gSubMenuSelection = code + 105; break; default: gSubMenuSelection = 0; break; } break; } case MENU_T_DCS: switch (gTxVfo->freq_config_TX.CodeType) { case CODE_TYPE_DIGITAL: gSubMenuSelection = gTxVfo->freq_config_TX.Code + 1; break; case CODE_TYPE_REVERSE_DIGITAL: gSubMenuSelection = gTxVfo->freq_config_TX.Code + 105; break; default: gSubMenuSelection = 0; break; } break; case MENU_T_CTCS: gSubMenuSelection = (gTxVfo->freq_config_TX.CodeType == CODE_TYPE_CONTINUOUS_TONE) ? gTxVfo->freq_config_TX.Code + 1 : 0; break; case MENU_SFT_D: gSubMenuSelection = gTxVfo->TX_OFFSET_FREQUENCY_DIRECTION; break; case MENU_OFFSET: gSubMenuSelection = gTxVfo->TX_OFFSET_FREQUENCY; break; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_W_N: gSubMenuSelection = gTxVfo->CHANNEL_BANDWIDTH; break; #endif case MENU_SCR: gSubMenuSelection = gTxVfo->SCRAMBLING_TYPE; break; case MENU_BCL: gSubMenuSelection = gTxVfo->BUSY_CHANNEL_LOCK; break; case MENU_MEM_CH: #if 0 gSubMenuSelection = gEeprom.MrChannel[0]; #else gSubMenuSelection = gEeprom.MrChannel[gEeprom.TX_VFO]; #endif break; case MENU_MEM_NAME: gSubMenuSelection = gEeprom.MrChannel[gEeprom.TX_VFO]; break; case MENU_SAVE: gSubMenuSelection = gEeprom.BATTERY_SAVE; break; #ifdef ENABLE_VOX // case MENU_VOX: // gSubMenuSelection = gEeprom.VOX_SWITCH ? gEeprom.VOX_LEVEL + 1 : 0; // break; #endif case MENU_ABR: gSubMenuSelection = gEeprom.BACKLIGHT_TIME; break; // case MENU_ABR_MIN: // gSubMenuSelection = gEeprom.BACKLIGHT_MIN; // break; case MENU_ABR_MAX: gSubMenuSelection = gEeprom.BACKLIGHT_MAX; break; // case MENU_ABR_ON_TX_RX: // gSubMenuSelection = gSetting_backlight_on_tx_rx; // break; case MENU_TDR: gSubMenuSelection = (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) + (gEeprom.CROSS_BAND_RX_TX != CROSS_BAND_OFF) * 2; break; // case MENU_BEEP: // gSubMenuSelection = gEeprom.BEEP_CONTROL; // break; case MENU_TOT: gSubMenuSelection = gEeprom.TX_TIMEOUT_TIMER; break; #ifdef ENABLE_VOICE case MENU_VOICE: gSubMenuSelection = gEeprom.VOICE_PROMPT; break; #endif case MENU_SC_REV: gSubMenuSelection = gEeprom.SCAN_RESUME_MODE; break; case MENU_MDF: gSubMenuSelection = gEeprom.CHANNEL_DISPLAY_MODE; break; // case MENU_AUTOLK: // gSubMenuSelection = gEeprom.AUTO_KEYPAD_LOCK; // break; // case MENU_S_ADD1: // gSubMenuSelection = gTxVfo->SCANLIST1_PARTICIPATION; // break; // // case MENU_S_ADD2: // gSubMenuSelection = gTxVfo->SCANLIST2_PARTICIPATION; // break; case MENU_STE: gSubMenuSelection = gEeprom.TAIL_TONE_ELIMINATION; break; case MENU_RP_STE: gSubMenuSelection = gEeprom.REPEATER_TAIL_TONE_ELIMINATION; break; case MENU_MIC: gSubMenuSelection = gEeprom.MIC_SENSITIVITY; break; //#ifdef ENABLE_AUDIO_BAR // case MENU_MIC_BAR: // gSubMenuSelection = gSetting_mic_bar; // break; //#endif case MENU_COMPAND: gSubMenuSelection = gTxVfo->Compander; return; case MENU_1_CALL: gSubMenuSelection = gEeprom.CHAN_1_CALL; break; case MENU_S_LIST: gSubMenuSelection = gEeprom.SCAN_LIST_DEFAULT; break; case MENU_SLIST1: gSubMenuSelection = RADIO_FindNextChannel(0, 1, true, 0); break; case MENU_SLIST2: gSubMenuSelection = RADIO_FindNextChannel(0, 1, true, 1); break; #ifdef ENABLE_ALARM case MENU_AL_MOD: gSubMenuSelection = gEeprom.ALARM_MODE; break; #endif case MENU_D_ST: gSubMenuSelection = gEeprom.DTMF_SIDE_TONE; break; #ifdef ENABLE_DTMF_CALLING case MENU_D_RSP: gSubMenuSelection = gEeprom.DTMF_DECODE_RESPONSE; break; case MENU_D_HOLD: gSubMenuSelection = gEeprom.DTMF_auto_reset_time; break; #endif case MENU_D_PRE: gSubMenuSelection = gEeprom.DTMF_PRELOAD_TIME / 10; break; case MENU_PTT_ID: gSubMenuSelection = gTxVfo->DTMF_PTT_ID_TX_MODE; break; // case MENU_BAT_TXT: // gSubMenuSelection = gSetting_battery_text; // return; #ifdef ENABLE_DTMF_CALLING #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_D_DCD: gSubMenuSelection = gTxVfo->DTMF_DECODING_ENABLE; break; #endif case MENU_D_LIST: gSubMenuSelection = gDTMF_chosen_contact + 1; break; #endif case MENU_D_LIVE_DEC: gSubMenuSelection = gSetting_live_DTMF_decoder; break; #if ENABLE_CHINESE_FULL == 4 case MENU_PONMSG: gSubMenuSelection = gEeprom.POWER_ON_DISPLAY_MODE; break; #endif case MENU_ROGER: gSubMenuSelection = gEeprom.ROGER; break; // case MENU_AM: // gSubMenuSelection = gTxVfo->Modulation; // break; #ifdef ENABLE_AM_FIX case MENU_AM_FIX: gSubMenuSelection = gSetting_AM_fix; break; #endif #ifdef ENABLE_AM_FIX_TEST1 case MENU_AM_FIX_TEST1: gSubMenuSelection = gSetting_AM_fix_test1; break; #endif #ifdef ENABLE_NOAA case MENU_NOAA_S: gSubMenuSelection = gEeprom.NOAA_AUTO_SCAN; break; #endif case MENU_DEL_CH: #if 0 gSubMenuSelection = RADIO_FindNextChannel(gEeprom.MrChannel[0], 1, false, 1); #else gSubMenuSelection = RADIO_FindNextChannel(gEeprom.MrChannel[gEeprom.TX_VFO], 1, false, 1); #endif break; // case MENU_350TX: // gSubMenuSelection = gSetting_350TX; // break; case MENU_F_LOCK: gSubMenuSelection = gSetting_F_LOCK; break; // case MENU_200TX: // gSubMenuSelection = gSetting_200TX; // break; // // case MENU_500TX: // gSubMenuSelection = gSetting_500TX; // break; // // case MENU_350EN: // gSubMenuSelection = gSetting_350EN; // break; // case MENU_SCREN: // gSubMenuSelection = gSetting_ScrambleEnable; // break; #ifdef ENABLE_F_CAL_MENU case MENU_F_CALI: gSubMenuSelection = gEeprom.BK4819_XTAL_FREQ_LOW; break; #endif case MENU_BATCAL: gSubMenuSelection = gBatteryCalibration[3]; break; case MENU_BATTYP: gSubMenuSelection = gEeprom.BATTERY_TYPE; break; #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS case MENU_F1SHRT: case MENU_F1LONG: case MENU_F2SHRT: case MENU_F2LONG: case MENU_MLONG: { uint8_t *fun[] = { &gEeprom.KEY_1_SHORT_PRESS_ACTION, &gEeprom.KEY_1_LONG_PRESS_ACTION, &gEeprom.KEY_2_SHORT_PRESS_ACTION, &gEeprom.KEY_2_LONG_PRESS_ACTION, &gEeprom.KEY_M_LONG_PRESS_ACTION }; uint8_t id = *fun[UI_MENU_GetCurrentMenuId() - MENU_F1SHRT]; for (int i = 0; i < gSubMenu_SIDEFUNCTIONS_size; i++) { if (gSubMenu_SIDEFUNCTIONS[i].id == id) { gSubMenuSelection = i; break; } } break; } #endif default: return; } } static void MENU_Key_0_to_9(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { uint8_t Offset; int32_t Min; int32_t Max; uint16_t Value = 0; if (bKeyHeld || !bKeyPressed) return; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; uint8_t now_menu = UI_MENU_GetCurrentMenuId(); #ifdef ENABLE_MDC1200_EDIT //뷨 uint8_t end_index = now_menu == MENU_MEM_NAME ? MAX_EDIT_INDEX : 4; #else uint8_t end_index = MAX_EDIT_INDEX; #endif if ((now_menu == MENU_MEM_NAME //뷨 #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT || now_menu == MENU_MDC_ID #endif #endif ) && edit_index >= 0) { // currently editing the channel name if (edit_index < end_index) { if (Key <= KEY_9) { { #ifdef ENABLE_PINYIN #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT if (now_menu == MENU_MEM_NAME) { #endif #endif if (INPUT_MODE == 0) { //ƴ if (Key >= 2 && PINYIN_CODE_INDEX && INPUT_STAGE <= 1) { uint32_t tmp = PINYIN_CODE; PINYIN_CODE += Key * PINYIN_CODE_INDEX; PINYIN_CODE_INDEX /= 10; PINYIN_SOLVE(tmp); // if(end_index>100)end_index=0; } else if (INPUT_STAGE == 2) { uint8_t SHOW_NUM = CHN_NOW_NUM - CHN_NOW_PAGE * 6 > 6 ? 6 : CHN_NOW_NUM - CHN_NOW_PAGE * 6; if (Key > 0 && Key <= SHOW_NUM) { if (edit_chn[edit_index + 1] == 1)edit[edit_index + 2] = '_'; EEPROM_ReadBuffer(CHN_NOW_ADD + CHN_NOW_PAGE * 6 * 2 + 2 * (Key - 1), &edit[edit_index], 2); edit_index += 2; PINYIN_NUM_SELECT = 0; PINYIN_CODE = 0; PINYIN_SEARCH_MODE = 0; INPUT_STAGE = 0; CHN_NOW_PAGE = 0; PINYIN_CODE_INDEX = 100000; if (edit_index >= end_index) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } } } } else if (INPUT_MODE == 1) { if (INPUT_STAGE == 0) { if (Key >= KEY_2) { //ѡĸ INPUT_STAGE = 1; INPUT_SELECT = Key; } } else { if (Key >= 1 && Key <= 2 *num_size[INPUT_SELECT - 2]) {//ѡĸ if (edit_chn[edit_index] == 1) edit[edit_index+1] = '_'; if (Key > num_size[INPUT_SELECT - 2]) edit[edit_index] = num_excel[INPUT_SELECT - 2][Key - 1 - num_size[INPUT_SELECT - 2]] - 32; else edit[edit_index] = num_excel[INPUT_SELECT - 2][Key - 1]; if (++edit_index >= end_index) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } INPUT_STAGE = 0; } } } else if (INPUT_MODE == 2) { if (edit_chn[edit_index])edit[edit_index + 1] = '_'; edit[edit_index] = '0' + Key; if (++edit_index >= end_index) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } } #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT } else { edit[edit_index] = '0' + Key ; if (++edit_index >= end_index) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } } #endif #endif #else edit[edit_index] = '0' + Key ; if (++edit_index >= end_index) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } #endif } gRequestDisplayScreen = DISPLAY_MENU; } } return; } INPUTBOX_Append(Key); gRequestDisplayScreen = DISPLAY_MENU; if (!gIsInSubMenu) { switch (gInputBoxIndex) { case 2: gInputBoxIndex = 0; Value = (gInputBox[0] * 10) + gInputBox[1]; if (Value > 0 && Value <= gMenuListCount) { gMenuCursor = Value - 1; #ifndef ENABLE_MDC1200 if (gMenuCursor + 1 >= 26)gMenuCursor++; #endif gFlagRefreshSetting = true; return; } if (Value <= gMenuListCount) break; gInputBox[0] = gInputBox[1]; gInputBoxIndex = 1; [[fallthrough]]; case 1: Value = gInputBox[0]; if (Value > 0 && Value <= gMenuListCount) { gMenuCursor = Value - 1; #ifndef ENABLE_MDC1200 if (gMenuCursor + 1 >= 26)gMenuCursor++; #endif gFlagRefreshSetting = true; return; } break; } gInputBoxIndex = 0; gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (UI_MENU_GetCurrentMenuId() == MENU_OFFSET) { uint32_t Frequency; if (gInputBoxIndex < 6) { // invalid frequency #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif return; } #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif Frequency = StrToUL(INPUTBOX_GetAscii()) * 100; gSubMenuSelection = FREQUENCY_RoundToStep(Frequency, gTxVfo->StepFrequency); gInputBoxIndex = 0; return; } if (UI_MENU_GetCurrentMenuId() == MENU_MEM_CH || UI_MENU_GetCurrentMenuId() == MENU_DEL_CH || UI_MENU_GetCurrentMenuId() == MENU_1_CALL || UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) { // enter 3-digit channel number if (gInputBoxIndex < 3) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gRequestDisplayScreen = DISPLAY_MENU; return; } gInputBoxIndex = 0; Value = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1; if (IS_MR_CHANNEL(Value)) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gSubMenuSelection = Value; return; } gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) { gInputBoxIndex = 0; gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } Offset = (Max >= 100) ? 3 : (Max >= 10) ? 2 : 1; switch (gInputBoxIndex) { case 1: Value = gInputBox[0]; break; case 2: Value = (gInputBox[0] * 10) + gInputBox[1]; break; case 3: Value = (gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]; break; } if (Offset == gInputBoxIndex) gInputBoxIndex = 0; if (Value <= Max) { gSubMenuSelection = Value; return; } gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } static void MENU_Key_EXIT(bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) return; if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && gIsInSubMenu == true && edit_index >= 0&&gAskForConfirmation == 0) { #ifdef ENABLE_PINYIN if (INPUT_MODE == 0) { if (INPUT_STAGE == 1 && PINYIN_CODE > 0) { if (PINYIN_CODE_INDEX != 0) { PINYIN_CODE = PINYIN_CODE / (PINYIN_CODE_INDEX * 100) * (PINYIN_CODE_INDEX * 100); PINYIN_CODE_INDEX *= 10; } else { PINYIN_CODE = PINYIN_CODE - PINYIN_CODE % 10; PINYIN_CODE_INDEX = 1; } uint32_t tmp = PINYIN_CODE; PINYIN_SEARCH_MODE=0; PINYIN_NUM_SELECT = 0; PINYIN_SOLVE(tmp); if (PINYIN_CODE == 0) { INPUT_STAGE = 0; } } else if (INPUT_STAGE == 2) { INPUT_STAGE = 1; } else edit_index = -1; } else if (INPUT_MODE == 1) { if (INPUT_STAGE == 1)INPUT_STAGE = 0; else edit_index = -1; } else #endif edit_index = -1; return; } #ifdef ENABLE_PINYIN // if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && gAskForConfirmation == 0) { //뷨exit // // // } #endif gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; if (!gCssBackgroundScan) { /* Backlight related menus set full brightness. Set it back to the configured value, just in case we are exiting from one of them. */ BACKLIGHT_TurnOn(); if (gIsInSubMenu) { if (gInputBoxIndex == 0 || UI_MENU_GetCurrentMenuId() != MENU_OFFSET) { gAskForConfirmation = 0; gIsInSubMenu = false; gInputBoxIndex = 0; gFlagRefreshSetting = true; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif } else gInputBox[--gInputBoxIndex] = 10; // *********************** gRequestDisplayScreen = DISPLAY_MENU; return; } #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif gRequestDisplayScreen = DISPLAY_MAIN; if (gEeprom.BACKLIGHT_TIME == 0) // backlight set to always off { BACKLIGHT_TurnOff(); // turn the backlight OFF } } else { MENU_StopCssScan(); #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_STOP; #endif gRequestDisplayScreen = DISPLAY_MENU; } gPttWasReleased = true; } #ifdef ENABLE_PINYIN void UPDATE_CHN() { uint8_t tmp[5]; EEPROM_ReadBuffer(PINYIN_NOW_INDEX * 128 + 0X20000 + 16 + PINYIN_NUM_SELECT * 16 + 6, tmp, 5); CHN_NOW_ADD = tmp[1] | tmp[2] << 8 | tmp[3] << 16 | tmp[4] << 24; CHN_NOW_NUM = tmp[0]; CHN_NOW_PAGE = 0; } #endif static void MENU_Key_MENU(const bool bKeyPressed, const bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) return; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; gRequestDisplayScreen = DISPLAY_MENU; #ifdef ENABLE_PINYIN if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) { if (edit_index == -1) { //뷨ʼmenu INPUT_MODE = 0; INPUT_SELECT = 0; INPUT_STAGE = 0; INPUT_MODE_LAST = 0; PINYIN_CODE = 0; PINYIN_CODE_INDEX = 100000; } if (gIsInSubMenu) { if (INPUT_MODE == 0) { if (PINYIN_CODE && PINYIN_SEARCH_MODE == 0)return; if (PINYIN_SEARCH_MODE == 1) { if (INPUT_STAGE == 1) { PINYIN_NUM_SELECT = 0; INPUT_STAGE = 2; UPDATE_CHN(); return; } else if (INPUT_STAGE == 2) { if (PINYIN_NUM_SELECT < PINYIN_SEARCH_NUM - 1)PINYIN_NUM_SELECT++; else PINYIN_NUM_SELECT = 0; UPDATE_CHN(); return; } } } else if (INPUT_MODE == 3) { INPUT_MODE = INPUT_MODE_LAST; } } } #endif if (!gIsInSubMenu) { #ifdef ENABLE_VOICE if (UI_MENU_GetCurrentMenuId() != MENU_SCR) gAnotherVoiceID = MenuList[gMenuCursor].voice_id; #endif if (UI_MENU_GetCurrentMenuId() == MENU_DEL_CH || UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) // if (!RADIO_CheckValidChannel(gSubMenuSelection, false, 0)) // return; // invalid channel { uint8_t before=gSubMenuSelection; while(!RADIO_CheckValidChannel(gSubMenuSelection, false, 0)) { gSubMenuSelection++; if (gSubMenuSelection==before) return; // invalid channel else if(gSubMenuSelection==MR_CHANNEL_LAST)gSubMenuSelection=0; } } if (UI_MENU_GetCurrentMenuId() == MENU_UPCODE || UI_MENU_GetCurrentMenuId() == MENU_DWCODE #ifdef ENABLE_DTMF_CALLING || UI_MENU_GetCurrentMenuId() == MENU_ANI_ID #endif #ifndef ENABLE_MDC1200_EDIT || UI_MENU_GetCurrentMenuId() == MENU_MDC_ID #endif ) return; // invalid gAskForConfirmation = 0; gIsInSubMenu = true; // if (UI_MENU_GetCurrentMenuId() != MENU_D_LIST) { gInputBoxIndex = 0; edit_index = -1; } #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID) { edit_index = 0; memmove(edit_original, edit, sizeof(edit_original)); } #endif #endif return; } #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID && edit_index < 4) { // editing the channel name characters if (++edit_index < 4) return; // exit if (memcmp(edit_original, edit, sizeof(edit_original)) == 0) { // no change - drop it gIsInSubMenu = false; } //gFlagAcceptSetting = false; gAskForConfirmation = 0; } #endif #endif if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) { //뷨MENU if (edit_index < 0) { // enter channel name edit mode if (!RADIO_CheckValidChannel(gSubMenuSelection, false, 0)) return; SETTINGS_FetchChannelName(edit, gSubMenuSelection); // pad the channel name out with '_' edit_index = strlen(edit); while (edit_index < MAX_EDIT_INDEX)edit[edit_index++] = '_'; edit[edit_index] = 0; edit_index = 0; // 'edit_index' is going to be used as the cursor position memcpy(edit_original, edit, sizeof(edit_original)); return; } else if (edit_index >= 0 && edit_index < MAX_EDIT_INDEX) { // editing the channel name characters #ifdef ENABLE_PINYIN if (edit_chn[edit_index] == 1) edit_index++; #endif edit_index++; #ifdef ENABLE_PINYIN if (INPUT_MODE == 3)INPUT_MODE = INPUT_MODE_LAST; #endif if (edit_index < MAX_EDIT_INDEX) { #ifdef ENABLE_PINYIN if (INPUT_MODE == 0 && edit_index + 1 >= MAX_EDIT_INDEX) INPUT_MODE = 1; #endif return; } // exit if (memcmp(edit_original, edit, sizeof(edit_original)) == 0) { // no change - drop it gIsInSubMenu = false; } //gFlagAcceptSetting = false; gAskForConfirmation = 0; } } #ifdef ENABLE_PINYIN //˳ģʽ // PINYIN_MODE=0; #endif // exiting the sub menu if (gIsInSubMenu) { if (UI_MENU_GetCurrentMenuId() == MENU_RESET || UI_MENU_GetCurrentMenuId() == MENU_MEM_CH || UI_MENU_GetCurrentMenuId() == MENU_DEL_CH || UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT || UI_MENU_GetCurrentMenuId() == MENU_MDC_ID #endif #endif ) { switch (gAskForConfirmation) { case 0: gAskForConfirmation = 1; break; case 1: gAskForConfirmation = 2; UI_DisplayMenu(); if (UI_MENU_GetCurrentMenuId() == MENU_RESET) { #ifdef ENABLE_VOICE AUDIO_SetVoiceID(0, VOICE_ID_CONFIRM); AUDIO_PlaySingleVoice(true); #endif MENU_AcceptSetting(); #if defined(ENABLE_OVERLAY) overlay_FLASH_RebootToBootloader(); #else NVIC_SystemReset(); #endif } gFlagAcceptSetting = true; gIsInSubMenu = false; gAskForConfirmation = 0; } } else { gFlagAcceptSetting = true; gIsInSubMenu = false; } } SCANNER_Stop(); #ifdef ENABLE_VOICE if (UI_MENU_GetCurrentMenuId() == MENU_SCR) gAnotherVoiceID = (gSubMenuSelection == 0) ? VOICE_ID_SCRAMBLER_OFF : VOICE_ID_SCRAMBLER_ON; else gAnotherVoiceID = VOICE_ID_CONFIRM; #endif gInputBoxIndex = 0; } static void MENU_Key_STAR(const bool bKeyPressed, const bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) return; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; //뷨ģʽл if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && edit_index >= 0) { // currently editing the channel name if (edit_index < MAX_EDIT_INDEX) { #ifndef ENABLE_PINYIN edit[edit_index] = '-'; if (++edit_index >= MAX_EDIT_INDEX) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } #else //뷨ģʽл INPUT_MODE++; if (INPUT_MODE >= 3)INPUT_MODE = 0; if (INPUT_MODE == 0 && edit_index + 1 >= MAX_EDIT_INDEX) INPUT_MODE = 1; if (INPUT_MODE == 0) { PINYIN_CODE = 0; PINYIN_CODE_INDEX = 100000; } INPUT_STAGE = 0; #endif gRequestDisplayScreen = DISPLAY_MENU; } return; } RADIO_SelectVfos(); #ifdef ENABLE_NOAA if (!IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gRxVfo->Modulation == MODULATION_FM) #else if (gRxVfo->Modulation == MODULATION_FM) #endif { if ((UI_MENU_GetCurrentMenuId() == MENU_R_CTCS || UI_MENU_GetCurrentMenuId() == MENU_R_DCS) && gIsInSubMenu) { // scan CTCSS or DCS to find the tone/code of the incoming signal if (!SCANNER_IsScanning()) MENU_StartCssScan(); else MENU_StopCssScan(); } gPttWasReleased = true; return; } gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } static void MENU_Key_UP_DOWN(bool bKeyPressed, bool bKeyHeld, int8_t Direction) { uint8_t VFO; uint8_t Channel; bool bCheckScanList; if (gIsInSubMenu && edit_index >= 0) { //뷨UP DOWN if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) { // change the character if (bKeyPressed && edit_index < MAX_EDIT_INDEX) { #ifdef ENABLE_PINYIN//ƴ if (INPUT_MODE == 0) { if (INPUT_STAGE == 2) { if (PINYIN_SEARCH_MODE == 1)//׼ȷ { if (Direction == 1) { if (CHN_NOW_PAGE) CHN_NOW_PAGE--; } else if (Direction == -1) { if ((CHN_NOW_PAGE + 1) * 6 < CHN_NOW_NUM)CHN_NOW_PAGE++; } return; } } } if (((INPUT_MODE == 0 || INPUT_MODE == 1) && INPUT_STAGE == 0) || INPUT_MODE == 2 || INPUT_MODE == 3) { INPUT_MODE_LAST = INPUT_MODE; INPUT_MODE = 3; if (edit_chn[edit_index]) { edit[edit_index + 1] = '_'; edit[edit_index] = '_'; } char c = edit[edit_index] + Direction; while (c >= 32 && c <= 126) { if ((c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z' )|| ( c >= '0' && c <= '9')) { // choose next character c += Direction; } else break; } edit[edit_index] = ((uint8_t) c < 32) ? 126 : ((uint8_t) c > 126) ? 32 : c; } #else if (isChineseChar(edit[edit_index], edit_index, MAX_EDIT_INDEX)) { edit[edit_index + 1] = '_'; edit[edit_index] = '_'; } const char unwanted[] = "$%&!\"':;?^`|{}"; char c = edit[edit_index] + Direction; unsigned int i = 0; while (i < sizeof(unwanted) && c >= 32 && c <= 126) { if (c == unwanted[i++]) { // choose next character c += Direction; i = 0; } } edit[edit_index] = ((uint8_t) c < 32) ? 126 : ((uint8_t) c > 126) ? 32 : c; #endif gRequestDisplayScreen = DISPLAY_MENU; } return; } #ifdef ENABLE_MDC1200 #ifdef ENABLE_MDC1200_EDIT if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID) { if (bKeyPressed && edit_index < 4) { char c = edit[edit_index] + Direction; if (c < '0')c = 'F'; else if (c > 'F')c = '0'; else if (c > '9' && c < 'A') { if (Direction == 1)c = 'A'; else c = '9'; } edit[edit_index] = c; gRequestDisplayScreen = DISPLAY_MENU; } return; } #endif #endif } if (!bKeyHeld) { if (!bKeyPressed) return; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; gInputBoxIndex = 0; } else if (!bKeyPressed) return; if (SCANNER_IsScanning()) { return; } if (!gIsInSubMenu) { #ifndef ENABLE_MDC1200 uint8_t last_num = gMenuCursor; #endif gMenuCursor = NUMBER_AddWithWraparound(gMenuCursor, key_dir * Direction, 0, gMenuListCount - 1); #ifndef ENABLE_MDC1200 if (last_num + 1 < 26 && gMenuCursor + 1 == 26)gMenuCursor++; else if (last_num + 1 == 27 && gMenuCursor + 1 == 26)gMenuCursor--; #endif gFlagRefreshSetting = true; gRequestDisplayScreen = DISPLAY_MENU; if (UI_MENU_GetCurrentMenuId() != MENU_ABR && UI_MENU_GetCurrentMenuId() != MENU_ABR_MAX && gEeprom.BACKLIGHT_TIME == 0) // backlight always off and not in the backlight menu { BACKLIGHT_TurnOff(); } return; } if (UI_MENU_GetCurrentMenuId() == MENU_OFFSET) { int32_t Offset = (Direction * gTxVfo->StepFrequency) + gSubMenuSelection; if (Offset < 99999990) { if (Offset < 0) Offset = 99999990; } else Offset = 0; gSubMenuSelection = FREQUENCY_RoundToStep(Offset, gTxVfo->StepFrequency); gRequestDisplayScreen = DISPLAY_MENU; return; } VFO = 0; switch (UI_MENU_GetCurrentMenuId()) { case MENU_DEL_CH: case MENU_1_CALL: case MENU_MEM_NAME: bCheckScanList = false; break; case MENU_SLIST2: VFO = 1; [[fallthrough]]; case MENU_SLIST1: bCheckScanList = true; break; default: MENU_ClampSelection(Direction); gRequestDisplayScreen = DISPLAY_MENU; return; } Channel = RADIO_FindNextChannel(gSubMenuSelection + Direction, Direction, bCheckScanList, VFO); if (Channel != 0xFF) gSubMenuSelection = Channel; gRequestDisplayScreen = DISPLAY_MENU; } void MENU_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { switch (Key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: MENU_Key_0_to_9(Key, bKeyPressed, bKeyHeld); break; case KEY_MENU: MENU_Key_MENU(bKeyPressed, bKeyHeld); break; case KEY_UP: MENU_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1); break; case KEY_DOWN: MENU_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1); break; case KEY_EXIT: MENU_Key_EXIT(bKeyPressed, bKeyHeld); break; case KEY_STAR: MENU_Key_STAR(bKeyPressed, bKeyHeld); break; case KEY_F: if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && //뷨 edit_index >= 0) { // currently editing the channel name if (!bKeyHeld && bKeyPressed) { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; #ifdef ENABLE_PINYIN bool flag_space = true; if ((INPUT_MODE == 0 && INPUT_STAGE > 0 )|| (INPUT_MODE == 1 && INPUT_STAGE > 0))flag_space = false; #endif if (edit_index < MAX_EDIT_INDEX #ifdef ENABLE_PINYIN && flag_space #endif ) { #ifdef ENABLE_PINYIN if (edit_chn[edit_index]) { edit[edit_index + 1] = '_'; } #endif edit[edit_index] = ' '; if (++edit_index >= MAX_EDIT_INDEX) { // exit edit //gFlagAcceptSetting = false; gAskForConfirmation = 1; } gRequestDisplayScreen = DISPLAY_MENU; } } break; } GENERIC_Key_F(bKeyPressed, bKeyHeld); break; case KEY_PTT: GENERIC_Key_PTT(bKeyPressed); break; default: if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; } if (gScreenToDisplay == DISPLAY_MENU) { if (/*UI_MENU_GetCurrentMenuId() == MENU_VOL||*/ #ifdef ENABLE_F_CAL_MENU UI_MENU_GetCurrentMenuId() == MENU_F_CALI|| #endif UI_MENU_GetCurrentMenuId() == MENU_BATCAL ) { gMenuCountdown = menu_timeout_long_500ms; } else { gMenuCountdown = menu_timeout_500ms; } } } ================================================ FILE: app/menu.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_MENU_H #define APP_MENU_H #include "driver/keyboard.h" #ifdef ENABLE_F_CAL_MENU void writeXtalFreqCal(const int32_t value, const bool update_eeprom); #endif //extern uint8_t gUnlockAllTxConfCnt; int MENU_GetLimits(uint8_t menu_id, int32_t *pMin, int32_t *pMax); void MENU_AcceptSetting(void); void MENU_ShowCurrentSetting(void); void MENU_StartCssScan(void); void MENU_CssScanFound(void); void MENU_StopCssScan(void); void MENU_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); #endif ================================================ FILE: app/messenger.c ================================================ #include "app/mdc1200.h" #include #include "driver/keyboard.h" #include "driver/st7565.h" #include "driver/bk4819.h" #include "external/printf/printf.h" #include "misc.h" #include "settings.h" #include "radio.h" #include "app.h" #include "audio.h" #include "functions.h" #include "frequencies.h" #include "driver/system.h" #include "app/messenger.h" #include "ui/ui.h" #include "driver/uart.h" #include "stdbool.h" #if defined(ENABLE_UART) #include "driver/uart.h" #endif #ifdef ENABLE_MESSENGER bool stop_mdc_flag=0; //bool stop_mdc_rx=0; const uint8_t MSG_BUTTON_STATE_HELD = 1 << 1; const uint8_t MSG_BUTTON_EVENT_SHORT = 0; const uint8_t MSG_BUTTON_EVENT_LONG = MSG_BUTTON_STATE_HELD; const uint8_t MAX_MSG_LENGTH = TX_MSG_LENGTH - 1; const uint16_t TONE2_FREQ = 0x3065; // 0x2854 #define NEXT_CHAR_DELAY 100 // 10ms tick char T9TableLow[9][4] = { {',', '.', '?', '!'}, {'a', 'b', 'c', '\0'}, {'d', 'e', 'f', '\0'}, {'g', 'h', 'i', '\0'}, {'j', 'k', 'l', '\0'}, {'m', 'n', 'o', '\0'}, {'p', 'q', 'r', 's'}, {'t', 'u', 'v', '\0'}, {'w', 'x', 'y', 'z'} }; char T9TableUp[9][4] = { {',', '.', '?', '!'}, {'A', 'B', 'C', '\0'}, {'D', 'E', 'F', '\0'}, {'G', 'H', 'I', '\0'}, {'J', 'K', 'L', '\0'}, {'M', 'N', 'O', '\0'}, {'P', 'Q', 'R', 'S'}, {'T', 'U', 'V', '\0'}, {'W', 'X', 'Y', 'Z'} }; unsigned char numberOfLettersAssignedToKey[9] = { 4, 3, 3, 3, 3, 3, 4, 3, 4 }; char T9TableNum[9][4] = { {'1', '\0', '\0', '\0'}, {'2', '\0', '\0', '\0'}, {'3', '\0', '\0', '\0'}, {'4', '\0', '\0', '\0'}, {'5', '\0', '\0', '\0'}, {'6', '\0', '\0', '\0'}, {'7', '\0', '\0', '\0'}, {'8', '\0', '\0', '\0'}, {'9', '\0', '\0', '\0'} }; unsigned char numberOfNumsAssignedToKey[9] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 }; char cMessage[TX_MSG_LENGTH]; char lastcMessage[TX_MSG_LENGTH]; char rxMessage[4][MAX_RX_MSG_LENGTH + 2]; unsigned char cIndex = 0; unsigned char prevKey = 0, prevLetter = 0; KeyboardType keyboardType = UPPERCASE; MsgStatus msgStatus = READY; uint8_t msgFSKBuffer[MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH]; uint16_t gErrorsDuringMSG; uint8_t hasNewMessage = 0; uint8_t keyTickCounter = 0; // ----------------------------------------------------- void MSG_FSKSendData() { uint16_t fsk_reg59; // REG_51 // // <15> TxCTCSS/CDCSS 0 = disable 1 = Enable // // turn off CTCSS/CDCSS during FFSK const uint16_t css_val = BK4819_ReadRegister(BK4819_REG_51); BK4819_WriteRegister(BK4819_REG_51, 0); // set the FM deviation level const uint16_t dev_val = BK4819_ReadRegister(BK4819_REG_40); //UART_printf("\n BANDWIDTH : 0x%.4X", dev_val); { uint16_t deviation = 850; switch (gEeprom.VfoInfo[gEeprom.TX_VFO].CHANNEL_BANDWIDTH) { case BK4819_FILTER_BW_WIDE: deviation = 1050; break; case BK4819_FILTER_BW_NARROW: deviation = 850; break; case BK4819_FILTER_BW_NARROWER: deviation = 750; break; } //BK4819_WriteRegister(0x40, (3u << 12) | (deviation & 0xfff)); BK4819_WriteRegister(BK4819_REG_40, (dev_val & 0xf000) | (deviation & 0xfff)); } // REG_2B 0 // // <15> 1 Enable CTCSS/CDCSS DC cancellation after FM Demodulation 1 = enable 0 = disable // <14> 1 Enable AF DC cancellation after FM Demodulation 1 = enable 0 = disable // <10> 0 AF RX HPF 300Hz filter 0 = enable 1 = disable // <9> 0 AF RX LPF 3kHz filter 0 = enable 1 = disable // <8> 0 AF RX de-emphasis filter 0 = enable 1 = disable // <2> 0 AF TX HPF 300Hz filter 0 = enable 1 = disable // <1> 0 AF TX LPF filter 0 = enable 1 = disable // <0> 0 AF TX pre-emphasis filter 0 = enable 1 = disable // // disable the 300Hz HPF and FM pre-emphasis filter // const uint16_t filt_val = BK4819_ReadRegister(BK4819_REG_2B); BK4819_WriteRegister(BK4819_REG_2B, (1u << 2) | (1u << 0)); // ******************************************* // setup the FFSK modem as best we can // Uses 1200/1800 Hz FSK tone frequencies 1200 bits/s // BK4819_WriteRegister(BK4819_REG_58, // 0x37C3); // 001 101 11 11 00 001 1 (1u << 13) | // 1 FSK TX mode selection // 0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM // 1 = FFSK 1200/1800 TX // 2 = ??? // 3 = FFSK 1200/2400 TX // 4 = ??? // 5 = NOAA SAME TX // 6 = ??? // 7 = ??? // (7u << 10) | // 0 FSK RX mode selection // 0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM // 1 = ??? // 2 = ??? // 3 = ??? // 4 = FFSK 1200/2400 RX // 5 = ??? // 6 = ??? // 7 = FFSK 1200/1800 RX // (0u << 8) | // 0 FSK RX gain // 0 ~ 3 // (0u << 6) | // 0 ??? // 0 ~ 3 // (0u << 4) | // 0 FSK preamble type selection // 0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0 // 1 = ??? // 2 = 0x55 // 3 = 0xAA // (1u << 1) | // 1 FSK RX bandwidth setting // 0 = FSK 1.2K .. no tones, direct FM // 1 = FFSK 1200/1800 // 2 = NOAA SAME RX // 3 = ??? // 4 = FSK 2.4K and FFSK 1200/2400 // 5 = ??? // 6 = ??? // 7 = ??? // (1u << 0)); // 1 FSK enable // 0 = disable // 1 = enable // REG_72 // // <15:0> 0x2854 TONE-2 / FSK frequency control word // = freq(Hz) * 10.32444 for XTAL 13M / 26M or // = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M // // tone-2 = 1200Hz // 18583,92 BK4819_WriteRegister(BK4819_REG_72, TONE2_FREQ); // REG_70 // // <15> 0 TONE-1 // 1 = enable // 0 = disable // // <14:8> 0 TONE-1 tuning // // <7> 0 TONE-2 // 1 = enable // 0 = disable // // <6:0> 0 TONE-2 / FSK tuning // 0 ~ 127 // // enable tone-2, set gain // BK4819_WriteRegister(BK4819_REG_70, // 0 0000000 1 1100000 ( 0u << 15) | // 0 ( 0u << 8) | // 0 ( 1u << 7) | // 1 (96u << 0)); // 96 // REG_59 // // <15> 0 TX FIFO 1 = clear // <14> 0 RX FIFO 1 = clear // <13> 0 FSK Scramble 1 = Enable // <12> 0 FSK RX 1 = Enable // <11> 0 FSK TX 1 = Enable // <10> 0 FSK data when RX 1 = Invert // <9> 0 FSK data when TX 1 = Invert // <8> 0 ??? // // <7:4> 0 FSK preamble length selection // 0 = 1 byte // 1 = 2 bytes // 2 = 3 bytes // 15 = 16 bytes // // <3> 0 FSK sync length selection // 0 = 2 bytes (FSK Sync Byte 0, 1) // 1 = 4 bytes (FSK Sync Byte 0, 1, 2, 3) // // <2:0> 0 ??? // fsk_reg59 = (0u << 15) | // 0/1 1 = clear TX FIFO (0u << 14) | // 0/1 1 = clear RX FIFO (0u << 13) | // 0/1 1 = scramble (0u << 12) | // 0/1 1 = enable RX (0u << 11) | // 0/1 1 = enable TX (0u << 10) | // 0/1 1 = invert data when RX (0u << 9) | // 0/1 1 = invert data when TX (0u << 8) | // 0/1 ??? (15u << 4) | // 0 ~ 15 preamble length .. bit toggling (1u << 3) | // 0/1 sync length (0u << 0); // 0 ~ 7 ??? // Set packet length (not including pre-amble and sync bytes that we can't seem to disable) BK4819_WriteRegister(BK4819_REG_5D, ((MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) << 8)); // REG_5A // // <15:8> 0x55 FSK Sync Byte 0 (Sync Byte 0 first, then 1,2,3) // <7:0> 0x55 FSK Sync Byte 1 // BK4819_WriteRegister(BK4819_REG_5A, 0x7240); // bytes 1 & 2 // REG_5B // // <15:8> 0x55 FSK Sync Byte 2 (Sync Byte 0 first, then 1,2,3) // <7:0> 0xAA FSK Sync Byte 3 // BK4819_WriteRegister(BK4819_REG_5B, 0x99a7); // bytes 2 & 3 // CRC setting (plus other stuff we don't know what) // // REG_5C // // <15:7> ??? // // <6> 1 CRC option enable 0 = disable 1 = enable // // <5:0> ??? // // disable CRC // // NB, this also affects TX pre-amble in some way // BK4819_WriteRegister(BK4819_REG_5C, 0x5625); // 010101100 0 100101 // BK4819_WriteRegister(0x5C, 0xAA30); // 101010100 0 110000 // BK4819_WriteRegister(0x5C, 0x0030); // 000000000 0 110000 BK4819_WriteRegister(BK4819_REG_59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's BK4819_WriteRegister(BK4819_REG_59, fsk_reg59); SYSTEM_DelayMs(100); { // load the entire packet data into the TX FIFO buffer const uint16_t len_buff = (MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH); for (size_t i = 0, j = 0; i < len_buff; i += 2, j++) { BK4819_WriteRegister(BK4819_REG_5F, (msgFSKBuffer[i + 1] << 8) | msgFSKBuffer[i]); } } // enable FSK TX BK4819_WriteRegister(BK4819_REG_59, (1u << 11) | fsk_reg59); { // allow up to 310ms for the TX to complete // if it takes any longer then somethings gone wrong, we shut the TX down unsigned int timeout = 1000 / 5; while (timeout-- > 0) { SYSTEM_DelayMs(5); if (BK4819_ReadRegister(BK4819_REG_0C) & (1u << 0)) { // we have interrupt flags BK4819_WriteRegister(BK4819_REG_02, 0); if (BK4819_ReadRegister(BK4819_REG_02) & BK4819_REG_02_FSK_TX_FINISHED) timeout = 0; // TX is complete } } } //BK4819_WriteRegister(BK4819_REG_02, 0); SYSTEM_DelayMs(100); // disable FSK BK4819_WriteRegister(BK4819_REG_59, fsk_reg59); // restore FM deviation level BK4819_WriteRegister(BK4819_REG_40, dev_val); // restore TX/RX filtering BK4819_WriteRegister(BK4819_REG_2B, filt_val); // restore the CTCSS/CDCSS setting BK4819_WriteRegister(BK4819_REG_51, css_val); } // ----------------------------------------------------- void moveUP(char (*rxMessages)[MAX_RX_MSG_LENGTH + 2]) { // Shift existing lines up strcpy(rxMessages[0], rxMessages[1]); strcpy(rxMessages[1], rxMessages[2]); strcpy(rxMessages[2], rxMessages[3]); // Insert the new line at the last position memset(rxMessages[3], 0, sizeof(rxMessages[3])); } void MSG_Send(const char *txMessage, bool bServiceMessage) { if ( msgStatus != READY ) return; stop_mdc_flag=1; if ( strlen(txMessage) > 0 && (TX_freq_check(gCurrentVfo->pTX->Frequency) == 0) ) { msgStatus = SENDING; RADIO_SetVfoState(VFO_STATE_NORMAL); BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, true); // memset(msgFSKBuffer, 0, sizeof(msgFSKBuffer)); // ? ToDo // first 20 byte sync, msg type and ID msgFSKBuffer[0] = 'M'; msgFSKBuffer[1] = 'S'; // next 20 for msg memcpy(msgFSKBuffer + 2, txMessage, TX_MSG_LENGTH); // CRC ? ToDo msgFSKBuffer[MAX_RX_MSG_LENGTH - 1] = '\0'; msgFSKBuffer[MAX_RX_MSG_LENGTH + 0] = 'I'; msgFSKBuffer[MAX_RX_MSG_LENGTH + 1] = 'D'; msgFSKBuffer[MAX_RX_MSG_LENGTH + 2] = '0'; msgFSKBuffer[(MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) - 1] = '#'; msgFSKBuffer[(MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) ] = '\0'; BK4819_DisableDTMF(); //RADIO_SetTxParameters(); FUNCTION_Select(FUNCTION_TRANSMIT); //SYSTEM_DelayMs(500); BK4819_PlayRogerNormal(); SYSTEM_DelayMs(100); BK4819_ExitTxMute(); MSG_FSKSendData(); //SYSTEM_DelayMs(100); APP_EndTransmission(true); //OK RADIO_SetVfoState(VFO_STATE_NORMAL); BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, false); enable_msg_rx(true); if (!bServiceMessage) { moveUP(rxMessage); sprintf(rxMessage[3], "> %s", txMessage); // memset(lastcMessage, 0, sizeof(lastcMessage)); memcpy(lastcMessage, txMessage, TX_MSG_LENGTH); lastcMessage[TX_MSG_LENGTH]=0; cIndex = 0; prevKey = 0; prevLetter = 0; memset(cMessage, 0, sizeof(cMessage)); // cMessage[0]='\0'; } msgStatus = READY; } #ifdef ENABLE_WARNING else { AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); } #endif stop_mdc_flag=0; } uint8_t validate_char( uint8_t rchar ) { if ( (rchar == 0x1b) || (rchar >= 32 && rchar <= 127) ) { return rchar; } return 32; } void MSG_Init() { memset(rxMessage, 0, sizeof(rxMessage)); // memset(cMessage, 0, sizeof(cMessage)); // memset(lastcMessage, 0, sizeof(lastcMessage)); lastcMessage[0]=0;cMessage[0]=0; hasNewMessage = 0; msgStatus = READY; prevKey = 0; prevLetter = 0; cIndex = 0; } // --------------------------------------------------------------------------------- void insertCharInMessage(uint8_t key) { if ( key == KEY_0 ) { if ( keyboardType == NUMERIC ) { cMessage[cIndex] = '0'; } else { cMessage[cIndex] = ' '; } if ( cIndex < MAX_MSG_LENGTH ) { cIndex++; } } else if (prevKey == key) { cIndex = (cIndex > 0) ? cIndex - 1 : 0; if ( keyboardType == NUMERIC ) { cMessage[cIndex] = T9TableNum[key - 1][(++prevLetter) % numberOfNumsAssignedToKey[key - 1]]; } else if ( keyboardType == LOWERCASE ) { cMessage[cIndex] = T9TableLow[key - 1][(++prevLetter) % numberOfLettersAssignedToKey[key - 1]]; } else { cMessage[cIndex] = T9TableUp[key - 1][(++prevLetter) % numberOfLettersAssignedToKey[key - 1]]; } if ( cIndex < MAX_MSG_LENGTH ) { cIndex++; } } else { prevLetter = 0; if ( cIndex >= MAX_MSG_LENGTH ) { cIndex = (cIndex > 0) ? cIndex - 1 : 0; } if ( keyboardType == NUMERIC ) { cMessage[cIndex] = T9TableNum[key - 1][prevLetter]; } else if ( keyboardType == LOWERCASE ) { cMessage[cIndex] = T9TableLow[key - 1][prevLetter]; } else { cMessage[cIndex] = T9TableUp[key - 1][prevLetter]; } if ( cIndex < MAX_MSG_LENGTH ) { cIndex++; } } cMessage[cIndex] = '\0'; if ( keyboardType == NUMERIC ) { prevKey = 0; prevLetter = 0; } else { prevKey = key; } } void processBackspace() { cIndex = (cIndex > 0) ? cIndex - 1 : 0; cMessage[cIndex] = '\0'; prevKey = 0; prevLetter = 0; } void MSG_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { uint8_t state = bKeyPressed + 2 * bKeyHeld; if (state == MSG_BUTTON_EVENT_SHORT) { switch (Key) { case KEY_0...KEY_9: if ( keyTickCounter > NEXT_CHAR_DELAY) { prevKey = 0; prevLetter = 0; } insertCharInMessage(Key); keyTickCounter = 0; break; case KEY_STAR: keyboardType = (KeyboardType)((keyboardType + 1) % END_TYPE_KBRD); break; case KEY_F: processBackspace(); break; case KEY_UP: // memset(cMessage, 0, sizeof(cMessage)); memcpy(cMessage, lastcMessage, TX_MSG_LENGTH); cMessage[TX_MSG_LENGTH]='\0'; cIndex = strlen(cMessage); break; /*case KEY_DOWN: break;*/ case KEY_MENU: // Send message MSG_Send(cMessage, false); break; case KEY_EXIT: gRequestDisplayScreen = DISPLAY_MAIN; break; default: #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); #endif break; } } else if (state == MSG_BUTTON_EVENT_LONG) { switch (Key) { case KEY_F: MSG_Init(); break; default: #ifdef ENABLE_WARNING AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL); #endif break; } } } #endif void solve_sign(const uint16_t interrupt_bits) { //const uint16_t rx_sync_flags = BK4819_ReadRegister(BK4819_REG_0B); const bool rx_sync = (interrupt_bits & BK4819_REG_02_FSK_RX_SYNC) ? true : false; const bool rx_fifo_almost_full = (interrupt_bits & BK4819_REG_02_FSK_FIFO_ALMOST_FULL) ? true : false; const bool rx_finished = (interrupt_bits & BK4819_REG_02_FSK_RX_FINISHED) ? true : false; const uint16_t rx_sync_flags = BK4819_ReadRegister(0x0B); #if defined(ENABLE_MDC1200)||defined(ENABLE_MESSENGER) const bool rx_sync_neg = (rx_sync_flags & (1u << 7)) ? true : false; #endif if (rx_sync) { #ifdef ENABLE_MESSENGER gFSKWriteIndex = 0; // memset(msgFSKBuffer, 0, sizeof(msgFSKBuffer)); msgStatus = RECEIVING; #endif #ifdef ENABLE_MDC1200 mdc1200_rx_buffer_index = 0; { // memset(mdc1200_rx_buffer, 0, sizeof(mdc1200_rx_buffer)); for (unsigned int i = 0; i < sizeof(mdc1200_sync_suc_xor); i++) mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = mdc1200_sync_suc_xor[i] ^ (rx_sync_neg ? 0xFF : 0x00); } #endif } if (rx_fifo_almost_full) { const uint16_t count = BK4819_ReadRegister(BK4819_REG_5E) & (7u << 0); // almost full threshold #if defined(ENABLE_MDC1200)||defined(ENABLE_MESSENGER) uint16_t read_reg[count]; #endif #ifdef ENABLE_MDC1200 { // fetch received packet data for (int i = 0; i < count; i++) { read_reg[i]=BK4819_ReadRegister(0x5F); const uint16_t word =read_reg[i] ^ (rx_sync_neg ? 0xFFFF : 0x0000); if (mdc1200_rx_buffer_index < sizeof(mdc1200_rx_buffer)) mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = (word >> 0) & 0xff; if (mdc1200_rx_buffer_index < sizeof(mdc1200_rx_buffer)) mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = (word >> 8) & 0xff; #ifdef ENABLE_MESSENGER if (gFSKWriteIndex < sizeof(msgFSKBuffer)) msgFSKBuffer[gFSKWriteIndex++] = validate_char((read_reg[i] >> 0) & 0xff); if (gFSKWriteIndex < sizeof(msgFSKBuffer)) msgFSKBuffer[gFSKWriteIndex++] = validate_char((read_reg[i] >> 8) & 0xff); #endif } #ifdef ENABLE_MESSENGER msgFSKBuffer[gFSKWriteIndex]='\0'; #endif if (mdc1200_rx_buffer_index >= sizeof(mdc1200_rx_buffer)) { if (MDC1200_process_rx_data( mdc1200_rx_buffer, mdc1200_rx_buffer_index, &mdc1200_op, &mdc1200_arg, &mdc1200_unit_id)) { mdc1200_rx_ready_tick_500ms = 2 * 5; // 6 second MDC display time gUpdateDisplay = true; } mdc1200_rx_buffer_index = 0; } } #endif } if (rx_finished) { const uint16_t fsk_reg59 = BK4819_ReadRegister(BK4819_REG_59) & ~((1u << 15) | (1u << 14) | (1u << 12) | (1u << 11)); BK4819_WriteRegister(BK4819_REG_59, (1u << 15) | (1u << 14) | fsk_reg59); BK4819_WriteRegister(BK4819_REG_59, (1u << 12) | fsk_reg59); #ifdef ENABLE_MESSENGER msgStatus = READY; // if (gFSKWriteIndex > 2) { // If there's three 0x1b bytes, then it's a service message if (msgFSKBuffer[2] == 0x1b && msgFSKBuffer[3] == 0x1b && msgFSKBuffer[4] == 0x1b) { #ifdef ENABLE_MESSENGER_DELIVERY_NOTIFICATION // If the next 4 bytes are "RCVD", then it's a delivery notification if (msgFSKBuffer[5] == 'R' && msgFSKBuffer[6] == 'C' && msgFSKBuffer[7] == 'V' && msgFSKBuffer[8] == 'D') { rxMessage[3][strlen(rxMessage[3])] = '+'; gUpdateStatus = true; gUpdateDisplay = true; } #endif } else { bool show_flag=0; if (msgFSKBuffer[0] == 'M' && msgFSKBuffer[1] == 'S') { moveUP(rxMessage); show_flag=1; snprintf(rxMessage[3], TX_MSG_LENGTH + 2, "< %s", &msgFSKBuffer[2]); MSG_Send("\x1b\x1b\x1bRCVD", true); } if(show_flag){ if ( gScreenToDisplay != DISPLAY_MSG ) { hasNewMessage = 1; gUpdateStatus = true; gUpdateDisplay = true; #ifdef ENABLE_MESSENGER_NOTIFICATION gPlayMSGRing = true; #endif } else { gUpdateDisplay = true; } } } // } gFSKWriteIndex = 0; #endif } } ================================================ FILE: app/messenger.h ================================================ #ifndef APP_MSG_H #define APP_MSG_H #include #include #include #include "driver/keyboard.h" #ifdef ENABLE_MESSENGER typedef enum KeyboardType { UPPERCASE, LOWERCASE, NUMERIC, END_TYPE_KBRD } KeyboardType; typedef enum MsgStatus { READY, SENDING, RECEIVING, } MsgStatus; enum { TX_MSG_LENGTH = 30, MSG_HEADER_LENGTH = 20, MAX_RX_MSG_LENGTH = TX_MSG_LENGTH + 2 }; //const uint8_t TX_MSG_LENGTH = 30; //const uint8_t MAX_RX_MSG_LENGTH = TX_MSG_LENGTH + 2; uint8_t validate_char( uint8_t rchar ) ; extern KeyboardType keyboardType; extern uint16_t gErrorsDuringMSG; extern char cMessage[TX_MSG_LENGTH]; extern char rxMessage[4][MAX_RX_MSG_LENGTH + 2]; extern uint8_t hasNewMessage; extern uint8_t keyTickCounter; void MSG_Init(); void MSG_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); void MSG_Send(const char *txMessage, bool bServiceMessage); extern unsigned char cIndex ; //extern bool stop_mdc_rx; extern uint8_t msgFSKBuffer[MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH]; void moveUP(char (*rxMessages)[MAX_RX_MSG_LENGTH + 2]) ; extern MsgStatus msgStatus ; extern bool stop_mdc_flag; #endif void solve_sign(const uint16_t interrupt_bits); #endif ================================================ FILE: app/scanner.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "app/app.h" #include "app/dtmf.h" #include "app/generic.h" #include "app/menu.h" #include "app/scanner.h" #include "audio.h" #include "driver/bk4819.h" #include "frequencies.h" #include "misc.h" #include "radio.h" #include "settings.h" #include "ui/inputbox.h" #include "ui/ui.h" DCS_CodeType_t gScanCssResultType; uint8_t gScanCssResultCode; #ifdef TEST_UNDE_CTCSS uint16_t gScanCssResultCode_all; #endif bool gScanSingleFrequency; // scan CTCSS/DCS codes for current frequency SCAN_SaveState_t gScannerSaveState; uint8_t gScanChannel; uint32_t gScanFrequency; SCAN_CssState_t gScanCssState; uint8_t gScanProgressIndicator; bool gScanUseCssResult; STEP_Setting_t stepSetting; uint8_t scanHitCount; static void SCANNER_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { if (!bKeyHeld && bKeyPressed) { if (gScannerSaveState == SCAN_SAVE_CHAN_SEL) { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; INPUTBOX_Append(Key); gRequestDisplayScreen = DISPLAY_SCANNER; if (gInputBoxIndex < 3) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif return; } gInputBoxIndex = 0; uint16_t chan = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1; if (IS_MR_CHANNEL(chan)) { #ifdef ENABLE_VOICE gAnotherVoiceID = (VOICE_ID_t)Key; #endif gShowChPrefix = RADIO_CheckValidChannel(chan, false, 0); gScanChannel = (uint8_t) chan; return; } } gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } } static void SCANNER_Key_EXIT(bool bKeyPressed, bool bKeyHeld) { if (!bKeyHeld && bKeyPressed) { // short pressed gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; switch (gScannerSaveState) { case SCAN_SAVE_NO_PROMPT: SCANNER_Stop(); gRequestDisplayScreen = DISPLAY_MAIN; break; case SCAN_SAVE_CHAN_SEL: if (gInputBoxIndex > 0) { gInputBox[--gInputBoxIndex] = 10; gRequestDisplayScreen = DISPLAY_SCANNER; break; } // Fallthrough case SCAN_SAVE_CHANNEL: gScannerSaveState = SCAN_SAVE_NO_PROMPT; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif gRequestDisplayScreen = DISPLAY_SCANNER; break; } } } static void SCANNER_Key_MENU(bool bKeyPressed, bool bKeyHeld) { if (bKeyHeld || !bKeyPressed) // ignore long press or release button events return; if (gScanCssState == SCAN_CSS_STATE_OFF && !gScanSingleFrequency) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (gScanCssState == SCAN_CSS_STATE_SCANNING && gScanSingleFrequency) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } if (gScanCssState == SCAN_CSS_STATE_FAILED) { gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; return; } gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; switch (gScannerSaveState) { case SCAN_SAVE_NO_PROMPT: if (!gScanSingleFrequency) { uint32_t freq250 = FREQUENCY_RoundToStep(gScanFrequency, 250); uint32_t freq625 = FREQUENCY_RoundToStep(gScanFrequency, 625); uint32_t diff250 = gScanFrequency > freq250 ? gScanFrequency - freq250 : freq250 - gScanFrequency; uint32_t diff625 = gScanFrequency > freq625 ? gScanFrequency - freq625 : freq625 - gScanFrequency; if (diff250 > diff625) { stepSetting = STEP_6_25kHz; gScanFrequency = freq625; } else { stepSetting = STEP_2_5kHz; gScanFrequency = freq250; } } if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) { gScannerSaveState = SCAN_SAVE_CHAN_SEL; gScanChannel = gTxVfo->CHANNEL_SAVE; gShowChPrefix = RADIO_CheckValidChannel(gTxVfo->CHANNEL_SAVE, false, 0); } else { gScannerSaveState = SCAN_SAVE_CHANNEL; } gScanCssState = SCAN_CSS_STATE_FOUND; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_MEMORY_CHANNEL; #endif gRequestDisplayScreen = DISPLAY_SCANNER; gUpdateStatus = true; break; case SCAN_SAVE_CHAN_SEL: if (gInputBoxIndex == 0) { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; gRequestDisplayScreen = DISPLAY_SCANNER; gScannerSaveState = SCAN_SAVE_CHANNEL; } break; case SCAN_SAVE_CHANNEL: if (!gScanSingleFrequency) { RADIO_InitInfo(gTxVfo, gTxVfo->CHANNEL_SAVE, gScanFrequency); if (gScanUseCssResult) { gTxVfo->freq_config_RX.CodeType = gScanCssResultType; gTxVfo->freq_config_RX.Code = gScanCssResultCode; } gTxVfo->freq_config_TX = gTxVfo->freq_config_RX; gTxVfo->STEP_SETTING = stepSetting; } else { RADIO_ConfigureChannel(0, VFO_CONFIGURE_RELOAD); RADIO_ConfigureChannel(1, VFO_CONFIGURE_RELOAD); gTxVfo->freq_config_RX.CodeType = gScanCssResultType; gTxVfo->freq_config_RX.Code = gScanCssResultCode; gTxVfo->freq_config_TX.CodeType = gScanCssResultType; gTxVfo->freq_config_TX.Code = gScanCssResultCode; } uint8_t chan; if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) { chan = gScanChannel; gEeprom.MrChannel[gEeprom.TX_VFO] = chan; } else { chan = gTxVfo->Band + FREQ_CHANNEL_FIRST; gEeprom.FreqChannel[gEeprom.TX_VFO] = chan; } gTxVfo->CHANNEL_SAVE = chan; gEeprom.ScreenChannel[gEeprom.TX_VFO] = chan; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CONFIRM; #endif gRequestDisplayScreen = DISPLAY_SCANNER; gRequestSaveChannel = 2; gScannerSaveState = SCAN_SAVE_NO_PROMPT; break; default: gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; break; } } static void SCANNER_Key_STAR(bool bKeyPressed, bool bKeyHeld) { if (!bKeyHeld && bKeyPressed) { gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; SCANNER_Start(gScanSingleFrequency); } return; } static void SCANNER_Key_UP_DOWN(bool bKeyPressed, bool pKeyHeld, int8_t Direction) { if (pKeyHeld) { if (!bKeyPressed) return; } else { if (!bKeyPressed) return; gInputBoxIndex = 0; gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL; } if (gScannerSaveState == SCAN_SAVE_CHAN_SEL) { gScanChannel = NUMBER_AddWithWraparound(gScanChannel, Direction, 0, MR_CHANNEL_LAST); gShowChPrefix = RADIO_CheckValidChannel(gScanChannel, false, 0); gRequestDisplayScreen = DISPLAY_SCANNER; } else gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; } void SCANNER_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) { switch (Key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: SCANNER_Key_DIGITS(Key, bKeyPressed, bKeyHeld); break; case KEY_MENU: SCANNER_Key_MENU(bKeyPressed, bKeyHeld); break; case KEY_UP: SCANNER_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1); break; case KEY_DOWN: SCANNER_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1); break; case KEY_EXIT: SCANNER_Key_EXIT(bKeyPressed, bKeyHeld); break; case KEY_STAR: SCANNER_Key_STAR(bKeyPressed, bKeyHeld); break; case KEY_PTT: GENERIC_Key_PTT(bKeyPressed); break; default: if (!bKeyHeld && bKeyPressed) gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL; break; } } void SCANNER_Start(bool singleFreq) { gScanSingleFrequency = singleFreq; gMonitor = false; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_SCANNING_BEGIN; #endif BK4819_StopScan(); RADIO_SelectVfos(); #ifdef ENABLE_NOAA if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) gRxVfo->CHANNEL_SAVE = FREQ_CHANNEL_FIRST + BAND6_400MHz; #endif uint8_t backupStep = gRxVfo->STEP_SETTING; uint16_t backupFrequency = gRxVfo->StepFrequency; RADIO_InitInfo(gRxVfo, gRxVfo->CHANNEL_SAVE, gRxVfo->pRX->Frequency); gRxVfo->STEP_SETTING = backupStep; gRxVfo->StepFrequency = backupFrequency; RADIO_SetupRegisters(true); #ifdef ENABLE_NOAA gIsNoaaMode = false; #endif if (gScanSingleFrequency) { gScanCssState = SCAN_CSS_STATE_SCANNING; gScanFrequency = gRxVfo->pRX->Frequency; stepSetting = gRxVfo->STEP_SETTING; BK4819_PickRXFilterPathBasedOnFrequency(gScanFrequency); BK4819_SetScanFrequency(gScanFrequency); gUpdateStatus = true; } else { gScanCssState = SCAN_CSS_STATE_OFF; gScanFrequency = 0xFFFFFFFF; BK4819_PickRXFilterPathBasedOnFrequency(gScanFrequency); BK4819_EnableFrequencyScan(); gUpdateStatus = true; } #ifdef ENABLE_DTMF_CALLING DTMF_clear_RX(); #endif gScanDelay_10ms = scan_delay_10ms; gScanCssResultCode = 0xFF; #ifdef TEST_UNDE_CTCSS gScanCssResultCode_all=0xffff; #endif gScanCssResultType = 0xFF; scanHitCount = 0; gScanUseCssResult = false; g_CxCSS_TAIL_Found = false; g_CDCSS_Lost = false; gCDCSSCodeType = 0; g_CTCSS_Lost = false; #ifdef ENABLE_VOX g_VOX_Lost = false; #endif g_SquelchLost = false; gScannerSaveState = SCAN_SAVE_NO_PROMPT; gScanProgressIndicator = 0; } void SCANNER_Stop(void) { if (SCANNER_IsScanning()) { gEeprom.CROSS_BAND_RX_TX = gBackup_CROSS_BAND_RX_TX; gVfoConfigureMode = VFO_CONFIGURE_RELOAD; gFlagResetVfos = true; gUpdateStatus = true; gCssBackgroundScan = false; gScanUseCssResult = false; #ifdef ENABLE_VOICE gAnotherVoiceID = VOICE_ID_CANCEL; #endif BK4819_StopScan(); } } void SCANNER_TimeSlice10ms(void) { if (!SCANNER_IsScanning()) return; if (gScanDelay_10ms > 0) { gScanDelay_10ms--; return; } if (gScannerSaveState != SCAN_SAVE_NO_PROMPT) { return; } switch (gScanCssState) { case SCAN_CSS_STATE_OFF: { // must be RF frequency scanning if we're here ? uint32_t result; if (!BK4819_GetFrequencyScanResult(&result)) break; int32_t delta = result - gScanFrequency; gScanFrequency = result; if (delta < 0) delta = -delta; if (delta < 100) scanHitCount++; else scanHitCount = 0; BK4819_DisableFrequencyScan(); if (scanHitCount < 3) { BK4819_EnableFrequencyScan(); } else { BK4819_SetScanFrequency(gScanFrequency); gScanCssResultCode = 0xFF; #ifdef TEST_UNDE_CTCSS gScanCssResultCode_all=0xffff; #endif gScanCssResultType = 0xFF; scanHitCount = 0; gScanUseCssResult = false; gScanProgressIndicator = 0; gScanCssState = SCAN_CSS_STATE_SCANNING; if (!gCssBackgroundScan) GUI_SelectNextDisplay(DISPLAY_SCANNER); gUpdateStatus = true; } gScanDelay_10ms = scan_delay_10ms; //gScanDelay_10ms = 1; // 10ms break; } case SCAN_CSS_STATE_SCANNING: { uint32_t cdcssFreq; uint16_t ctcssFreq; BK4819_CssScanResult_t scanResult = BK4819_GetCxCSSScanResult(&cdcssFreq, &ctcssFreq); if (scanResult == BK4819_CSS_RESULT_NOT_FOUND) break; BK4819_Disable(); if (scanResult == BK4819_CSS_RESULT_CDCSS) { const uint8_t Code = DCS_GetCdcssCode(cdcssFreq); if (Code != 0xFF) { gScanCssResultCode = Code; gScanCssResultType = CODE_TYPE_DIGITAL; gScanCssState = SCAN_CSS_STATE_FOUND; gScanUseCssResult = true; gUpdateStatus = true; } } else if (scanResult == BK4819_CSS_RESULT_CTCSS) { #ifdef TEST_UNDE_CTCSS const uint16_t Code = DCS_GetCtcssCode_ALL(ctcssFreq); #else const uint8_t Code = DCS_GetCtcssCode(ctcssFreq); #endif #ifdef TEST_UNDE_CTCSS if (Code != 0xFFFF) { if (Code == gScanCssResultCode_all && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) { #else if (Code != 0xFF) { if (Code == gScanCssResultCode && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) { #endif if (++scanHitCount >= 2) { gScanCssState = SCAN_CSS_STATE_FOUND; gScanUseCssResult = true; gUpdateStatus = true; } } else scanHitCount = 0; gScanCssResultType = CODE_TYPE_CONTINUOUS_TONE; #ifdef TEST_UNDE_CTCSS gScanCssResultCode_all = Code; #else gScanCssResultCode = Code; #endif } } // else if (scanResult == BK4819_CSS_RESULT_CTCSS) { // const uint8_t Code = DCS_GetCtcssCode(ctcssFreq); // if (Code != 0xFF) { // if (Code == gScanCssResultCode && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) { // if (++scanHitCount >= 2) { // gScanCssState = SCAN_CSS_STATE_FOUND; // gScanUseCssResult = true; // gUpdateStatus = true; // } // } // else // scanHitCount = 0; // // gScanCssResultType = CODE_TYPE_CONTINUOUS_TONE; // gScanCssResultCode = Code; // } // } if (gScanCssState < SCAN_CSS_STATE_FOUND) { // scanning or off BK4819_SetScanFrequency(gScanFrequency); gScanDelay_10ms = scan_delay_10ms; break; } if (gCssBackgroundScan) { gCssBackgroundScan = false; if (gScanUseCssResult) MENU_CssScanFound(); } else GUI_SelectNextDisplay(DISPLAY_SCANNER); break; } default: gCssBackgroundScan = false; break; } } void SCANNER_TimeSlice500ms(void) { if (SCANNER_IsScanning() && gScannerSaveState == SCAN_SAVE_NO_PROMPT && gScanCssState < SCAN_CSS_STATE_FOUND) { gScanProgressIndicator++; #ifndef ENABLE_NO_CODE_SCAN_TIMEOUT if (gScanProgressIndicator > 32) { if (gScanCssState == SCAN_CSS_STATE_SCANNING && !gScanSingleFrequency) gScanCssState = SCAN_CSS_STATE_FOUND; else gScanCssState = SCAN_CSS_STATE_FAILED; gUpdateStatus = true; } #endif gUpdateDisplay = true; } else if (gCssBackgroundScan) { gUpdateDisplay = true; } } bool SCANNER_IsScanning(void) { return gCssBackgroundScan || (gScreenToDisplay == DISPLAY_SCANNER); } ================================================ FILE: app/scanner.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_SCANNER_H #define APP_SCANNER_H #include "dcs.h" #include "driver/keyboard.h" typedef enum { SCAN_CSS_STATE_OFF, SCAN_CSS_STATE_SCANNING, SCAN_CSS_STATE_FOUND, SCAN_CSS_STATE_FAILED } SCAN_CssState_t; typedef enum { SCAN_SAVE_NO_PROMPT, // saving process not initiated SCAN_SAVE_CHAN_SEL, // "SAVE: ", channel select prompt, actives only in channel mode SCAN_SAVE_CHANNEL, // "SAVE?" prompt, waits for confirmation to save settings to channel, or current VFO } SCAN_SaveState_t; extern DCS_CodeType_t gScanCssResultType; extern uint8_t gScanCssResultCode; extern uint16_t gScanCssResultCode_all; extern bool gScanSingleFrequency; extern SCAN_SaveState_t gScannerSaveState; extern uint8_t gScanChannel; extern uint32_t gScanFrequency; extern SCAN_CssState_t gScanCssState; extern uint8_t gScanProgressIndicator; extern bool gScanUseCssResult; void SCANNER_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld); void SCANNER_Start(bool singleFreq); void SCANNER_Stop(void); void SCANNER_TimeSlice10ms(void); void SCANNER_TimeSlice500ms(void); bool SCANNER_IsScanning(void); #endif ================================================ FILE: app/si.c ================================================ #include "si.h" #include "../driver/bk4819.h" #include "../driver/si473x.h" #include "../helper/rds.h" #include "../misc.h" // // Created by RUPC on 2024/3/10. // #include "board.h" #include "driver/si473x.h" #include "bsp/dp32g030/gpio.h" #include "bsp/dp32g030/syscon.h" #include "driver/gpio.h" #include "driver/i2c.h" #include "driver/system.h" #include "frequencies.h" #include "misc.h" #include "ui/helper.h" #include #include "./si.h" #include "app/fm.h" #include "driver/st7565.h" #include "external/printf/printf.h" #include "misc.h" #include "settings.h" #include "ui/fmradio.h" #include "ui/helper.h" #include "ui/inputbox.h" #include "stdbool.h" #include "driver/eeprom.h" #include "driver/backlight.h" #include "ui/helper.h" #include typedef enum { FM_BT, MW_BT, SW_BT, LW_BT, } BandType; static const char SI47XX_BW_NAMES[5][6] = { "6 kHz", "4 kHz", "3 kHz", "2 kHz", "1 kHz", }; static const char SI47XX_SSB_BW_NAMES[6][8] = { "1.2 kHz", "2.2 kHz", "3 kHz", "4 kHz", "0.5 kHz", "1 kHz", }; static const char SI47XX_MODE_NAMES[5][4] = { "FM", "AM", "LSB", "USB", "CW", }; static SI47XX_FilterBW bw = SI47XX_BW_6_kHz; static SI47XX_SsbFilterBW ssbBw = SI47XX_SSB_BW_3_kHz; static int8_t currentBandIndex = -1; bool SNR_flag = true; bool SI_run = true; #include "app/spectrum.h" typedef struct // Band data { const char *bandName; // Bandname // BandType bandType; // Band type (FM, MW or SW) // SI47XX_MODE prefmod; // Pref. modulation uint16_t minimumFreq; // Minimum frequency of the band uint16_t maximumFreq; // maximum frequency of the band // uint16_t currentFreq; // Default frequency or current frequency // uint8_t currentStep; // Default step (increment and decrement) // int lastBFO; // Last BFO per band // int lastmanuBFO; // Last Manual BFO per band using X-Tal } SIBand; SIBand bands[] = { {"LW"/*, LW_BT, SI47XX_AM*/, 148, 283/*, 198, 9, 0, 0*/}, // LW 1 {"LW"/*, LW_BT, SI47XX_AM*/, 100, 514/*, 198, 9, 0, 0*/}, // LW 1 {"MW Bcast"/*, MW_BT, SI47XX_AM*/, 526, 1606/*, 1395, 9, 0, 0*/}, // MW 2 {"MW"/*, MW_BT, SI47XX_AM*/, 514, 1800/*, 1395, 9, 0, 0*/}, // MW 2 {"BACON Ham"/*, LW_BT, SI47XX_AM*/, 280, 470/*, 284, 1, 0, 0*/}, // Ham 800M 3 {"630M Ham"/*, SW_BT, SI47XX_LSB*/, 470, 480/*, 475, 1, 0, 0*/}, // Ham 630M 4 {"160M Ham"/*, SW_BT, SI47XX_LSB*/, 1800, 2000/*, 1850, 1, 0, 0*/}, // Ham 160M 5 {"120M Bcast"/*, SW_BT, SI47XX_AM*/, 2300, 2495/*, 2400, 5, 0, 0*/}, // 120M 6 {"120M"/*, SW_BT, SI47XX_AM*/, 2000, 3200/*, 2400, 5, 0, 0*/}, // 120M 6 {"90M Bcast"/*, SW_BT, SI47XX_AM*/, 3200, 3400/*, 3300, 5, 0, 0*/}, // 90M 7 {"90M"/*, SW_BT, SI47XX_AM*/, 3200, 3500/*, 3300, 5, 0, 0*/}, // 90M 7 {"80M Ham"/*, SW_BT, SI47XX_LSB*/, 3500, 3900/*, 3630, 1, 0, 0*/}, // Ham 80M 8 {"75M Bcast"/*, SW_BT, SI47XX_AM*/, 3900, 4000/*, 3950, 5, 0, 0*/}, // 75M 9 {"75M Bacst"/*, SW_BT, SI47XX_AM*/, 4750, 5100/*, 3950, 5, 0, 0*/}, // 75M 9 {"75M"/*, SW_BT, SI47XX_AM*/, 3900, 5300/*, 3950, 5, 0, 0*/}, // 75M 9 {"60M"/*, SW_BT, SI47XX_USB*/, 5300, 5900/*, 5375, 1, 0, 0*/}, // Ham 60M 10 {"49M Bcast"/*, SW_BT, SI47XX_AM*/, 5850, 6350/*, 6000, 5, 0, 0*/}, // 49M 11 {"49M"/*, SW_BT, SI47XX_AM*/, 5900, 7000/*, 6000, 5, 0, 0*/}, // 49M 11 {"41M Bcast"/*, SW_BT, SI47XX_AM*/, 7200, 7500/*, 7210, 5, 0, 0*/}, // 41M 13 {"40M Ham"/*, SW_BT, SI47XX_LSB*/, 7000, 7500/*, 7074, 1, 0, 0*/}, // Ham 40M 12 {"41M"/*, SW_BT, SI47XX_AM*/, 7500, 9000/*, 7210, 5, 0, 0*/}, // 41M 13 {"31M Bcast"/*, SW_BT, SI47XX_AM*/, 9400, 9990/*, 9600, 5, 0, 0*/}, // 31M 14 {"31M"/*, SW_BT, SI47XX_AM*/, 9000, 10000/*, 9600, 5, 0, 0*/}, // 31M 14 {"30M Ham"/*, SW_BT, SI47XX_USB*/, 10000, 10200/*, 10099, 1, 0, 0*/}, // Ham 30M 15 {"25M Bcast"/*, SW_BT, SI47XX_AM*/, 11600, 12100/*, 11700, 5, 0, 0*/}, // 25M 16 {"25M"/*, SW_BT, SI47XX_AM*/, 10200, 13500/*, 11700, 5, 0, 0*/}, // 25M 16 {"22M Bcast"/*, SW_BT, SI47XX_AM*/, 13500, 13870/*, 13700, 5, 0,0*/}, // 22M 17 {"22M"/*, SW_BT, SI47XX_AM*/, 13500, 14000/*, 13700, 5, 0, 0*/}, // 22M 17 {"20M Ham"/*, SW_BT, SI47XX_USB*/, 14000, 14500/*, 14074, 1, 0, 0*/}, // Ham 20M 18 {"19M Bcast"/*, SW_BT, SI47XX_AM*/, 15100, 15800/*, 15700, 5, 0, 0*/}, // 19M 19 {"17M Bcast"/*, SW_BT, SI47XX_AM*/, 17480, 18050/*, 17600, 5, 0, 0*/}, // 17M 20 {"19M"/*, SW_BT, SI47XX_AM*/, 14500, 17500/*, 15700, 5, 0, 0*/}, // 19M 19 {"17M"/*, SW_BT, SI47XX_AM*/, 17500, 18000/*, 17600, 5, 0, 0*/}, // 17M 20 {"16M Ham"/*, SW_BT, SI47XX_USB*/, 18000, 18500/*, 18100, 1, 0, 0*/}, // Ham 16M 21 {"15M Bcast"/*, SW_BT, SI47XX_AM*/, 18900, 19020/*, 18950, 5, 0,0*/}, // 15M 22 {"15M"/*, SW_BT, SI47XX_AM*/, 18500, 21000/*, 18950, 5, 0, 0*/}, // 15M 22 {"14M Ham"/*, SW_BT, SI47XX_USB*/, 21000, 21450/*, 21074, 1, 0,0*/}, // Ham 14M 23 {"14M Bcast"/*, SW_BT, SI47XX_USB*/, 21450, 21850/*, 21074, 1, 0,0*/}, // Ham 14M 23 {"13M"/*, SW_BT, SI47XX_AM*/, 21500, 24000/*, 21500, 5, 0, 0*/}, // 13M 24 {"12M Ham"/*, SW_BT, SI47XX_USB*/, 24000, 25500/*, 24940, 1, 0,0*/}, // Ham 12M 25 {"11M Bcast"/*, SW_BT, SI47XX_AM*/, 25600, 26100/*, 25800, 5, 0,0*/}, // 11M 26 {"11M"/*, SW_BT, SI47XX_AM*/, 25500, 26100/*, 25800, 5, 0, 0*/}, // 11M 26 {"CB"/*, SW_BT, SI47XX_AM*/, 26100, 28000/*, 27200, 1, 0, 0*/}, // CB band 27 {"10M Ham"/*, SW_BT, SI47XX_USB*/, 28000, 29750/*, 28500, 1, 0,0*/}, // Ham 10M 28 {"10M"/*, SW_BT, SI47XX_USB*/, 28000, 30000/*, 28500, 1, 0, 0*/}, // Ham 10M 28 {"SW" /*, SW_BT, SI47XX_AM*/, 100, 30000/*, 15500, 5, 0, 0*/} // Whole SW 29 }; static const uint8_t BANDS_COUNT = ARRAY_SIZE(bands); static int8_t getCurrentBandIndex() { for (int8_t i = 0; i < BANDS_COUNT; ++i) { if (siCurrentFreq >= bands[i].minimumFreq && siCurrentFreq <= bands[i].maximumFreq) { return i; } } return -1; } static uint8_t att = 0; static uint16_t step = 10; static DateTime dt; static int16_t bfo = 0; uint32_t light_time; bool INPUT_STATE = false; static void light_open() { if(gEeprom.BACKLIGHT_TIME) { light_time = (BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1]-1>=0?BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1]-1:0)*500; BACKLIGHT_TurnOn(); } } void WaitDisplay() { UI_DisplayClear(); UI_PrintStringSmall("SI4732 Wait...", 0, 127, 3); ST7565_BlitFullScreen(); } static void tune(uint32_t f) { if (si4732mode == SI47XX_FM) { if (f < 6400000 || f > 10800000) { return; } } else { if (f < 15000 || f > 3000000) { return; } } EEPROM_WriteBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t * ) & f, 4); f /= divider; if (si4732mode == SI47XX_FM) { f -= f % 5; } SI47XX_ClearRDS(); SI47XX_SetFreq(f); SI47XX_SetAutomaticGainControl(att > 0, att); currentBandIndex = getCurrentBandIndex(); } void SI_init() { SI_run = true; BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, false); BK4819_Disable(); SI47XX_PowerUp(); SI47XX_SetAutomaticGainControl(att > 0, att); } static bool seeking = false; static uint8_t seeking_way = 0; static void resetBFO() { bfo = 0; SI47XX_SetBFO(bfo); } void SI_deinit() { SI47XX_PowerDown(); BK4819_RX_TurnOn(); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH); #ifdef ENABLE_DOPPLER SYSCON_DEV_CLK_GATE|=(1<<22); #endif } bool display_flag = 0; KeyboardState kbds = {KEY_INVALID, KEY_INVALID, 0}; void SI4732_Display() { UI_DisplayClear(); memset(gStatusLine, 0, sizeof(gStatusLine)); if (INPUT_STATE) { UI_PrintStringSmall(freqInputString, 2, 127, 1); } else { uint8_t String[19]; //频率显示 uint32_t f = siCurrentFreq * divider; uint16_t fp1 = f / 100000; uint16_t fp2 = f / 100 % 1000; sprintf(String, "%3u.%03u", fp1, fp2); UI_DisplayFrequency(String, 64 - strlen(String) * 13 / 2, 2, false); //模式显示 const uint8_t BASE = 38; GUI_DisplaySmallest(SI47XX_MODE_NAMES[si4732mode], LCD_WIDTH - 12, BASE - 10 - 8, false, true); if (SI47XX_IsSSB()) { sprintf(String, "%d", bfo); GUI_DisplaySmallest(String, LCD_WIDTH - strlen(String) * 4, BASE - 8, false, true); } if (si4732mode == SI47XX_FM) { if (rds.RDSSignal) { GUI_DisplaySmallest("RDS", LCD_WIDTH - 12, 12 - 8, false, true); } char genre[17]; const char wd[8][3] = {"SU", "MO", "TU", "WE", "TH", "FR", "SA", "SU"}; SI47XX_GetProgramType(genre); GUI_DisplaySmallest(genre, 64 - strlen(genre) * 2, 15 - 8, false, true); if (SI47XX_GetLocalDateTime(&dt)) { sprintf(String, "%02u.%02u.%04u, %s %02u:%02u", dt.day, dt.month, dt.year, wd[dt.wday], dt.hour, dt.minute); GUI_DisplaySmallest(String, 64 - strlen(String) * 2, 22 - 8, false, true); } GUI_DisplaySmallest(rds.radioText, 0, LCD_HEIGHT - 8 - 8, false, true); } if (si4732mode == SI47XX_FM) { sprintf(String, "STP %u ATT %u", step, att); } else if (SI47XX_IsSSB()) { sprintf(String, "STP %u ATT %u BW %s", step, att, SI47XX_SSB_BW_NAMES[ssbBw]); } else { sprintf(String, "STP %u ATT %u BW %s", step, att, SI47XX_BW_NAMES[bw]); } GUI_DisplaySmallest(String, 64 - strlen(String) * 2, BASE + 6 - 8, false, true); if (si4732mode != SI47XX_FM) { if (currentBandIndex >= 0) { sprintf(String, "%s %d - %dkHz", bands[currentBandIndex].bandName, bands[currentBandIndex].minimumFreq, bands[currentBandIndex].maximumFreq); GUI_DisplaySmallest(String, 64 - strlen(String) * 2, LCD_HEIGHT - 5 - 9, false, true); } } if (SNR_flag) { uint8_t rssi = rsqStatus.resp.RSSI; if (rssi > 64) { rssi = 64; } for (int i = 0; i < rssi * 2; ++i) { gFrameBuffer[0][i] |= 0b00111100; } sprintf(String, "SNR %u", rsqStatus.resp.SNR); GUI_DisplaySmallest(String, 0, 15 - 8, false, true); } } ST7565_BlitFullScreen(); } static void OnKeyDownFreqInput(uint8_t key) { switch (key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: case KEY_STAR: UpdateFreqInput(key); break; case KEY_EXIT: if (freqInputIndex == 0) { INPUT_STATE = false; break; } UpdateFreqInput(key); break; case KEY_MENU: if (!FreqCheck(tempFreq)) { break; } INPUT_STATE = false; tune(tempFreq); resetBFO(); break; default: break; } } void HandleUserInput() { kbds.prev = kbds.current; kbds.current = GetKey(); bool KEY_TYPE1 = false, KEY_TYPE2 = false, KEY_TYPE3 = false; // 无按键 if (kbds.current == KEY_INVALID) { if (kbds.counter > 2 && kbds.counter <= 6) { // 短按松手 KEY_TYPE3 = true; } kbds.counter = 0; } else { if (kbds.counter >= 6 && kbds.counter % 2 == 1) { KEY_TYPE1 = true; } if (kbds.current == kbds.prev) { // 持续按下 if (kbds.counter <= 14) { KEY_TYPE2 = true; kbds.counter++; } } else { // 按键变化，重置计数器 kbds.counter = 1; } SYSTEM_DelayMs(20); } if (KEY_TYPE1 || KEY_TYPE2 || KEY_TYPE3) { light_open(); display_flag = 1; } SI_key(kbds.current, KEY_TYPE1, KEY_TYPE2, KEY_TYPE3, kbds.prev); } void SI_key(KEY_Code_t key, bool KEY_TYPE1, bool KEY_TYPE2, bool KEY_TYPE3, KEY_Code_t key_prev) { // up-down keys if (INPUT_STATE && KEY_TYPE3) { OnKeyDownFreqInput(key_prev); return ; } if (KEY_TYPE1 || KEY_TYPE3) { if (KEY_TYPE3)key = key_prev; switch (key) { case KEY_UP: case KEY_DOWN: tune((siCurrentFreq + (key == KEY_UP ? step : -step)) * divider); resetBFO(); return ; #ifdef ENABLE_4732SSB case KEY_SIDE1: case KEY_SIDE2: if (SI47XX_IsSSB()) { if (key == KEY_SIDE1 ? (bfo < INT16_MAX - 10) : (bfo > INT16_MIN + 10)) { bfo = bfo + (key == KEY_SIDE1 ? 10 : -10); } SI47XX_SetBFO(bfo); } return ; #endif case KEY_2: case KEY_8: if (key == KEY_2 ? att < 37 : att > 0) { key == KEY_2 ? att++ : att--; SI47XX_SetAutomaticGainControl(key == KEY_2 ? 1 : att > 0, att); } return ; default: break; } } // Simple keypress if (KEY_TYPE3) { switch (key_prev) { case KEY_4: SNR_flag = !SNR_flag; return ; case KEY_1: if (step < 1000) { if (step == 1 || step == 10 || step == 100 ) { step *= 5; } else { step *= 2; } } return ; case KEY_7: if (step > 1) { if ( step == 10 || step == 100 || step == 1000) { step /= 2; } else { step /= 5; } } return ; case KEY_6: #ifdef ENABLE_4732SSB if (SI47XX_IsSSB()) { if (ssbBw == SI47XX_SSB_BW_1_0_kHz) { ssbBw = SI47XX_SSB_BW_1_2_kHz; } else { ssbBw++; } SI47XX_SetSsbBandwidth(ssbBw); } else { #endif if (bw == SI47XX_BW_1_kHz) { bw = SI47XX_BW_6_kHz; } else { bw++; } SI47XX_SetBandwidth(bw, true); #ifdef ENABLE_4732SSB } #endif return ; case KEY_5: INPUT_STATE = 1; FreqInput(); return ; case KEY_0: divider = 100; WaitDisplay(); if (si4732mode == SI47XX_FM) { SI47XX_SwitchMode(SI47XX_AM); SI47XX_SetBandwidth(bw, true); // tune(720000); step = 5; } #ifdef ENABLE_4732SSB else if (si4732mode == SI47XX_AM) { SI47XX_SwitchMode(SI47XX_LSB); SI47XX_SetSsbBandwidth(ssbBw); // tune(711300); step = 1; } #endif else { divider = 1000; SI47XX_SwitchMode(SI47XX_FM); // tune(10000000); step = 10; } tune(Read_FreqSaved()); resetBFO(); return ; #ifdef ENABLE_4732SSB case KEY_F: if (SI47XX_IsSSB()) { uint32_t tmpF; SI47XX_SwitchMode(si4732mode == SI47XX_LSB ? SI47XX_USB : SI47XX_LSB); tune(Read_FreqSaved()); // to apply SSB return ; } #endif case KEY_EXIT: if (seeking) { SI47XX_PowerDown(); SI47XX_PowerUp(); seeking = false; } else SI_run = false; return ; case KEY_3: case KEY_9: #ifdef ENABLE_4732SSB if (SI47XX_IsSSB()) { return ; } #endif if (si4732mode == SI47XX_FM) { SI47XX_SetSeekFmSpacing(step); } else { SI47XX_SetSeekAmSpacing(step); } SI47XX_Seek(key == KEY_3 ? 1 : 0, 1); if (key == KEY_3)seeking_way = 1; else seeking_way = 0; seeking = true; return ; default: break; } } return ; } void SI4732_Main() { #ifdef ENABLE_DOPPLER SYSCON_DEV_CLK_GATE= SYSCON_DEV_CLK_GATE & ( ~(1 << 22)); #endif light_open(); SI_init(); uint16_t cnt = 500; while (SI_run) { if (light_time && gEeprom.BACKLIGHT_TIME != 7) { light_time--; if (light_time == 0)BACKLIGHT_TurnOff(); } if (cnt == 500) { DrawPower(); ST7565_BlitStatusLine(); cnt = 0; if (si4732mode == SI47XX_FM) { if (SI47XX_GetRDS()) display_flag = 1; } if (SNR_flag) { RSQ_GET(); display_flag = 1; } } if (cnt % 25 == 0) { HandleUserInput(); } if (seeking && cnt % 100 == 0) { UI_PrintStringSmallBuffer("*", gStatusLine); bool valid = false; siCurrentFreq = SI47XX_getFrequency(&valid); uint32_t f = siCurrentFreq * divider; EEPROM_WriteBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t * ) & f, 4); if (valid) { seeking = false; light_open(); tune((siCurrentFreq) * divider); } display_flag = 1; } cnt++; if (display_flag) { display_flag = 0; SI4732_Display(); } SYSTEM_DelayMs(1); } SI_deinit(); } ================================================ FILE: app/si.h ================================================ #ifndef APP_SI_H #define APP_SI_H #include "spectrum.h" #include "../driver/keyboard.h" #include #include void SI_init(); void SI_update(); void SI_key(KEY_Code_t key, bool KEY_TYPE1, bool KEY_TYPE2, bool KEY_TYPE3,KEY_Code_t key_prev) ; void SI_render(); void SI_deinit(); void Key_FM(KeyboardState kbds) ; void HandleUserInput() ; void SI4732_Main(); #endif /* end of include guard: APP_SI_H */ ================================================ FILE: app/spectrum.c ================================================ /* Copyright 2023 fagci * https://github.com/fagci * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ //#define ENABLE_DOPPLER #include "functions.h" #include "stdbool.h" #ifdef ENABLE_DOPPLER #include "app/doppler.h" #include "bsp/dp32g030/rtc.h" #endif #include "app/spectrum.h" #include "am_fix.h" #include "audio.h" #include "misc.h" //#define ENABLE_DOPPLER #ifdef ENABLE_SCAN_RANGES #include "chFrScanner.h" #endif #include "driver/eeprom.h" #include "driver/backlight.h" #include "frequencies.h" #include "ui/helper.h" #include "ui/main.h" static void ToggleRX(bool on); struct FrequencyBandInfo { uint32_t lower; uint32_t upper; uint32_t middle; }; int Mid(uint16_t *array, uint8_t n) { int32_t sum = 0; for (int i = 0; i < n; ++i) { sum += array[i]; } return sum / n; } // //static void UpdateBatteryInfo() { // for (uint8_t i = 0; i < 4; i++) { // BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[i], &gBatteryCurrent); // } // // uint16_t voltage = Mid(gBatteryVoltages, ARRAY_SIZE(gBatteryVoltages)); // gBatteryDisplayLevel = 0; // // for (int i = ARRAY_SIZE(gBatteryCalibration) - 1; i >= 0; --i) { // if (gBatteryCalibration[i] < voltage) { // gBatteryDisplayLevel = i + 1; // break; // } // } //} #define F_MIN frequencyBandTable[0].lower #define F_MAX frequencyBandTable[BAND_N_ELEM - 1].upper const uint16_t RSSI_MAX_VALUE = 65535; int32_t time_diff, time_diff1; static uint32_t initialFreq; static char String[32]; #ifdef ENABLE_DOPPLER bool DOPPLER_MODE = 0; #endif bool TX_ON = false; bool isInitialized = false; bool isListening = true; bool monitorMode = false; bool redrawStatus = true; bool redrawScreen = false; bool newScanStart = true; bool preventKeypress = true; bool audioState = true; bool lockAGC = false; State currentState ,previousState ; PeakInfo peak; ScanInfo scanInfo; KeyboardState kbd = {KEY_INVALID, KEY_INVALID, 0}; #ifdef ENABLE_SCAN_RANGES static uint16_t blacklistFreqs[15]; static uint8_t blacklistFreqsIdx; #endif const char *bwOptions[] = {" 25k", "12.5k", "6.25k"}; const uint8_t modulationTypeTuneSteps[] = {100, 50, 10}; const uint8_t modTypeReg47Values[] = {1, 7, 5}; SpectrumSettings settings = {.stepsCount = STEPS_64, .scanStepIndex = S_STEP_25_0kHz, .frequencyChangeStep = 80000, .scanDelay = 3200, .rssiTriggerLevel = 150, .backlightState = true, .bw = BK4819_FILTER_BW_WIDE, .listenBw = BK4819_FILTER_BW_WIDE, .modulationType = false, .dbMin = -130, .dbMax = -50 }; uint32_t fMeasure = 0; uint32_t currentFreq, tempFreq; uint16_t rssiHistory[128]; int vfo; uint8_t freqInputIndex = 0; uint8_t freqInputDotIndex = 0; KEY_Code_t freqInputArr[10]; char freqInputString[11]; uint8_t menuState = 0; uint16_t listenT = 0; RegisterSpec registerSpecs[] = { {}, {"LNAs", BK4819_REG_13, 8, 0b11, 1}, {"LNA", BK4819_REG_13, 5, 0b111, 1}, {"PGA", BK4819_REG_13, 0, 0b111, 1}, {"IF", BK4819_REG_3D, 0, 0xFFFF, 0x2aaa}, // {"MIX", 0x13, 3, 0b11, 1}, // ' }; uint16_t statuslineUpdateTimer = 0; VfoState_t txAllowState; bool isTransmitting = false; static uint8_t DBm2S(int dbm) { uint8_t i = 0; dbm *= -1; for (i = 0; i < ARRAY_SIZE(U8RssiMap); i++) { if (dbm >= U8RssiMap[i]) { return i; } } return i; } uint16_t registersVault[128] = {0}; #ifdef ENABLE_DOPPLER static void RegBackup() { for (int i = 0; i < 128; ++i) { registersVault[i] = BK4819_ReadRegister(i); } } #endif #ifdef ENABLE_DOPPLER static void RegRestore() { for (int i = 0; i < 128; ++i) { BK4819_WriteRegister(i, registersVault[i]); } } #endif static void ToggleAudio(bool on) { // if (on == audioState) { // return; // } // audioState = on; if (on) { AUDIO_AudioPathOn(); } else { AUDIO_AudioPathOff(); } } void SetTxF(uint32_t f, bool precise) { BK4819_PickRXFilterPathBasedOnFrequency(f); BK4819_SetFrequency(f); uint16_t reg = BK4819_ReadRegister(BK4819_REG_30); if (precise) { BK4819_WriteRegister(BK4819_REG_30, 0x0200); // from radtel-rt-890-oefw } else { BK4819_WriteRegister(BK4819_REG_30, reg & ~BK4819_REG_30_ENABLE_VCO_CALIB); } BK4819_WriteRegister(BK4819_REG_30, reg); } #ifdef ENABLE_DOPPLER static void ToggleTX(bool on) { if (isTransmitting == on) { return; } isTransmitting = on; if (on) { ToggleRX(false); } BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, on); if (on) { TX_ON=1; fMeasure = satellite_data.UPLink; AUDIO_AudioPathOff(); SetTxF(fMeasure, true); RegBackup(); BK4819_WriteRegister(BK4819_REG_47, 0x6040); BK4819_WriteRegister(BK4819_REG_7E, 0x302E); BK4819_WriteRegister(BK4819_REG_50, 0x3B20); BK4819_WriteRegister(BK4819_REG_37, 0x1D0F); BK4819_WriteRegister(BK4819_REG_52, 0x028F); BK4819_WriteRegister(BK4819_REG_30, 0x0000); BK4819_WriteRegister(BK4819_REG_30, 0xC1FE); BK4819_WriteRegister(BK4819_REG_51, 0x9033); //亚音 if (satellite.SEND_CTCSS == 0) BK4819_ExitSubAu(); else BK4819_SetCTCSSFrequency(satellite.SEND_CTCSS); //功率 FREQUENCY_Band_t Band = FREQUENCY_GetBand(fMeasure); uint8_t Txp[3]; EEPROM_ReadBuffer(0x1ED0 + (Band * 16) + (OUTPUT_POWER_HIGH * 3), Txp, 3); BK4819_SetupPowerAmplifier(Txp[2], fMeasure); #if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200) enable_msg_rx(false); #endif //DTMF BK4819_DisableDTMF(); //加密 BK4819_DisableScramble(); } else { BK4819_GenTail(4); // CTC55 BK4819_WriteRegister(BK4819_REG_51, 0x904A); // SYSTEM_DelayMs(200); BK4819_SetupPowerAmplifier(0, 0); RegRestore(); //TODO:发射频率 fMeasure = satellite_data.DownLink; SetTxF(fMeasure, true); TX_ON=0; } BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, !on); BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, on); } #endif static int Rssi2DBm(uint16_t rssi) { return (rssi / 2) - 160 + dBmCorrTable[gRxVfo->Band]; } static uint16_t GetRegMenuValue(uint8_t st) { RegisterSpec s = registerSpecs[st]; return (BK4819_ReadRegister(s.num) >> s.offset) & s.mask; } void LockAGC() { RADIO_SetupAGC(settings.modulationType == MODULATION_AM, lockAGC); lockAGC = true; } static void SetRegMenuValue(uint8_t st, bool add) { uint16_t v = GetRegMenuValue(st); RegisterSpec s = registerSpecs[st]; if (s.num == BK4819_REG_13) LockAGC(); uint16_t reg = BK4819_ReadRegister(s.num); if (add && v <= s.mask - s.inc) { v += s.inc; } else if (!add && v >= 0 + s.inc) { v -= s.inc; } // mask in spec reg &= ~(s.mask << s.offset); BK4819_WriteRegister(s.num, reg | (v << s.offset)); redrawScreen = true; } // Utility functions static int clamp(int v, int min, int max) { return v <= min ? min : (v >= max ? max : v); } static uint8_t my_abs(signed v) { return v > 0 ? v : -v; } void SetState(State state) { previousState = currentState; currentState = state; redrawScreen = true; redrawStatus = true; } // Radio functions static void ToggleAFBit(bool on) { uint16_t reg = BK4819_ReadRegister(BK4819_REG_47); reg &= ~(1 << 8); if (on) reg |= on << 8; BK4819_WriteRegister(BK4819_REG_47, reg); } static const BK4819_REGISTER_t registers_to_save[] = { // BK4819_REG_30, // BK4819_REG_37, // BK4819_REG_3D, // BK4819_REG_43, // BK4819_REG_47, // BK4819_REG_48, // BK4819_REG_7E, 0x13, 0x30, 0x31, 0x37, 0x3D, 0x40, 0x43, 0x47, 0x48, 0x7D, 0x7E, }; static uint16_t registers_stack[sizeof(registers_to_save)]; static void BackupRegisters() { for (uint32_t i = 0; i < ARRAY_SIZE(registers_to_save); i++) { registers_stack[i] = BK4819_ReadRegister(registers_to_save[i]); } } static void RestoreRegisters() { for (uint32_t i = 0; i < ARRAY_SIZE(registers_to_save); i++) { BK4819_WriteRegister(registers_to_save[i], registers_stack[i]); } } static void ToggleAFDAC(bool on) { uint32_t Reg = BK4819_ReadRegister(BK4819_REG_30); Reg &= ~(1 << 9); if (on) Reg |= (1 << 9); BK4819_WriteRegister(BK4819_REG_30, Reg); } static void SetF(uint32_t f) { fMeasure = f; BK4819_SetFrequency(fMeasure); BK4819_PickRXFilterPathBasedOnFrequency(fMeasure); uint16_t reg = BK4819_ReadRegister(BK4819_REG_30); BK4819_WriteRegister(BK4819_REG_30, 0); BK4819_WriteRegister(BK4819_REG_30, reg); } // Spectrum related bool IsPeakOverLevel() { return peak.rssi >= settings.rssiTriggerLevel; } static void ResetPeak() { peak.t = 0; peak.rssi = 0; } bool IsCenterMode() { return settings.scanStepIndex < S_STEP_2_5kHz; } // scan step in 0.01khz uint16_t GetScanStep() { return scanStepValues[settings.scanStepIndex]; } uint16_t GetStepsCount() { #ifdef ENABLE_SCAN_RANGES if(gScanRangeStart) { return (gScanRangeStop - gScanRangeStart) / GetScanStep(); } #endif return 128 >> settings.stepsCount; } uint32_t GetBW() { return GetStepsCount() * GetScanStep(); } uint32_t GetFStart() { return IsCenterMode() ? currentFreq - (GetBW() >> 1) : currentFreq; } uint32_t GetFEnd() { return currentFreq + GetBW(); } static void TuneToPeak() { scanInfo.f = peak.f; scanInfo.rssi = peak.rssi; scanInfo.i = peak.i; SetF(scanInfo.f); } static void DeInitSpectrum() { SetF(initialFreq); RestoreRegisters(); isInitialized = false; } static uint8_t GetBWRegValueForScan() { return scanStepBWRegValues[settings.scanStepIndex]; } static uint16_t GetRssi() { // SYSTICK_DelayUs(800); // testing autodelay based on Glitch value while ((BK4819_ReadRegister(0x63) & 0b11111111) >= 255) { SYSTICK_DelayUs(100); } uint16_t rssi = BK4819_GetRSSI(); #ifdef ENABLE_AM_FIX if(settings.modulationType==MODULATION_AM && gSetting_AM_fix) rssi += AM_fix_get_gain_diff()*2; #endif return rssi; } static void ToggleRX(bool on) { // if(isTransmitting&&on)return; isListening = on; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE && on) { ToggleTX(false); } #endif RADIO_SetupAGC(on, lockAGC); BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, on); ToggleAudio(on); ToggleAFDAC(on); ToggleAFBit(on); if (on) { listenT = 1000; BK4819_WriteRegister(0x43, listenBWRegValues[settings.listenBw]); } else { BK4819_WriteRegister(0x43, GetBWRegValueForScan()); } } // Scan info static void ResetScanStats() { scanInfo.rssi = 0; scanInfo.rssiMax = 0; scanInfo.iPeak = 0; scanInfo.fPeak = 0; } static void InitScan() { ResetScanStats(); scanInfo.i = 0; scanInfo.f = GetFStart(); scanInfo.scanStep = GetScanStep(); scanInfo.measurementsCount = GetStepsCount(); } static void ResetBlacklist() { for (int i = 0; i < 128; ++i) { if (rssiHistory[i] == RSSI_MAX_VALUE) rssiHistory[i] = 0; } #ifdef ENABLE_SCAN_RANGES memset(blacklistFreqs, 0, sizeof(blacklistFreqs)); blacklistFreqsIdx = 0; #endif } static void RelaunchScan() { InitScan(); ResetPeak(); ToggleRX(false); #ifdef SPECTRUM_AUTOMATIC_SQUELCH settings.rssiTriggerLevel = RSSI_MAX_VALUE; #endif preventKeypress = true; scanInfo.rssiMin = RSSI_MAX_VALUE; } static void UpdateScanInfo() { if (scanInfo.rssi > scanInfo.rssiMax) { scanInfo.rssiMax = scanInfo.rssi; scanInfo.fPeak = scanInfo.f; scanInfo.iPeak = scanInfo.i; } if (scanInfo.rssi < scanInfo.rssiMin) { scanInfo.rssiMin = scanInfo.rssi; settings.dbMin = Rssi2DBm(scanInfo.rssiMin); redrawStatus = true; } } static void AutoTriggerLevel() { if (settings.rssiTriggerLevel == RSSI_MAX_VALUE) { settings.rssiTriggerLevel = clamp(scanInfo.rssiMax + 8, 0, RSSI_MAX_VALUE); } } static void UpdatePeakInfoForce() { peak.t = 0; peak.rssi = scanInfo.rssiMax; peak.f = scanInfo.fPeak; peak.i = scanInfo.iPeak; AutoTriggerLevel(); } static void UpdatePeakInfo() { if (peak.f == 0 || peak.t >= 1024 || peak.rssi < scanInfo.rssiMax) UpdatePeakInfoForce(); } static void SetRssiHistory(uint16_t idx, uint16_t rssi) { #ifdef ENABLE_SCAN_RANGES if(scanInfo.measurementsCount > 128) { uint8_t i = (uint32_t)ARRAY_SIZE(rssiHistory) * 1000 / scanInfo.measurementsCount * idx / 1000; if(rssiHistory[i] < rssi || isListening) rssiHistory[i] = rssi; rssiHistory[(i+1)%128] = 0; return; } #endif rssiHistory[idx] = rssi; } static void Measure() { uint16_t rssi = scanInfo.rssi = GetRssi(); SetRssiHistory(scanInfo.i, rssi); } // Update things by keypress static uint16_t dbm2rssi(int dBm) { return (dBm + 160 - dBmCorrTable[gRxVfo->Band]) * 2; } static void ClampRssiTriggerLevel() { settings.rssiTriggerLevel = clamp(settings.rssiTriggerLevel, dbm2rssi(settings.dbMin), dbm2rssi(settings.dbMax)); } static void UpdateRssiTriggerLevel(bool inc) { if (inc) settings.rssiTriggerLevel += 2; else settings.rssiTriggerLevel -= 2; ClampRssiTriggerLevel(); redrawScreen = true; redrawStatus = true; } static void UpdateDBMax(bool inc) { uint8_t tmp = 12; #ifdef ENBALE_DOPPLER if(DOPPLER_MODE) tmp=10; #endif if (inc && settings.dbMax < 10) { settings.dbMax += 1; } else if (!inc && settings.dbMax > tmp + settings.dbMin) { settings.dbMax -= 1; } else { return; } ClampRssiTriggerLevel(); redrawStatus = true; redrawScreen = true; SYSTEM_DelayMs(20); } static void UpdateScanStep(bool inc) { if (inc) { settings.scanStepIndex = settings.scanStepIndex != S_STEP_100_0kHz ? settings.scanStepIndex + 1 : 0; } else { settings.scanStepIndex = settings.scanStepIndex != 0 ? settings.scanStepIndex - 1 : S_STEP_100_0kHz; } settings.frequencyChangeStep = GetBW() >> 1; RelaunchScan(); ResetBlacklist(); redrawScreen = true; } static void UpdateCurrentFreq(bool inc) { if (inc && currentFreq < F_MAX) { currentFreq += settings.frequencyChangeStep; } else if (!inc && currentFreq > F_MIN) { currentFreq -= settings.frequencyChangeStep; } else { return; } RelaunchScan(); ResetBlacklist(); redrawScreen = true; } static void UpdateCurrentFreqStill(bool inc) { uint8_t offset = modulationTypeTuneSteps[settings.modulationType]; uint32_t f = fMeasure; if (inc && f < F_MAX) { f += offset; } else if (!inc && f > F_MIN) { f -= offset; } SetF(f); redrawScreen = true; } static void UpdateFreqChangeStep(bool inc) { uint16_t diff = GetScanStep() * 4; if (inc && settings.frequencyChangeStep < 200000) { settings.frequencyChangeStep += diff; } else if (!inc && settings.frequencyChangeStep > 10000) { settings.frequencyChangeStep -= diff; } SYSTEM_DelayMs(100); redrawScreen = true; } static void ToggleModulation() { if (settings.modulationType < MODULATION_UKNOWN - 1) { settings.modulationType++; } else { settings.modulationType = MODULATION_FM; } RADIO_SetModulation(settings.modulationType); RelaunchScan(); redrawScreen = true; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) redrawStatus = true; #endif } static void ToggleListeningBW() { if (settings.listenBw == BK4819_FILTER_BW_NARROWER) { settings.listenBw = BK4819_FILTER_BW_WIDE; } else { settings.listenBw++; } redrawScreen = true; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) redrawStatus = true; #endif } static void ToggleBacklight() { settings.backlightState = !settings.backlightState; if (settings.backlightState) { BACKLIGHT_TurnOn(); } else { BACKLIGHT_TurnOff(); } } static void ToggleStepsCount() { if (settings.stepsCount == STEPS_128) { settings.stepsCount = STEPS_16; } else { settings.stepsCount--; } settings.frequencyChangeStep = GetBW() >> 1; RelaunchScan(); ResetBlacklist(); redrawScreen = true; } void ResetFreqInput() { tempFreq = 0; for (int i = 0; i < 10; ++i) { freqInputString[i] = '-'; } } void FreqInput() { freqInputIndex = 0; freqInputDotIndex = 0; ResetFreqInput(); SetState(FREQ_INPUT); } void UpdateFreqInput(KEY_Code_t key) { if (key != KEY_EXIT && freqInputIndex >= 10) { return; } if (key == KEY_STAR) { if (freqInputIndex == 0 || freqInputDotIndex) { return; } freqInputDotIndex = freqInputIndex; } if (key == KEY_EXIT) { freqInputIndex--; if (freqInputDotIndex == freqInputIndex) freqInputDotIndex = 0; } else { freqInputArr[freqInputIndex++] = key; } ResetFreqInput(); uint8_t dotIndex = freqInputDotIndex == 0 ? freqInputIndex : freqInputDotIndex; KEY_Code_t digitKey; for (int i = 0; i < 10; ++i) { if (i < freqInputIndex) { digitKey = freqInputArr[i]; freqInputString[i] = digitKey <= KEY_9 ? '0' + digitKey : '.'; } else { freqInputString[i] = '-'; } } uint32_t base = 100000; // 1MHz in BK units //#ifdef ENABLE_DOPPLER // if(DOPPLER_MODE)base=1; //#endif for (int i = dotIndex - 1; i >= 0; --i) { tempFreq += (freqInputArr[i]) * base; base *= 10; } base = 10000; // 0.1MHz in BK units if (dotIndex < freqInputIndex) { for (int i = dotIndex + 1; i < freqInputIndex; ++i) { tempFreq += (freqInputArr[i]) * base; base /= 10; } } redrawScreen = true; } static void Blacklist() { #ifdef ENABLE_SCAN_RANGES blacklistFreqs[blacklistFreqsIdx++ % ARRAY_SIZE(blacklistFreqs)] = peak.i; #endif SetRssiHistory(peak.i, RSSI_MAX_VALUE); ResetPeak(); ToggleRX(false); ResetScanStats(); } #ifdef ENABLE_SCAN_RANGES static bool IsBlacklisted(uint16_t idx) { for(uint8_t i = 0; i < ARRAY_SIZE(blacklistFreqs); i++) if(blacklistFreqs[i] == idx) return true; return false; } #endif // Draw things // applied x2 to prevent initial rounding static uint8_t Rssi2PX(uint16_t rssi, uint8_t pxMin, uint8_t pxMax) { const int DB_MIN = settings.dbMin << 1; const int DB_MAX = settings.dbMax << 1; const int DB_RANGE = DB_MAX - DB_MIN; const uint8_t PX_RANGE = pxMax - pxMin; int dbm = clamp(Rssi2DBm(rssi) << 1, DB_MIN, DB_MAX); // return ((dbm - DB_MIN) * PX_RANGE + DB_RANGE / 2) / DB_RANGE + pxMin; return (dbm - DB_MIN) * PX_RANGE / DB_RANGE + pxMin; } uint8_t Rssi2Y(uint16_t rssi) { return DrawingEndY - Rssi2PX(rssi, 0, DrawingEndY); } static void DrawSpectrum() { for (uint8_t x = 0; x < 128; ++x) { uint16_t rssi = rssiHistory[x >> settings.stepsCount]; if (rssi != RSSI_MAX_VALUE) { DrawVLine(Rssi2Y(rssi), DrawingEndY, x, true); } } } void DrawPower() { BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[gBatteryCheckCounter++ % 4], &gBatteryCurrent); uint16_t voltage = (gBatteryVoltages[0] + gBatteryVoltages[1] + gBatteryVoltages[2] + gBatteryVoltages[3]) / 4 * 760 / gBatteryCalibration[3]; unsigned perc = BATTERY_VoltsToPercent(voltage); // sprintf(String, "%d %d", voltage, perc); // GUI_DisplaySmallest(String, 48, 1, true, true); gStatusLine[116] = 0b00011100; gStatusLine[117] = 0b00111110; for (int i = 118; i <= 126; i++) { gStatusLine[i] = 0b00100010; } for (unsigned i = 127; i >= 118; i--) { if (127 - i <= (perc + 5) * 9 / 100) { gStatusLine[i] = 0b00111110; } } } static void DrawStatus() { #ifdef SPECTRUM_EXTRA_VALUES sprintf(String, "%d/%d P:%d T:%d", settings.dbMin, settings.dbMax, Rssi2DBm(peak.rssi), Rssi2DBm(settings.rssiTriggerLevel)); #else sprintf(String, "%d/%d", settings.dbMin, settings.dbMax); #endif #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) { //UI绘制状态栏 memset(gStatusLine, 0x7f, 39); GUI_DisplaySmallest(satellite.name, 2, 1, true, false); GUI_DisplaySmallest(String, 42 + (settings.dbMax > -100 ? 4 : 0), 1, true, true); sprintf(String, "%3s", gModulationStr[settings.modulationType]); GUI_DisplaySmallest(String, 42 + 38, 1, true, true); sprintf(String, "%s", bwOptions[settings.listenBw]); GUI_DisplaySmallest(String, 42 + 53 - (settings.listenBw == 0 ? 8 : 0), 1, true, true); } else { #endif GUI_DisplaySmallest(String, 0, 1, true, true); #ifdef ENABLE_DOPPLER } #endif DrawPower(); } static void DrawF(uint32_t f) { #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) { //UI绘制 sprintf(String, "%03u.%05u", f / 100000, f % 100000); UI_DisplayFrequency(String, 8, 0, false); } else { #endif sprintf(String, "%u.%05u", f / 100000, f % 100000); UI_PrintStringSmall(String, 8, 127, 0); sprintf(String, "%3s", gModulationStr[settings.modulationType]); GUI_DisplaySmallest(String, 116, 1, false, true); sprintf(String, "%s", bwOptions[settings.listenBw]); GUI_DisplaySmallest(String, 108, 7, false, true); #ifdef ENABLE_DOPPLER } #endif } static void DrawNums() { if (currentState == SPECTRUM) { sprintf(String, "%ux", GetStepsCount()); GUI_DisplaySmallest(String, 0, 1, false, true); sprintf(String, "%u.%02uk", GetScanStep() / 100, GetScanStep() % 100); GUI_DisplaySmallest(String, 0, 7, false, true); } if (IsCenterMode()) { sprintf(String, "%u.%05u \x7F%u.%02uk", currentFreq / 100000, currentFreq % 100000, settings.frequencyChangeStep / 100, settings.frequencyChangeStep % 100); GUI_DisplaySmallest(String, 36, 49, false, true); } else { sprintf(String, "%u.%05u", GetFStart() / 100000, GetFStart() % 100000); GUI_DisplaySmallest(String, 0, 49, false, true); sprintf(String, "\x7F%u.%02uk", settings.frequencyChangeStep / 100, settings.frequencyChangeStep % 100); GUI_DisplaySmallest(String, 48, 49, false, true); sprintf(String, "%u.%05u", GetFEnd() / 100000, GetFEnd() % 100000); GUI_DisplaySmallest(String, 93, 49, false, true); } } static void DrawRssiTriggerLevel() { if (settings.rssiTriggerLevel == RSSI_MAX_VALUE || monitorMode) return; uint8_t y = Rssi2Y(settings.rssiTriggerLevel); for (uint8_t x = 0; x < 128; x += 2) { PutPixel(x, y, true); } } static void DrawTicks() { uint32_t f = GetFStart(); uint32_t span = GetFEnd() - GetFStart(); uint32_t step = span / 128; for (uint8_t i = 0; i < 128; i += (1 << settings.stepsCount)) { f = GetFStart() + span * i / 128; uint8_t barValue = 0b00000001; (f % 10000) < step && (barValue |= 0b00000010); (f % 50000) < step && (barValue |= 0b00000100); (f % 100000) < step && (barValue |= 0b00011000); gFrameBuffer[5][i] |= barValue; } // center if (IsCenterMode()) { memset(gFrameBuffer[5] + 62, 0x80, 5); gFrameBuffer[5][64] = 0xff; } else { memset(gFrameBuffer[5] + 1, 0x80, 3); memset(gFrameBuffer[5] + 124, 0x80, 3); gFrameBuffer[5][0] = 0xff; gFrameBuffer[5][127] = 0xff; } } static void DrawArrow(uint8_t x) { for (signed i = -2; i <= 2; ++i) { signed v = x + i; if (!(v & 128)) { gFrameBuffer[5][v] |= (0b01111000 << my_abs(i)) & 0b01111000; } } } static void OnKeyDown(uint8_t key) { switch (key) { case KEY_3: UpdateDBMax(true); break; case KEY_9: UpdateDBMax(false); break; case KEY_1: UpdateScanStep(true); break; case KEY_7: UpdateScanStep(false); break; case KEY_2: UpdateFreqChangeStep(true); break; case KEY_8: UpdateFreqChangeStep(false); break; case KEY_UP: #ifdef ENABLE_SCAN_RANGES if(!gScanRangeStart) #endif UpdateCurrentFreq(true); break; case KEY_DOWN: #ifdef ENABLE_SCAN_RANGES if(!gScanRangeStart) #endif UpdateCurrentFreq(false); break; case KEY_SIDE1: Blacklist(); break; case KEY_STAR: UpdateRssiTriggerLevel(true); break; case KEY_F: UpdateRssiTriggerLevel(false); break; case KEY_5: #ifdef ENABLE_SCAN_RANGES if(!gScanRangeStart) #endif FreqInput(); break; case KEY_0: ToggleModulation(); break; case KEY_6: ToggleListeningBW(); break; case KEY_4: #ifdef ENABLE_SCAN_RANGES if(!gScanRangeStart) #endif ToggleStepsCount(); break; case KEY_SIDE2: ToggleBacklight(); break; case KEY_PTT: SetState(STILL); TuneToPeak(); break; case KEY_MENU: break; case KEY_EXIT: if (menuState) { menuState = 0; break; } DeInitSpectrum(); break; default: break; } } static void OnKeyDownFreqInput(uint8_t key) { switch (key) { case KEY_0: case KEY_1: case KEY_2: case KEY_3: case KEY_4: case KEY_5: case KEY_6: case KEY_7: case KEY_8: case KEY_9: case KEY_STAR: UpdateFreqInput(key); break; case KEY_EXIT: if (freqInputIndex == 0) { SetState(previousState); break; } UpdateFreqInput(key); break; case KEY_MENU: #ifdef ENABLE_DOPPLER if(DOPPLER_MODE) { time[3]=tempFreq/100000; time[4]=(tempFreq/1000)%100; time[5]=(tempFreq/10)%100; RTC_Set(); SetState(previousState); break; } #endif if (tempFreq < F_MIN || tempFreq > F_MAX) { break; } SetState(previousState); currentFreq = tempFreq; if (currentState == SPECTRUM) { ResetBlacklist(); RelaunchScan(); } else { SetF(currentFreq); } break; default: break; } } void OnKeyDownStill(KEY_Code_t key) { switch (key) { case KEY_3: UpdateDBMax(true); break; case KEY_9: UpdateDBMax(false); break; case KEY_UP: if (menuState) { SetRegMenuValue(menuState, true); break; } #ifdef ENABLE_DOPPLER if (!DOPPLER_MODE) #endif UpdateCurrentFreqStill(true); break; case KEY_DOWN: if (menuState) { SetRegMenuValue(menuState, false); break; } #ifdef ENABLE_DOPPLER if (!DOPPLER_MODE) #endif UpdateCurrentFreqStill(false); break; case KEY_STAR: UpdateRssiTriggerLevel(true); break; case KEY_F: UpdateRssiTriggerLevel(false); break; case KEY_5: //#ifdef ENABLE_DOPPLER // if (DOPPLER_MODE) { // // // } else //#endif FreqInput(); break; case KEY_0: #ifdef ENABLE_DOPPLER if (!DOPPLER_MODE) #endif ToggleModulation(); break; case KEY_6: #ifdef ENABLE_DOPPLER if (!DOPPLER_MODE) #endif ToggleListeningBW(); break; case KEY_SIDE1: monitorMode = !monitorMode; break; case KEY_SIDE2: ToggleBacklight(); break; case KEY_PTT: #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) { ToggleTX(true); redrawScreen = true; } #endif break; case KEY_MENU: if (menuState == ARRAY_SIZE(registerSpecs) - 1) { menuState = 1; } else { menuState++; } redrawScreen = true; break; case KEY_EXIT: if (!menuState) { SetState(SPECTRUM); lockAGC = false; monitorMode = false; RelaunchScan(); #ifdef ENABLE_DOPPLER if (DOPPLER_MODE)DeInitSpectrum(); #endif break; } menuState = 0; break; default: break; } } void RenderFreqInput() { UI_PrintStringSmall(freqInputString, 2, 127, 0); // show_uint32(tempFreq,3); } static void UpdateStill() { if (TX_ON)return; Measure(); redrawScreen = true; preventKeypress = false; peak.rssi = scanInfo.rssi; AutoTriggerLevel(); ToggleRX((IsPeakOverLevel() || monitorMode)); } static void RenderStatus() { memset(gStatusLine, 0, sizeof(gStatusLine)); DrawStatus(); ST7565_BlitStatusLine(); } static void RenderSpectrum() { DrawTicks(); DrawArrow(128u * peak.i / GetStepsCount()); DrawSpectrum(); DrawRssiTriggerLevel(); DrawF(peak.f); DrawNums(); } #ifdef ENABLE_DOPPLER static void Draw_DOPPLER_Process(uint8_t DATA_LINE) { int process = 0; if (time_diff > 0)//还没来卫星 { if (time_diff > 1000)//还早 { strcpy(String, "Long"); } else//1000s以内 { sprintf(String, "-%4d sec", time_diff); process = time_diff * 45 / 1000; } } else { //已经来了 if (time_diff1 >= 0)//正在过境 { sprintf(String, "+%4d sec", satellite.sum_time + time_diff); process = 45 - (satellite.sum_time + time_diff) * 45 / satellite.sum_time; } else { strcpy(String, "Passed"); } } GUI_DisplaySmallest(String, 85, DATA_LINE + 15, false, true); memset(&gFrameBuffer[6][80], 0b01000000, 45); gFrameBuffer[6][79] = 0b00111110; gFrameBuffer[6][45 + 80] = 0b00111110; for (int i = 0; i < 45; i++) { if (i < process) gFrameBuffer[6][i + 80] = 0b00111110; else gFrameBuffer[6][i + 80] = 0b00100010; } sprintf(String, "20%02d-%02d-%02d %02d:%02d:%02d", time[0], time[1], time[2], time[3], time[4], time[5]); GUI_DisplaySmallest(String, 1, DATA_LINE + 23, false, true); } #endif static void RenderStill() { DrawF(fMeasure);//绘制频率 uint8_t METER_PAD_LEFT = 3; uint8_t P_WIDTH = 120; uint8_t S_LINE = 25; uint8_t S_X = 4; uint8_t DBM_X = 22; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) { P_WIDTH = 50; METER_PAD_LEFT = 70; S_LINE = 18; S_X = 58; DBM_X = 6; } #endif memset(&gFrameBuffer[2][METER_PAD_LEFT], 0b01000000, P_WIDTH); for (int i = 0; i <= P_WIDTH; i += 5) { //小刻度 gFrameBuffer[2][i + METER_PAD_LEFT] = 0b01100000; } uint8_t x = Rssi2PX(scanInfo.rssi, 0, P_WIDTH);//信号强度 for (int i = 0; i < x; i++) { if (i % 5) { gFrameBuffer[2][i + METER_PAD_LEFT] |= 0b00001110; } } //S表参数绘制 int dbm = Rssi2DBm(scanInfo.rssi); uint8_t s = DBm2S(dbm); bool fill = true; #ifdef ENABLE_DOPPLER if ((monitorMode || IsPeakOverLevel()) && DOPPLER_MODE) { memset(gFrameBuffer[2] + DBM_X - 2, 0b11111110, 51); fill = false; } #endif sprintf(String, "S%u", s); GUI_DisplaySmallest(String, S_X, S_LINE, false, true); sprintf(String, "%4d/%4ddBm", dbm, Rssi2DBm(settings.rssiTriggerLevel)); GUI_DisplaySmallest(String, DBM_X, S_LINE, false, fill); if (!monitorMode) { uint8_t x = Rssi2PX(settings.rssiTriggerLevel, 0, P_WIDTH); gFrameBuffer[2][METER_PAD_LEFT + x] = 0b11111111; } //增益参数 const uint8_t PAD_LEFT = 4; const uint8_t CELL_WIDTH = 30; uint8_t offset = PAD_LEFT; uint8_t row = 4; uint8_t DATA_LINE; uint8_t SHOW_LINE=4; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE)SHOW_LINE = 3; #endif for (int i = 0, idx = 1; idx <= 4; ++i, ++idx) { // if (idx == 5) { // row += 2; // i = 0; // } offset = PAD_LEFT + i * CELL_WIDTH; if (menuState == idx) { for (int j = 0; j < CELL_WIDTH; ++j) { gFrameBuffer[SHOW_LINE][j + offset] = 0xFF; gFrameBuffer[SHOW_LINE + 1][j + offset] = 0xFF; } } DATA_LINE = row * 8 + 2; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE)DATA_LINE -= 8; #endif sprintf(String, "%s", registerSpecs[idx].name); GUI_DisplaySmallest(String, offset + 2, DATA_LINE, false, menuState != idx); sprintf(String, "%u", GetRegMenuValue(idx)); GUI_DisplaySmallest(String, offset + 2, DATA_LINE + 7, false, menuState != idx); } #ifdef ENABLE_DOPPLER if (DOPPLER_MODE) { Draw_DOPPLER_Process(26); bool flag = true; if (!isTransmitting) sprintf(String, "UPLink:%4d.%05d", satellite_data.UPLink / 100000, satellite_data.UPLink % 100000); else { memset(gFrameBuffer[5], 0x7f, 77); flag = false; sprintf(String, "DownLink:%4d.%05d", satellite_data.DownLink / 100000, satellite_data.DownLink % 100000); } GUI_DisplaySmallest(String, 1, DATA_LINE + 15, false, flag); } #endif } static void Render() { UI_DisplayClear(); switch (currentState) { case SPECTRUM: RenderSpectrum(); break; case FREQ_INPUT: RenderFreqInput(); break; case STILL: RenderStill(); break; } ST7565_BlitFullScreen(); } static void HandleUserInput() { kbd.prev = kbd.current; kbd.current = GetKey(); if (kbd.current == KEY_INVALID) { kbd.counter = 0; #ifdef ENABLE_DOPPLER if (DOPPLER_MODE && isTransmitting) { ToggleTX(false); } #endif // return true; } if (kbd.current != KEY_INVALID && kbd.current == kbd.prev) { if (kbd.counter < 16) kbd.counter++; else kbd.counter -= 3; SYSTEM_DelayMs(20); } else { kbd.counter = 0; } if (kbd.counter == 2 || kbd.counter == 16) { switch (currentState) { case SPECTRUM: OnKeyDown(kbd.current); break; case FREQ_INPUT: OnKeyDownFreqInput(kbd.current); break; case STILL: OnKeyDownStill(kbd.current); break; } } } static void Scan() { if (rssiHistory[scanInfo.i] != RSSI_MAX_VALUE #ifdef ENABLE_SCAN_RANGES && !IsBlacklisted(scanInfo.i) #endif ) { SetF(scanInfo.f); Measure(); UpdateScanInfo(); } } static void NextScanStep() { ++peak.t; ++scanInfo.i; scanInfo.f += scanInfo.scanStep; } static void UpdateScan() { Scan(); if (scanInfo.i < scanInfo.measurementsCount) { NextScanStep(); return; } if (scanInfo.measurementsCount < 128) memset(&rssiHistory[scanInfo.measurementsCount], 0, sizeof(rssiHistory) - scanInfo.measurementsCount * sizeof(rssiHistory[0])); redrawScreen = true; preventKeypress = false; UpdatePeakInfo(); if (IsPeakOverLevel()) { ToggleRX(true); TuneToPeak(); return; } newScanStart = true; } static void UpdateListening() { preventKeypress = false; if (currentState == STILL) { listenT = 0; } if (listenT) { listenT--; SYSTEM_DelayMs(1); return; } if (currentState == SPECTRUM) { BK4819_WriteRegister(0x43, GetBWRegValueForScan()); Measure(); BK4819_WriteRegister(0x43, listenBWRegValues[settings.listenBw]); } else { Measure(); } peak.rssi = scanInfo.rssi; redrawScreen = true; if (IsPeakOverLevel() || monitorMode) { listenT = 1000; return; } ToggleRX(false); ResetScanStats(); } static void Tick() { #ifdef ENABLE_AM_FIX if (gNextTimeslice) { gNextTimeslice = false; if(settings.modulationType == MODULATION_AM && !lockAGC) { AM_fix_10ms(vfo); //allow AM_Fix to apply its AGC action } } #endif #ifdef ENABLE_SCAN_RANGES if (gNextTimeslice_500ms) { gNextTimeslice_500ms = false; // if a lot of steps then it takes long time // we don't want to wait for whole scan // listening has it's own timer if(GetStepsCount()>128 && !isListening) { UpdatePeakInfo(); if (IsPeakOverLevel()) { ToggleRX(true); TuneToPeak(); return; } redrawScreen = true; preventKeypress = false; } } #endif if (!preventKeypress) { HandleUserInput(); } if (newScanStart) { InitScan(); newScanStart = false; } if (isListening && currentState != FREQ_INPUT) { UpdateListening(); } else { if (currentState == SPECTRUM) { UpdateScan(); } else if (currentState == STILL) { UpdateStill(); } } if (redrawStatus || ++statuslineUpdateTimer > 4096) { RenderStatus(); redrawStatus = false; statuslineUpdateTimer = 0; } if (redrawScreen) { Render(); redrawScreen = false; } } void APP_RunSpectrum() { currentState = SPECTRUM; previousState=SPECTRUM; // TX here coz it always? set to active VFO vfo = gEeprom.TX_VFO; // set the current frequency in the middle of the display #ifdef ENABLE_SCAN_RANGES if(gScanRangeStart) { currentFreq = initialFreq = gScanRangeStart; for(uint8_t i = 0; i < ARRAY_SIZE(scanStepValues); i++) { if(scanStepValues[i] >= gTxVfo->StepFrequency) { settings.scanStepIndex = i; break; } } settings.stepsCount = STEPS_128; } else #endif { currentFreq = initialFreq = gTxVfo->pRX->Frequency - ((GetStepsCount() / 2) * GetScanStep()); } BackupRegisters(); isListening = true; // to turn off RX later redrawStatus = true; redrawScreen = true; newScanStart = true; ToggleRX(true), ToggleRX(false); // hack to prevent noise when squelch off RADIO_SetModulation(settings.modulationType = gTxVfo->Modulation); BK4819_SetFilterBandwidth(settings.listenBw = BK4819_FILTER_BW_WIDE, false); RelaunchScan(); memset(rssiHistory, 0, sizeof(rssiHistory)); isInitialized = true; #ifdef ENABLE_DOPPLER statuslineUpdateTimer = 4097; if (DOPPLER_MODE) { settings.listenBw = 0; settings.modulationType = MODULATION_FM; SetState(STILL); TuneToPeak(); settings.dbMin = -130; } #endif while (isInitialized) { //#ifdef ENABLE_DOPPLER // // if (DOPPLER_MODE) { // satellite_data.DownLink=43850000; // SetF(satellite_data.DownLink); // currentFreq = satellite_data.DownLink; // } //#endif #ifdef ENABLE_DOPPLER if (DOPPLER_MODE&&!isTransmitting&¤tFreq!=satellite_data.DownLink) { SetF(satellite_data.DownLink); currentFreq = satellite_data.DownLink; } #endif Tick(); } } #ifdef ENABLE_DOPPLER void RTCHandler(void) { RTC_Get(); int32_t NOW_UNIX_TIME = UNIX_TIME(time); time_diff = satellite.START_TIME_UNIX - NOW_UNIX_TIME; //卫星开始时间-现在时间 time_diff1 = satellite.sum_time + time_diff;//结束-开始+开始-现在 READ_DATA(time_diff, time_diff1); RTC_IF |= (1 << 5);//清除中断标志位 } #endif ================================================ FILE: app/spectrum.h ================================================ /* Copyright 2023 fagci * https://github.com/fagci * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef SPECTRUM_H #define SPECTRUM_H #include "../bitmaps.h" #include "../board.h" #include "../bsp/dp32g030/gpio.h" #include "../driver/bk4819-regs.h" #include "../driver/bk4819.h" #include "../driver/gpio.h" #include "../driver/keyboard.h" #include "../driver/st7565.h" #include "../driver/system.h" #include "../driver/systick.h" #include "../external/printf/printf.h" #include "../font.h" #include "../helper/battery.h" #include "../misc.h" #include "../radio.h" #include "../settings.h" #include "../ui/helper.h" #include #include #include static const uint8_t DrawingEndY = 40; static const uint8_t U8RssiMap[] = { 121, 115, 109, 103, 97, 91, 85, 79, 73, 63, }; static const uint16_t scanStepValues[] = { 1, 10, 50, 100, 250, 500, 625, 833, 1000, 1250, 1500, 2000, 2500, 5000, 10000, }; static const uint16_t scanStepBWRegValues[] = { // RX RXw TX BW // 0b0 000 000 001 01 1000 // 1 0b0000000001011000, // 6.25 // 10 0b0000000001011000, // 6.25 // 50 0b0000000001011000, // 6.25 // 100 0b0000000001011000, // 6.25 // 250 0b0000000001011000, // 6.25 // 500 0b0010010001011000, // 6.25 // 625 0b0100100001011000, // 6.25 // 833 0b0110110001001000, // 6.25 // 1000 0b0110110001001000, // 6.25 // 1250 0b0111111100001000, // 6.25 // 2500 0b0011011000101000, // 25 // 10000 0b0011011000101000, // 25 }; static const uint16_t listenBWRegValues[] = { 0b0011011000101000, // 25 0b0111111100001000, // 12.5 0b0100100001011000, // 6.25 }; typedef enum State { SPECTRUM, FREQ_INPUT, STILL, } State; typedef enum StepsCount { STEPS_128, STEPS_64, STEPS_32, STEPS_16, } StepsCount; typedef enum ScanStep { S_STEP_0_01kHz, S_STEP_0_1kHz, S_STEP_0_5kHz, S_STEP_1_0kHz, S_STEP_2_5kHz, S_STEP_5_0kHz, S_STEP_6_25kHz, S_STEP_8_33kHz, S_STEP_10_0kHz, S_STEP_12_5kHz, S_STEP_15_0kHz, S_STEP_20_0kHz, S_STEP_25_0kHz, S_STEP_50_0kHz, S_STEP_100_0kHz, } ScanStep; typedef struct SpectrumSettings { uint32_t frequencyChangeStep; StepsCount stepsCount; ScanStep scanStepIndex; uint16_t scanDelay; uint16_t rssiTriggerLevel; BK4819_FilterBandwidth_t bw; BK4819_FilterBandwidth_t listenBw; int dbMin; int dbMax; ModulationMode_t modulationType; bool backlightState; } SpectrumSettings; typedef enum { KEY_STATE_IDLE, KEY_STATE_PRESSED, KEY_STATE_HELD, KEY_STATE_RELEASED } KeyState_t; typedef struct KeyboardState { KEY_Code_t current; KEY_Code_t prev; uint8_t counter; KeyState_t state; bool gRepeatHeld; } KeyboardState; typedef struct ScanInfo { uint16_t rssi, rssiMin, rssiMax; uint16_t i, iPeak; uint32_t f, fPeak; uint16_t scanStep; uint16_t measurementsCount; } ScanInfo; typedef struct PeakInfo { uint16_t t; uint16_t rssi; uint32_t f; uint16_t i; } PeakInfo; extern uint32_t tempFreq; extern char freqInputString[11]; extern uint8_t freqInputIndex ; extern uint8_t freqInputDotIndex ; extern State currentState , previousState ; void SetState(State state) ; void ResetFreqInput() ; void UpdateFreqInput(KEY_Code_t key) ; void RenderFreqInput() ; void FreqInput() ; extern KEY_Code_t freqInputArr[10]; void APP_RunSpectrum(void); void DrawPower(); #ifdef ENABLE_DOPPLER extern bool DOPPLER_MODE; void RTCHandler(); #endif #endif /* ifndef SPECTRUM_H */ // vim: ft=c ================================================ FILE: app/uart.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "font.h" #if !defined(ENABLE_OVERLAY) #include "ARMCM0.h" #endif #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #ifdef ENABLE_DOPPLER #include "bsp/dp32g030/rtc.h" #endif #include "app/uart.h" #include "board.h" #include "bsp/dp32g030/dma.h" #include "bsp/dp32g030/gpio.h" #include "driver/aes.h" #include "driver/backlight.h" #include "driver/bk4819.h" #include "driver/crc.h" #include "driver/eeprom.h" #include "driver/gpio.h" #include "driver/uart.h" #include "functions.h" #include "misc.h" #include "settings.h" #if defined(ENABLE_OVERLAY) #include "sram-overlay.h" #endif #include "version.h" #define DMA_INDEX(x, y) (((x) + (y)) % sizeof(UART_DMA_Buffer)) typedef struct { uint16_t ID; uint16_t Size; } Header_t; #ifdef ENABLE_DOCK typedef struct { Header_t Header; uint8_t Key; uint8_t Padding; uint32_t Timestamp; } CMD_0801_t; // simulate key press #endif typedef struct { uint8_t Padding[2]; uint16_t ID; } Footer_t; typedef struct { Header_t Header; uint32_t Timestamp; } CMD_0514_t; typedef struct { Header_t Header; struct { char Version[16]; bool bHasCustomAesKey; bool bIsInLockScreen; uint8_t Padding[2]; uint32_t Challenge[4]; } Data; } REPLY_0514_t; typedef struct { Header_t Header; uint16_t Offset; uint8_t Size; uint8_t Padding; uint32_t Timestamp; uint8_t ADD[2]; } CMD_051B_t; typedef struct { Header_t Header; uint16_t Offset; uint8_t Size; uint8_t Padding; uint32_t Timestamp; uint8_t ADD[2]; } CMD_052B_t; typedef struct { Header_t Header; struct { uint16_t Offset; uint8_t Size; uint8_t Padding; uint8_t Data[128]; } Data; } REPLY_051B_t; typedef struct { Header_t Header; uint16_t Offset; uint8_t Size; bool bAllowPassword; uint32_t Timestamp; uint8_t Data[0]; } CMD_051D_t; typedef struct { Header_t Header; struct { uint16_t Offset; } Data; } REPLY_051D_t; typedef struct { Header_t Header; struct { uint16_t RSSI; uint8_t ExNoiseIndicator; uint8_t GlitchIndicator; } Data; } REPLY_0527_t; typedef struct { Header_t Header; struct { uint16_t Voltage; uint16_t Current; } Data; } REPLY_0529_t; typedef struct { Header_t Header; uint32_t Response[4]; } CMD_052D_t; #ifdef ENABLE_BLOCK typedef struct { Header_t Header; struct { bool bIsLocked; uint8_t Padding[3]; } Data; } REPLY_052D_t; #endif typedef struct { Header_t Header; uint32_t Timestamp; } CMD_052F_t; static const uint8_t Obfuscation[16] = { 0x16, 0x6C, 0x14, 0xE6, 0x2E, 0x91, 0x0D, 0x40, 0x21, 0x35, 0xD5, 0x40, 0x13, 0x03, 0xE9, 0x80 }; static union { uint8_t Buffer[256]; struct { Header_t Header; uint8_t Data[252]; }; } UART_Command; static uint32_t Timestamp; static uint16_t gUART_WriteIndex; static bool bIsEncrypted = true; static void SendReply(void *pReply, uint16_t Size) { Header_t Header; Footer_t Footer; if (bIsEncrypted) { uint8_t *pBytes = (uint8_t *) pReply; unsigned int i; for (i = 0; i < Size; i++) pBytes[i] ^= Obfuscation[i % 16]; } Header.ID = 0xCDAB; Header.Size = Size; UART_Send(&Header, sizeof(Header)); UART_Send(pReply, Size); if (bIsEncrypted) { Footer.Padding[0] = Obfuscation[(Size + 0) % 16] ^ 0xFF; Footer.Padding[1] = Obfuscation[(Size + 1) % 16] ^ 0xFF; } else { Footer.Padding[0] = 0xFF; Footer.Padding[1] = 0xFF; } Footer.ID = 0xBADC; UART_Send(&Footer, sizeof(Footer)); } static void SendVersion(void) { REPLY_0514_t Reply; Reply.Header.ID = 0x0515; Reply.Header.Size = sizeof(Reply.Data); strcpy(Reply.Data.Version, Version); Reply.Data.bHasCustomAesKey = bHasCustomAesKey; Reply.Data.bIsInLockScreen = bIsInLockScreen; Reply.Data.Challenge[0] = gChallenge[0]; Reply.Data.Challenge[1] = gChallenge[1]; Reply.Data.Challenge[2] = gChallenge[2]; Reply.Data.Challenge[3] = gChallenge[3]; SendReply(&Reply, sizeof(Reply)); } #ifdef ENABLE_BLOCK static bool IsBadChallenge(const uint32_t *pKey, const uint32_t *pIn, const uint32_t *pResponse) { unsigned int i; uint32_t IV[4]; IV[0] = 0; IV[1] = 0; IV[2] = 0; IV[3] = 0; AES_Encrypt(pKey, IV, pIn, IV, true); for (i = 0; i < 4; i++) if (IV[i] != pResponse[i]) return true; return false; } #endif static void CMD_0514(const uint8_t *pBuffer) { const CMD_0514_t *pCmd = (const CMD_0514_t *) pBuffer; Timestamp = pCmd->Timestamp; #ifdef ENABLE_FMRADIO gFmRadioCountdown_500ms = fm_radio_countdown_500ms; #endif gSerialConfigCountDown_500ms = 12; // 6 sec // turn the LCD backlight off BACKLIGHT_TurnOff(); SendVersion(); } static void CMD_051B(const uint8_t *pBuffer) { const CMD_051B_t *pCmd = (const CMD_051B_t *) pBuffer; REPLY_051B_t Reply; #ifdef ENABLE_BLOCK bool bLocked = false; #endif if (pCmd->Timestamp != Timestamp) return; gSerialConfigCountDown_500ms = 12; // 6 sec #ifdef ENABLE_FMRADIO gFmRadioCountdown_500ms = fm_radio_countdown_500ms; #endif // memset(&Reply, 0, sizeof(Reply)); Reply.Header.ID = 0x051C; Reply.Header.Size = pCmd->Size + 4; Reply.Data.Offset = pCmd->Offset; Reply.Data.Size = pCmd->Size; #ifdef ENABLE_BLOCK if (bHasCustomAesKey) bLocked = gIsLocked; if (!bLocked) #endif if (pCmd->Header.ID == 0x051B) EEPROM_ReadBuffer(pCmd->Offset, Reply.Data.Data, pCmd->Size); else EEPROM_ReadBuffer(((pCmd->Offset) << 16) + ((pCmd->ADD[1]) << 8) + (pCmd->ADD[0]), Reply.Data.Data, pCmd->Size); SendReply(&Reply, pCmd->Size + 8); } static void CMD_051D(const uint8_t *pBuffer) { const CMD_051D_t *pCmd = (const CMD_051D_t *) pBuffer; REPLY_051D_t Reply; #ifdef ENABLE_BLOCK bool bIsLocked; #endif if (pCmd->Timestamp != Timestamp) return; gSerialConfigCountDown_500ms = 12; // 6 sec #ifdef ENABLE_FMRADIO gFmRadioCountdown_500ms = fm_radio_countdown_500ms; #endif Reply.Header.ID = 0x051E; Reply.Header.Size = sizeof(Reply.Data); Reply.Data.Offset = pCmd->Offset; #ifdef ENABLE_BLOCK bIsLocked = bHasCustomAesKey ? gIsLocked : bHasCustomAesKey; #endif #ifdef ENABLE_BLOCK if (!bIsLocked) { #endif for (unsigned int i = 0; i < (pCmd->Size / 8); i++) { const uint16_t Offset = pCmd->Offset + (i * 8U); #ifdef ENABLE_BLOCK if (Offset >= 0x0F30 && Offset < 0x0F40) if (!gIsLocked) #endif #ifdef ENABLE_BLOCK if ((Offset < 0x0E98 || Offset >= 0x0EA0) || !bIsInLockScreen || pCmd->bAllowPassword) #endif EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U], 8); } SETTINGS_InitEEPROM(); #ifdef ENABLE_BLOCK } #endif SendReply(&Reply, sizeof(Reply)); } static void CMD_0527(void) { REPLY_0527_t Reply; Reply.Header.ID = 0x0528; Reply.Header.Size = sizeof(Reply.Data); Reply.Data.RSSI = BK4819_ReadRegister(BK4819_REG_67) & 0x01FF; Reply.Data.ExNoiseIndicator = BK4819_ReadRegister(BK4819_REG_65) & 0x007F; Reply.Data.GlitchIndicator = BK4819_ReadRegister(BK4819_REG_63); SendReply(&Reply, sizeof(Reply)); } static void CMD_0529(void) { REPLY_0529_t Reply; Reply.Header.ID = 0x52A; Reply.Header.Size = sizeof(Reply.Data); // Original doesn't actually send current! BOARD_ADC_GetBatteryInfo(&Reply.Data.Voltage, &Reply.Data.Current); SendReply(&Reply, sizeof(Reply)); } #ifdef ENABLE_BLOCK static void CMD_052D(const uint8_t *pBuffer) { const CMD_052D_t *pCmd = (const CMD_052D_t *) pBuffer; REPLY_052D_t Reply; bool bIsLocked; #ifdef ENABLE_FMRADIO gFmRadioCountdown_500ms = fm_radio_countdown_500ms; #endif Reply.Header.ID = 0x052E; Reply.Header.Size = sizeof(Reply.Data); bIsLocked = bHasCustomAesKey; if (!bIsLocked) bIsLocked = IsBadChallenge(gCustomAesKey, gChallenge, pCmd->Response); if (!bIsLocked) { bIsLocked = IsBadChallenge(gDefaultAesKey, gChallenge, pCmd->Response); if (bIsLocked) gTryCount++; } if (gTryCount < 3) { if (!bIsLocked) gTryCount = 0; } else { gTryCount = 3; bIsLocked = true; } gIsLocked = bIsLocked; Reply.Data.bIsLocked = bIsLocked; SendReply(&Reply, sizeof(Reply)); } #endif // session init, sends back version info and state // timestamp is a session id really // this command also disables dual watch, crossband, // DTMF side tones, freq reverse, PTT ID, DTMF decoding, frequency offset // exits power save, sets main VFO to upper, static void CMD_052F(const uint8_t *pBuffer) { const CMD_052F_t *pCmd = (const CMD_052F_t *) pBuffer; gEeprom.DUAL_WATCH = DUAL_WATCH_OFF; gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF; gEeprom.RX_VFO = 0; gEeprom.DTMF_SIDE_TONE = false; gEeprom.VfoInfo[0].FrequencyReverse = 0; gEeprom.VfoInfo[0].pRX = &gEeprom.VfoInfo[0].freq_config_RX; gEeprom.VfoInfo[0].pTX = &gEeprom.VfoInfo[0].freq_config_TX; gEeprom.VfoInfo[0].TX_OFFSET_FREQUENCY_DIRECTION = TX_OFFSET_FREQUENCY_DIRECTION_OFF; gEeprom.VfoInfo[0].DTMF_PTT_ID_TX_MODE = PTT_ID_OFF; #ifdef ENABLE_DTMF_CALLING gEeprom.VfoInfo[0].DTMF_DECODING_ENABLE = false; #endif #ifdef ENABLE_NOAA gIsNoaaMode = false; #endif if (gCurrentFunction == FUNCTION_POWER_SAVE) FUNCTION_Select(FUNCTION_FOREGROUND); //OK gSerialConfigCountDown_500ms = 12; // 6 sec Timestamp = pCmd->Timestamp; // turn the LCD backlight off BACKLIGHT_TurnOff(); SendVersion(); } #ifdef ENABLE_UART_RW_BK_REGS static void CMD_0601_ReadBK4819Reg(const uint8_t *pBuffer) { typedef struct __attribute__((__packed__)) { Header_t header; uint8_t reg; } CMD_0601_t; CMD_0601_t *cmd = (CMD_0601_t*) pBuffer; struct __attribute__((__packed__)) { Header_t header; struct __attribute__((__packed__)) { uint8_t reg; uint16_t value; } data; } reply; reply.header.ID = 0x0601; reply.header.Size = sizeof(reply.data); reply.data.reg = cmd->reg; reply.data.value = BK4819_ReadRegister(cmd->reg); SendReply(&reply, sizeof(reply)); } static void CMD_0602_WriteBK4819Reg(const uint8_t *pBuffer) { typedef struct __attribute__((__packed__)) { Header_t header; uint8_t reg; uint16_t value; } CMD_0602_t; CMD_0602_t *cmd = (CMD_0602_t*) pBuffer; BK4819_WriteRegister(cmd->reg, cmd->value); } #endif bool UART_IsCommandAvailable(void) { uint16_t Index; uint16_t TailIndex; uint16_t Size; uint16_t CRC; uint16_t CommandLength; uint16_t DmaLength = DMA_CH0->ST & 0xFFFU; while (1) { if (gUART_WriteIndex == DmaLength) return false; while (gUART_WriteIndex != DmaLength && UART_DMA_Buffer[gUART_WriteIndex] != 0xABU) gUART_WriteIndex = DMA_INDEX(gUART_WriteIndex, 1); if (gUART_WriteIndex == DmaLength) return false; if (gUART_WriteIndex < DmaLength) CommandLength = DmaLength - gUART_WriteIndex; else CommandLength = (DmaLength + sizeof(UART_DMA_Buffer)) - gUART_WriteIndex; if (CommandLength < 8) return 0; if (UART_DMA_Buffer[DMA_INDEX(gUART_WriteIndex, 1)] == 0xCD) break; gUART_WriteIndex = DMA_INDEX(gUART_WriteIndex, 1); } Index = DMA_INDEX(gUART_WriteIndex, 2); Size = (UART_DMA_Buffer[DMA_INDEX(Index, 1)] << 8) | UART_DMA_Buffer[Index]; if ((Size + 8u) > sizeof(UART_DMA_Buffer)) { gUART_WriteIndex = DmaLength; return false; } if (CommandLength < (Size + 8)) return false; Index = DMA_INDEX(Index, 2); TailIndex = DMA_INDEX(Index, Size + 2); if (UART_DMA_Buffer[TailIndex] != 0xDC || UART_DMA_Buffer[DMA_INDEX(TailIndex, 1)] != 0xBA) { gUART_WriteIndex = DmaLength; return false; } if (TailIndex < Index) { const uint16_t ChunkSize = sizeof(UART_DMA_Buffer) - Index; memcpy(UART_Command.Buffer, UART_DMA_Buffer + Index, ChunkSize); memcpy(UART_Command.Buffer + ChunkSize, UART_DMA_Buffer, TailIndex); } else memcpy(UART_Command.Buffer, UART_DMA_Buffer + Index, TailIndex - Index); TailIndex = DMA_INDEX(TailIndex, 2); if (TailIndex < gUART_WriteIndex) { memset(UART_DMA_Buffer + gUART_WriteIndex, 0, sizeof(UART_DMA_Buffer) - gUART_WriteIndex); memset(UART_DMA_Buffer, 0, TailIndex); } else memset(UART_DMA_Buffer + gUART_WriteIndex, 0, TailIndex - gUART_WriteIndex); gUART_WriteIndex = TailIndex; if (UART_Command.Header.ID == 0x0514) bIsEncrypted = false; if (UART_Command.Header.ID == 0x6902) bIsEncrypted = true; if (bIsEncrypted) { unsigned int i; for (i = 0; i < (Size + 2u); i++) UART_Command.Buffer[i] ^= Obfuscation[i % 16]; } CRC = UART_Command.Buffer[Size] | (UART_Command.Buffer[Size + 1] << 8); // char b[2]="3K"; // uint8_t tmp[Size]; // for (int i = 0; i < Size; i++) { // tmp[i]=UART_Command.Buffer[i]; // } bool judge = (CRC_Calculate1(UART_Command.Buffer, Size) != CRC) ? false : true; return judge; } #if ENABLE_CHINESE_FULL == 4 // //static void CMD_052B(const uint8_t *pBuffer)//read //{ // const CMD_052B_t *pCmd = (const CMD_052B_t *) pBuffer; // REPLY_051B_t Reply; // // // if (pCmd->Timestamp != Timestamp) // return; // // gSerialConfigCountDown_500ms = 12; // 6 sec // //#ifdef ENABLE_FMRADIO // gFmRadioCountdown_500ms = fm_radio_countdown_500ms; //#endif // //// memset(&Reply, 0, sizeof(Reply)); // Reply.Header.ID = 0x051C; // Reply.Header.Size = pCmd->Size + 4; // Reply.Data.Offset = pCmd->Offset; // // Reply.Data.Size = pCmd->Size; // // // EEPROM_ReadBuffer(((pCmd->Offset) << 16) + ((pCmd->ADD[1]) << 8) + (pCmd->ADD[0]), Reply.Data.Data, pCmd->Size); // // SendReply(&Reply, pCmd->Size + 8); //} static void CMD_0538(const uint8_t *pBuffer)//write { const CMD_051D_t *pCmd = (const CMD_051D_t *) pBuffer; REPLY_051D_t Reply; if (pCmd->Timestamp != Timestamp) return; gSerialConfigCountDown_500ms = 12; // 6 sec #ifdef ENABLE_FMRADIO gFmRadioCountdown_500ms = fm_radio_countdown_500ms; #endif Reply.Header.ID = 0x051E; Reply.Header.Size = sizeof(Reply.Data); Reply.Data.Offset = pCmd->Offset; int add=((pCmd->Size) - 2)%8; for ( int i = 0; i < ((pCmd->Size) - 2) / 8+(add==0?0:1); i++) { const uint32_t Offset = ((pCmd->Offset) << 16) + ((pCmd->Data[1]) << 8) + (pCmd->Data[0]) + (i * 8U); //#ifdef ENABLE_DOPPLER // if(Offset>=0x90000) // { // memcpy(time,pCmd->Data[i * 8U + 2],6); // RTC_Set(time); // continue; // } //#endif if(add&&i==((pCmd->Size) - 2) / 8+(add==0?0:1)-1) EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U + 2], add); else EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U + 2], 8); } SETTINGS_InitEEPROM(); SendReply(&Reply, sizeof(Reply)); } #endif #ifdef ENABLE_DOCK static void CMD_0801(const uint8_t *pBuffer) { const CMD_0801_t *pCmd = (const CMD_0801_t *)pBuffer; const uint8_t key = pCmd->Key & 0x1f; const bool click = pCmd->Key & 32; if(key != KEY_INVALID) { gSimulateKey = key; gDebounceDefeat = 0; } gSimulateHold = click ? KEY_INVALID : key; } #endif void UART_HandleCommand(void) { switch (UART_Command.Header.ID) { #if ENABLE_CHINESE_FULL == 4 case 0x052B://read CMD_051B(UART_Command.Buffer); break; case 0x0538://write CMD_0538(UART_Command.Buffer); break; #endif #ifdef ENABLE_DOCK case 0x0801: CMD_0801(UART_Command.Buffer); break; #endif case 0x0514: CMD_0514(UART_Command.Buffer); break; case 0x051B: CMD_051B(UART_Command.Buffer); break; case 0x051D: CMD_051D(UART_Command.Buffer); break; case 0x0527: CMD_0527(); break; case 0x0529: CMD_0529(); break; #ifdef ENABLE_BLOCK case 0x052D: CMD_052D(UART_Command.Buffer); break; #endif case 0x052F: CMD_052F(UART_Command.Buffer); break; case 0x05DD: #if defined(ENABLE_OVERLAY) overlay_FLASH_RebootToBootloader(); #else NVIC_SystemReset(); #endif break; #ifdef ENABLE_UART_RW_BK_REGS case 0x0601: CMD_0601_ReadBK4819Reg(UART_Command.Buffer); break; case 0x0602: CMD_0602_WriteBK4819Reg(UART_Command.Buffer); break; #endif } } ================================================ FILE: app/uart.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef APP_UART_H #define APP_UART_H #include bool UART_IsCommandAvailable(void); void UART_HandleCommand(void); #endif ================================================ FILE: audio.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "audio.h" #include "bsp/dp32g030/gpio.h" #ifdef ENABLE_FMRADIO #include "driver/bk1080.h" #endif #include "driver/bk4819.h" #include "driver/gpio.h" #include "driver/system.h" #include "driver/systick.h" #include "functions.h" #include "misc.h" #include "settings.h" #include "ui/ui.h" BEEP_Type_t gBeepToPlay = BEEP_NONE; void AUDIO_PlayBeep(BEEP_Type_t Beep) { if (Beep != BEEP_880HZ_60MS_TRIPLE_BEEP && Beep != BEEP_500HZ_60MS_DOUBLE_BEEP && Beep != BEEP_440HZ_500MS && Beep != BEEP_880HZ_200MS && Beep != BEEP_880HZ_500MS && !gEeprom.BEEP_CONTROL) return; #ifdef ENABLE_AIRCOPY if (gScreenToDisplay == DISPLAY_AIRCOPY) return; #endif if (gCurrentFunction == FUNCTION_RECEIVE || gCurrentFunction == FUNCTION_MONITOR) return; #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Mute(true); #endif AUDIO_AudioPathOff(); if (gCurrentFunction == FUNCTION_POWER_SAVE && gRxIdleMode) BK4819_RX_TurnOn(); SYSTEM_DelayMs(20); uint16_t ToneConfig = BK4819_ReadRegister(BK4819_REG_71); uint16_t ToneFrequency; switch (Beep) { default: case BEEP_NONE: ToneFrequency = 220; break; case BEEP_1KHZ_60MS_OPTIONAL: ToneFrequency = 1000; break; case BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL: case BEEP_500HZ_60MS_DOUBLE_BEEP: ToneFrequency = 500; break; case BEEP_440HZ_40MS_OPTIONAL: case BEEP_440HZ_500MS: ToneFrequency = 440; break; case BEEP_880HZ_40MS_OPTIONAL: case BEEP_880HZ_60MS_TRIPLE_BEEP: case BEEP_880HZ_200MS: case BEEP_880HZ_500MS: ToneFrequency = 880; break; } BK4819_PlayTone(ToneFrequency, true); SYSTEM_DelayMs(2); AUDIO_AudioPathOn(); SYSTEM_DelayMs(60); uint16_t Duration; switch (Beep) { case BEEP_880HZ_60MS_TRIPLE_BEEP: BK4819_ExitTxMute(); SYSTEM_DelayMs(60); BK4819_EnterTxMute(); SYSTEM_DelayMs(20); [[fallthrough]]; case BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL: case BEEP_500HZ_60MS_DOUBLE_BEEP: BK4819_ExitTxMute(); SYSTEM_DelayMs(60); BK4819_EnterTxMute(); SYSTEM_DelayMs(20); [[fallthrough]]; case BEEP_1KHZ_60MS_OPTIONAL: BK4819_ExitTxMute(); Duration = 60; break; case BEEP_880HZ_40MS_OPTIONAL: case BEEP_440HZ_40MS_OPTIONAL: BK4819_ExitTxMute(); Duration = 40; break; case BEEP_880HZ_200MS: BK4819_ExitTxMute(); Duration = 200; break; case BEEP_440HZ_500MS: case BEEP_880HZ_500MS: default: BK4819_ExitTxMute(); Duration = 500; break; } SYSTEM_DelayMs(Duration); BK4819_EnterTxMute(); SYSTEM_DelayMs(20); AUDIO_AudioPathOff(); SYSTEM_DelayMs(5); BK4819_TurnsOffTones_TurnsOnRX(); SYSTEM_DelayMs(5); BK4819_WriteRegister(BK4819_REG_71, ToneConfig); if (gEnableSpeaker) AUDIO_AudioPathOn(); #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Mute(false); #endif if (gCurrentFunction == FUNCTION_POWER_SAVE && gRxIdleMode) BK4819_Sleep(); #ifdef ENABLE_VOX gVoxResumeCountdown = 80; #endif } #ifdef ENABLE_VOICE static const uint8_t VoiceClipLengthChinese[58] = { 0x32, 0x32, 0x32, 0x37, 0x37, 0x32, 0x32, 0x32, 0x32, 0x37, 0x37, 0x32, 0x64, 0x64, 0x64, 0x64, 0x64, 0x69, 0x64, 0x69, 0x5A, 0x5F, 0x5F, 0x64, 0x64, 0x69, 0x64, 0x64, 0x69, 0x69, 0x69, 0x64, 0x64, 0x6E, 0x69, 0x5F, 0x64, 0x64, 0x64, 0x69, 0x69, 0x69, 0x64, 0x69, 0x64, 0x64, 0x55, 0x5F, 0x5A, 0x4B, 0x4B, 0x46, 0x46, 0x69, 0x64, 0x6E, 0x5A, 0x64, }; static const uint8_t VoiceClipLengthEnglish[76] = { 0x50, 0x32, 0x2D, 0x2D, 0x2D, 0x37, 0x37, 0x37, 0x32, 0x32, 0x3C, 0x37, 0x46, 0x46, 0x4B, 0x82, 0x82, 0x6E, 0x82, 0x46, 0x96, 0x64, 0x46, 0x6E, 0x78, 0x6E, 0x87, 0x64, 0x96, 0x96, 0x46, 0x9B, 0x91, 0x82, 0x82, 0x73, 0x78, 0x64, 0x82, 0x6E, 0x78, 0x82, 0x87, 0x6E, 0x55, 0x78, 0x64, 0x69, 0x9B, 0x5A, 0x50, 0x3C, 0x32, 0x55, 0x64, 0x64, 0x50, 0x46, 0x46, 0x46, 0x4B, 0x4B, 0x50, 0x50, 0x55, 0x4B, 0x4B, 0x32, 0x32, 0x32, 0x32, 0x37, 0x41, 0x32, 0x3C, 0x37, }; VOICE_ID_t gVoiceID[8]; uint8_t gVoiceReadIndex; uint8_t gVoiceWriteIndex; volatile uint16_t gCountdownToPlayNextVoice_10ms; volatile bool gFlagPlayQueuedVoice; VOICE_ID_t gAnotherVoiceID = VOICE_ID_INVALID; static void AUDIO_PlayVoice(uint8_t VoiceID) { unsigned int i; GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0); SYSTEM_DelayMs(20); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0); for (i = 0; i < 8; i++) { if ((VoiceID & 0x80U) == 0) GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_1); else GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_1); SYSTICK_DelayUs(1000); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0); SYSTICK_DelayUs(1200); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0); VoiceID <<= 1; SYSTICK_DelayUs(200); } } void AUDIO_PlaySingleVoice(bool bFlag) { uint8_t VoiceID; uint8_t Delay; VoiceID = gVoiceID[0]; if (gEeprom.VOICE_PROMPT != VOICE_PROMPT_OFF && gVoiceWriteIndex > 0) { if (gEeprom.VOICE_PROMPT == VOICE_PROMPT_CHINESE) { // Chinese if (VoiceID >= ARRAY_SIZE(VoiceClipLengthChinese)) goto Bailout; Delay = VoiceClipLengthChinese[VoiceID]; VoiceID += VOICE_ID_CHI_BASE; } else { // English if (VoiceID >= ARRAY_SIZE(VoiceClipLengthEnglish)) goto Bailout; Delay = VoiceClipLengthEnglish[VoiceID]; VoiceID += VOICE_ID_ENG_BASE; } if (FUNCTION_IsRx()) // 1of11 BK4819_SetAF(BK4819_AF_MUTE); #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Mute(true); #endif AUDIO_AudioPathOn(); #ifdef ENABLE_VOX gVoxResumeCountdown = 2000; #endif SYSTEM_DelayMs(5); AUDIO_PlayVoice(VoiceID); if (gVoiceWriteIndex == 1) Delay += 3; if (bFlag) { SYSTEM_DelayMs(Delay * 10); if (FUNCTION_IsRx()) // 1of11 RADIO_SetModulation(gRxVfo->Modulation); #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Mute(false); #endif if (!gEnableSpeaker) AUDIO_AudioPathOff(); gVoiceWriteIndex = 0; gVoiceReadIndex = 0; #ifdef ENABLE_VOX gVoxResumeCountdown = 80; #endif return; } gVoiceReadIndex = 1; gCountdownToPlayNextVoice_10ms = Delay; gFlagPlayQueuedVoice = false; return; } Bailout: gVoiceReadIndex = 0; gVoiceWriteIndex = 0; } void AUDIO_SetVoiceID(uint8_t Index, VOICE_ID_t VoiceID) { if (Index >= ARRAY_SIZE(gVoiceID)) return; if (Index == 0) { gVoiceWriteIndex = 0; gVoiceReadIndex = 0; } gVoiceID[Index] = VoiceID; gVoiceWriteIndex++; } uint8_t AUDIO_SetDigitVoice(uint8_t Index, uint16_t Value) { uint16_t Remainder; uint8_t Result; uint8_t Count; if (Index == 0) { gVoiceWriteIndex = 0; gVoiceReadIndex = 0; } Count = 0; Result = Value / 1000U; Remainder = Value % 1000U; if (Remainder < 100U) { if (Remainder < 10U) goto Skip; } else { Result = Remainder / 100U; gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Result; Count++; Remainder -= Result * 100U; } Result = Remainder / 10U; gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Result; Count++; Remainder -= Result * 10U; Skip: gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Remainder; return Count + 1U; } void AUDIO_PlayQueuedVoice(void) { uint8_t VoiceID; uint8_t Delay; bool Skip; Skip = false; if (gVoiceReadIndex != gVoiceWriteIndex && gEeprom.VOICE_PROMPT != VOICE_PROMPT_OFF) { VoiceID = gVoiceID[gVoiceReadIndex]; if (gEeprom.VOICE_PROMPT == VOICE_PROMPT_CHINESE) { if (VoiceID < ARRAY_SIZE(VoiceClipLengthChinese)) { Delay = VoiceClipLengthChinese[VoiceID]; VoiceID += VOICE_ID_CHI_BASE; } else Skip = true; } else { if (VoiceID < ARRAY_SIZE(VoiceClipLengthEnglish)) { Delay = VoiceClipLengthEnglish[VoiceID]; VoiceID += VOICE_ID_ENG_BASE; } else Skip = true; } gVoiceReadIndex++; if (!Skip) { if (gVoiceReadIndex == gVoiceWriteIndex) Delay += 3; AUDIO_PlayVoice(VoiceID); gCountdownToPlayNextVoice_10ms = Delay; gFlagPlayQueuedVoice = false; #ifdef ENABLE_VOX gVoxResumeCountdown = 2000; #endif return; } } if (FUNCTION_IsRx()) { RADIO_SetModulation(gRxVfo->Modulation); // 1of11 } #ifdef ENABLE_FMRADIO if (gFmRadioMode) BK1080_Mute(false); #endif if (!gEnableSpeaker) AUDIO_AudioPathOff(); #ifdef ENABLE_VOX gVoxResumeCountdown = 80; #endif gVoiceWriteIndex = 0; gVoiceReadIndex = 0; } #endif ================================================ FILE: audio.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef AUDIO_H #define AUDIO_H #include #include #include "bsp/dp32g030/gpio.h" #include "driver/gpio.h" enum BEEP_Type_t { BEEP_NONE = 0, BEEP_1KHZ_60MS_OPTIONAL, BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL, BEEP_440HZ_500MS, BEEP_880HZ_200MS, BEEP_880HZ_500MS, BEEP_500HZ_60MS_DOUBLE_BEEP, BEEP_440HZ_40MS_OPTIONAL, BEEP_880HZ_40MS_OPTIONAL, BEEP_880HZ_60MS_TRIPLE_BEEP }; typedef enum BEEP_Type_t BEEP_Type_t; extern BEEP_Type_t gBeepToPlay; void AUDIO_PlayBeep(BEEP_Type_t Beep); enum { VOICE_ID_CHI_BASE = 0x10U, VOICE_ID_ENG_BASE = 0x60U, }; enum VOICE_ID_t { VOICE_ID_0 = 0x00U, VOICE_ID_1 = 0x01U, VOICE_ID_2 = 0x02U, VOICE_ID_3 = 0x03U, VOICE_ID_4 = 0x04U, VOICE_ID_5 = 0x05U, VOICE_ID_6 = 0x06U, VOICE_ID_7 = 0x07U, VOICE_ID_8 = 0x08U, VOICE_ID_9 = 0x09U, VOICE_ID_10 = 0x0AU, VOICE_ID_100 = 0x0BU, VOICE_ID_WELCOME = 0x0CU, VOICE_ID_LOCK = 0x0DU, VOICE_ID_UNLOCK = 0x0EU, VOICE_ID_SCANNING_BEGIN = 0x0FU, VOICE_ID_SCANNING_STOP = 0x10U, VOICE_ID_SCRAMBLER_ON = 0x11U, VOICE_ID_SCRAMBLER_OFF = 0x12U, VOICE_ID_FUNCTION = 0x13U, VOICE_ID_CTCSS = 0x14U, VOICE_ID_DCS = 0x15U, VOICE_ID_POWER = 0x16U, VOICE_ID_SAVE_MODE = 0x17U, VOICE_ID_MEMORY_CHANNEL = 0x18U, VOICE_ID_DELETE_CHANNEL = 0x19U, VOICE_ID_FREQUENCY_STEP = 0x1AU, VOICE_ID_SQUELCH = 0x1BU, VOICE_ID_TRANSMIT_OVER_TIME = 0x1CU, VOICE_ID_BACKLIGHT_SELECTION = 0x1DU, VOICE_ID_VOX = 0x1EU, VOICE_ID_TX_OFFSET_FREQUENCY_DIRECTION = 0x1FU, VOICE_ID_TX_OFFSET_FREQUENCY = 0x20U, VOICE_ID_TRANSMITING_MEMORY = 0x21U, VOICE_ID_RECEIVING_MEMORY = 0x22U, VOICE_ID_EMERGENCY_CALL = 0x23U, VOICE_ID_LOW_VOLTAGE = 0x24U, VOICE_ID_CHANNEL_MODE = 0x25U, VOICE_ID_FREQUENCY_MODE = 0x26U, VOICE_ID_VOICE_PROMPT = 0x27U, VOICE_ID_BAND_SELECTION = 0x28U, VOICE_ID_DUAL_STANDBY = 0x29U, VOICE_ID_CHANNEL_BANDWIDTH = 0x2AU, VOICE_ID_OPTIONAL_SIGNAL = 0x2BU, VOICE_ID_MUTE_MODE = 0x2CU, VOICE_ID_BUSY_LOCKOUT = 0x2DU, VOICE_ID_BEEP_PROMPT = 0x2EU, VOICE_ID_ANI_CODE = 0x2FU, VOICE_ID_INITIALISATION = 0x30U, VOICE_ID_CONFIRM = 0x31U, VOICE_ID_CANCEL = 0x32U, VOICE_ID_ON = 0x33U, VOICE_ID_OFF = 0x34U, VOICE_ID_2_TONE = 0x35U, VOICE_ID_5_TONE = 0x36U, VOICE_ID_DIGITAL_SIGNAL = 0x37U, VOICE_ID_REPEATER = 0x38U, VOICE_ID_MENU = 0x39U, VOICE_ID_11 = 0x3AU, VOICE_ID_12 = 0x3BU, VOICE_ID_13 = 0x3CU, VOICE_ID_14 = 0x3DU, VOICE_ID_15 = 0x3EU, VOICE_ID_16 = 0x3FU, VOICE_ID_17 = 0x40U, VOICE_ID_18 = 0x41U, VOICE_ID_19 = 0x42U, VOICE_ID_20 = 0x43U, VOICE_ID_30 = 0x44U, VOICE_ID_40 = 0x45U, VOICE_ID_50 = 0x46U, VOICE_ID_60 = 0x47U, VOICE_ID_70 = 0x48U, VOICE_ID_80 = 0x49U, VOICE_ID_90 = 0x4AU, VOICE_ID_END = 0x4BU, VOICE_ID_INVALID = 0xFFU, }; typedef enum VOICE_ID_t VOICE_ID_t; static inline void AUDIO_AudioPathOn(void) { GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH); } static inline void AUDIO_AudioPathOff(void) { GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH); } #ifdef ENABLE_VOICE extern VOICE_ID_t gVoiceID[8]; extern uint8_t gVoiceReadIndex; extern uint8_t gVoiceWriteIndex; extern volatile uint16_t gCountdownToPlayNextVoice_10ms; extern volatile bool gFlagPlayQueuedVoice; extern VOICE_ID_t gAnotherVoiceID; void AUDIO_PlaySingleVoice(bool bFlag); void AUDIO_SetVoiceID(uint8_t Index, VOICE_ID_t VoiceID); uint8_t AUDIO_SetDigitVoice(uint8_t Index, uint16_t Value); void AUDIO_PlayQueuedVoice(void); #endif #endif ================================================ FILE: bitmaps.c ================================================ #include "bitmaps.h" // all these images are on their right sides // turn your monitor 90-deg anti-clockwise to see the images const uint8_t BITMAP_POWERSAVE[8] = { // "PS" 0b00000000, 0b01111111, 0b00010001, 0b00001110, 0b00000000, 0b01000110, 0b01001001, 0b00110001 }; const uint8_t BITMAP_TX[6] = { // "TX" 0b00000000, 0b00000001, 0b00000001, 0b01111111, 0b00000001, 0b00000001, // 0b00000000, // 0b00000000 }; const uint8_t BITMAP_RX[5] = { // "RX" 0b00000000, 0b01111111, 0b00001001, 0b00011001, 0b01100110, // 0b00000000, // 0b00000000, // 0b00000000 }; const uint8_t BITMAP_FM[10] = { // "FM" 0b00000000, 0b01111111, 0b00001001, 0b00000001, 0b00000000, 0b01111111, 0b00000010, 0b00001100, 0b00000010, 0b01111111 }; const uint8_t BITMAP_BatteryLevel[2] = { 0b01011101, 0b01011101 }; #ifndef ENABLE_REVERSE_BAT_SYMBOL // Quansheng way (+ pole to the left) const uint8_t BITMAP_BatteryLevel1[17] = { 0b00000000, 0b00111110, 0b00100010, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01111111 }; #else // reversed (+ pole to the right) const uint8_t BITMAP_BatteryLevel1[17] = { 0b00000000, 0b01111111, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b01000001, 0b00100010, 0b00111110 }; #endif const uint8_t BITMAP_USB_C[9] = { // USB symbol 0b00000000, 0b00011100, 0b00100111, 0b01000100, 0b01000100, 0b01000100, 0b01000100, 0b00100111, 0b00011100 }; const uint8_t BITMAP_KeyLock[6] = { // teeny padlock symbol 0b00000000, 0b01111100, 0b01000110, 0b01000101, 0b01000110, 0b01111100 }; const uint8_t BITMAP_F_Key[6] = { // F-Key symbol 0b00000000, 0b01011111, 0b01000101, 0b01000101, 0b01000101, 0b01000001 }; #ifdef ENABLE_VOX const uint8_t BITMAP_VOX[18] = { // "VOX" 0b00000000, 0b00011111, 0b00100000, 0b01000000, 0b00100000, 0b00011111, 0b00000000, 0b00111110, 0b01000001, 0b01000001, 0b01000001, 0b00111110, 0b00000000, 0b01100011, 0b00010100, 0b00001000, 0b00010100, 0b01100011 }; #endif // 'XB' (cross-band/cross-VFO) const uint8_t BITMAP_XB[12] = { // "XB" 0b00000000, 0b01100011, 0b00010100, 0b00001000, 0b00010100, 0b01100011, 0b00000000, 0b01111111, 0b01001001, 0b01001001, 0b01001001, 0b00110110 }; const uint8_t BITMAP_TDR1[16] = { // "DWR" 0b00000000, 0b01111111, 0b01000001, 0b01000001, 0b00111110, 0b00000000, 0b01111111, 0b00100000, 0b00011000, 0b00100000, 0b01111111, 0b00000000, 0b01111111, 0b00011001, 0b00101001, 0b01000110 }; const uint8_t BITMAP_TDR2[9] = { // "><" .. DW on hold // 0b00000000, 0b00100010, 0b00110110, 0b00011100, 0b00001000, 0b00000000, 0b00001000, 0b00011100, 0b00110110, 0b00100010, }; #ifdef ENABLE_VOICE const uint8_t BITMAP_VoicePrompt[9] = { 0b00000000, 0b00011000, 0b00011000, 0b00100100, 0b00100100, 0b01000010, 0b01000010, 0b11111111, 0b00011000 }; #endif #ifdef ENABLE_NOAA const uint8_t BITMAP_NOAA[11] = { // "NS" 0b00000000, 0b01111111, 0b00000100, 0b00001000, 0b00010000, 0b01111111, 0b00000000, 0b01000110, 0b01001001, 0b01001001, 0b00110001 }; #endif const uint8_t BITMAP_Antenna[5] = { 0b00000011, 0b00000101, 0b01111111, 0b00000101, 0b00000011 }; const uint8_t BITMAP_VFO_Default[7] = { // 0b00000000, 0b01111111, 0b01111111, 0b00111110, 0b00111110, 0b00011100, 0b00011100, 0b00001000 }; const uint8_t BITMAP_VFO_NotDefault[7] = { // 0b00000000, 0b01000001, 0b01000001, 0b00100010, 0b00100010, 0b00010100, 0b00010100, 0b00001000 }; const uint8_t BITMAP_ScanList1[3] = { // 'I' symbol // 0b00000000, // 0b00000000, 0b01000010, 0b01111110, 0b01000010, // 0b00000000 }; const uint8_t BITMAP_ScanList2[5] = { // 'II' symbol // 0b00000000, 0b01000010, 0b01111110, 0b01000010, 0b01111110, 0b01000010 }; const uint8_t BITMAP_compand[5] = { // 0b00000000, 0b00111100, 0b01000010, 0b01000010, 0b01000010, 0b00100100 }; const uint8_t BITMAP_RECV[13] = { 0x7F, 0x7F, 0x1B, 0x3B, 0x7F, 0x66,0X00,0x63, 0x77, 0x1C, 0x1C, 0x77, 0x63 }; const uint8_t BITMAP_SEND[13] = { 0x03, 0x03, 0x7F, 0x7F, 0x03, 0x03,0X00, 0x63, 0x77, 0x1C, 0x1C, 0x77, 0x63 }; #ifdef ENABLE_MESSENGER const uint8_t BITMAP_NEWMSG[7] = { // message icon // 0b00000000, 0b01111110, 0b01000110, 0b01001010, 0b01010010, 0b01001010, 0b01000110, 0b01111110, }; const uint8_t BITMAP_t[6] = { // "t" 0b00000000, 0b00000100, 0b00000100, 0b00111111, 0b01000100, 0b00100100, }; const uint8_t BITMAP_1[6] = { // "1" 0b00000000, 0b00000000, 0b01000010, 0b01111111, 0b01000000, 0b00000000, }; #endif #include "ui/helper.h" #ifdef ENABLE_PINYIN const uint8_t BITMAP_ARRAY_DOWN[5] = { 0b00000011, 0b00001111, 0b00011111, 0b00001111, 0b00000011 }; const uint8_t BITMAP_ARRAY_UP[5] = { 0b01100000, 0b01111000, 0b01111110, 0b01111000, 0b01100000 }; const uint8_t BITMAP_CN[7] ={ 0b00111100, 0b00100100, 0b00100100, 0b11111111, 0b00100100, 0b00100100, 0b00111100, }; const uint8_t BITMAP_POINT[2] ={ 0b0000011, 0b00110000, }; #endif ================================================ FILE: bitmaps.h ================================================ #ifndef BITMAP_H #define BITMAP_H #include extern const uint8_t BITMAP_POWERSAVE[8]; extern const uint8_t BITMAP_TX[6]; extern const uint8_t BITMAP_RX[5]; extern const uint8_t BITMAP_FM[10]; extern const uint8_t BITMAP_BatteryLevel[2]; extern const uint8_t BITMAP_BatteryLevel1[17]; extern const uint8_t BITMAP_USB_C[9]; extern const uint8_t BITMAP_KeyLock[6]; extern const uint8_t BITMAP_F_Key[6]; #ifdef ENABLE_VOX extern const uint8_t BITMAP_VOX[18]; #endif extern const uint8_t BITMAP_XB[12]; extern const uint8_t BITMAP_TDR1[16]; extern const uint8_t BITMAP_TDR2[9]; #ifdef ENABLE_VOICE extern const uint8_t BITMAP_VoicePrompt[9]; #endif #ifdef ENABLE_NOAA extern const uint8_t BITMAP_NOAA[11]; #endif extern const uint8_t BITMAP_Antenna[5]; extern const uint8_t BITMAP_VFO_Default[7]; extern const uint8_t BITMAP_VFO_NotDefault[7]; extern const uint8_t BITMAP_ScanList1[3]; extern const uint8_t BITMAP_ScanList2[5]; extern const uint8_t BITMAP_compand[5]; extern const uint8_t BITMAP_RECV[13] ; extern const uint8_t BITMAP_SEND[13] ; #ifdef ENABLE_MESSENGER extern const uint8_t BITMAP_1[6] ; extern const uint8_t BITMAP_t[6] ; extern const uint8_t BITMAP_NEWMSG[7] ; #endif #ifdef ENABLE_PINYIN extern const uint8_t BITMAP_ARRAY_DOWN[5] ; extern const uint8_t BITMAP_ARRAY_UP[5] ; extern const uint8_t BITMAP_CN[7] ; #endif #endif ================================================ FILE: board.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "board.h" #include "bsp/dp32g030/gpio.h" #include "bsp/dp32g030/portcon.h" #include "bsp/dp32g030/saradc.h" #include "bsp/dp32g030/syscon.h" #include "driver/adc.h" #include "driver/backlight.h" #include "ARMCM0.h" #include "bsp/dp32g030/pmu.h" #include "bsp/dp32g030/saradc.h" #include "bsp/dp32g030/syscon.h" #include "sram-overlay.h" #include "driver/eeprom.h" #ifdef ENABLE_FMRADIO #include "driver/bk1080.h" #endif #include "driver/crc.h" #include "driver/eeprom.h" #include "driver/flash.h" #include "driver/gpio.h" #include "driver/system.h" #include "driver/st7565.h" #include "frequencies.h" #include "helper/battery.h" #include "misc.h" #include "settings.h" #if defined(ENABLE_OVERLAY) #include "sram-overlay.h" #endif #if defined(ENABLE_OVERLAY) void BOARD_FLASH_Init(void) { FLASH_Init(FLASH_READ_MODE_1_CYCLE); FLASH_ConfigureTrimValues(); SYSTEM_ConfigureClocks(); overlay_FLASH_MainClock = 48000000; overlay_FLASH_ClockMultiplier = 48; FLASH_Init(FLASH_READ_MODE_2_CYCLE); } #endif void BOARD_GPIO_Init(void) { GPIOA->DIR |= 0 // A7 = UART1 TX default as OUTPUT from bootloader! // A8 = UART1 RX default as INPUT from bootloader! // Key pad + I2C | GPIO_DIR_10_BITS_OUTPUT // Key pad + I2C | GPIO_DIR_11_BITS_OUTPUT // Key pad + Voice chip | GPIO_DIR_12_BITS_OUTPUT // Key pad + Voice chip | GPIO_DIR_13_BITS_OUTPUT; GPIOA->DIR &= ~(0 // Key pad | GPIO_DIR_3_MASK // INPUT // Key pad | GPIO_DIR_4_MASK // INPUT // Key pad | GPIO_DIR_5_MASK // INPUT // Key pad | GPIO_DIR_6_MASK // INPUT ); GPIOB->DIR |= 0 // ST7565 | GPIO_DIR_9_BITS_OUTPUT // ST7565 + SWD IO | GPIO_DIR_11_BITS_OUTPUT // B14 = SWD_CLK assumed INPUT by default // BK1080 | GPIO_DIR_15_BITS_OUTPUT; GPIOC->DIR |= 0 // BK4819 SCN | GPIO_DIR_0_BITS_OUTPUT // BK4819 SCL | GPIO_DIR_1_BITS_OUTPUT // BK4819 SDA | GPIO_DIR_2_BITS_OUTPUT // Flash light | GPIO_DIR_3_BITS_OUTPUT // Speaker | GPIO_DIR_4_BITS_OUTPUT; GPIOC->DIR &= ~(0 // PTT button | GPIO_DIR_5_MASK // INPUT ); #if defined(ENABLE_FMRADIO) GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080); #endif } void BOARD_PORTCON_Init(void) { // PORT A pin selection PORTCON_PORTA_SEL0 &= ~(0 // Key pad | PORTCON_PORTA_SEL0_A3_MASK // Key pad | PORTCON_PORTA_SEL0_A4_MASK // Key pad | PORTCON_PORTA_SEL0_A5_MASK // Key pad | PORTCON_PORTA_SEL0_A6_MASK ); PORTCON_PORTA_SEL0 |= 0 // Key pad | PORTCON_PORTA_SEL0_A3_BITS_GPIOA3 // Key pad | PORTCON_PORTA_SEL0_A4_BITS_GPIOA4 // Key pad | PORTCON_PORTA_SEL0_A5_BITS_GPIOA5 // Key pad | PORTCON_PORTA_SEL0_A6_BITS_GPIOA6 // UART1 TX, wasn't cleared in previous step / relying on default value! | PORTCON_PORTA_SEL0_A7_BITS_UART1_TX; PORTCON_PORTA_SEL1 &= ~(0 // Key pad + I2C | PORTCON_PORTA_SEL1_A10_MASK // Key pad + I2C | PORTCON_PORTA_SEL1_A11_MASK // Key pad + Voice chip | PORTCON_PORTA_SEL1_A12_MASK // Key pad + Voice chip | PORTCON_PORTA_SEL1_A13_MASK ); PORTCON_PORTA_SEL1 |= 0 // UART1 RX, wasn't cleared in previous step / relying on default value! | PORTCON_PORTA_SEL1_A8_BITS_UART1_RX // Battery voltage, wasn't cleared in previous step / relying on default value! | PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4 // Key pad + I2C | PORTCON_PORTA_SEL1_A10_BITS_GPIOA10 // Key pad + I2C | PORTCON_PORTA_SEL1_A11_BITS_GPIOA11 // Key pad + Voice chip | PORTCON_PORTA_SEL1_A12_BITS_GPIOA12 // Key pad + Voice chip | PORTCON_PORTA_SEL1_A13_BITS_GPIOA13 // Battery Current, wasn't cleared in previous step / relying on default value! | PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9; // PORT B pin selection PORTCON_PORTB_SEL0 &= ~(0 // SPI0 SSN | PORTCON_PORTB_SEL0_B7_MASK ); PORTCON_PORTB_SEL0 |= 0 // SPI0 SSN | PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN; PORTCON_PORTB_SEL1 &= ~(0 // ST7565 | PORTCON_PORTB_SEL1_B9_MASK // ST7565 + SWD IO | PORTCON_PORTB_SEL1_B11_MASK // SWD CLK | PORTCON_PORTB_SEL1_B14_MASK // BK1080 | PORTCON_PORTB_SEL1_B15_MASK ); PORTCON_PORTB_SEL1 |= 0 // SPI0 CLK, wasn't cleared in previous step / relying on default value! | PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK // ST7565 | PORTCON_PORTB_SEL1_B9_BITS_GPIOB9 // SPI0 MOSI, wasn't cleared in previous step / relying on default value! | PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI #if defined(ENABLE_SWD) // SWD IO | PORTCON_PORTB_SEL1_B11_BITS_SWDIO // SWD CLK | PORTCON_PORTB_SEL1_B14_BITS_SWCLK #else // ST7565 | PORTCON_PORTB_SEL1_B11_BITS_GPIOB11 #endif ; // PORT C pin selection PORTCON_PORTC_SEL0 &= ~(0 // BK4819 SCN | PORTCON_PORTC_SEL0_C0_MASK // BK4819 SCL | PORTCON_PORTC_SEL0_C1_MASK // BK4819 SDA | PORTCON_PORTC_SEL0_C2_MASK // Flash light | PORTCON_PORTC_SEL0_C3_MASK // Speaker | PORTCON_PORTC_SEL0_C4_MASK // PTT button | PORTCON_PORTC_SEL0_C5_MASK ); // PORT A pin configuration PORTCON_PORTA_IE |= 0 // Keypad | PORTCON_PORTA_IE_A3_BITS_ENABLE // Keypad | PORTCON_PORTA_IE_A4_BITS_ENABLE // Keypad | PORTCON_PORTA_IE_A5_BITS_ENABLE // Keypad | PORTCON_PORTA_IE_A6_BITS_ENABLE // A7 = UART1 TX disabled by default // UART1 RX | PORTCON_PORTA_IE_A8_BITS_ENABLE; PORTCON_PORTA_IE &= ~(0 // Keypad + I2C | PORTCON_PORTA_IE_A10_MASK // Keypad + I2C | PORTCON_PORTA_IE_A11_MASK // Keypad + Voice chip | PORTCON_PORTA_IE_A12_MASK // Keypad + Voice chip | PORTCON_PORTA_IE_A13_MASK ); PORTCON_PORTA_PU |= 0 // Keypad | PORTCON_PORTA_PU_A3_BITS_ENABLE // Keypad | PORTCON_PORTA_PU_A4_BITS_ENABLE // Keypad | PORTCON_PORTA_PU_A5_BITS_ENABLE // Keypad | PORTCON_PORTA_PU_A6_BITS_ENABLE; PORTCON_PORTA_PU &= ~(0 // Keypad + I2C | PORTCON_PORTA_PU_A10_MASK // Keypad + I2C | PORTCON_PORTA_PU_A11_MASK // Keypad + Voice chip | PORTCON_PORTA_PU_A12_MASK // Keypad + Voice chip | PORTCON_PORTA_PU_A13_MASK ); PORTCON_PORTA_PD &= ~(0 // Keypad | PORTCON_PORTA_PD_A3_MASK // Keypad | PORTCON_PORTA_PD_A4_MASK // Keypad | PORTCON_PORTA_PD_A5_MASK // Keypad | PORTCON_PORTA_PD_A6_MASK // Keypad + I2C | PORTCON_PORTA_PD_A10_MASK // Keypad + I2C | PORTCON_PORTA_PD_A11_MASK // Keypad + Voice chip | PORTCON_PORTA_PD_A12_MASK // Keypad + Voice chip | PORTCON_PORTA_PD_A13_MASK ); PORTCON_PORTA_OD |= 0 // Keypad | PORTCON_PORTA_OD_A3_BITS_ENABLE // Keypad | PORTCON_PORTA_OD_A4_BITS_ENABLE // Keypad | PORTCON_PORTA_OD_A5_BITS_ENABLE // Keypad | PORTCON_PORTA_OD_A6_BITS_ENABLE; PORTCON_PORTA_OD &= ~(0 // Keypad + I2C | PORTCON_PORTA_OD_A10_MASK // Keypad + I2C | PORTCON_PORTA_OD_A11_MASK // Keypad + Voice chip | PORTCON_PORTA_OD_A12_MASK // Keypad + Voice chip | PORTCON_PORTA_OD_A13_MASK ); // PORT B pin configuration PORTCON_PORTB_IE |= 0 | PORTCON_PORTB_IE_B14_BITS_ENABLE; PORTCON_PORTB_IE &= ~(0 // Back light | PORTCON_PORTB_IE_B6_MASK // UART1 | PORTCON_PORTB_IE_B7_MASK | PORTCON_PORTB_IE_B8_MASK // ST7565 | PORTCON_PORTB_IE_B9_MASK // SPI0 MOSI | PORTCON_PORTB_IE_B10_MASK #if !defined(ENABLE_SWD) // ST7565 | PORTCON_PORTB_IE_B11_MASK #endif // BK1080 | PORTCON_PORTB_IE_B15_MASK ); PORTCON_PORTB_PU &= ~(0 // Back light | PORTCON_PORTB_PU_B6_MASK // ST7565 | PORTCON_PORTB_PU_B9_MASK // ST7565 + SWD IO | PORTCON_PORTB_PU_B11_MASK // SWD CLK | PORTCON_PORTB_PU_B14_MASK // BK1080 | PORTCON_PORTB_PU_B15_MASK ); PORTCON_PORTB_PD &= ~(0 // Back light | PORTCON_PORTB_PD_B6_MASK // ST7565 | PORTCON_PORTB_PD_B9_MASK // ST7565 + SWD IO | PORTCON_PORTB_PD_B11_MASK // SWD CLK | PORTCON_PORTB_PD_B14_MASK // BK1080 | PORTCON_PORTB_PD_B15_MASK ); PORTCON_PORTB_OD &= ~(0 // Back light | PORTCON_PORTB_OD_B6_MASK // ST7565 | PORTCON_PORTB_OD_B9_MASK // ST7565 + SWD IO | PORTCON_PORTB_OD_B11_MASK // BK1080 | PORTCON_PORTB_OD_B15_MASK ); PORTCON_PORTB_OD |= 0 // SWD CLK | PORTCON_PORTB_OD_B14_BITS_ENABLE; // PORT C pin configuration PORTCON_PORTC_IE |= 0 // PTT button | PORTCON_PORTC_IE_C5_BITS_ENABLE; PORTCON_PORTC_IE &= ~(0 // BK4819 SCN | PORTCON_PORTC_IE_C0_MASK // BK4819 SCL | PORTCON_PORTC_IE_C1_MASK // BK4819 SDA | PORTCON_PORTC_IE_C2_MASK // Flash Light | PORTCON_PORTC_IE_C3_MASK // Speaker | PORTCON_PORTC_IE_C4_MASK ); PORTCON_PORTC_PU |= 0 // PTT button | PORTCON_PORTC_PU_C5_BITS_ENABLE; PORTCON_PORTC_PU &= ~(0 // BK4819 SCN | PORTCON_PORTC_PU_C0_MASK // BK4819 SCL | PORTCON_PORTC_PU_C1_MASK // BK4819 SDA | PORTCON_PORTC_PU_C2_MASK // Flash Light | PORTCON_PORTC_PU_C3_MASK // Speaker | PORTCON_PORTC_PU_C4_MASK ); PORTCON_PORTC_PD &= ~(0 // BK4819 SCN | PORTCON_PORTC_PD_C0_MASK // BK4819 SCL | PORTCON_PORTC_PD_C1_MASK // BK4819 SDA | PORTCON_PORTC_PD_C2_MASK // Flash Light | PORTCON_PORTC_PD_C3_MASK // Speaker | PORTCON_PORTC_PD_C4_MASK // PTT Button | PORTCON_PORTC_PD_C5_MASK ); PORTCON_PORTC_OD &= ~(0 // BK4819 SCN | PORTCON_PORTC_OD_C0_MASK // BK4819 SCL | PORTCON_PORTC_OD_C1_MASK // BK4819 SDA | PORTCON_PORTC_OD_C2_MASK // Flash Light | PORTCON_PORTC_OD_C3_MASK // Speaker | PORTCON_PORTC_OD_C4_MASK ); PORTCON_PORTC_OD |= 0 // BK4819 SCN | PORTCON_PORTC_OD_C0_BITS_DISABLE // BK4819 SCL | PORTCON_PORTC_OD_C1_BITS_DISABLE // BK4819 SDA | PORTCON_PORTC_OD_C2_BITS_DISABLE // Flash Light | PORTCON_PORTC_OD_C3_BITS_DISABLE // Speaker | PORTCON_PORTC_OD_C4_BITS_DISABLE // PTT button | PORTCON_PORTC_OD_C5_BITS_ENABLE; } void BOARD_ADC_Init(void) { ADC_Configure(); ADC_Enable(); ADC_SoftReset(); } void BOARD_ADC_GetBatteryInfo(uint16_t *pVoltage, uint16_t *pCurrent) { ADC_Start(); while (!ADC_CheckEndOfConversion(ADC_CH9)) {} *pVoltage = ADC_GetValue(ADC_CH4); *pCurrent = ADC_GetValue(ADC_CH9); } void BOARD_Init(void) { BOARD_PORTCON_Init(); BOARD_GPIO_Init(); BACKLIGHT_InitHardware(); BOARD_ADC_Init(); ST7565_Init(); #ifdef ENABLE_FMRADIO BK1080_Init(0, false); #endif #if defined(ENABLE_UART) || defined(ENABLED_AIRCOPY) CRC_Init(); #endif } void write_to_memory(uint32_t address, uint32_t data) { // ֵַתΪָ uint32_t *target_address = (uint32_t *) address; // Ŀַд *target_address = data; // Ϊ˱Żȷ벻ᱻŻ volatile uint32_t read_back = *target_address; } //JUMP_TO_FLASH(0xa10A,0x20003ff0); void JUMP_TO_FLASH(uint32_t flash_add,uint32_t stack_add) { __disable_irq(); ClearStack(); __set_MSP(stack_add); __set_PC(flash_add); } ================================================ FILE: board.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef BOARD_H #define BOARD_H #include #include void BOARD_FLASH_Init(void); void BOARD_GPIO_Init(void); void BOARD_PORTCON_Init(void); void BOARD_ADC_Init(void); void BOARD_ADC_GetBatteryInfo(uint16_t *pVoltage, uint16_t *pCurrent); void BOARD_Init(void); void JUMP_TO_FLASH(uint32_t flash_add,uint32_t stack_add); void write_to_memory(uint32_t address, uint32_t data) ; #endif ================================================ FILE: bsp/dp32g030/aes.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_AES_H #define HARDWARE_DP32G030_AES_H #if !defined(__ASSEMBLY__) #include #endif /* -------- AES -------- */ #define AES_BASE_ADDR 0x400BD000U #define AES_BASE_SIZE 0x00000800U #define AES_CR_ADDR (AES_BASE_ADDR + 0x0000U) #define AES_CR (*(volatile uint32_t *)AES_CR_ADDR) #define AES_CR_EN_SHIFT 0 #define AES_CR_EN_WIDTH 1 #define AES_CR_EN_MASK (((1U << AES_CR_EN_WIDTH) - 1U) << AES_CR_EN_SHIFT) #define AES_CR_EN_VALUE_DISABLE 0U #define AES_CR_EN_BITS_DISABLE (AES_CR_EN_VALUE_DISABLE << AES_CR_EN_SHIFT) #define AES_CR_EN_VALUE_ENABLE 1U #define AES_CR_EN_BITS_ENABLE (AES_CR_EN_VALUE_ENABLE << AES_CR_EN_SHIFT) #define AES_CR_CHMOD_SHIFT 5 #define AES_CR_CHMOD_WIDTH 2 #define AES_CR_CHMOD_MASK (((1U << AES_CR_CHMOD_WIDTH) - 1U) << AES_CR_CHMOD_SHIFT) #define AES_CR_CHMOD_VALUE_ECB 0U #define AES_CR_CHMOD_BITS_ECB (AES_CR_CHMOD_VALUE_ECB << AES_CR_CHMOD_SHIFT) #define AES_CR_CHMOD_VALUE_CBC 1U #define AES_CR_CHMOD_BITS_CBC (AES_CR_CHMOD_VALUE_CBC << AES_CR_CHMOD_SHIFT) #define AES_CR_CHMOD_VALUE_CTR 2U #define AES_CR_CHMOD_BITS_CTR (AES_CR_CHMOD_VALUE_CTR << AES_CR_CHMOD_SHIFT) #define AES_CR_CCFC_SHIFT 7 #define AES_CR_CCFC_WIDTH 1 #define AES_CR_CCFC_MASK (((1U << AES_CR_CCFC_WIDTH) - 1U) << AES_CR_CCFC_SHIFT) #define AES_CR_CCFC_VALUE_SET 1U #define AES_CR_CCFC_BITS_SET (AES_CR_CCFC_VALUE_SET << AES_CR_CCFC_SHIFT) #define AES_SR_ADDR (AES_BASE_ADDR + 0x0004U) #define AES_SR (*(volatile uint32_t *)AES_SR_ADDR) #define AES_SR_CCF_SHIFT 0 #define AES_SR_CCF_WIDTH 1 #define AES_SR_CCF_MASK (((1U << AES_SR_CCF_WIDTH) - 1U) << AES_SR_CCF_SHIFT) #define AES_SR_CCF_VALUE_NOT_COMPLETE 0U #define AES_SR_CCF_BITS_NOT_COMPLETE (AES_SR_CCF_VALUE_NOT_COMPLETE << AES_SR_CCF_SHIFT) #define AES_SR_CCF_VALUE_COMPLETE 1U #define AES_SR_CCF_BITS_COMPLETE (AES_SR_CCF_VALUE_COMPLETE << AES_SR_CCF_SHIFT) #define AES_DINR_ADDR (AES_BASE_ADDR + 0x0008U) #define AES_DINR (*(volatile uint32_t *)AES_DINR_ADDR) #define AES_DOUTR_ADDR (AES_BASE_ADDR + 0x000CU) #define AES_DOUTR (*(volatile uint32_t *)AES_DOUTR_ADDR) #define AES_KEYR0_ADDR (AES_BASE_ADDR + 0x0010U) #define AES_KEYR0 (*(volatile uint32_t *)AES_KEYR0_ADDR) #define AES_KEYR1_ADDR (AES_BASE_ADDR + 0x0014U) #define AES_KEYR1 (*(volatile uint32_t *)AES_KEYR1_ADDR) #define AES_KEYR2_ADDR (AES_BASE_ADDR + 0x0018U) #define AES_KEYR2 (*(volatile uint32_t *)AES_KEYR2_ADDR) #define AES_KEYR3_ADDR (AES_BASE_ADDR + 0x001CU) #define AES_KEYR3 (*(volatile uint32_t *)AES_KEYR3_ADDR) #define AES_IVR0_ADDR (AES_BASE_ADDR + 0x0020U) #define AES_IVR0 (*(volatile uint32_t *)AES_IVR0_ADDR) #define AES_IVR1_ADDR (AES_BASE_ADDR + 0x0024U) #define AES_IVR1 (*(volatile uint32_t *)AES_IVR1_ADDR) #define AES_IVR2_ADDR (AES_BASE_ADDR + 0x0028U) #define AES_IVR2 (*(volatile uint32_t *)AES_IVR2_ADDR) #define AES_IVR3_ADDR (AES_BASE_ADDR + 0x002CU) #define AES_IVR3 (*(volatile uint32_t *)AES_IVR3_ADDR) #endif ================================================ FILE: bsp/dp32g030/crc.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_CRC_H #define HARDWARE_DP32G030_CRC_H #if !defined(__ASSEMBLY__) #include #endif /* -------- CRC -------- */ #define CRC_BASE_ADDR 0x40003000U #define CRC_BASE_SIZE 0x00000800U #define CRC_CR_ADDR (CRC_BASE_ADDR + 0x0000U) #define CRC_CR (*(volatile uint32_t *)CRC_CR_ADDR) #define CRC_CR_CRC_EN_SHIFT 0 #define CRC_CR_CRC_EN_WIDTH 1 #define CRC_CR_CRC_EN_MASK (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT) #define CRC_CR_CRC_EN_VALUE_DISABLE 0U #define CRC_CR_CRC_EN_BITS_DISABLE (CRC_CR_CRC_EN_VALUE_DISABLE << CRC_CR_CRC_EN_SHIFT) #define CRC_CR_CRC_EN_VALUE_ENABLE 1U #define CRC_CR_CRC_EN_BITS_ENABLE (CRC_CR_CRC_EN_VALUE_ENABLE << CRC_CR_CRC_EN_SHIFT) #define CRC_CR_INPUT_REV_SHIFT 1 #define CRC_CR_INPUT_REV_WIDTH 1 #define CRC_CR_INPUT_REV_MASK (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT) #define CRC_CR_INPUT_REV_VALUE_NORMAL 0U #define CRC_CR_INPUT_REV_BITS_NORMAL (CRC_CR_INPUT_REV_VALUE_NORMAL << CRC_CR_INPUT_REV_SHIFT) #define CRC_CR_INPUT_REV_VALUE_REVERSED 1U #define CRC_CR_INPUT_REV_BITS_REVERSED (CRC_CR_INPUT_REV_VALUE_REVERSED << CRC_CR_INPUT_REV_SHIFT) #define CRC_CR_INPUT_INV_SHIFT 2 #define CRC_CR_INPUT_INV_WIDTH 2 #define CRC_CR_INPUT_INV_MASK (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT) #define CRC_CR_INPUT_INV_VALUE_NORMAL 0U #define CRC_CR_INPUT_INV_BITS_NORMAL (CRC_CR_INPUT_INV_VALUE_NORMAL << CRC_CR_INPUT_INV_SHIFT) #define CRC_CR_INPUT_INV_VALUE_BIT_INVERTED 1U #define CRC_CR_INPUT_INV_BITS_BIT_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_INVERTED << CRC_CR_INPUT_INV_SHIFT) #define CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED 2U #define CRC_CR_INPUT_INV_BITS_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) #define CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED 3U #define CRC_CR_INPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) #define CRC_CR_OUTPUT_REV_SHIFT 4 #define CRC_CR_OUTPUT_REV_WIDTH 1 #define CRC_CR_OUTPUT_REV_MASK (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT) #define CRC_CR_OUTPUT_REV_VALUE_NORMAL 0U #define CRC_CR_OUTPUT_REV_BITS_NORMAL (CRC_CR_OUTPUT_REV_VALUE_NORMAL << CRC_CR_OUTPUT_REV_SHIFT) #define CRC_CR_OUTPUT_REV_VALUE_REVERSED 1U #define CRC_CR_OUTPUT_REV_BITS_REVERSED (CRC_CR_OUTPUT_REV_VALUE_REVERSED << CRC_CR_OUTPUT_REV_SHIFT) #define CRC_CR_OUTPUT_INV_SHIFT 5 #define CRC_CR_OUTPUT_INV_WIDTH 2 #define CRC_CR_OUTPUT_INV_MASK (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT) #define CRC_CR_OUTPUT_INV_VALUE_NORMAL 0U #define CRC_CR_OUTPUT_INV_BITS_NORMAL (CRC_CR_OUTPUT_INV_VALUE_NORMAL << CRC_CR_OUTPUT_INV_SHIFT) #define CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED 1U #define CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) #define CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED 2U #define CRC_CR_OUTPUT_INV_BITS_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) #define CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED 3U #define CRC_CR_OUTPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) #define CRC_CR_DATA_WIDTH_SHIFT 7 #define CRC_CR_DATA_WIDTH_WIDTH 2 #define CRC_CR_DATA_WIDTH_MASK (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT) #define CRC_CR_DATA_WIDTH_VALUE_32 0U #define CRC_CR_DATA_WIDTH_BITS_32 (CRC_CR_DATA_WIDTH_VALUE_32 << CRC_CR_DATA_WIDTH_SHIFT) #define CRC_CR_DATA_WIDTH_VALUE_16 1U #define CRC_CR_DATA_WIDTH_BITS_16 (CRC_CR_DATA_WIDTH_VALUE_16 << CRC_CR_DATA_WIDTH_SHIFT) #define CRC_CR_DATA_WIDTH_VALUE_8 2U #define CRC_CR_DATA_WIDTH_BITS_8 (CRC_CR_DATA_WIDTH_VALUE_8 << CRC_CR_DATA_WIDTH_SHIFT) #define CRC_CR_CRC_SEL_SHIFT 9 #define CRC_CR_CRC_SEL_WIDTH 2 #define CRC_CR_CRC_SEL_MASK (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT) #define CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT 0U #define CRC_CR_CRC_SEL_BITS_CRC_16_CCITT (CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT << CRC_CR_CRC_SEL_SHIFT) #define CRC_CR_CRC_SEL_VALUE_CRC_8_ATM 1U #define CRC_CR_CRC_SEL_BITS_CRC_8_ATM (CRC_CR_CRC_SEL_VALUE_CRC_8_ATM << CRC_CR_CRC_SEL_SHIFT) #define CRC_CR_CRC_SEL_VALUE_CRC_16 2U #define CRC_CR_CRC_SEL_BITS_CRC_16 (CRC_CR_CRC_SEL_VALUE_CRC_16 << CRC_CR_CRC_SEL_SHIFT) #define CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 3U #define CRC_CR_CRC_SEL_BITS_CRC_32_IEEE802_3 (CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 << CRC_CR_CRC_SEL_SHIFT) #define CRC_IV_ADDR (CRC_BASE_ADDR + 0x0004U) #define CRC_IV (*(volatile uint32_t *)CRC_IV_ADDR) #define CRC_DATAIN_ADDR (CRC_BASE_ADDR + 0x0008U) #define CRC_DATAIN (*(volatile uint32_t *)CRC_DATAIN_ADDR) #define CRC_DATAOUT_ADDR (CRC_BASE_ADDR + 0x000CU) #define CRC_DATAOUT (*(volatile uint32_t *)CRC_DATAOUT_ADDR) #endif ================================================ FILE: bsp/dp32g030/dma.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_DMA_H #define HARDWARE_DP32G030_DMA_H #if !defined(__ASSEMBLY__) #include #endif /* -------- DMA -------- */ #define DMA_BASE_ADDR 0x40001000U #define DMA_BASE_SIZE 0x00000100U #define DMA_CTR_ADDR (DMA_BASE_ADDR + 0x0000U) #define DMA_CTR (*(volatile uint32_t *)DMA_CTR_ADDR) #define DMA_CTR_DMAEN_SHIFT 0 #define DMA_CTR_DMAEN_WIDTH 1 #define DMA_CTR_DMAEN_MASK (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT) #define DMA_CTR_DMAEN_VALUE_DISABLE 0U #define DMA_CTR_DMAEN_BITS_DISABLE (DMA_CTR_DMAEN_VALUE_DISABLE << DMA_CTR_DMAEN_SHIFT) #define DMA_CTR_DMAEN_VALUE_ENABLE 1U #define DMA_CTR_DMAEN_BITS_ENABLE (DMA_CTR_DMAEN_VALUE_ENABLE << DMA_CTR_DMAEN_SHIFT) #define DMA_INTEN_ADDR (DMA_BASE_ADDR + 0x0004U) #define DMA_INTEN (*(volatile uint32_t *)DMA_INTEN_ADDR) #define DMA_INTEN_CH0_TC_INTEN_SHIFT 0 #define DMA_INTEN_CH0_TC_INTEN_WIDTH 1 #define DMA_INTEN_CH0_TC_INTEN_MASK (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT) #define DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH0_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) #define DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH0_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) #define DMA_INTEN_CH1_TC_INTEN_SHIFT 1 #define DMA_INTEN_CH1_TC_INTEN_WIDTH 1 #define DMA_INTEN_CH1_TC_INTEN_MASK (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT) #define DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH1_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) #define DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH1_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) #define DMA_INTEN_CH2_TC_INTEN_SHIFT 2 #define DMA_INTEN_CH2_TC_INTEN_WIDTH 1 #define DMA_INTEN_CH2_TC_INTEN_MASK (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT) #define DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH2_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) #define DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH2_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) #define DMA_INTEN_CH3_TC_INTEN_SHIFT 3 #define DMA_INTEN_CH3_TC_INTEN_WIDTH 1 #define DMA_INTEN_CH3_TC_INTEN_MASK (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT) #define DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH3_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) #define DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH3_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) #define DMA_INTEN_CH0_THC_INTEN_SHIFT 8 #define DMA_INTEN_CH0_THC_INTEN_WIDTH 1 #define DMA_INTEN_CH0_THC_INTEN_MASK (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT) #define DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH0_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) #define DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH0_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) #define DMA_INTEN_CH1_THC_INTEN_SHIFT 9 #define DMA_INTEN_CH1_THC_INTEN_WIDTH 1 #define DMA_INTEN_CH1_THC_INTEN_MASK (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT) #define DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH1_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) #define DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH1_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) #define DMA_INTEN_CH2_THC_INTEN_SHIFT 10 #define DMA_INTEN_CH2_THC_INTEN_WIDTH 1 #define DMA_INTEN_CH2_THC_INTEN_MASK (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT) #define DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH2_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) #define DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH2_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) #define DMA_INTEN_CH3_THC_INTEN_SHIFT 11 #define DMA_INTEN_CH3_THC_INTEN_WIDTH 1 #define DMA_INTEN_CH3_THC_INTEN_MASK (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT) #define DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE 0U #define DMA_INTEN_CH3_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) #define DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE 1U #define DMA_INTEN_CH3_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) #define DMA_INTST_ADDR (DMA_BASE_ADDR + 0x0008U) #define DMA_INTST (*(volatile uint32_t *)DMA_INTST_ADDR) #define DMA_INTST_CH0_TC_INTST_SHIFT 0 #define DMA_INTST_CH0_TC_INTST_WIDTH 1 #define DMA_INTST_CH0_TC_INTST_MASK (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT) #define DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH0_TC_INTST_BITS_NOT_SET (DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_TC_INTST_SHIFT) #define DMA_INTST_CH0_TC_INTST_VALUE_SET 1U #define DMA_INTST_CH0_TC_INTST_BITS_SET (DMA_INTST_CH0_TC_INTST_VALUE_SET << DMA_INTST_CH0_TC_INTST_SHIFT) #define DMA_INTST_CH1_TC_INTST_SHIFT 1 #define DMA_INTST_CH1_TC_INTST_WIDTH 1 #define DMA_INTST_CH1_TC_INTST_MASK (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT) #define DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH1_TC_INTST_BITS_NOT_SET (DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_TC_INTST_SHIFT) #define DMA_INTST_CH1_TC_INTST_VALUE_SET 1U #define DMA_INTST_CH1_TC_INTST_BITS_SET (DMA_INTST_CH1_TC_INTST_VALUE_SET << DMA_INTST_CH1_TC_INTST_SHIFT) #define DMA_INTST_CH2_TC_INTST_SHIFT 2 #define DMA_INTST_CH2_TC_INTST_WIDTH 1 #define DMA_INTST_CH2_TC_INTST_MASK (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT) #define DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH2_TC_INTST_BITS_NOT_SET (DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_TC_INTST_SHIFT) #define DMA_INTST_CH2_TC_INTST_VALUE_SET 1U #define DMA_INTST_CH2_TC_INTST_BITS_SET (DMA_INTST_CH2_TC_INTST_VALUE_SET << DMA_INTST_CH2_TC_INTST_SHIFT) #define DMA_INTST_CH3_TC_INTST_SHIFT 3 #define DMA_INTST_CH3_TC_INTST_WIDTH 1 #define DMA_INTST_CH3_TC_INTST_MASK (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT) #define DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH3_TC_INTST_BITS_NOT_SET (DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_TC_INTST_SHIFT) #define DMA_INTST_CH3_TC_INTST_VALUE_SET 1U #define DMA_INTST_CH3_TC_INTST_BITS_SET (DMA_INTST_CH3_TC_INTST_VALUE_SET << DMA_INTST_CH3_TC_INTST_SHIFT) #define DMA_INTST_CH0_THC_INTST_SHIFT 8 #define DMA_INTST_CH0_THC_INTST_WIDTH 1 #define DMA_INTST_CH0_THC_INTST_MASK (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT) #define DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH0_THC_INTST_BITS_NOT_SET (DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_THC_INTST_SHIFT) #define DMA_INTST_CH0_THC_INTST_VALUE_SET 1U #define DMA_INTST_CH0_THC_INTST_BITS_SET (DMA_INTST_CH0_THC_INTST_VALUE_SET << DMA_INTST_CH0_THC_INTST_SHIFT) #define DMA_INTST_CH1_THC_INTST_SHIFT 9 #define DMA_INTST_CH1_THC_INTST_WIDTH 1 #define DMA_INTST_CH1_THC_INTST_MASK (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT) #define DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH1_THC_INTST_BITS_NOT_SET (DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_THC_INTST_SHIFT) #define DMA_INTST_CH1_THC_INTST_VALUE_SET 1U #define DMA_INTST_CH1_THC_INTST_BITS_SET (DMA_INTST_CH1_THC_INTST_VALUE_SET << DMA_INTST_CH1_THC_INTST_SHIFT) #define DMA_INTST_CH2_THC_INTST_SHIFT 10 #define DMA_INTST_CH2_THC_INTST_WIDTH 1 #define DMA_INTST_CH2_THC_INTST_MASK (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT) #define DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH2_THC_INTST_BITS_NOT_SET (DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_THC_INTST_SHIFT) #define DMA_INTST_CH2_THC_INTST_VALUE_SET 1U #define DMA_INTST_CH2_THC_INTST_BITS_SET (DMA_INTST_CH2_THC_INTST_VALUE_SET << DMA_INTST_CH2_THC_INTST_SHIFT) #define DMA_INTST_CH3_THC_INTST_SHIFT 11 #define DMA_INTST_CH3_THC_INTST_WIDTH 1 #define DMA_INTST_CH3_THC_INTST_MASK (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT) #define DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET 0U #define DMA_INTST_CH3_THC_INTST_BITS_NOT_SET (DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_THC_INTST_SHIFT) #define DMA_INTST_CH3_THC_INTST_VALUE_SET 1U #define DMA_INTST_CH3_THC_INTST_BITS_SET (DMA_INTST_CH3_THC_INTST_VALUE_SET << DMA_INTST_CH3_THC_INTST_SHIFT) /* -------- DMA_CH0 -------- */ #define DMA_CH0_BASE_ADDR 0x40001100U #define DMA_CH0_BASE_SIZE 0x00000020U #define DMA_CH0 ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR) /* -------- DMA_CH1 -------- */ #define DMA_CH1_BASE_ADDR 0x40001120U #define DMA_CH1_BASE_SIZE 0x00000020U #define DMA_CH1 ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR) /* -------- DMA_CH2 -------- */ #define DMA_CH2_BASE_ADDR 0x40001140U #define DMA_CH2_BASE_SIZE 0x00000020U #define DMA_CH2 ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR) /* -------- DMA_CH3 -------- */ #define DMA_CH3_BASE_ADDR 0x40001160U #define DMA_CH3_BASE_SIZE 0x00000020U #define DMA_CH3 ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR) /* -------- DMA_CH -------- */ typedef struct { uint32_t CTR; uint32_t MOD; uint32_t MSADDR; uint32_t MDADDR; uint32_t ST; } DMA_Channel_t; #define DMA_CH_CTR_CH_EN_SHIFT 0 #define DMA_CH_CTR_CH_EN_WIDTH 1 #define DMA_CH_CTR_CH_EN_MASK (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT) #define DMA_CH_CTR_CH_EN_VALUE_DISABLE 0U #define DMA_CH_CTR_CH_EN_BITS_DISABLE (DMA_CH_CTR_CH_EN_VALUE_DISABLE << DMA_CH_CTR_CH_EN_SHIFT) #define DMA_CH_CTR_CH_EN_VALUE_ENABLE 1U #define DMA_CH_CTR_CH_EN_BITS_ENABLE (DMA_CH_CTR_CH_EN_VALUE_ENABLE << DMA_CH_CTR_CH_EN_SHIFT) #define DMA_CH_CTR_LENGTH_SHIFT 1 #define DMA_CH_CTR_LENGTH_WIDTH 12 #define DMA_CH_CTR_LENGTH_MASK (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT) #define DMA_CH_CTR_LOOP_SHIFT 13 #define DMA_CH_CTR_LOOP_WIDTH 1 #define DMA_CH_CTR_LOOP_MASK (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT) #define DMA_CH_CTR_LOOP_VALUE_DISABLE 0U #define DMA_CH_CTR_LOOP_BITS_DISABLE (DMA_CH_CTR_LOOP_VALUE_DISABLE << DMA_CH_CTR_LOOP_SHIFT) #define DMA_CH_CTR_LOOP_VALUE_ENABLE 1U #define DMA_CH_CTR_LOOP_BITS_ENABLE (DMA_CH_CTR_LOOP_VALUE_ENABLE << DMA_CH_CTR_LOOP_SHIFT) #define DMA_CH_CTR_PRI_SHIFT 14 #define DMA_CH_CTR_PRI_WIDTH 2 #define DMA_CH_CTR_PRI_MASK (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT) #define DMA_CH_CTR_PRI_VALUE_LOW 0U #define DMA_CH_CTR_PRI_BITS_LOW (DMA_CH_CTR_PRI_VALUE_LOW << DMA_CH_CTR_PRI_SHIFT) #define DMA_CH_CTR_PRI_VALUE_MEDIUM 1U #define DMA_CH_CTR_PRI_BITS_MEDIUM (DMA_CH_CTR_PRI_VALUE_MEDIUM << DMA_CH_CTR_PRI_SHIFT) #define DMA_CH_CTR_PRI_VALUE_HIGH 2U #define DMA_CH_CTR_PRI_BITS_HIGH (DMA_CH_CTR_PRI_VALUE_HIGH << DMA_CH_CTR_PRI_SHIFT) #define DMA_CH_CTR_PRI_VALUE_HIGHEST 3U #define DMA_CH_CTR_PRI_BITS_HIGHEST (DMA_CH_CTR_PRI_VALUE_HIGHEST << DMA_CH_CTR_PRI_SHIFT) #define DMA_CH_CTR_SWREQ_SHIFT 16 #define DMA_CH_CTR_SWREQ_WIDTH 1 #define DMA_CH_CTR_SWREQ_MASK (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT) #define DMA_CH_CTR_SWREQ_VALUE_SET 1U #define DMA_CH_CTR_SWREQ_BITS_SET (DMA_CH_CTR_SWREQ_VALUE_SET << DMA_CH_CTR_SWREQ_SHIFT) #define DMA_CH_MOD_MS_ADDMOD_SHIFT 0 #define DMA_CH_MOD_MS_ADDMOD_WIDTH 1 #define DMA_CH_MOD_MS_ADDMOD_MASK (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT) #define DMA_CH_MOD_MS_ADDMOD_VALUE_NONE 0U #define DMA_CH_MOD_MS_ADDMOD_BITS_NONE (DMA_CH_MOD_MS_ADDMOD_VALUE_NONE << DMA_CH_MOD_MS_ADDMOD_SHIFT) #define DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT 1U #define DMA_CH_MOD_MS_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MS_ADDMOD_SHIFT) #define DMA_CH_MOD_MS_SIZE_SHIFT 1 #define DMA_CH_MOD_MS_SIZE_WIDTH 2 #define DMA_CH_MOD_MS_SIZE_MASK (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT) #define DMA_CH_MOD_MS_SIZE_VALUE_8BIT 0U #define DMA_CH_MOD_MS_SIZE_BITS_8BIT (DMA_CH_MOD_MS_SIZE_VALUE_8BIT << DMA_CH_MOD_MS_SIZE_SHIFT) #define DMA_CH_MOD_MS_SIZE_VALUE_16BIT 1U #define DMA_CH_MOD_MS_SIZE_BITS_16BIT (DMA_CH_MOD_MS_SIZE_VALUE_16BIT << DMA_CH_MOD_MS_SIZE_SHIFT) #define DMA_CH_MOD_MS_SIZE_VALUE_32BIT 2U #define DMA_CH_MOD_MS_SIZE_BITS_32BIT (DMA_CH_MOD_MS_SIZE_VALUE_32BIT << DMA_CH_MOD_MS_SIZE_SHIFT) #define DMA_CH_MOD_MS_SIZE_VALUE_KEEP 3U #define DMA_CH_MOD_MS_SIZE_BITS_KEEP (DMA_CH_MOD_MS_SIZE_VALUE_KEEP << DMA_CH_MOD_MS_SIZE_SHIFT) #define DMA_CH_MOD_MS_SEL_SHIFT 3 #define DMA_CH_MOD_MS_SEL_WIDTH 3 #define DMA_CH_MOD_MS_SEL_MASK (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_SRAM 0U #define DMA_CH_MOD_MS_SEL_BITS_SRAM (DMA_CH_MOD_MS_SEL_VALUE_SRAM << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 1U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 2U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 3U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 4U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 5U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 6U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 7U #define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MS_SEL_SHIFT) #define DMA_CH_MOD_MD_ADDMOD_SHIFT 8 #define DMA_CH_MOD_MD_ADDMOD_WIDTH 1 #define DMA_CH_MOD_MD_ADDMOD_MASK (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT) #define DMA_CH_MOD_MD_ADDMOD_VALUE_NONE 0U #define DMA_CH_MOD_MD_ADDMOD_BITS_NONE (DMA_CH_MOD_MD_ADDMOD_VALUE_NONE << DMA_CH_MOD_MD_ADDMOD_SHIFT) #define DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT 1U #define DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MD_ADDMOD_SHIFT) #define DMA_CH_MOD_MD_SIZE_SHIFT 9 #define DMA_CH_MOD_MD_SIZE_WIDTH 2 #define DMA_CH_MOD_MD_SIZE_MASK (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT) #define DMA_CH_MOD_MD_SIZE_VALUE_8BIT 0U #define DMA_CH_MOD_MD_SIZE_BITS_8BIT (DMA_CH_MOD_MD_SIZE_VALUE_8BIT << DMA_CH_MOD_MD_SIZE_SHIFT) #define DMA_CH_MOD_MD_SIZE_VALUE_16BIT 1U #define DMA_CH_MOD_MD_SIZE_BITS_16BIT (DMA_CH_MOD_MD_SIZE_VALUE_16BIT << DMA_CH_MOD_MD_SIZE_SHIFT) #define DMA_CH_MOD_MD_SIZE_VALUE_32BIT 2U #define DMA_CH_MOD_MD_SIZE_BITS_32BIT (DMA_CH_MOD_MD_SIZE_VALUE_32BIT << DMA_CH_MOD_MD_SIZE_SHIFT) #define DMA_CH_MOD_MD_SIZE_VALUE_KEEP 3U #define DMA_CH_MOD_MD_SIZE_BITS_KEEP (DMA_CH_MOD_MD_SIZE_VALUE_KEEP << DMA_CH_MOD_MD_SIZE_SHIFT) #define DMA_CH_MOD_MD_SEL_SHIFT 11 #define DMA_CH_MOD_MD_SEL_WIDTH 3 #define DMA_CH_MOD_MD_SEL_MASK (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_SRAM 0U #define DMA_CH_MOD_MD_SEL_BITS_SRAM (DMA_CH_MOD_MD_SEL_VALUE_SRAM << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 1U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 2U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 3U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 4U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 5U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 6U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MD_SEL_SHIFT) #define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 7U #define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MD_SEL_SHIFT) #endif ================================================ FILE: bsp/dp32g030/flash.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_FLASH_H #define HARDWARE_DP32G030_FLASH_H #if !defined(__ASSEMBLY__) #include #endif /* -------- FLASH -------- */ #define FLASH_BASE_ADDR 0x4006F000U #define FLASH_BASE_SIZE 0x00000800U #define FLASH_CFG_ADDR (FLASH_BASE_ADDR + 0x0000U) #define FLASH_CFG (*(volatile uint32_t *)FLASH_CFG_ADDR) #define FLASH_CFG_READ_MD_SHIFT 0 #define FLASH_CFG_READ_MD_WIDTH 1 #define FLASH_CFG_READ_MD_MASK (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT) #define FLASH_CFG_READ_MD_VALUE_1_CYCLE 0U #define FLASH_CFG_READ_MD_BITS_1_CYCLE (FLASH_CFG_READ_MD_VALUE_1_CYCLE << FLASH_CFG_READ_MD_SHIFT) #define FLASH_CFG_READ_MD_VALUE_2_CYCLE 1U #define FLASH_CFG_READ_MD_BITS_2_CYCLE (FLASH_CFG_READ_MD_VALUE_2_CYCLE << FLASH_CFG_READ_MD_SHIFT) #define FLASH_CFG_NVR_SEL_SHIFT 1 #define FLASH_CFG_NVR_SEL_WIDTH 1 #define FLASH_CFG_NVR_SEL_MASK (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT) #define FLASH_CFG_NVR_SEL_VALUE_MAIN 0U #define FLASH_CFG_NVR_SEL_BITS_MAIN (FLASH_CFG_NVR_SEL_VALUE_MAIN << FLASH_CFG_NVR_SEL_SHIFT) #define FLASH_CFG_NVR_SEL_VALUE_NVR 1U #define FLASH_CFG_NVR_SEL_BITS_NVR (FLASH_CFG_NVR_SEL_VALUE_NVR << FLASH_CFG_NVR_SEL_SHIFT) #define FLASH_CFG_MODE_SHIFT 2 #define FLASH_CFG_MODE_WIDTH 3 #define FLASH_CFG_MODE_MASK (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT) #define FLASH_CFG_MODE_VALUE_READ_AHB 0U #define FLASH_CFG_MODE_BITS_READ_AHB (FLASH_CFG_MODE_VALUE_READ_AHB << FLASH_CFG_MODE_SHIFT) #define FLASH_CFG_MODE_VALUE_PROGRAM 1U #define FLASH_CFG_MODE_BITS_PROGRAM (FLASH_CFG_MODE_VALUE_PROGRAM << FLASH_CFG_MODE_SHIFT) #define FLASH_CFG_MODE_VALUE_ERASE 2U #define FLASH_CFG_MODE_BITS_ERASE (FLASH_CFG_MODE_VALUE_ERASE << FLASH_CFG_MODE_SHIFT) #define FLASH_CFG_MODE_VALUE_READ_APB 5U #define FLASH_CFG_MODE_BITS_READ_APB (FLASH_CFG_MODE_VALUE_READ_APB << FLASH_CFG_MODE_SHIFT) #define FLASH_CFG_DEEP_PD_SHIFT 31 #define FLASH_CFG_DEEP_PD_WIDTH 1 #define FLASH_CFG_DEEP_PD_MASK (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT) #define FLASH_CFG_DEEP_PD_VALUE_NORMAL 0U #define FLASH_CFG_DEEP_PD_BITS_NORMAL (FLASH_CFG_DEEP_PD_VALUE_NORMAL << FLASH_CFG_DEEP_PD_SHIFT) #define FLASH_CFG_DEEP_PD_VALUE_LOW_POWER 1U #define FLASH_CFG_DEEP_PD_BITS_LOW_POWER (FLASH_CFG_DEEP_PD_VALUE_LOW_POWER << FLASH_CFG_DEEP_PD_SHIFT) #define FLASH_ADDR_ADDR (FLASH_BASE_ADDR + 0x0004U) #define FLASH_ADDR (*(volatile uint32_t *)FLASH_ADDR_ADDR) #define FLASH_WDATA_ADDR (FLASH_BASE_ADDR + 0x0008U) #define FLASH_WDATA (*(volatile uint32_t *)FLASH_WDATA_ADDR) #define FLASH_RDATA_ADDR (FLASH_BASE_ADDR + 0x000CU) #define FLASH_RDATA (*(volatile uint32_t *)FLASH_RDATA_ADDR) #define FLASH_START_ADDR (FLASH_BASE_ADDR + 0x0010U) #define FLASH_START (*(volatile uint32_t *)FLASH_START_ADDR) #define FLASH_START_START_SHIFT 0 #define FLASH_START_START_WIDTH 1 #define FLASH_START_START_MASK (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT) #define FLASH_START_START_VALUE_START 1U #define FLASH_START_START_BITS_START (FLASH_START_START_VALUE_START << FLASH_START_START_SHIFT) #define FLASH_ST_ADDR (FLASH_BASE_ADDR + 0x0014U) #define FLASH_ST (*(volatile uint32_t *)FLASH_ST_ADDR) #define FLASH_ST_INIT_BUSY_SHIFT 0 #define FLASH_ST_INIT_BUSY_WIDTH 1 #define FLASH_ST_INIT_BUSY_MASK (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT) #define FLASH_ST_INIT_BUSY_VALUE_COMPLETE 0U #define FLASH_ST_INIT_BUSY_BITS_COMPLETE (FLASH_ST_INIT_BUSY_VALUE_COMPLETE << FLASH_ST_INIT_BUSY_SHIFT) #define FLASH_ST_INIT_BUSY_VALUE_BUSY 1U #define FLASH_ST_INIT_BUSY_BITS_BUSY (FLASH_ST_INIT_BUSY_VALUE_BUSY << FLASH_ST_INIT_BUSY_SHIFT) #define FLASH_ST_BUSY_SHIFT 1 #define FLASH_ST_BUSY_WIDTH 1 #define FLASH_ST_BUSY_MASK (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT) #define FLASH_ST_BUSY_VALUE_READY 0U #define FLASH_ST_BUSY_BITS_READY (FLASH_ST_BUSY_VALUE_READY << FLASH_ST_BUSY_SHIFT) #define FLASH_ST_BUSY_VALUE_BUSY 1U #define FLASH_ST_BUSY_BITS_BUSY (FLASH_ST_BUSY_VALUE_BUSY << FLASH_ST_BUSY_SHIFT) #define FLASH_ST_PROG_BUF_EMPTY_SHIFT 2 #define FLASH_ST_PROG_BUF_EMPTY_WIDTH 1 #define FLASH_ST_PROG_BUF_EMPTY_MASK (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT) #define FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY 0U #define FLASH_ST_PROG_BUF_EMPTY_BITS_NOT_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) #define FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY 1U #define FLASH_ST_PROG_BUF_EMPTY_BITS_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) #define FLASH_LOCK_ADDR (FLASH_BASE_ADDR + 0x0018U) #define FLASH_LOCK (*(volatile uint32_t *)FLASH_LOCK_ADDR) #define FLASH_LOCK_LOCK_SHIFT 0 #define FLASH_LOCK_LOCK_WIDTH 8 #define FLASH_LOCK_LOCK_MASK (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT) #define FLASH_LOCK_LOCK_VALUE_LOCK 85U #define FLASH_LOCK_LOCK_BITS_LOCK (FLASH_LOCK_LOCK_VALUE_LOCK << FLASH_LOCK_LOCK_SHIFT) #define FLASH_UNLOCK_ADDR (FLASH_BASE_ADDR + 0x001CU) #define FLASH_UNLOCK (*(volatile uint32_t *)FLASH_UNLOCK_ADDR) #define FLASH_UNLOCK_UNLOCK_SHIFT 0 #define FLASH_UNLOCK_UNLOCK_WIDTH 8 #define FLASH_UNLOCK_UNLOCK_MASK (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT) #define FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK 170U #define FLASH_UNLOCK_UNLOCK_BITS_UNLOCK (FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK << FLASH_UNLOCK_UNLOCK_SHIFT) #define FLASH_MASK_ADDR (FLASH_BASE_ADDR + 0x0020U) #define FLASH_MASK (*(volatile uint32_t *)FLASH_MASK_ADDR) #define FLASH_MASK_SEL_SHIFT 0 #define FLASH_MASK_SEL_WIDTH 2 #define FLASH_MASK_SEL_MASK (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT) #define FLASH_MASK_SEL_VALUE_NONE 0U #define FLASH_MASK_SEL_BITS_NONE (FLASH_MASK_SEL_VALUE_NONE << FLASH_MASK_SEL_SHIFT) #define FLASH_MASK_SEL_VALUE_2KB 1U #define FLASH_MASK_SEL_BITS_2KB (FLASH_MASK_SEL_VALUE_2KB << FLASH_MASK_SEL_SHIFT) #define FLASH_MASK_SEL_VALUE_4KB 2U #define FLASH_MASK_SEL_BITS_4KB (FLASH_MASK_SEL_VALUE_4KB << FLASH_MASK_SEL_SHIFT) #define FLASH_MASK_SEL_VALUE_8KB 3U #define FLASH_MASK_SEL_BITS_8KB (FLASH_MASK_SEL_VALUE_8KB << FLASH_MASK_SEL_SHIFT) #define FLASH_MASK_LOCK_SHIFT 2 #define FLASH_MASK_LOCK_WIDTH 1 #define FLASH_MASK_LOCK_MASK (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT) #define FLASH_MASK_LOCK_VALUE_NOT_SET 0U #define FLASH_MASK_LOCK_BITS_NOT_SET (FLASH_MASK_LOCK_VALUE_NOT_SET << FLASH_MASK_LOCK_SHIFT) #define FLASH_MASK_LOCK_VALUE_SET 1U #define FLASH_MASK_LOCK_BITS_SET (FLASH_MASK_LOCK_VALUE_SET << FLASH_MASK_LOCK_SHIFT) #define FLASH_ERASETIME_ADDR (FLASH_BASE_ADDR + 0x0024U) #define FLASH_ERASETIME (*(volatile uint32_t *)FLASH_ERASETIME_ADDR) #define FLASH_ERASETIME_TERASE_SHIFT 0 #define FLASH_ERASETIME_TERASE_WIDTH 19 #define FLASH_ERASETIME_TERASE_MASK (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT) #define FLASH_ERASETIME_TRCV_SHIFT 19 #define FLASH_ERASETIME_TRCV_WIDTH 12 #define FLASH_ERASETIME_TRCV_MASK (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT) #define FLASH_PROGTIME_ADDR (FLASH_BASE_ADDR + 0x0028U) #define FLASH_PROGTIME (*(volatile uint32_t *)FLASH_PROGTIME_ADDR) #define FLASH_PROGTIME_TPROG_SHIFT 0 #define FLASH_PROGTIME_TPROG_WIDTH 11 #define FLASH_PROGTIME_TPROG_MASK (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT) #define FLASH_PROGTIME_TPGS_SHIFT 11 #define FLASH_PROGTIME_TPGS_WIDTH 11 #define FLASH_PROGTIME_TPGS_MASK (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT) #endif ================================================ FILE: bsp/dp32g030/gpio.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_GPIO_H #define HARDWARE_DP32G030_GPIO_H #if !defined(__ASSEMBLY__) #include #endif /* -------- GPIOA -------- */ #define GPIOA_BASE_ADDR 0x40060000U #define GPIOA_BASE_SIZE 0x00000800U #define GPIOA ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR) /* -------- GPIOB -------- */ #define GPIOB_BASE_ADDR 0x40060800U #define GPIOB_BASE_SIZE 0x00000800U #define GPIOB ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR) /* -------- GPIOC -------- */ #define GPIOC_BASE_ADDR 0x40061000U #define GPIOC_BASE_SIZE 0x00000800U #define GPIOC ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR) /* -------- GPIO -------- */ typedef struct { uint32_t DATA; uint32_t DIR; } GPIO_Bank_t; #define GPIO_DIR_0_SHIFT 0 #define GPIO_DIR_0_WIDTH 1 #define GPIO_DIR_0_MASK (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT) #define GPIO_DIR_0_VALUE_INPUT 0U #define GPIO_DIR_0_BITS_INPUT (GPIO_DIR_0_VALUE_INPUT << GPIO_DIR_0_SHIFT) #define GPIO_DIR_0_VALUE_OUTPUT 1U #define GPIO_DIR_0_BITS_OUTPUT (GPIO_DIR_0_VALUE_OUTPUT << GPIO_DIR_0_SHIFT) #define GPIO_DIR_1_SHIFT 1 #define GPIO_DIR_1_WIDTH 1 #define GPIO_DIR_1_MASK (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT) #define GPIO_DIR_1_VALUE_INPUT 0U #define GPIO_DIR_1_BITS_INPUT (GPIO_DIR_1_VALUE_INPUT << GPIO_DIR_1_SHIFT) #define GPIO_DIR_1_VALUE_OUTPUT 1U #define GPIO_DIR_1_BITS_OUTPUT (GPIO_DIR_1_VALUE_OUTPUT << GPIO_DIR_1_SHIFT) #define GPIO_DIR_2_SHIFT 2 #define GPIO_DIR_2_WIDTH 1 #define GPIO_DIR_2_MASK (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT) #define GPIO_DIR_2_VALUE_INPUT 0U #define GPIO_DIR_2_BITS_INPUT (GPIO_DIR_2_VALUE_INPUT << GPIO_DIR_2_SHIFT) #define GPIO_DIR_2_VALUE_OUTPUT 1U #define GPIO_DIR_2_BITS_OUTPUT (GPIO_DIR_2_VALUE_OUTPUT << GPIO_DIR_2_SHIFT) #define GPIO_DIR_3_SHIFT 3 #define GPIO_DIR_3_WIDTH 1 #define GPIO_DIR_3_MASK (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT) #define GPIO_DIR_3_VALUE_INPUT 0U #define GPIO_DIR_3_BITS_INPUT (GPIO_DIR_3_VALUE_INPUT << GPIO_DIR_3_SHIFT) #define GPIO_DIR_3_VALUE_OUTPUT 1U #define GPIO_DIR_3_BITS_OUTPUT (GPIO_DIR_3_VALUE_OUTPUT << GPIO_DIR_3_SHIFT) #define GPIO_DIR_4_SHIFT 4 #define GPIO_DIR_4_WIDTH 1 #define GPIO_DIR_4_MASK (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT) #define GPIO_DIR_4_VALUE_INPUT 0U #define GPIO_DIR_4_BITS_INPUT (GPIO_DIR_4_VALUE_INPUT << GPIO_DIR_4_SHIFT) #define GPIO_DIR_4_VALUE_OUTPUT 1U #define GPIO_DIR_4_BITS_OUTPUT (GPIO_DIR_4_VALUE_OUTPUT << GPIO_DIR_4_SHIFT) #define GPIO_DIR_5_SHIFT 5 #define GPIO_DIR_5_WIDTH 1 #define GPIO_DIR_5_MASK (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT) #define GPIO_DIR_5_VALUE_INPUT 0U #define GPIO_DIR_5_BITS_INPUT (GPIO_DIR_5_VALUE_INPUT << GPIO_DIR_5_SHIFT) #define GPIO_DIR_5_VALUE_OUTPUT 1U #define GPIO_DIR_5_BITS_OUTPUT (GPIO_DIR_5_VALUE_OUTPUT << GPIO_DIR_5_SHIFT) #define GPIO_DIR_6_SHIFT 6 #define GPIO_DIR_6_WIDTH 1 #define GPIO_DIR_6_MASK (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT) #define GPIO_DIR_6_VALUE_INPUT 0U #define GPIO_DIR_6_BITS_INPUT (GPIO_DIR_6_VALUE_INPUT << GPIO_DIR_6_SHIFT) #define GPIO_DIR_6_VALUE_OUTPUT 1U #define GPIO_DIR_6_BITS_OUTPUT (GPIO_DIR_6_VALUE_OUTPUT << GPIO_DIR_6_SHIFT) #define GPIO_DIR_7_SHIFT 7 #define GPIO_DIR_7_WIDTH 1 #define GPIO_DIR_7_MASK (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT) #define GPIO_DIR_7_VALUE_INPUT 0U #define GPIO_DIR_7_BITS_INPUT (GPIO_DIR_7_VALUE_INPUT << GPIO_DIR_7_SHIFT) #define GPIO_DIR_7_VALUE_OUTPUT 1U #define GPIO_DIR_7_BITS_OUTPUT (GPIO_DIR_7_VALUE_OUTPUT << GPIO_DIR_7_SHIFT) #define GPIO_DIR_8_SHIFT 8 #define GPIO_DIR_8_WIDTH 1 #define GPIO_DIR_8_MASK (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT) #define GPIO_DIR_8_VALUE_INPUT 0U #define GPIO_DIR_8_BITS_INPUT (GPIO_DIR_8_VALUE_INPUT << GPIO_DIR_8_SHIFT) #define GPIO_DIR_8_VALUE_OUTPUT 1U #define GPIO_DIR_8_BITS_OUTPUT (GPIO_DIR_8_VALUE_OUTPUT << GPIO_DIR_8_SHIFT) #define GPIO_DIR_9_SHIFT 9 #define GPIO_DIR_9_WIDTH 1 #define GPIO_DIR_9_MASK (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT) #define GPIO_DIR_9_VALUE_INPUT 0U #define GPIO_DIR_9_BITS_INPUT (GPIO_DIR_9_VALUE_INPUT << GPIO_DIR_9_SHIFT) #define GPIO_DIR_9_VALUE_OUTPUT 1U #define GPIO_DIR_9_BITS_OUTPUT (GPIO_DIR_9_VALUE_OUTPUT << GPIO_DIR_9_SHIFT) #define GPIO_DIR_10_SHIFT 10 #define GPIO_DIR_10_WIDTH 1 #define GPIO_DIR_10_MASK (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT) #define GPIO_DIR_10_VALUE_INPUT 0U #define GPIO_DIR_10_BITS_INPUT (GPIO_DIR_10_VALUE_INPUT << GPIO_DIR_10_SHIFT) #define GPIO_DIR_10_VALUE_OUTPUT 1U #define GPIO_DIR_10_BITS_OUTPUT (GPIO_DIR_10_VALUE_OUTPUT << GPIO_DIR_10_SHIFT) #define GPIO_DIR_11_SHIFT 11 #define GPIO_DIR_11_WIDTH 1 #define GPIO_DIR_11_MASK (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT) #define GPIO_DIR_11_VALUE_INPUT 0U #define GPIO_DIR_11_BITS_INPUT (GPIO_DIR_11_VALUE_INPUT << GPIO_DIR_11_SHIFT) #define GPIO_DIR_11_VALUE_OUTPUT 1U #define GPIO_DIR_11_BITS_OUTPUT (GPIO_DIR_11_VALUE_OUTPUT << GPIO_DIR_11_SHIFT) #define GPIO_DIR_12_SHIFT 12 #define GPIO_DIR_12_WIDTH 1 #define GPIO_DIR_12_MASK (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT) #define GPIO_DIR_12_VALUE_INPUT 0U #define GPIO_DIR_12_BITS_INPUT (GPIO_DIR_12_VALUE_INPUT << GPIO_DIR_12_SHIFT) #define GPIO_DIR_12_VALUE_OUTPUT 1U #define GPIO_DIR_12_BITS_OUTPUT (GPIO_DIR_12_VALUE_OUTPUT << GPIO_DIR_12_SHIFT) #define GPIO_DIR_13_SHIFT 13 #define GPIO_DIR_13_WIDTH 1 #define GPIO_DIR_13_MASK (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT) #define GPIO_DIR_13_VALUE_INPUT 0U #define GPIO_DIR_13_BITS_INPUT (GPIO_DIR_13_VALUE_INPUT << GPIO_DIR_13_SHIFT) #define GPIO_DIR_13_VALUE_OUTPUT 1U #define GPIO_DIR_13_BITS_OUTPUT (GPIO_DIR_13_VALUE_OUTPUT << GPIO_DIR_13_SHIFT) #define GPIO_DIR_14_SHIFT 14 #define GPIO_DIR_14_WIDTH 1 #define GPIO_DIR_14_MASK (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT) #define GPIO_DIR_14_VALUE_INPUT 0U #define GPIO_DIR_14_BITS_INPUT (GPIO_DIR_14_VALUE_INPUT << GPIO_DIR_14_SHIFT) #define GPIO_DIR_14_VALUE_OUTPUT 1U #define GPIO_DIR_14_BITS_OUTPUT (GPIO_DIR_14_VALUE_OUTPUT << GPIO_DIR_14_SHIFT) #define GPIO_DIR_15_SHIFT 15 #define GPIO_DIR_15_WIDTH 1 #define GPIO_DIR_15_MASK (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT) #define GPIO_DIR_15_VALUE_INPUT 0U #define GPIO_DIR_15_BITS_INPUT (GPIO_DIR_15_VALUE_INPUT << GPIO_DIR_15_SHIFT) #define GPIO_DIR_15_VALUE_OUTPUT 1U #define GPIO_DIR_15_BITS_OUTPUT (GPIO_DIR_15_VALUE_OUTPUT << GPIO_DIR_15_SHIFT) #endif ================================================ FILE: bsp/dp32g030/irq.h ================================================ #ifndef DP32G030_IRQ_H #define DP32G030_IRQ_H enum { DP32_WWDT_IRQn = 0, DP32_IWDT_IRQn, DP32_RTC_IRQn, DP32_DMA_IRQn, DP32_SARADC_IRQn, DP32_TIMER_BASE0_IRQn, DP32_TIMER_BASE1_IRQn, DP32_TIMER_PLUS0_IRQn, DP32_TIMER_PLUS1_IRQn, DP32_PWM_BASE0_IRQn, DP32_PWM_BASE1_IRQn, DP32_PWM_PLUS0_IRQn, DP32_PWM_PLUS1_IRQn, DP32_UART0_IRQn, DP32_UART1_IRQn, DP32_UART2_IRQn, DP32_SPI0_IRQn, DP32_SPI1_IRQn, DP32_IIC0_IRQn, DP32_IIC1_IRQn, DP32_CMP_IRQn, DP32_TIMER_BASE2_IRQn, DP32_GPIOA5_IRQn, DP32_GPIOA6_IRQn, DP32_GPIOA7_IRQn, DP32_GPIOB0_IRQn, DP32_GPIOB1_IRQn, DP32_GPIOC0_IRQn, DP32_GPIOC1_IRQn, DP32_GPIOA_IRQn, DP32_GPIOB_IRQn, DP32_GPIOC_IRQn, }; #endif ================================================ FILE: bsp/dp32g030/pmu.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_PMU_H #define HARDWARE_DP32G030_PMU_H #if !defined(__ASSEMBLY__) #include #endif /* -------- PMU -------- */ #define PMU_BASE_ADDR 0x40000800U #define PMU_BASE_SIZE 0x00000800U #define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U) #define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR) #define PMU_SRC_CFG_RCHF_EN_SHIFT 0 #define PMU_SRC_CFG_RCHF_EN_WIDTH 1 #define PMU_SRC_CFG_RCHF_EN_MASK (((1U << PMU_SRC_CFG_RCHF_EN_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_EN_SHIFT) #define PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE 0U #define PMU_SRC_CFG_RCHF_EN_BITS_DISABLE (PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE << PMU_SRC_CFG_RCHF_EN_SHIFT) #define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U #define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT) #define PMU_SRC_CFG_RCHF_SEL_SHIFT 1 #define PMU_SRC_CFG_RCHF_SEL_WIDTH 1 #define PMU_SRC_CFG_RCHF_SEL_MASK (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT) #define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ 0U #define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) #define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ 1U #define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) #define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U) #define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR) #define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U) #define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR) #define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U) #define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR) #define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU) #define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR) #define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U) #define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR) #define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U) #define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR) #define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U) #define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR) #define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU) #define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR) #endif ================================================ FILE: bsp/dp32g030/portcon.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_PORTCON_H #define HARDWARE_DP32G030_PORTCON_H #if !defined(__ASSEMBLY__) #include #endif /* -------- PORTCON -------- */ #define PORTCON_BASE_ADDR 0x400B0000U #define PORTCON_BASE_SIZE 0x00000800U #define PORTCON_PORTA_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0000U) #define PORTCON_PORTA_SEL0 (*(volatile uint32_t *)PORTCON_PORTA_SEL0_ADDR) #define PORTCON_PORTA_SEL0_A0_SHIFT 0 #define PORTCON_PORTA_SEL0_A0_WIDTH 4 #define PORTCON_PORTA_SEL0_A0_MASK (((1U << PORTCON_PORTA_SEL0_A0_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 0U #define PORTCON_PORTA_SEL0_A0_BITS_GPIOA0 (PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 1U #define PORTCON_PORTA_SEL0_A0_BITS_PWMP1_PLUS0 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 2U #define PORTCON_PORTA_SEL0_A0_BITS_PWMP0_PLUS1 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A0_VALUE_TM 3U #define PORTCON_PORTA_SEL0_A0_BITS_TM (PORTCON_PORTA_SEL0_A0_VALUE_TM << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 4U #define PORTCON_PORTA_SEL0_A0_BITS_WAKEUP0 (PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 << PORTCON_PORTA_SEL0_A0_SHIFT) #define PORTCON_PORTA_SEL0_A1_SHIFT 4 #define PORTCON_PORTA_SEL0_A1_WIDTH 4 #define PORTCON_PORTA_SEL0_A1_MASK (((1U << PORTCON_PORTA_SEL0_A1_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A1_SHIFT) #define PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 0U #define PORTCON_PORTA_SEL0_A1_BITS_GPIOA1 (PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 << PORTCON_PORTA_SEL0_A1_SHIFT) #define PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI 1U #define PORTCON_PORTA_SEL0_A1_BITS_XTAL_XI (PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI << PORTCON_PORTA_SEL0_A1_SHIFT) #define PORTCON_PORTA_SEL0_A2_SHIFT 8 #define PORTCON_PORTA_SEL0_A2_WIDTH 4 #define PORTCON_PORTA_SEL0_A2_MASK (((1U << PORTCON_PORTA_SEL0_A2_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A2_SHIFT) #define PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 0U #define PORTCON_PORTA_SEL0_A2_BITS_GPIOA2 (PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 << PORTCON_PORTA_SEL0_A2_SHIFT) #define PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO 1U #define PORTCON_PORTA_SEL0_A2_BITS_XTAL_XO (PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO << PORTCON_PORTA_SEL0_A2_SHIFT) #define PORTCON_PORTA_SEL0_A3_SHIFT 12 #define PORTCON_PORTA_SEL0_A3_WIDTH 4 #define PORTCON_PORTA_SEL0_A3_MASK (((1U << PORTCON_PORTA_SEL0_A3_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A3_SHIFT) #define PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 0U #define PORTCON_PORTA_SEL0_A3_BITS_GPIOA3 (PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 << PORTCON_PORTA_SEL0_A3_SHIFT) #define PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN 1U #define PORTCON_PORTA_SEL0_A3_BITS_CMP0_VN (PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN << PORTCON_PORTA_SEL0_A3_SHIFT) #define PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI 2U #define PORTCON_PORTA_SEL0_A3_BITS_XTAH_XI (PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI << PORTCON_PORTA_SEL0_A3_SHIFT) #define PORTCON_PORTA_SEL0_A4_SHIFT 16 #define PORTCON_PORTA_SEL0_A4_WIDTH 4 #define PORTCON_PORTA_SEL0_A4_MASK (((1U << PORTCON_PORTA_SEL0_A4_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A4_SHIFT) #define PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 0U #define PORTCON_PORTA_SEL0_A4_BITS_GPIOA4 (PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 << PORTCON_PORTA_SEL0_A4_SHIFT) #define PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP 1U #define PORTCON_PORTA_SEL0_A4_BITS_CMP0_VP (PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP << PORTCON_PORTA_SEL0_A4_SHIFT) #define PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO 2U #define PORTCON_PORTA_SEL0_A4_BITS_XTAH_XO (PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO << PORTCON_PORTA_SEL0_A4_SHIFT) #define PORTCON_PORTA_SEL0_A5_SHIFT 20 #define PORTCON_PORTA_SEL0_A5_WIDTH 4 #define PORTCON_PORTA_SEL0_A5_MASK (((1U << PORTCON_PORTA_SEL0_A5_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 0U #define PORTCON_PORTA_SEL0_A5_BITS_GPIOA5 (PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS 1U #define PORTCON_PORTA_SEL0_A5_BITS_UART1_CTS (PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 2U #define PORTCON_PORTA_SEL0_A5_BITS_PWMP1_PLUS1 (PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 3U #define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L 4U #define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 5U #define PORTCON_PORTA_SEL0_A5_BITS_WAKEUP1 (PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 6U #define PORTCON_PORTA_SEL0_A5_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A5_SHIFT) #define PORTCON_PORTA_SEL0_A6_SHIFT 24 #define PORTCON_PORTA_SEL0_A6_WIDTH 4 #define PORTCON_PORTA_SEL0_A6_MASK (((1U << PORTCON_PORTA_SEL0_A6_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 0U #define PORTCON_PORTA_SEL0_A6_BITS_GPIOA6 (PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS 1U #define PORTCON_PORTA_SEL0_A6_BITS_UART1_RTS (PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 2U #define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H 3U #define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 4U #define PORTCON_PORTA_SEL0_A6_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT 5U #define PORTCON_PORTA_SEL0_A6_BITS_OPA0_OUT (PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT << PORTCON_PORTA_SEL0_A6_SHIFT) #define PORTCON_PORTA_SEL0_A7_SHIFT 28 #define PORTCON_PORTA_SEL0_A7_WIDTH 4 #define PORTCON_PORTA_SEL0_A7_MASK (((1U << PORTCON_PORTA_SEL0_A7_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 0U #define PORTCON_PORTA_SEL0_A7_BITS_GPIOA7 (PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX 1U #define PORTCON_PORTA_SEL0_A7_BITS_UART1_TX (PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 2U #define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L 3U #define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 4U #define PORTCON_PORTA_SEL0_A7_BITS_SARADC_CH2 (PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP 5U #define PORTCON_PORTA_SEL0_A7_BITS_OPA0_VP (PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP << PORTCON_PORTA_SEL0_A7_SHIFT) #define PORTCON_PORTA_SEL1_ADDR (PORTCON_BASE_ADDR + 0x0004U) #define PORTCON_PORTA_SEL1 (*(volatile uint32_t *)PORTCON_PORTA_SEL1_ADDR) #define PORTCON_PORTA_SEL1_A8_SHIFT 0 #define PORTCON_PORTA_SEL1_A8_WIDTH 4 #define PORTCON_PORTA_SEL1_A8_MASK (((1U << PORTCON_PORTA_SEL1_A8_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 0U #define PORTCON_PORTA_SEL1_A8_BITS_GPIOA8 (PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX 1U #define PORTCON_PORTA_SEL1_A8_BITS_UART1_RX (PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 2U #define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H 3U #define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 4U #define PORTCON_PORTA_SEL1_A8_BITS_SARADC_CH3 (PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN 5U #define PORTCON_PORTA_SEL1_A8_BITS_OPA0_VN (PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN << PORTCON_PORTA_SEL1_A8_SHIFT) #define PORTCON_PORTA_SEL1_A9_SHIFT 4 #define PORTCON_PORTA_SEL1_A9_WIDTH 4 #define PORTCON_PORTA_SEL1_A9_MASK (((1U << PORTCON_PORTA_SEL1_A9_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 0U #define PORTCON_PORTA_SEL1_A9_BITS_GPIOA9 (PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN 1U #define PORTCON_PORTA_SEL1_A9_BITS_SPI0_SSN (PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 2U #define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L 3U #define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_TM 4U #define PORTCON_PORTA_SEL1_A9_BITS_TM (PORTCON_PORTA_SEL1_A9_VALUE_TM << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 5U #define PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4 (PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN 6U #define PORTCON_PORTA_SEL1_A9_BITS_CMP1_VN (PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN << PORTCON_PORTA_SEL1_A9_SHIFT) #define PORTCON_PORTA_SEL1_A10_SHIFT 8 #define PORTCON_PORTA_SEL1_A10_WIDTH 4 #define PORTCON_PORTA_SEL1_A10_MASK (((1U << PORTCON_PORTA_SEL1_A10_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A10_SHIFT) #define PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 0U #define PORTCON_PORTA_SEL1_A10_BITS_GPIOA10 (PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 << PORTCON_PORTA_SEL1_A10_SHIFT) #define PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK 1U #define PORTCON_PORTA_SEL1_A10_BITS_SPI0_CLK (PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK << PORTCON_PORTA_SEL1_A10_SHIFT) #define PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 2U #define PORTCON_PORTA_SEL1_A10_BITS_SARADC_CH5 (PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 << PORTCON_PORTA_SEL1_A10_SHIFT) #define PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP 3U #define PORTCON_PORTA_SEL1_A10_BITS_CMP1_VP (PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP << PORTCON_PORTA_SEL1_A10_SHIFT) #define PORTCON_PORTA_SEL1_A11_SHIFT 12 #define PORTCON_PORTA_SEL1_A11_WIDTH 4 #define PORTCON_PORTA_SEL1_A11_MASK (((1U << PORTCON_PORTA_SEL1_A11_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 0U #define PORTCON_PORTA_SEL1_A11_BITS_GPIOA11 (PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO 1U #define PORTCON_PORTA_SEL1_A11_BITS_SPI0_MISO (PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 2U #define PORTCON_PORTA_SEL1_A11_BITS_PWMB0_CH0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 3U #define PORTCON_PORTA_SEL1_A11_BITS_PWMP0_BRAKE0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 4U #define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H 5U #define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 6U #define PORTCON_PORTA_SEL1_A11_BITS_SARADC_CH6 (PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 << PORTCON_PORTA_SEL1_A11_SHIFT) #define PORTCON_PORTA_SEL1_A12_SHIFT 16 #define PORTCON_PORTA_SEL1_A12_WIDTH 4 #define PORTCON_PORTA_SEL1_A12_MASK (((1U << PORTCON_PORTA_SEL1_A12_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 0U #define PORTCON_PORTA_SEL1_A12_BITS_GPIOA12 (PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI 1U #define PORTCON_PORTA_SEL1_A12_BITS_SPI0_MOSI (PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 2U #define PORTCON_PORTA_SEL1_A12_BITS_PWMB0_CH1 (PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N 3U #define PORTCON_PORTA_SEL1_A12_BITS_PWMP0_CH0N (PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 4U #define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L 5U #define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 6U #define PORTCON_PORTA_SEL1_A12_BITS_SARADC_CH7 (PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 << PORTCON_PORTA_SEL1_A12_SHIFT) #define PORTCON_PORTA_SEL1_A13_SHIFT 20 #define PORTCON_PORTA_SEL1_A13_WIDTH 4 #define PORTCON_PORTA_SEL1_A13_MASK (((1U << PORTCON_PORTA_SEL1_A13_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 0U #define PORTCON_PORTA_SEL1_A13_BITS_GPIOA13 (PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 1U #define PORTCON_PORTA_SEL1_A13_BITS_PWMB0_CH2 (PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N 2U #define PORTCON_PORTA_SEL1_A13_BITS_PWMP0_CH1N (PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 3U #define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H 4U #define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 5U #define PORTCON_PORTA_SEL1_A13_BITS_SARADC_CH8 (PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 << PORTCON_PORTA_SEL1_A13_SHIFT) #define PORTCON_PORTA_SEL1_A14_SHIFT 24 #define PORTCON_PORTA_SEL1_A14_WIDTH 4 #define PORTCON_PORTA_SEL1_A14_MASK (((1U << PORTCON_PORTA_SEL1_A14_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 0U #define PORTCON_PORTA_SEL1_A14_BITS_GPIOA14 (PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 1U #define PORTCON_PORTA_SEL1_A14_BITS_PWMB1_CH0 (PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N 2U #define PORTCON_PORTA_SEL1_A14_BITS_PWMP0_CH2N (PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 3U #define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L 4U #define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 5U #define PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9 (PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 << PORTCON_PORTA_SEL1_A14_SHIFT) #define PORTCON_PORTA_SEL1_A15_SHIFT 28 #define PORTCON_PORTA_SEL1_A15_WIDTH 4 #define PORTCON_PORTA_SEL1_A15_MASK (((1U << PORTCON_PORTA_SEL1_A15_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 0U #define PORTCON_PORTA_SEL1_A15_BITS_GPIOA15 (PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 1U #define PORTCON_PORTA_SEL1_A15_BITS_PWMB1_CH1 (PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 2U #define PORTCON_PORTA_SEL1_A15_BITS_PWMP0_CH0 (PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 3U #define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H 4U #define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A15_SHIFT) #define PORTCON_PORTB_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0008U) #define PORTCON_PORTB_SEL0 (*(volatile uint32_t *)PORTCON_PORTB_SEL0_ADDR) #define PORTCON_PORTB_SEL0_B0_SHIFT 0 #define PORTCON_PORTB_SEL0_B0_WIDTH 4 #define PORTCON_PORTB_SEL0_B0_MASK (((1U << PORTCON_PORTB_SEL0_B0_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 0U #define PORTCON_PORTB_SEL0_B0_BITS_GPIOB0 (PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX 1U #define PORTCON_PORTB_SEL0_B0_BITS_UART2_TX (PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL 2U #define PORTCON_PORTB_SEL0_B0_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 3U #define PORTCON_PORTB_SEL0_B0_BITS_PWMB1_CH2 (PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 4U #define PORTCON_PORTB_SEL0_B0_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B0_SHIFT) #define PORTCON_PORTB_SEL0_B1_SHIFT 4 #define PORTCON_PORTB_SEL0_B1_WIDTH 4 #define PORTCON_PORTB_SEL0_B1_MASK (((1U << PORTCON_PORTB_SEL0_B1_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B1_SHIFT) #define PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 0U #define PORTCON_PORTB_SEL0_B1_BITS_GPIOB1 (PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 << PORTCON_PORTB_SEL0_B1_SHIFT) #define PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX 1U #define PORTCON_PORTB_SEL0_B1_BITS_UART2_RX (PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX << PORTCON_PORTB_SEL0_B1_SHIFT) #define PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA 2U #define PORTCON_PORTB_SEL0_B1_BITS_IIC0_SDA (PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA << PORTCON_PORTB_SEL0_B1_SHIFT) #define PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 3U #define PORTCON_PORTB_SEL0_B1_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL0_B1_SHIFT) #define PORTCON_PORTB_SEL0_B2_SHIFT 8 #define PORTCON_PORTB_SEL0_B2_WIDTH 4 #define PORTCON_PORTB_SEL0_B2_MASK (((1U << PORTCON_PORTB_SEL0_B2_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B2_SHIFT) #define PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 0U #define PORTCON_PORTB_SEL0_B2_BITS_GPIOB2 (PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 << PORTCON_PORTB_SEL0_B2_SHIFT) #define PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN 1U #define PORTCON_PORTB_SEL0_B2_BITS_SPI1_SSN (PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN << PORTCON_PORTB_SEL0_B2_SHIFT) #define PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 2U #define PORTCON_PORTB_SEL0_B2_BITS_PWMP0_BRAKE1 (PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 << PORTCON_PORTB_SEL0_B2_SHIFT) #define PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 3U #define PORTCON_PORTB_SEL0_B2_BITS_TIMERP1_HALL0 (PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 << PORTCON_PORTB_SEL0_B2_SHIFT) #define PORTCON_PORTB_SEL0_B3_SHIFT 12 #define PORTCON_PORTB_SEL0_B3_WIDTH 4 #define PORTCON_PORTB_SEL0_B3_MASK (((1U << PORTCON_PORTB_SEL0_B3_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 0U #define PORTCON_PORTB_SEL0_B3_BITS_GPIOB3 (PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK 1U #define PORTCON_PORTB_SEL0_B3_BITS_SPI1_CLK (PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA 2U #define PORTCON_PORTB_SEL0_B3_BITS_IIC1_SDA (PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N 3U #define PORTCON_PORTB_SEL0_B3_BITS_PWMP0_CH0N (PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 4U #define PORTCON_PORTB_SEL0_B3_BITS_TIMERP1_HALL1 (PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 << PORTCON_PORTB_SEL0_B3_SHIFT) #define PORTCON_PORTB_SEL0_B4_SHIFT 16 #define PORTCON_PORTB_SEL0_B4_WIDTH 4 #define PORTCON_PORTB_SEL0_B4_MASK (((1U << PORTCON_PORTB_SEL0_B4_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 0U #define PORTCON_PORTB_SEL0_B4_BITS_GPIOB4 (PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO 1U #define PORTCON_PORTB_SEL0_B4_BITS_SPI1_MISO (PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL 2U #define PORTCON_PORTB_SEL0_B4_BITS_IIC1_SCL (PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 3U #define PORTCON_PORTB_SEL0_B4_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N 4U #define PORTCON_PORTB_SEL0_B4_BITS_PWMP0_CH1N (PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 5U #define PORTCON_PORTB_SEL0_B4_BITS_TIMERP1_HALL2 (PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 << PORTCON_PORTB_SEL0_B4_SHIFT) #define PORTCON_PORTB_SEL0_B5_SHIFT 20 #define PORTCON_PORTB_SEL0_B5_WIDTH 4 #define PORTCON_PORTB_SEL0_B5_MASK (((1U << PORTCON_PORTB_SEL0_B5_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 0U #define PORTCON_PORTB_SEL0_B5_BITS_GPIOB5 (PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI 1U #define PORTCON_PORTB_SEL0_B5_BITS_SPI1_MOSI (PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N 2U #define PORTCON_PORTB_SEL0_B5_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N 3U #define PORTCON_PORTB_SEL0_B5_BITS_PWMP0_CH2N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 4U #define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_IN0 (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L 5U #define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_OUT_L (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L << PORTCON_PORTB_SEL0_B5_SHIFT) #define PORTCON_PORTB_SEL0_B6_SHIFT 24 #define PORTCON_PORTB_SEL0_B6_WIDTH 4 #define PORTCON_PORTB_SEL0_B6_MASK (((1U << PORTCON_PORTB_SEL0_B6_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B6_SHIFT) #define PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 0U #define PORTCON_PORTB_SEL0_B6_BITS_GPIOB6 (PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 << PORTCON_PORTB_SEL0_B6_SHIFT) #define PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 1U #define PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0 (PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 << PORTCON_PORTB_SEL0_B6_SHIFT) #define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 2U #define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_IN1 (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 << PORTCON_PORTB_SEL0_B6_SHIFT) #define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H 3U #define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_OUT_H (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H << PORTCON_PORTB_SEL0_B6_SHIFT) #define PORTCON_PORTB_SEL0_B7_SHIFT 28 #define PORTCON_PORTB_SEL0_B7_WIDTH 4 #define PORTCON_PORTB_SEL0_B7_MASK (((1U << PORTCON_PORTB_SEL0_B7_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 0U #define PORTCON_PORTB_SEL0_B7_BITS_GPIOB7 (PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN 1U #define PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN (PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX 2U #define PORTCON_PORTB_SEL0_B7_BITS_UART0_TX (PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL 3U #define PORTCON_PORTB_SEL0_B7_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 4U #define PORTCON_PORTB_SEL0_B7_BITS_PWMP1_BRAKE0 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 5U #define PORTCON_PORTB_SEL0_B7_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B7_SHIFT) #define PORTCON_PORTB_SEL1_ADDR (PORTCON_BASE_ADDR + 0x000CU) #define PORTCON_PORTB_SEL1 (*(volatile uint32_t *)PORTCON_PORTB_SEL1_ADDR) #define PORTCON_PORTB_SEL1_B8_SHIFT 0 #define PORTCON_PORTB_SEL1_B8_WIDTH 4 #define PORTCON_PORTB_SEL1_B8_MASK (((1U << PORTCON_PORTB_SEL1_B8_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 0U #define PORTCON_PORTB_SEL1_B8_BITS_GPIOB8 (PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK 1U #define PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK (PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX 2U #define PORTCON_PORTB_SEL1_B8_BITS_UART0_RX (PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA 3U #define PORTCON_PORTB_SEL1_B8_BITS_IIC0_SDA (PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 4U #define PORTCON_PORTB_SEL1_B8_BITS_PWMB0_CH0 (PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 5U #define PORTCON_PORTB_SEL1_B8_BITS_PWMP1_BRAKE1 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 6U #define PORTCON_PORTB_SEL1_B8_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL1_B8_SHIFT) #define PORTCON_PORTB_SEL1_B9_SHIFT 4 #define PORTCON_PORTB_SEL1_B9_WIDTH 4 #define PORTCON_PORTB_SEL1_B9_MASK (((1U << PORTCON_PORTB_SEL1_B9_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 0U #define PORTCON_PORTB_SEL1_B9_BITS_GPIOB9 (PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO 1U #define PORTCON_PORTB_SEL1_B9_BITS_SPI0_MISO (PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS 2U #define PORTCON_PORTB_SEL1_B9_BITS_UART0_CTS (PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 3U #define PORTCON_PORTB_SEL1_B9_BITS_PWMB0_CH1 (PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 4U #define PORTCON_PORTB_SEL1_B9_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 5U #define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_IN1 (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H 6U #define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_OUT_H (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H << PORTCON_PORTB_SEL1_B9_SHIFT) #define PORTCON_PORTB_SEL1_B10_SHIFT 8 #define PORTCON_PORTB_SEL1_B10_WIDTH 4 #define PORTCON_PORTB_SEL1_B10_MASK (((1U << PORTCON_PORTB_SEL1_B10_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 0U #define PORTCON_PORTB_SEL1_B10_BITS_GPIOB10 (PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI 1U #define PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI (PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS 2U #define PORTCON_PORTB_SEL1_B10_BITS_UART0_RTS (PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 3U #define PORTCON_PORTB_SEL1_B10_BITS_PWMB0_CH2 (PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 4U #define PORTCON_PORTB_SEL1_B10_BITS_PWMP1_CH1 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 5U #define PORTCON_PORTB_SEL1_B10_BITS_PWMP0_PLUS0 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 6U #define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_IN0 (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L 7U #define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_OUT_L (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L << PORTCON_PORTB_SEL1_B10_SHIFT) #define PORTCON_PORTB_SEL1_B11_SHIFT 12 #define PORTCON_PORTB_SEL1_B11_WIDTH 4 #define PORTCON_PORTB_SEL1_B11_MASK (((1U << PORTCON_PORTB_SEL1_B11_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B11_SHIFT) #define PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 0U #define PORTCON_PORTB_SEL1_B11_BITS_GPIOB11 (PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 << PORTCON_PORTB_SEL1_B11_SHIFT) #define PORTCON_PORTB_SEL1_B11_VALUE_SWDIO 1U #define PORTCON_PORTB_SEL1_B11_BITS_SWDIO (PORTCON_PORTB_SEL1_B11_VALUE_SWDIO << PORTCON_PORTB_SEL1_B11_SHIFT) #define PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 2U #define PORTCON_PORTB_SEL1_B11_BITS_PWMP1_CH2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 << PORTCON_PORTB_SEL1_B11_SHIFT) #define PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 3U #define PORTCON_PORTB_SEL1_B11_BITS_PWMP0_BRAKE2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 << PORTCON_PORTB_SEL1_B11_SHIFT) #define PORTCON_PORTB_SEL1_B12_SHIFT 16 #define PORTCON_PORTB_SEL1_B12_WIDTH 4 #define PORTCON_PORTB_SEL1_B12_MASK (((1U << PORTCON_PORTB_SEL1_B12_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B12_SHIFT) #define PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 0U #define PORTCON_PORTB_SEL1_B12_BITS_GPIOB12 (PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 << PORTCON_PORTB_SEL1_B12_SHIFT) #define PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX 1U #define PORTCON_PORTB_SEL1_B12_BITS_UART1_TX (PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX << PORTCON_PORTB_SEL1_B12_SHIFT) #define PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL 2U #define PORTCON_PORTB_SEL1_B12_BITS_IIC1_SCL (PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL << PORTCON_PORTB_SEL1_B12_SHIFT) #define PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N 3U #define PORTCON_PORTB_SEL1_B12_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL1_B12_SHIFT) #define PORTCON_PORTB_SEL1_B13_SHIFT 20 #define PORTCON_PORTB_SEL1_B13_WIDTH 4 #define PORTCON_PORTB_SEL1_B13_MASK (((1U << PORTCON_PORTB_SEL1_B13_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B13_SHIFT) #define PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 0U #define PORTCON_PORTB_SEL1_B13_BITS_GPIOB13 (PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 << PORTCON_PORTB_SEL1_B13_SHIFT) #define PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX 1U #define PORTCON_PORTB_SEL1_B13_BITS_UART1_RX (PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX << PORTCON_PORTB_SEL1_B13_SHIFT) #define PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA 2U #define PORTCON_PORTB_SEL1_B13_BITS_IIC1_SDA (PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA << PORTCON_PORTB_SEL1_B13_SHIFT) #define PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N 3U #define PORTCON_PORTB_SEL1_B13_BITS_PWMP1_CH1N (PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N << PORTCON_PORTB_SEL1_B13_SHIFT) #define PORTCON_PORTB_SEL1_B14_SHIFT 24 #define PORTCON_PORTB_SEL1_B14_WIDTH 4 #define PORTCON_PORTB_SEL1_B14_MASK (((1U << PORTCON_PORTB_SEL1_B14_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B14_SHIFT) #define PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 0U #define PORTCON_PORTB_SEL1_B14_BITS_GPIOB14 (PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 << PORTCON_PORTB_SEL1_B14_SHIFT) #define PORTCON_PORTB_SEL1_B14_VALUE_SWCLK 1U #define PORTCON_PORTB_SEL1_B14_BITS_SWCLK (PORTCON_PORTB_SEL1_B14_VALUE_SWCLK << PORTCON_PORTB_SEL1_B14_SHIFT) #define PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX 2U #define PORTCON_PORTB_SEL1_B14_BITS_UART2_TX (PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX << PORTCON_PORTB_SEL1_B14_SHIFT) #define PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N 3U #define PORTCON_PORTB_SEL1_B14_BITS_PWMP1_CH2N (PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N << PORTCON_PORTB_SEL1_B14_SHIFT) #define PORTCON_PORTB_SEL1_B15_SHIFT 28 #define PORTCON_PORTB_SEL1_B15_WIDTH 4 #define PORTCON_PORTB_SEL1_B15_MASK (((1U << PORTCON_PORTB_SEL1_B15_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B15_SHIFT) #define PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 0U #define PORTCON_PORTB_SEL1_B15_BITS_GPIOB15 (PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 << PORTCON_PORTB_SEL1_B15_SHIFT) #define PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN 1U #define PORTCON_PORTB_SEL1_B15_BITS_SPI1_SSN (PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN << PORTCON_PORTB_SEL1_B15_SHIFT) #define PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX 2U #define PORTCON_PORTB_SEL1_B15_BITS_UART2_RX (PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX << PORTCON_PORTB_SEL1_B15_SHIFT) #define PORTCON_PORTC_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0010U) #define PORTCON_PORTC_SEL0 (*(volatile uint32_t *)PORTCON_PORTC_SEL0_ADDR) #define PORTCON_PORTC_SEL0_C0_SHIFT 0 #define PORTCON_PORTC_SEL0_C0_WIDTH 4 #define PORTCON_PORTC_SEL0_C0_MASK (((1U << PORTCON_PORTC_SEL0_C0_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C0_SHIFT) #define PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 0U #define PORTCON_PORTC_SEL0_C0_BITS_GPIOC0 (PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 << PORTCON_PORTC_SEL0_C0_SHIFT) #define PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK 1U #define PORTCON_PORTC_SEL0_C0_BITS_SPI1_CLK (PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK << PORTCON_PORTC_SEL0_C0_SHIFT) #define PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS 2U #define PORTCON_PORTC_SEL0_C0_BITS_UART2_CTS (PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS << PORTCON_PORTC_SEL0_C0_SHIFT) #define PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 3U #define PORTCON_PORTC_SEL0_C0_BITS_PWMB1_CH0 (PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 << PORTCON_PORTC_SEL0_C0_SHIFT) #define PORTCON_PORTC_SEL0_C1_SHIFT 4 #define PORTCON_PORTC_SEL0_C1_WIDTH 4 #define PORTCON_PORTC_SEL0_C1_MASK (((1U << PORTCON_PORTC_SEL0_C1_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 0U #define PORTCON_PORTC_SEL0_C1_BITS_GPIOC1 (PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO 1U #define PORTCON_PORTC_SEL0_C1_BITS_SPI1_MISO (PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS 2U #define PORTCON_PORTC_SEL0_C1_BITS_UART2_RTS (PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 3U #define PORTCON_PORTC_SEL0_C1_BITS_PWMB1_CH1 (PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 4U #define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_IN0 (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L 5U #define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_OUT_L (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L << PORTCON_PORTC_SEL0_C1_SHIFT) #define PORTCON_PORTC_SEL0_C2_SHIFT 8 #define PORTCON_PORTC_SEL0_C2_WIDTH 4 #define PORTCON_PORTC_SEL0_C2_MASK (((1U << PORTCON_PORTC_SEL0_C2_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 0U #define PORTCON_PORTC_SEL0_C2_BITS_GPIOC2 (PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI 1U #define PORTCON_PORTC_SEL0_C2_BITS_SPI1_MOSI (PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 2U #define PORTCON_PORTC_SEL0_C2_BITS_PWMB1_CH2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 3U #define PORTCON_PORTC_SEL0_C2_BITS_PWMP1_BRAKE2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 4U #define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_IN1 (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H 5U #define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_OUT_H (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H << PORTCON_PORTC_SEL0_C2_SHIFT) #define PORTCON_PORTC_SEL0_C3_SHIFT 12 #define PORTCON_PORTC_SEL0_C3_WIDTH 4 #define PORTCON_PORTC_SEL0_C3_MASK (((1U << PORTCON_PORTC_SEL0_C3_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 0U #define PORTCON_PORTC_SEL0_C3_BITS_GPIOC3 (PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX 1U #define PORTCON_PORTC_SEL0_C3_BITS_UART0_TX (PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL 2U #define PORTCON_PORTC_SEL0_C3_BITS_IIC0_SCL (PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N 3U #define PORTCON_PORTC_SEL0_C3_BITS_PWMP1_CH1N (PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 4U #define PORTCON_PORTC_SEL0_C3_BITS_TIMERP0_HALL0 (PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN 5U #define PORTCON_PORTC_SEL0_C3_BITS_CMP2_VN (PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN << PORTCON_PORTC_SEL0_C3_SHIFT) #define PORTCON_PORTC_SEL0_C4_SHIFT 16 #define PORTCON_PORTC_SEL0_C4_WIDTH 4 #define PORTCON_PORTC_SEL0_C4_MASK (((1U << PORTCON_PORTC_SEL0_C4_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 0U #define PORTCON_PORTC_SEL0_C4_BITS_GPIOC4 (PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX 1U #define PORTCON_PORTC_SEL0_C4_BITS_UART0_RX (PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA 2U #define PORTCON_PORTC_SEL0_C4_BITS_IIC0_SDA (PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N 3U #define PORTCON_PORTC_SEL0_C4_BITS_PWMP1_CH2N (PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 4U #define PORTCON_PORTC_SEL0_C4_BITS_TIMERP0_HALL1 (PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP 5U #define PORTCON_PORTC_SEL0_C4_BITS_CMP2_VP (PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP << PORTCON_PORTC_SEL0_C4_SHIFT) #define PORTCON_PORTC_SEL0_C5_SHIFT 20 #define PORTCON_PORTC_SEL0_C5_WIDTH 4 #define PORTCON_PORTC_SEL0_C5_MASK (((1U << PORTCON_PORTC_SEL0_C5_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C5_SHIFT) #define PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 0U #define PORTCON_PORTC_SEL0_C5_BITS_GPIOC5 (PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 << PORTCON_PORTC_SEL0_C5_SHIFT) #define PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 1U #define PORTCON_PORTC_SEL0_C5_BITS_TIMERP0_HALL2 (PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 << PORTCON_PORTC_SEL0_C5_SHIFT) #define PORTCON_PORTC_SEL0_C5_VALUE_TM 2U #define PORTCON_PORTC_SEL0_C5_BITS_TM (PORTCON_PORTC_SEL0_C5_VALUE_TM << PORTCON_PORTC_SEL0_C5_SHIFT) #define PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP 3U #define PORTCON_PORTC_SEL0_C5_BITS_OPA1_VP (PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP << PORTCON_PORTC_SEL0_C5_SHIFT) #define PORTCON_PORTC_SEL0_C6_SHIFT 24 #define PORTCON_PORTC_SEL0_C6_WIDTH 4 #define PORTCON_PORTC_SEL0_C6_MASK (((1U << PORTCON_PORTC_SEL0_C6_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 0U #define PORTCON_PORTC_SEL0_C6_BITS_GPIOC6 (PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL 1U #define PORTCON_PORTC_SEL0_C6_BITS_IIC1_SCL (PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 2U #define PORTCON_PORTC_SEL0_C6_BITS_PWMP1_CH1 (PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 3U #define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_IN1 (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H 4U #define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_OUT_H (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN 5U #define PORTCON_PORTC_SEL0_C6_BITS_OPA1_VN (PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN << PORTCON_PORTC_SEL0_C6_SHIFT) #define PORTCON_PORTC_SEL0_C7_SHIFT 28 #define PORTCON_PORTC_SEL0_C7_WIDTH 4 #define PORTCON_PORTC_SEL0_C7_MASK (((1U << PORTCON_PORTC_SEL0_C7_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 0U #define PORTCON_PORTC_SEL0_C7_BITS_GPIOC7 (PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA 1U #define PORTCON_PORTC_SEL0_C7_BITS_IIC1_SDA (PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 2U #define PORTCON_PORTC_SEL0_C7_BITS_PWMP1_CH2 (PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 3U #define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_IN0 (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L 4U #define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_OUT_L (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT 5U #define PORTCON_PORTC_SEL0_C7_BITS_OPA1_OUT (PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT << PORTCON_PORTC_SEL0_C7_SHIFT) #define PORTCON_PORTA_IE_ADDR (PORTCON_BASE_ADDR + 0x0100U) #define PORTCON_PORTA_IE (*(volatile uint32_t *)PORTCON_PORTA_IE_ADDR) #define PORTCON_PORTA_IE_A0_SHIFT 0 #define PORTCON_PORTA_IE_A0_WIDTH 1 #define PORTCON_PORTA_IE_A0_MASK (((1U << PORTCON_PORTA_IE_A0_WIDTH) - 1U) << PORTCON_PORTA_IE_A0_SHIFT) #define PORTCON_PORTA_IE_A0_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A0_BITS_DISABLE (PORTCON_PORTA_IE_A0_VALUE_DISABLE << PORTCON_PORTA_IE_A0_SHIFT) #define PORTCON_PORTA_IE_A0_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A0_BITS_ENABLE (PORTCON_PORTA_IE_A0_VALUE_ENABLE << PORTCON_PORTA_IE_A0_SHIFT) #define PORTCON_PORTA_IE_A1_SHIFT 1 #define PORTCON_PORTA_IE_A1_WIDTH 1 #define PORTCON_PORTA_IE_A1_MASK (((1U << PORTCON_PORTA_IE_A1_WIDTH) - 1U) << PORTCON_PORTA_IE_A1_SHIFT) #define PORTCON_PORTA_IE_A1_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A1_BITS_DISABLE (PORTCON_PORTA_IE_A1_VALUE_DISABLE << PORTCON_PORTA_IE_A1_SHIFT) #define PORTCON_PORTA_IE_A1_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A1_BITS_ENABLE (PORTCON_PORTA_IE_A1_VALUE_ENABLE << PORTCON_PORTA_IE_A1_SHIFT) #define PORTCON_PORTA_IE_A2_SHIFT 2 #define PORTCON_PORTA_IE_A2_WIDTH 1 #define PORTCON_PORTA_IE_A2_MASK (((1U << PORTCON_PORTA_IE_A2_WIDTH) - 1U) << PORTCON_PORTA_IE_A2_SHIFT) #define PORTCON_PORTA_IE_A2_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A2_BITS_DISABLE (PORTCON_PORTA_IE_A2_VALUE_DISABLE << PORTCON_PORTA_IE_A2_SHIFT) #define PORTCON_PORTA_IE_A2_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A2_BITS_ENABLE (PORTCON_PORTA_IE_A2_VALUE_ENABLE << PORTCON_PORTA_IE_A2_SHIFT) #define PORTCON_PORTA_IE_A3_SHIFT 3 #define PORTCON_PORTA_IE_A3_WIDTH 1 #define PORTCON_PORTA_IE_A3_MASK (((1U << PORTCON_PORTA_IE_A3_WIDTH) - 1U) << PORTCON_PORTA_IE_A3_SHIFT) #define PORTCON_PORTA_IE_A3_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A3_BITS_DISABLE (PORTCON_PORTA_IE_A3_VALUE_DISABLE << PORTCON_PORTA_IE_A3_SHIFT) #define PORTCON_PORTA_IE_A3_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A3_BITS_ENABLE (PORTCON_PORTA_IE_A3_VALUE_ENABLE << PORTCON_PORTA_IE_A3_SHIFT) #define PORTCON_PORTA_IE_A4_SHIFT 4 #define PORTCON_PORTA_IE_A4_WIDTH 1 #define PORTCON_PORTA_IE_A4_MASK (((1U << PORTCON_PORTA_IE_A4_WIDTH) - 1U) << PORTCON_PORTA_IE_A4_SHIFT) #define PORTCON_PORTA_IE_A4_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A4_BITS_DISABLE (PORTCON_PORTA_IE_A4_VALUE_DISABLE << PORTCON_PORTA_IE_A4_SHIFT) #define PORTCON_PORTA_IE_A4_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A4_BITS_ENABLE (PORTCON_PORTA_IE_A4_VALUE_ENABLE << PORTCON_PORTA_IE_A4_SHIFT) #define PORTCON_PORTA_IE_A5_SHIFT 5 #define PORTCON_PORTA_IE_A5_WIDTH 1 #define PORTCON_PORTA_IE_A5_MASK (((1U << PORTCON_PORTA_IE_A5_WIDTH) - 1U) << PORTCON_PORTA_IE_A5_SHIFT) #define PORTCON_PORTA_IE_A5_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A5_BITS_DISABLE (PORTCON_PORTA_IE_A5_VALUE_DISABLE << PORTCON_PORTA_IE_A5_SHIFT) #define PORTCON_PORTA_IE_A5_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A5_BITS_ENABLE (PORTCON_PORTA_IE_A5_VALUE_ENABLE << PORTCON_PORTA_IE_A5_SHIFT) #define PORTCON_PORTA_IE_A6_SHIFT 6 #define PORTCON_PORTA_IE_A6_WIDTH 1 #define PORTCON_PORTA_IE_A6_MASK (((1U << PORTCON_PORTA_IE_A6_WIDTH) - 1U) << PORTCON_PORTA_IE_A6_SHIFT) #define PORTCON_PORTA_IE_A6_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A6_BITS_DISABLE (PORTCON_PORTA_IE_A6_VALUE_DISABLE << PORTCON_PORTA_IE_A6_SHIFT) #define PORTCON_PORTA_IE_A6_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A6_BITS_ENABLE (PORTCON_PORTA_IE_A6_VALUE_ENABLE << PORTCON_PORTA_IE_A6_SHIFT) #define PORTCON_PORTA_IE_A7_SHIFT 7 #define PORTCON_PORTA_IE_A7_WIDTH 1 #define PORTCON_PORTA_IE_A7_MASK (((1U << PORTCON_PORTA_IE_A7_WIDTH) - 1U) << PORTCON_PORTA_IE_A7_SHIFT) #define PORTCON_PORTA_IE_A7_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A7_BITS_DISABLE (PORTCON_PORTA_IE_A7_VALUE_DISABLE << PORTCON_PORTA_IE_A7_SHIFT) #define PORTCON_PORTA_IE_A7_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A7_BITS_ENABLE (PORTCON_PORTA_IE_A7_VALUE_ENABLE << PORTCON_PORTA_IE_A7_SHIFT) #define PORTCON_PORTA_IE_A8_SHIFT 8 #define PORTCON_PORTA_IE_A8_WIDTH 1 #define PORTCON_PORTA_IE_A8_MASK (((1U << PORTCON_PORTA_IE_A8_WIDTH) - 1U) << PORTCON_PORTA_IE_A8_SHIFT) #define PORTCON_PORTA_IE_A8_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A8_BITS_DISABLE (PORTCON_PORTA_IE_A8_VALUE_DISABLE << PORTCON_PORTA_IE_A8_SHIFT) #define PORTCON_PORTA_IE_A8_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A8_BITS_ENABLE (PORTCON_PORTA_IE_A8_VALUE_ENABLE << PORTCON_PORTA_IE_A8_SHIFT) #define PORTCON_PORTA_IE_A9_SHIFT 9 #define PORTCON_PORTA_IE_A9_WIDTH 1 #define PORTCON_PORTA_IE_A9_MASK (((1U << PORTCON_PORTA_IE_A9_WIDTH) - 1U) << PORTCON_PORTA_IE_A9_SHIFT) #define PORTCON_PORTA_IE_A9_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A9_BITS_DISABLE (PORTCON_PORTA_IE_A9_VALUE_DISABLE << PORTCON_PORTA_IE_A9_SHIFT) #define PORTCON_PORTA_IE_A9_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A9_BITS_ENABLE (PORTCON_PORTA_IE_A9_VALUE_ENABLE << PORTCON_PORTA_IE_A9_SHIFT) #define PORTCON_PORTA_IE_A10_SHIFT 10 #define PORTCON_PORTA_IE_A10_WIDTH 1 #define PORTCON_PORTA_IE_A10_MASK (((1U << PORTCON_PORTA_IE_A10_WIDTH) - 1U) << PORTCON_PORTA_IE_A10_SHIFT) #define PORTCON_PORTA_IE_A10_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A10_BITS_DISABLE (PORTCON_PORTA_IE_A10_VALUE_DISABLE << PORTCON_PORTA_IE_A10_SHIFT) #define PORTCON_PORTA_IE_A10_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A10_BITS_ENABLE (PORTCON_PORTA_IE_A10_VALUE_ENABLE << PORTCON_PORTA_IE_A10_SHIFT) #define PORTCON_PORTA_IE_A11_SHIFT 11 #define PORTCON_PORTA_IE_A11_WIDTH 1 #define PORTCON_PORTA_IE_A11_MASK (((1U << PORTCON_PORTA_IE_A11_WIDTH) - 1U) << PORTCON_PORTA_IE_A11_SHIFT) #define PORTCON_PORTA_IE_A11_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A11_BITS_DISABLE (PORTCON_PORTA_IE_A11_VALUE_DISABLE << PORTCON_PORTA_IE_A11_SHIFT) #define PORTCON_PORTA_IE_A11_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A11_BITS_ENABLE (PORTCON_PORTA_IE_A11_VALUE_ENABLE << PORTCON_PORTA_IE_A11_SHIFT) #define PORTCON_PORTA_IE_A12_SHIFT 12 #define PORTCON_PORTA_IE_A12_WIDTH 1 #define PORTCON_PORTA_IE_A12_MASK (((1U << PORTCON_PORTA_IE_A12_WIDTH) - 1U) << PORTCON_PORTA_IE_A12_SHIFT) #define PORTCON_PORTA_IE_A12_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A12_BITS_DISABLE (PORTCON_PORTA_IE_A12_VALUE_DISABLE << PORTCON_PORTA_IE_A12_SHIFT) #define PORTCON_PORTA_IE_A12_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A12_BITS_ENABLE (PORTCON_PORTA_IE_A12_VALUE_ENABLE << PORTCON_PORTA_IE_A12_SHIFT) #define PORTCON_PORTA_IE_A13_SHIFT 13 #define PORTCON_PORTA_IE_A13_WIDTH 1 #define PORTCON_PORTA_IE_A13_MASK (((1U << PORTCON_PORTA_IE_A13_WIDTH) - 1U) << PORTCON_PORTA_IE_A13_SHIFT) #define PORTCON_PORTA_IE_A13_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A13_BITS_DISABLE (PORTCON_PORTA_IE_A13_VALUE_DISABLE << PORTCON_PORTA_IE_A13_SHIFT) #define PORTCON_PORTA_IE_A13_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A13_BITS_ENABLE (PORTCON_PORTA_IE_A13_VALUE_ENABLE << PORTCON_PORTA_IE_A13_SHIFT) #define PORTCON_PORTA_IE_A14_SHIFT 14 #define PORTCON_PORTA_IE_A14_WIDTH 1 #define PORTCON_PORTA_IE_A14_MASK (((1U << PORTCON_PORTA_IE_A14_WIDTH) - 1U) << PORTCON_PORTA_IE_A14_SHIFT) #define PORTCON_PORTA_IE_A14_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A14_BITS_DISABLE (PORTCON_PORTA_IE_A14_VALUE_DISABLE << PORTCON_PORTA_IE_A14_SHIFT) #define PORTCON_PORTA_IE_A14_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A14_BITS_ENABLE (PORTCON_PORTA_IE_A14_VALUE_ENABLE << PORTCON_PORTA_IE_A14_SHIFT) #define PORTCON_PORTA_IE_A15_SHIFT 15 #define PORTCON_PORTA_IE_A15_WIDTH 1 #define PORTCON_PORTA_IE_A15_MASK (((1U << PORTCON_PORTA_IE_A15_WIDTH) - 1U) << PORTCON_PORTA_IE_A15_SHIFT) #define PORTCON_PORTA_IE_A15_VALUE_DISABLE 0U #define PORTCON_PORTA_IE_A15_BITS_DISABLE (PORTCON_PORTA_IE_A15_VALUE_DISABLE << PORTCON_PORTA_IE_A15_SHIFT) #define PORTCON_PORTA_IE_A15_VALUE_ENABLE 1U #define PORTCON_PORTA_IE_A15_BITS_ENABLE (PORTCON_PORTA_IE_A15_VALUE_ENABLE << PORTCON_PORTA_IE_A15_SHIFT) #define PORTCON_PORTB_IE_ADDR (PORTCON_BASE_ADDR + 0x0104U) #define PORTCON_PORTB_IE (*(volatile uint32_t *)PORTCON_PORTB_IE_ADDR) #define PORTCON_PORTB_IE_B0_SHIFT 0 #define PORTCON_PORTB_IE_B0_WIDTH 1 #define PORTCON_PORTB_IE_B0_MASK (((1U << PORTCON_PORTB_IE_B0_WIDTH) - 1U) << PORTCON_PORTB_IE_B0_SHIFT) #define PORTCON_PORTB_IE_B0_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B0_BITS_DISABLE (PORTCON_PORTB_IE_B0_VALUE_DISABLE << PORTCON_PORTB_IE_B0_SHIFT) #define PORTCON_PORTB_IE_B0_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B0_BITS_ENABLE (PORTCON_PORTB_IE_B0_VALUE_ENABLE << PORTCON_PORTB_IE_B0_SHIFT) #define PORTCON_PORTB_IE_B1_SHIFT 1 #define PORTCON_PORTB_IE_B1_WIDTH 1 #define PORTCON_PORTB_IE_B1_MASK (((1U << PORTCON_PORTB_IE_B1_WIDTH) - 1U) << PORTCON_PORTB_IE_B1_SHIFT) #define PORTCON_PORTB_IE_B1_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B1_BITS_DISABLE (PORTCON_PORTB_IE_B1_VALUE_DISABLE << PORTCON_PORTB_IE_B1_SHIFT) #define PORTCON_PORTB_IE_B1_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B1_BITS_ENABLE (PORTCON_PORTB_IE_B1_VALUE_ENABLE << PORTCON_PORTB_IE_B1_SHIFT) #define PORTCON_PORTB_IE_B2_SHIFT 2 #define PORTCON_PORTB_IE_B2_WIDTH 1 #define PORTCON_PORTB_IE_B2_MASK (((1U << PORTCON_PORTB_IE_B2_WIDTH) - 1U) << PORTCON_PORTB_IE_B2_SHIFT) #define PORTCON_PORTB_IE_B2_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B2_BITS_DISABLE (PORTCON_PORTB_IE_B2_VALUE_DISABLE << PORTCON_PORTB_IE_B2_SHIFT) #define PORTCON_PORTB_IE_B2_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B2_BITS_ENABLE (PORTCON_PORTB_IE_B2_VALUE_ENABLE << PORTCON_PORTB_IE_B2_SHIFT) #define PORTCON_PORTB_IE_B3_SHIFT 3 #define PORTCON_PORTB_IE_B3_WIDTH 1 #define PORTCON_PORTB_IE_B3_MASK (((1U << PORTCON_PORTB_IE_B3_WIDTH) - 1U) << PORTCON_PORTB_IE_B3_SHIFT) #define PORTCON_PORTB_IE_B3_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B3_BITS_DISABLE (PORTCON_PORTB_IE_B3_VALUE_DISABLE << PORTCON_PORTB_IE_B3_SHIFT) #define PORTCON_PORTB_IE_B3_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B3_BITS_ENABLE (PORTCON_PORTB_IE_B3_VALUE_ENABLE << PORTCON_PORTB_IE_B3_SHIFT) #define PORTCON_PORTB_IE_B4_SHIFT 4 #define PORTCON_PORTB_IE_B4_WIDTH 1 #define PORTCON_PORTB_IE_B4_MASK (((1U << PORTCON_PORTB_IE_B4_WIDTH) - 1U) << PORTCON_PORTB_IE_B4_SHIFT) #define PORTCON_PORTB_IE_B4_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B4_BITS_DISABLE (PORTCON_PORTB_IE_B4_VALUE_DISABLE << PORTCON_PORTB_IE_B4_SHIFT) #define PORTCON_PORTB_IE_B4_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B4_BITS_ENABLE (PORTCON_PORTB_IE_B4_VALUE_ENABLE << PORTCON_PORTB_IE_B4_SHIFT) #define PORTCON_PORTB_IE_B5_SHIFT 5 #define PORTCON_PORTB_IE_B5_WIDTH 1 #define PORTCON_PORTB_IE_B5_MASK (((1U << PORTCON_PORTB_IE_B5_WIDTH) - 1U) << PORTCON_PORTB_IE_B5_SHIFT) #define PORTCON_PORTB_IE_B5_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B5_BITS_DISABLE (PORTCON_PORTB_IE_B5_VALUE_DISABLE << PORTCON_PORTB_IE_B5_SHIFT) #define PORTCON_PORTB_IE_B5_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B5_BITS_ENABLE (PORTCON_PORTB_IE_B5_VALUE_ENABLE << PORTCON_PORTB_IE_B5_SHIFT) #define PORTCON_PORTB_IE_B6_SHIFT 6 #define PORTCON_PORTB_IE_B6_WIDTH 1 #define PORTCON_PORTB_IE_B6_MASK (((1U << PORTCON_PORTB_IE_B6_WIDTH) - 1U) << PORTCON_PORTB_IE_B6_SHIFT) #define PORTCON_PORTB_IE_B6_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B6_BITS_DISABLE (PORTCON_PORTB_IE_B6_VALUE_DISABLE << PORTCON_PORTB_IE_B6_SHIFT) #define PORTCON_PORTB_IE_B6_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B6_BITS_ENABLE (PORTCON_PORTB_IE_B6_VALUE_ENABLE << PORTCON_PORTB_IE_B6_SHIFT) #define PORTCON_PORTB_IE_B7_SHIFT 7 #define PORTCON_PORTB_IE_B7_WIDTH 1 #define PORTCON_PORTB_IE_B7_MASK (((1U << PORTCON_PORTB_IE_B7_WIDTH) - 1U) << PORTCON_PORTB_IE_B7_SHIFT) #define PORTCON_PORTB_IE_B7_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B7_BITS_DISABLE (PORTCON_PORTB_IE_B7_VALUE_DISABLE << PORTCON_PORTB_IE_B7_SHIFT) #define PORTCON_PORTB_IE_B7_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B7_BITS_ENABLE (PORTCON_PORTB_IE_B7_VALUE_ENABLE << PORTCON_PORTB_IE_B7_SHIFT) #define PORTCON_PORTB_IE_B8_SHIFT 8 #define PORTCON_PORTB_IE_B8_WIDTH 1 #define PORTCON_PORTB_IE_B8_MASK (((1U << PORTCON_PORTB_IE_B8_WIDTH) - 1U) << PORTCON_PORTB_IE_B8_SHIFT) #define PORTCON_PORTB_IE_B8_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B8_BITS_DISABLE (PORTCON_PORTB_IE_B8_VALUE_DISABLE << PORTCON_PORTB_IE_B8_SHIFT) #define PORTCON_PORTB_IE_B8_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B8_BITS_ENABLE (PORTCON_PORTB_IE_B8_VALUE_ENABLE << PORTCON_PORTB_IE_B8_SHIFT) #define PORTCON_PORTB_IE_B9_SHIFT 9 #define PORTCON_PORTB_IE_B9_WIDTH 1 #define PORTCON_PORTB_IE_B9_MASK (((1U << PORTCON_PORTB_IE_B9_WIDTH) - 1U) << PORTCON_PORTB_IE_B9_SHIFT) #define PORTCON_PORTB_IE_B9_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B9_BITS_DISABLE (PORTCON_PORTB_IE_B9_VALUE_DISABLE << PORTCON_PORTB_IE_B9_SHIFT) #define PORTCON_PORTB_IE_B9_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B9_BITS_ENABLE (PORTCON_PORTB_IE_B9_VALUE_ENABLE << PORTCON_PORTB_IE_B9_SHIFT) #define PORTCON_PORTB_IE_B10_SHIFT 10 #define PORTCON_PORTB_IE_B10_WIDTH 1 #define PORTCON_PORTB_IE_B10_MASK (((1U << PORTCON_PORTB_IE_B10_WIDTH) - 1U) << PORTCON_PORTB_IE_B10_SHIFT) #define PORTCON_PORTB_IE_B10_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B10_BITS_DISABLE (PORTCON_PORTB_IE_B10_VALUE_DISABLE << PORTCON_PORTB_IE_B10_SHIFT) #define PORTCON_PORTB_IE_B10_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B10_BITS_ENABLE (PORTCON_PORTB_IE_B10_VALUE_ENABLE << PORTCON_PORTB_IE_B10_SHIFT) #define PORTCON_PORTB_IE_B11_SHIFT 11 #define PORTCON_PORTB_IE_B11_WIDTH 1 #define PORTCON_PORTB_IE_B11_MASK (((1U << PORTCON_PORTB_IE_B11_WIDTH) - 1U) << PORTCON_PORTB_IE_B11_SHIFT) #define PORTCON_PORTB_IE_B11_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B11_BITS_DISABLE (PORTCON_PORTB_IE_B11_VALUE_DISABLE << PORTCON_PORTB_IE_B11_SHIFT) #define PORTCON_PORTB_IE_B11_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B11_BITS_ENABLE (PORTCON_PORTB_IE_B11_VALUE_ENABLE << PORTCON_PORTB_IE_B11_SHIFT) #define PORTCON_PORTB_IE_B12_SHIFT 12 #define PORTCON_PORTB_IE_B12_WIDTH 1 #define PORTCON_PORTB_IE_B12_MASK (((1U << PORTCON_PORTB_IE_B12_WIDTH) - 1U) << PORTCON_PORTB_IE_B12_SHIFT) #define PORTCON_PORTB_IE_B12_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B12_BITS_DISABLE (PORTCON_PORTB_IE_B12_VALUE_DISABLE << PORTCON_PORTB_IE_B12_SHIFT) #define PORTCON_PORTB_IE_B12_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B12_BITS_ENABLE (PORTCON_PORTB_IE_B12_VALUE_ENABLE << PORTCON_PORTB_IE_B12_SHIFT) #define PORTCON_PORTB_IE_B13_SHIFT 13 #define PORTCON_PORTB_IE_B13_WIDTH 1 #define PORTCON_PORTB_IE_B13_MASK (((1U << PORTCON_PORTB_IE_B13_WIDTH) - 1U) << PORTCON_PORTB_IE_B13_SHIFT) #define PORTCON_PORTB_IE_B13_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B13_BITS_DISABLE (PORTCON_PORTB_IE_B13_VALUE_DISABLE << PORTCON_PORTB_IE_B13_SHIFT) #define PORTCON_PORTB_IE_B13_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B13_BITS_ENABLE (PORTCON_PORTB_IE_B13_VALUE_ENABLE << PORTCON_PORTB_IE_B13_SHIFT) #define PORTCON_PORTB_IE_B14_SHIFT 14 #define PORTCON_PORTB_IE_B14_WIDTH 1 #define PORTCON_PORTB_IE_B14_MASK (((1U << PORTCON_PORTB_IE_B14_WIDTH) - 1U) << PORTCON_PORTB_IE_B14_SHIFT) #define PORTCON_PORTB_IE_B14_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B14_BITS_DISABLE (PORTCON_PORTB_IE_B14_VALUE_DISABLE << PORTCON_PORTB_IE_B14_SHIFT) #define PORTCON_PORTB_IE_B14_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B14_BITS_ENABLE (PORTCON_PORTB_IE_B14_VALUE_ENABLE << PORTCON_PORTB_IE_B14_SHIFT) #define PORTCON_PORTB_IE_B15_SHIFT 15 #define PORTCON_PORTB_IE_B15_WIDTH 1 #define PORTCON_PORTB_IE_B15_MASK (((1U << PORTCON_PORTB_IE_B15_WIDTH) - 1U) << PORTCON_PORTB_IE_B15_SHIFT) #define PORTCON_PORTB_IE_B15_VALUE_DISABLE 0U #define PORTCON_PORTB_IE_B15_BITS_DISABLE (PORTCON_PORTB_IE_B15_VALUE_DISABLE << PORTCON_PORTB_IE_B15_SHIFT) #define PORTCON_PORTB_IE_B15_VALUE_ENABLE 1U #define PORTCON_PORTB_IE_B15_BITS_ENABLE (PORTCON_PORTB_IE_B15_VALUE_ENABLE << PORTCON_PORTB_IE_B15_SHIFT) #define PORTCON_PORTC_IE_ADDR (PORTCON_BASE_ADDR + 0x0108U) #define PORTCON_PORTC_IE (*(volatile uint32_t *)PORTCON_PORTC_IE_ADDR) #define PORTCON_PORTC_IE_C0_SHIFT 0 #define PORTCON_PORTC_IE_C0_WIDTH 1 #define PORTCON_PORTC_IE_C0_MASK (((1U << PORTCON_PORTC_IE_C0_WIDTH) - 1U) << PORTCON_PORTC_IE_C0_SHIFT) #define PORTCON_PORTC_IE_C0_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C0_BITS_DISABLE (PORTCON_PORTC_IE_C0_VALUE_DISABLE << PORTCON_PORTC_IE_C0_SHIFT) #define PORTCON_PORTC_IE_C0_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C0_BITS_ENABLE (PORTCON_PORTC_IE_C0_VALUE_ENABLE << PORTCON_PORTC_IE_C0_SHIFT) #define PORTCON_PORTC_IE_C1_SHIFT 1 #define PORTCON_PORTC_IE_C1_WIDTH 1 #define PORTCON_PORTC_IE_C1_MASK (((1U << PORTCON_PORTC_IE_C1_WIDTH) - 1U) << PORTCON_PORTC_IE_C1_SHIFT) #define PORTCON_PORTC_IE_C1_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C1_BITS_DISABLE (PORTCON_PORTC_IE_C1_VALUE_DISABLE << PORTCON_PORTC_IE_C1_SHIFT) #define PORTCON_PORTC_IE_C1_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C1_BITS_ENABLE (PORTCON_PORTC_IE_C1_VALUE_ENABLE << PORTCON_PORTC_IE_C1_SHIFT) #define PORTCON_PORTC_IE_C2_SHIFT 2 #define PORTCON_PORTC_IE_C2_WIDTH 1 #define PORTCON_PORTC_IE_C2_MASK (((1U << PORTCON_PORTC_IE_C2_WIDTH) - 1U) << PORTCON_PORTC_IE_C2_SHIFT) #define PORTCON_PORTC_IE_C2_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C2_BITS_DISABLE (PORTCON_PORTC_IE_C2_VALUE_DISABLE << PORTCON_PORTC_IE_C2_SHIFT) #define PORTCON_PORTC_IE_C2_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C2_BITS_ENABLE (PORTCON_PORTC_IE_C2_VALUE_ENABLE << PORTCON_PORTC_IE_C2_SHIFT) #define PORTCON_PORTC_IE_C3_SHIFT 3 #define PORTCON_PORTC_IE_C3_WIDTH 1 #define PORTCON_PORTC_IE_C3_MASK (((1U << PORTCON_PORTC_IE_C3_WIDTH) - 1U) << PORTCON_PORTC_IE_C3_SHIFT) #define PORTCON_PORTC_IE_C3_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C3_BITS_DISABLE (PORTCON_PORTC_IE_C3_VALUE_DISABLE << PORTCON_PORTC_IE_C3_SHIFT) #define PORTCON_PORTC_IE_C3_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C3_BITS_ENABLE (PORTCON_PORTC_IE_C3_VALUE_ENABLE << PORTCON_PORTC_IE_C3_SHIFT) #define PORTCON_PORTC_IE_C4_SHIFT 4 #define PORTCON_PORTC_IE_C4_WIDTH 1 #define PORTCON_PORTC_IE_C4_MASK (((1U << PORTCON_PORTC_IE_C4_WIDTH) - 1U) << PORTCON_PORTC_IE_C4_SHIFT) #define PORTCON_PORTC_IE_C4_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C4_BITS_DISABLE (PORTCON_PORTC_IE_C4_VALUE_DISABLE << PORTCON_PORTC_IE_C4_SHIFT) #define PORTCON_PORTC_IE_C4_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C4_BITS_ENABLE (PORTCON_PORTC_IE_C4_VALUE_ENABLE << PORTCON_PORTC_IE_C4_SHIFT) #define PORTCON_PORTC_IE_C5_SHIFT 5 #define PORTCON_PORTC_IE_C5_WIDTH 1 #define PORTCON_PORTC_IE_C5_MASK (((1U << PORTCON_PORTC_IE_C5_WIDTH) - 1U) << PORTCON_PORTC_IE_C5_SHIFT) #define PORTCON_PORTC_IE_C5_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C5_BITS_DISABLE (PORTCON_PORTC_IE_C5_VALUE_DISABLE << PORTCON_PORTC_IE_C5_SHIFT) #define PORTCON_PORTC_IE_C5_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C5_BITS_ENABLE (PORTCON_PORTC_IE_C5_VALUE_ENABLE << PORTCON_PORTC_IE_C5_SHIFT) #define PORTCON_PORTC_IE_C6_SHIFT 6 #define PORTCON_PORTC_IE_C6_WIDTH 1 #define PORTCON_PORTC_IE_C6_MASK (((1U << PORTCON_PORTC_IE_C6_WIDTH) - 1U) << PORTCON_PORTC_IE_C6_SHIFT) #define PORTCON_PORTC_IE_C6_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C6_BITS_DISABLE (PORTCON_PORTC_IE_C6_VALUE_DISABLE << PORTCON_PORTC_IE_C6_SHIFT) #define PORTCON_PORTC_IE_C6_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C6_BITS_ENABLE (PORTCON_PORTC_IE_C6_VALUE_ENABLE << PORTCON_PORTC_IE_C6_SHIFT) #define PORTCON_PORTC_IE_C7_SHIFT 7 #define PORTCON_PORTC_IE_C7_WIDTH 1 #define PORTCON_PORTC_IE_C7_MASK (((1U << PORTCON_PORTC_IE_C7_WIDTH) - 1U) << PORTCON_PORTC_IE_C7_SHIFT) #define PORTCON_PORTC_IE_C7_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C7_BITS_DISABLE (PORTCON_PORTC_IE_C7_VALUE_DISABLE << PORTCON_PORTC_IE_C7_SHIFT) #define PORTCON_PORTC_IE_C7_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C7_BITS_ENABLE (PORTCON_PORTC_IE_C7_VALUE_ENABLE << PORTCON_PORTC_IE_C7_SHIFT) #define PORTCON_PORTC_IE_C8_SHIFT 8 #define PORTCON_PORTC_IE_C8_WIDTH 1 #define PORTCON_PORTC_IE_C8_MASK (((1U << PORTCON_PORTC_IE_C8_WIDTH) - 1U) << PORTCON_PORTC_IE_C8_SHIFT) #define PORTCON_PORTC_IE_C8_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C8_BITS_DISABLE (PORTCON_PORTC_IE_C8_VALUE_DISABLE << PORTCON_PORTC_IE_C8_SHIFT) #define PORTCON_PORTC_IE_C8_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C8_BITS_ENABLE (PORTCON_PORTC_IE_C8_VALUE_ENABLE << PORTCON_PORTC_IE_C8_SHIFT) #define PORTCON_PORTC_IE_C9_SHIFT 9 #define PORTCON_PORTC_IE_C9_WIDTH 1 #define PORTCON_PORTC_IE_C9_MASK (((1U << PORTCON_PORTC_IE_C9_WIDTH) - 1U) << PORTCON_PORTC_IE_C9_SHIFT) #define PORTCON_PORTC_IE_C9_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C9_BITS_DISABLE (PORTCON_PORTC_IE_C9_VALUE_DISABLE << PORTCON_PORTC_IE_C9_SHIFT) #define PORTCON_PORTC_IE_C9_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C9_BITS_ENABLE (PORTCON_PORTC_IE_C9_VALUE_ENABLE << PORTCON_PORTC_IE_C9_SHIFT) #define PORTCON_PORTC_IE_C10_SHIFT 10 #define PORTCON_PORTC_IE_C10_WIDTH 1 #define PORTCON_PORTC_IE_C10_MASK (((1U << PORTCON_PORTC_IE_C10_WIDTH) - 1U) << PORTCON_PORTC_IE_C10_SHIFT) #define PORTCON_PORTC_IE_C10_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C10_BITS_DISABLE (PORTCON_PORTC_IE_C10_VALUE_DISABLE << PORTCON_PORTC_IE_C10_SHIFT) #define PORTCON_PORTC_IE_C10_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C10_BITS_ENABLE (PORTCON_PORTC_IE_C10_VALUE_ENABLE << PORTCON_PORTC_IE_C10_SHIFT) #define PORTCON_PORTC_IE_C11_SHIFT 11 #define PORTCON_PORTC_IE_C11_WIDTH 1 #define PORTCON_PORTC_IE_C11_MASK (((1U << PORTCON_PORTC_IE_C11_WIDTH) - 1U) << PORTCON_PORTC_IE_C11_SHIFT) #define PORTCON_PORTC_IE_C11_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C11_BITS_DISABLE (PORTCON_PORTC_IE_C11_VALUE_DISABLE << PORTCON_PORTC_IE_C11_SHIFT) #define PORTCON_PORTC_IE_C11_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C11_BITS_ENABLE (PORTCON_PORTC_IE_C11_VALUE_ENABLE << PORTCON_PORTC_IE_C11_SHIFT) #define PORTCON_PORTC_IE_C12_SHIFT 12 #define PORTCON_PORTC_IE_C12_WIDTH 1 #define PORTCON_PORTC_IE_C12_MASK (((1U << PORTCON_PORTC_IE_C12_WIDTH) - 1U) << PORTCON_PORTC_IE_C12_SHIFT) #define PORTCON_PORTC_IE_C12_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C12_BITS_DISABLE (PORTCON_PORTC_IE_C12_VALUE_DISABLE << PORTCON_PORTC_IE_C12_SHIFT) #define PORTCON_PORTC_IE_C12_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C12_BITS_ENABLE (PORTCON_PORTC_IE_C12_VALUE_ENABLE << PORTCON_PORTC_IE_C12_SHIFT) #define PORTCON_PORTC_IE_C13_SHIFT 13 #define PORTCON_PORTC_IE_C13_WIDTH 1 #define PORTCON_PORTC_IE_C13_MASK (((1U << PORTCON_PORTC_IE_C13_WIDTH) - 1U) << PORTCON_PORTC_IE_C13_SHIFT) #define PORTCON_PORTC_IE_C13_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C13_BITS_DISABLE (PORTCON_PORTC_IE_C13_VALUE_DISABLE << PORTCON_PORTC_IE_C13_SHIFT) #define PORTCON_PORTC_IE_C13_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C13_BITS_ENABLE (PORTCON_PORTC_IE_C13_VALUE_ENABLE << PORTCON_PORTC_IE_C13_SHIFT) #define PORTCON_PORTC_IE_C14_SHIFT 14 #define PORTCON_PORTC_IE_C14_WIDTH 1 #define PORTCON_PORTC_IE_C14_MASK (((1U << PORTCON_PORTC_IE_C14_WIDTH) - 1U) << PORTCON_PORTC_IE_C14_SHIFT) #define PORTCON_PORTC_IE_C14_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C14_BITS_DISABLE (PORTCON_PORTC_IE_C14_VALUE_DISABLE << PORTCON_PORTC_IE_C14_SHIFT) #define PORTCON_PORTC_IE_C14_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C14_BITS_ENABLE (PORTCON_PORTC_IE_C14_VALUE_ENABLE << PORTCON_PORTC_IE_C14_SHIFT) #define PORTCON_PORTC_IE_C15_SHIFT 15 #define PORTCON_PORTC_IE_C15_WIDTH 1 #define PORTCON_PORTC_IE_C15_MASK (((1U << PORTCON_PORTC_IE_C15_WIDTH) - 1U) << PORTCON_PORTC_IE_C15_SHIFT) #define PORTCON_PORTC_IE_C15_VALUE_DISABLE 0U #define PORTCON_PORTC_IE_C15_BITS_DISABLE (PORTCON_PORTC_IE_C15_VALUE_DISABLE << PORTCON_PORTC_IE_C15_SHIFT) #define PORTCON_PORTC_IE_C15_VALUE_ENABLE 1U #define PORTCON_PORTC_IE_C15_BITS_ENABLE (PORTCON_PORTC_IE_C15_VALUE_ENABLE << PORTCON_PORTC_IE_C15_SHIFT) #define PORTCON_PORTA_PU_ADDR (PORTCON_BASE_ADDR + 0x0200U) #define PORTCON_PORTA_PU (*(volatile uint32_t *)PORTCON_PORTA_PU_ADDR) #define PORTCON_PORTA_PU_A0_SHIFT 0 #define PORTCON_PORTA_PU_A0_WIDTH 1 #define PORTCON_PORTA_PU_A0_MASK (((1U << PORTCON_PORTA_PU_A0_WIDTH) - 1U) << PORTCON_PORTA_PU_A0_SHIFT) #define PORTCON_PORTA_PU_A0_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A0_BITS_DISABLE (PORTCON_PORTA_PU_A0_VALUE_DISABLE << PORTCON_PORTA_PU_A0_SHIFT) #define PORTCON_PORTA_PU_A0_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A0_BITS_ENABLE (PORTCON_PORTA_PU_A0_VALUE_ENABLE << PORTCON_PORTA_PU_A0_SHIFT) #define PORTCON_PORTA_PU_A1_SHIFT 1 #define PORTCON_PORTA_PU_A1_WIDTH 1 #define PORTCON_PORTA_PU_A1_MASK (((1U << PORTCON_PORTA_PU_A1_WIDTH) - 1U) << PORTCON_PORTA_PU_A1_SHIFT) #define PORTCON_PORTA_PU_A1_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A1_BITS_DISABLE (PORTCON_PORTA_PU_A1_VALUE_DISABLE << PORTCON_PORTA_PU_A1_SHIFT) #define PORTCON_PORTA_PU_A1_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A1_BITS_ENABLE (PORTCON_PORTA_PU_A1_VALUE_ENABLE << PORTCON_PORTA_PU_A1_SHIFT) #define PORTCON_PORTA_PU_A2_SHIFT 2 #define PORTCON_PORTA_PU_A2_WIDTH 1 #define PORTCON_PORTA_PU_A2_MASK (((1U << PORTCON_PORTA_PU_A2_WIDTH) - 1U) << PORTCON_PORTA_PU_A2_SHIFT) #define PORTCON_PORTA_PU_A2_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A2_BITS_DISABLE (PORTCON_PORTA_PU_A2_VALUE_DISABLE << PORTCON_PORTA_PU_A2_SHIFT) #define PORTCON_PORTA_PU_A2_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A2_BITS_ENABLE (PORTCON_PORTA_PU_A2_VALUE_ENABLE << PORTCON_PORTA_PU_A2_SHIFT) #define PORTCON_PORTA_PU_A3_SHIFT 3 #define PORTCON_PORTA_PU_A3_WIDTH 1 #define PORTCON_PORTA_PU_A3_MASK (((1U << PORTCON_PORTA_PU_A3_WIDTH) - 1U) << PORTCON_PORTA_PU_A3_SHIFT) #define PORTCON_PORTA_PU_A3_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A3_BITS_DISABLE (PORTCON_PORTA_PU_A3_VALUE_DISABLE << PORTCON_PORTA_PU_A3_SHIFT) #define PORTCON_PORTA_PU_A3_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A3_BITS_ENABLE (PORTCON_PORTA_PU_A3_VALUE_ENABLE << PORTCON_PORTA_PU_A3_SHIFT) #define PORTCON_PORTA_PU_A4_SHIFT 4 #define PORTCON_PORTA_PU_A4_WIDTH 1 #define PORTCON_PORTA_PU_A4_MASK (((1U << PORTCON_PORTA_PU_A4_WIDTH) - 1U) << PORTCON_PORTA_PU_A4_SHIFT) #define PORTCON_PORTA_PU_A4_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A4_BITS_DISABLE (PORTCON_PORTA_PU_A4_VALUE_DISABLE << PORTCON_PORTA_PU_A4_SHIFT) #define PORTCON_PORTA_PU_A4_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A4_BITS_ENABLE (PORTCON_PORTA_PU_A4_VALUE_ENABLE << PORTCON_PORTA_PU_A4_SHIFT) #define PORTCON_PORTA_PU_A5_SHIFT 5 #define PORTCON_PORTA_PU_A5_WIDTH 1 #define PORTCON_PORTA_PU_A5_MASK (((1U << PORTCON_PORTA_PU_A5_WIDTH) - 1U) << PORTCON_PORTA_PU_A5_SHIFT) #define PORTCON_PORTA_PU_A5_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A5_BITS_DISABLE (PORTCON_PORTA_PU_A5_VALUE_DISABLE << PORTCON_PORTA_PU_A5_SHIFT) #define PORTCON_PORTA_PU_A5_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A5_BITS_ENABLE (PORTCON_PORTA_PU_A5_VALUE_ENABLE << PORTCON_PORTA_PU_A5_SHIFT) #define PORTCON_PORTA_PU_A6_SHIFT 6 #define PORTCON_PORTA_PU_A6_WIDTH 1 #define PORTCON_PORTA_PU_A6_MASK (((1U << PORTCON_PORTA_PU_A6_WIDTH) - 1U) << PORTCON_PORTA_PU_A6_SHIFT) #define PORTCON_PORTA_PU_A6_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A6_BITS_DISABLE (PORTCON_PORTA_PU_A6_VALUE_DISABLE << PORTCON_PORTA_PU_A6_SHIFT) #define PORTCON_PORTA_PU_A6_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A6_BITS_ENABLE (PORTCON_PORTA_PU_A6_VALUE_ENABLE << PORTCON_PORTA_PU_A6_SHIFT) #define PORTCON_PORTA_PU_A7_SHIFT 7 #define PORTCON_PORTA_PU_A7_WIDTH 1 #define PORTCON_PORTA_PU_A7_MASK (((1U << PORTCON_PORTA_PU_A7_WIDTH) - 1U) << PORTCON_PORTA_PU_A7_SHIFT) #define PORTCON_PORTA_PU_A7_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A7_BITS_DISABLE (PORTCON_PORTA_PU_A7_VALUE_DISABLE << PORTCON_PORTA_PU_A7_SHIFT) #define PORTCON_PORTA_PU_A7_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A7_BITS_ENABLE (PORTCON_PORTA_PU_A7_VALUE_ENABLE << PORTCON_PORTA_PU_A7_SHIFT) #define PORTCON_PORTA_PU_A8_SHIFT 8 #define PORTCON_PORTA_PU_A8_WIDTH 1 #define PORTCON_PORTA_PU_A8_MASK (((1U << PORTCON_PORTA_PU_A8_WIDTH) - 1U) << PORTCON_PORTA_PU_A8_SHIFT) #define PORTCON_PORTA_PU_A8_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A8_BITS_DISABLE (PORTCON_PORTA_PU_A8_VALUE_DISABLE << PORTCON_PORTA_PU_A8_SHIFT) #define PORTCON_PORTA_PU_A8_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A8_BITS_ENABLE (PORTCON_PORTA_PU_A8_VALUE_ENABLE << PORTCON_PORTA_PU_A8_SHIFT) #define PORTCON_PORTA_PU_A9_SHIFT 9 #define PORTCON_PORTA_PU_A9_WIDTH 1 #define PORTCON_PORTA_PU_A9_MASK (((1U << PORTCON_PORTA_PU_A9_WIDTH) - 1U) << PORTCON_PORTA_PU_A9_SHIFT) #define PORTCON_PORTA_PU_A9_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A9_BITS_DISABLE (PORTCON_PORTA_PU_A9_VALUE_DISABLE << PORTCON_PORTA_PU_A9_SHIFT) #define PORTCON_PORTA_PU_A9_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A9_BITS_ENABLE (PORTCON_PORTA_PU_A9_VALUE_ENABLE << PORTCON_PORTA_PU_A9_SHIFT) #define PORTCON_PORTA_PU_A10_SHIFT 10 #define PORTCON_PORTA_PU_A10_WIDTH 1 #define PORTCON_PORTA_PU_A10_MASK (((1U << PORTCON_PORTA_PU_A10_WIDTH) - 1U) << PORTCON_PORTA_PU_A10_SHIFT) #define PORTCON_PORTA_PU_A10_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A10_BITS_DISABLE (PORTCON_PORTA_PU_A10_VALUE_DISABLE << PORTCON_PORTA_PU_A10_SHIFT) #define PORTCON_PORTA_PU_A10_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A10_BITS_ENABLE (PORTCON_PORTA_PU_A10_VALUE_ENABLE << PORTCON_PORTA_PU_A10_SHIFT) #define PORTCON_PORTA_PU_A11_SHIFT 11 #define PORTCON_PORTA_PU_A11_WIDTH 1 #define PORTCON_PORTA_PU_A11_MASK (((1U << PORTCON_PORTA_PU_A11_WIDTH) - 1U) << PORTCON_PORTA_PU_A11_SHIFT) #define PORTCON_PORTA_PU_A11_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A11_BITS_DISABLE (PORTCON_PORTA_PU_A11_VALUE_DISABLE << PORTCON_PORTA_PU_A11_SHIFT) #define PORTCON_PORTA_PU_A11_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A11_BITS_ENABLE (PORTCON_PORTA_PU_A11_VALUE_ENABLE << PORTCON_PORTA_PU_A11_SHIFT) #define PORTCON_PORTA_PU_A12_SHIFT 12 #define PORTCON_PORTA_PU_A12_WIDTH 1 #define PORTCON_PORTA_PU_A12_MASK (((1U << PORTCON_PORTA_PU_A12_WIDTH) - 1U) << PORTCON_PORTA_PU_A12_SHIFT) #define PORTCON_PORTA_PU_A12_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A12_BITS_DISABLE (PORTCON_PORTA_PU_A12_VALUE_DISABLE << PORTCON_PORTA_PU_A12_SHIFT) #define PORTCON_PORTA_PU_A12_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A12_BITS_ENABLE (PORTCON_PORTA_PU_A12_VALUE_ENABLE << PORTCON_PORTA_PU_A12_SHIFT) #define PORTCON_PORTA_PU_A13_SHIFT 13 #define PORTCON_PORTA_PU_A13_WIDTH 1 #define PORTCON_PORTA_PU_A13_MASK (((1U << PORTCON_PORTA_PU_A13_WIDTH) - 1U) << PORTCON_PORTA_PU_A13_SHIFT) #define PORTCON_PORTA_PU_A13_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A13_BITS_DISABLE (PORTCON_PORTA_PU_A13_VALUE_DISABLE << PORTCON_PORTA_PU_A13_SHIFT) #define PORTCON_PORTA_PU_A13_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A13_BITS_ENABLE (PORTCON_PORTA_PU_A13_VALUE_ENABLE << PORTCON_PORTA_PU_A13_SHIFT) #define PORTCON_PORTA_PU_A14_SHIFT 14 #define PORTCON_PORTA_PU_A14_WIDTH 1 #define PORTCON_PORTA_PU_A14_MASK (((1U << PORTCON_PORTA_PU_A14_WIDTH) - 1U) << PORTCON_PORTA_PU_A14_SHIFT) #define PORTCON_PORTA_PU_A14_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A14_BITS_DISABLE (PORTCON_PORTA_PU_A14_VALUE_DISABLE << PORTCON_PORTA_PU_A14_SHIFT) #define PORTCON_PORTA_PU_A14_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A14_BITS_ENABLE (PORTCON_PORTA_PU_A14_VALUE_ENABLE << PORTCON_PORTA_PU_A14_SHIFT) #define PORTCON_PORTA_PU_A15_SHIFT 15 #define PORTCON_PORTA_PU_A15_WIDTH 1 #define PORTCON_PORTA_PU_A15_MASK (((1U << PORTCON_PORTA_PU_A15_WIDTH) - 1U) << PORTCON_PORTA_PU_A15_SHIFT) #define PORTCON_PORTA_PU_A15_VALUE_DISABLE 0U #define PORTCON_PORTA_PU_A15_BITS_DISABLE (PORTCON_PORTA_PU_A15_VALUE_DISABLE << PORTCON_PORTA_PU_A15_SHIFT) #define PORTCON_PORTA_PU_A15_VALUE_ENABLE 1U #define PORTCON_PORTA_PU_A15_BITS_ENABLE (PORTCON_PORTA_PU_A15_VALUE_ENABLE << PORTCON_PORTA_PU_A15_SHIFT) #define PORTCON_PORTB_PU_ADDR (PORTCON_BASE_ADDR + 0x0204U) #define PORTCON_PORTB_PU (*(volatile uint32_t *)PORTCON_PORTB_PU_ADDR) #define PORTCON_PORTB_PU_B0_SHIFT 0 #define PORTCON_PORTB_PU_B0_WIDTH 1 #define PORTCON_PORTB_PU_B0_MASK (((1U << PORTCON_PORTB_PU_B0_WIDTH) - 1U) << PORTCON_PORTB_PU_B0_SHIFT) #define PORTCON_PORTB_PU_B0_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B0_BITS_DISABLE (PORTCON_PORTB_PU_B0_VALUE_DISABLE << PORTCON_PORTB_PU_B0_SHIFT) #define PORTCON_PORTB_PU_B0_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B0_BITS_ENABLE (PORTCON_PORTB_PU_B0_VALUE_ENABLE << PORTCON_PORTB_PU_B0_SHIFT) #define PORTCON_PORTB_PU_B1_SHIFT 1 #define PORTCON_PORTB_PU_B1_WIDTH 1 #define PORTCON_PORTB_PU_B1_MASK (((1U << PORTCON_PORTB_PU_B1_WIDTH) - 1U) << PORTCON_PORTB_PU_B1_SHIFT) #define PORTCON_PORTB_PU_B1_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B1_BITS_DISABLE (PORTCON_PORTB_PU_B1_VALUE_DISABLE << PORTCON_PORTB_PU_B1_SHIFT) #define PORTCON_PORTB_PU_B1_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B1_BITS_ENABLE (PORTCON_PORTB_PU_B1_VALUE_ENABLE << PORTCON_PORTB_PU_B1_SHIFT) #define PORTCON_PORTB_PU_B2_SHIFT 2 #define PORTCON_PORTB_PU_B2_WIDTH 1 #define PORTCON_PORTB_PU_B2_MASK (((1U << PORTCON_PORTB_PU_B2_WIDTH) - 1U) << PORTCON_PORTB_PU_B2_SHIFT) #define PORTCON_PORTB_PU_B2_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B2_BITS_DISABLE (PORTCON_PORTB_PU_B2_VALUE_DISABLE << PORTCON_PORTB_PU_B2_SHIFT) #define PORTCON_PORTB_PU_B2_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B2_BITS_ENABLE (PORTCON_PORTB_PU_B2_VALUE_ENABLE << PORTCON_PORTB_PU_B2_SHIFT) #define PORTCON_PORTB_PU_B3_SHIFT 3 #define PORTCON_PORTB_PU_B3_WIDTH 1 #define PORTCON_PORTB_PU_B3_MASK (((1U << PORTCON_PORTB_PU_B3_WIDTH) - 1U) << PORTCON_PORTB_PU_B3_SHIFT) #define PORTCON_PORTB_PU_B3_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B3_BITS_DISABLE (PORTCON_PORTB_PU_B3_VALUE_DISABLE << PORTCON_PORTB_PU_B3_SHIFT) #define PORTCON_PORTB_PU_B3_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B3_BITS_ENABLE (PORTCON_PORTB_PU_B3_VALUE_ENABLE << PORTCON_PORTB_PU_B3_SHIFT) #define PORTCON_PORTB_PU_B4_SHIFT 4 #define PORTCON_PORTB_PU_B4_WIDTH 1 #define PORTCON_PORTB_PU_B4_MASK (((1U << PORTCON_PORTB_PU_B4_WIDTH) - 1U) << PORTCON_PORTB_PU_B4_SHIFT) #define PORTCON_PORTB_PU_B4_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B4_BITS_DISABLE (PORTCON_PORTB_PU_B4_VALUE_DISABLE << PORTCON_PORTB_PU_B4_SHIFT) #define PORTCON_PORTB_PU_B4_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B4_BITS_ENABLE (PORTCON_PORTB_PU_B4_VALUE_ENABLE << PORTCON_PORTB_PU_B4_SHIFT) #define PORTCON_PORTB_PU_B5_SHIFT 5 #define PORTCON_PORTB_PU_B5_WIDTH 1 #define PORTCON_PORTB_PU_B5_MASK (((1U << PORTCON_PORTB_PU_B5_WIDTH) - 1U) << PORTCON_PORTB_PU_B5_SHIFT) #define PORTCON_PORTB_PU_B5_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B5_BITS_DISABLE (PORTCON_PORTB_PU_B5_VALUE_DISABLE << PORTCON_PORTB_PU_B5_SHIFT) #define PORTCON_PORTB_PU_B5_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B5_BITS_ENABLE (PORTCON_PORTB_PU_B5_VALUE_ENABLE << PORTCON_PORTB_PU_B5_SHIFT) #define PORTCON_PORTB_PU_B6_SHIFT 6 #define PORTCON_PORTB_PU_B6_WIDTH 1 #define PORTCON_PORTB_PU_B6_MASK (((1U << PORTCON_PORTB_PU_B6_WIDTH) - 1U) << PORTCON_PORTB_PU_B6_SHIFT) #define PORTCON_PORTB_PU_B6_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B6_BITS_DISABLE (PORTCON_PORTB_PU_B6_VALUE_DISABLE << PORTCON_PORTB_PU_B6_SHIFT) #define PORTCON_PORTB_PU_B6_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B6_BITS_ENABLE (PORTCON_PORTB_PU_B6_VALUE_ENABLE << PORTCON_PORTB_PU_B6_SHIFT) #define PORTCON_PORTB_PU_B7_SHIFT 7 #define PORTCON_PORTB_PU_B7_WIDTH 1 #define PORTCON_PORTB_PU_B7_MASK (((1U << PORTCON_PORTB_PU_B7_WIDTH) - 1U) << PORTCON_PORTB_PU_B7_SHIFT) #define PORTCON_PORTB_PU_B7_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B7_BITS_DISABLE (PORTCON_PORTB_PU_B7_VALUE_DISABLE << PORTCON_PORTB_PU_B7_SHIFT) #define PORTCON_PORTB_PU_B7_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B7_BITS_ENABLE (PORTCON_PORTB_PU_B7_VALUE_ENABLE << PORTCON_PORTB_PU_B7_SHIFT) #define PORTCON_PORTB_PU_B8_SHIFT 8 #define PORTCON_PORTB_PU_B8_WIDTH 1 #define PORTCON_PORTB_PU_B8_MASK (((1U << PORTCON_PORTB_PU_B8_WIDTH) - 1U) << PORTCON_PORTB_PU_B8_SHIFT) #define PORTCON_PORTB_PU_B8_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B8_BITS_DISABLE (PORTCON_PORTB_PU_B8_VALUE_DISABLE << PORTCON_PORTB_PU_B8_SHIFT) #define PORTCON_PORTB_PU_B8_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B8_BITS_ENABLE (PORTCON_PORTB_PU_B8_VALUE_ENABLE << PORTCON_PORTB_PU_B8_SHIFT) #define PORTCON_PORTB_PU_B9_SHIFT 9 #define PORTCON_PORTB_PU_B9_WIDTH 1 #define PORTCON_PORTB_PU_B9_MASK (((1U << PORTCON_PORTB_PU_B9_WIDTH) - 1U) << PORTCON_PORTB_PU_B9_SHIFT) #define PORTCON_PORTB_PU_B9_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B9_BITS_DISABLE (PORTCON_PORTB_PU_B9_VALUE_DISABLE << PORTCON_PORTB_PU_B9_SHIFT) #define PORTCON_PORTB_PU_B9_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B9_BITS_ENABLE (PORTCON_PORTB_PU_B9_VALUE_ENABLE << PORTCON_PORTB_PU_B9_SHIFT) #define PORTCON_PORTB_PU_B10_SHIFT 10 #define PORTCON_PORTB_PU_B10_WIDTH 1 #define PORTCON_PORTB_PU_B10_MASK (((1U << PORTCON_PORTB_PU_B10_WIDTH) - 1U) << PORTCON_PORTB_PU_B10_SHIFT) #define PORTCON_PORTB_PU_B10_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B10_BITS_DISABLE (PORTCON_PORTB_PU_B10_VALUE_DISABLE << PORTCON_PORTB_PU_B10_SHIFT) #define PORTCON_PORTB_PU_B10_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B10_BITS_ENABLE (PORTCON_PORTB_PU_B10_VALUE_ENABLE << PORTCON_PORTB_PU_B10_SHIFT) #define PORTCON_PORTB_PU_B11_SHIFT 11 #define PORTCON_PORTB_PU_B11_WIDTH 1 #define PORTCON_PORTB_PU_B11_MASK (((1U << PORTCON_PORTB_PU_B11_WIDTH) - 1U) << PORTCON_PORTB_PU_B11_SHIFT) #define PORTCON_PORTB_PU_B11_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B11_BITS_DISABLE (PORTCON_PORTB_PU_B11_VALUE_DISABLE << PORTCON_PORTB_PU_B11_SHIFT) #define PORTCON_PORTB_PU_B11_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B11_BITS_ENABLE (PORTCON_PORTB_PU_B11_VALUE_ENABLE << PORTCON_PORTB_PU_B11_SHIFT) #define PORTCON_PORTB_PU_B12_SHIFT 12 #define PORTCON_PORTB_PU_B12_WIDTH 1 #define PORTCON_PORTB_PU_B12_MASK (((1U << PORTCON_PORTB_PU_B12_WIDTH) - 1U) << PORTCON_PORTB_PU_B12_SHIFT) #define PORTCON_PORTB_PU_B12_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B12_BITS_DISABLE (PORTCON_PORTB_PU_B12_VALUE_DISABLE << PORTCON_PORTB_PU_B12_SHIFT) #define PORTCON_PORTB_PU_B12_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B12_BITS_ENABLE (PORTCON_PORTB_PU_B12_VALUE_ENABLE << PORTCON_PORTB_PU_B12_SHIFT) #define PORTCON_PORTB_PU_B13_SHIFT 13 #define PORTCON_PORTB_PU_B13_WIDTH 1 #define PORTCON_PORTB_PU_B13_MASK (((1U << PORTCON_PORTB_PU_B13_WIDTH) - 1U) << PORTCON_PORTB_PU_B13_SHIFT) #define PORTCON_PORTB_PU_B13_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B13_BITS_DISABLE (PORTCON_PORTB_PU_B13_VALUE_DISABLE << PORTCON_PORTB_PU_B13_SHIFT) #define PORTCON_PORTB_PU_B13_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B13_BITS_ENABLE (PORTCON_PORTB_PU_B13_VALUE_ENABLE << PORTCON_PORTB_PU_B13_SHIFT) #define PORTCON_PORTB_PU_B14_SHIFT 14 #define PORTCON_PORTB_PU_B14_WIDTH 1 #define PORTCON_PORTB_PU_B14_MASK (((1U << PORTCON_PORTB_PU_B14_WIDTH) - 1U) << PORTCON_PORTB_PU_B14_SHIFT) #define PORTCON_PORTB_PU_B14_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B14_BITS_DISABLE (PORTCON_PORTB_PU_B14_VALUE_DISABLE << PORTCON_PORTB_PU_B14_SHIFT) #define PORTCON_PORTB_PU_B14_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B14_BITS_ENABLE (PORTCON_PORTB_PU_B14_VALUE_ENABLE << PORTCON_PORTB_PU_B14_SHIFT) #define PORTCON_PORTB_PU_B15_SHIFT 15 #define PORTCON_PORTB_PU_B15_WIDTH 1 #define PORTCON_PORTB_PU_B15_MASK (((1U << PORTCON_PORTB_PU_B15_WIDTH) - 1U) << PORTCON_PORTB_PU_B15_SHIFT) #define PORTCON_PORTB_PU_B15_VALUE_DISABLE 0U #define PORTCON_PORTB_PU_B15_BITS_DISABLE (PORTCON_PORTB_PU_B15_VALUE_DISABLE << PORTCON_PORTB_PU_B15_SHIFT) #define PORTCON_PORTB_PU_B15_VALUE_ENABLE 1U #define PORTCON_PORTB_PU_B15_BITS_ENABLE (PORTCON_PORTB_PU_B15_VALUE_ENABLE << PORTCON_PORTB_PU_B15_SHIFT) #define PORTCON_PORTC_PU_ADDR (PORTCON_BASE_ADDR + 0x0208U) #define PORTCON_PORTC_PU (*(volatile uint32_t *)PORTCON_PORTC_PU_ADDR) #define PORTCON_PORTC_PU_C0_SHIFT 0 #define PORTCON_PORTC_PU_C0_WIDTH 1 #define PORTCON_PORTC_PU_C0_MASK (((1U << PORTCON_PORTC_PU_C0_WIDTH) - 1U) << PORTCON_PORTC_PU_C0_SHIFT) #define PORTCON_PORTC_PU_C0_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C0_BITS_DISABLE (PORTCON_PORTC_PU_C0_VALUE_DISABLE << PORTCON_PORTC_PU_C0_SHIFT) #define PORTCON_PORTC_PU_C0_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C0_BITS_ENABLE (PORTCON_PORTC_PU_C0_VALUE_ENABLE << PORTCON_PORTC_PU_C0_SHIFT) #define PORTCON_PORTC_PU_C1_SHIFT 1 #define PORTCON_PORTC_PU_C1_WIDTH 1 #define PORTCON_PORTC_PU_C1_MASK (((1U << PORTCON_PORTC_PU_C1_WIDTH) - 1U) << PORTCON_PORTC_PU_C1_SHIFT) #define PORTCON_PORTC_PU_C1_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C1_BITS_DISABLE (PORTCON_PORTC_PU_C1_VALUE_DISABLE << PORTCON_PORTC_PU_C1_SHIFT) #define PORTCON_PORTC_PU_C1_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C1_BITS_ENABLE (PORTCON_PORTC_PU_C1_VALUE_ENABLE << PORTCON_PORTC_PU_C1_SHIFT) #define PORTCON_PORTC_PU_C2_SHIFT 2 #define PORTCON_PORTC_PU_C2_WIDTH 1 #define PORTCON_PORTC_PU_C2_MASK (((1U << PORTCON_PORTC_PU_C2_WIDTH) - 1U) << PORTCON_PORTC_PU_C2_SHIFT) #define PORTCON_PORTC_PU_C2_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C2_BITS_DISABLE (PORTCON_PORTC_PU_C2_VALUE_DISABLE << PORTCON_PORTC_PU_C2_SHIFT) #define PORTCON_PORTC_PU_C2_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C2_BITS_ENABLE (PORTCON_PORTC_PU_C2_VALUE_ENABLE << PORTCON_PORTC_PU_C2_SHIFT) #define PORTCON_PORTC_PU_C3_SHIFT 3 #define PORTCON_PORTC_PU_C3_WIDTH 1 #define PORTCON_PORTC_PU_C3_MASK (((1U << PORTCON_PORTC_PU_C3_WIDTH) - 1U) << PORTCON_PORTC_PU_C3_SHIFT) #define PORTCON_PORTC_PU_C3_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C3_BITS_DISABLE (PORTCON_PORTC_PU_C3_VALUE_DISABLE << PORTCON_PORTC_PU_C3_SHIFT) #define PORTCON_PORTC_PU_C3_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C3_BITS_ENABLE (PORTCON_PORTC_PU_C3_VALUE_ENABLE << PORTCON_PORTC_PU_C3_SHIFT) #define PORTCON_PORTC_PU_C4_SHIFT 4 #define PORTCON_PORTC_PU_C4_WIDTH 1 #define PORTCON_PORTC_PU_C4_MASK (((1U << PORTCON_PORTC_PU_C4_WIDTH) - 1U) << PORTCON_PORTC_PU_C4_SHIFT) #define PORTCON_PORTC_PU_C4_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C4_BITS_DISABLE (PORTCON_PORTC_PU_C4_VALUE_DISABLE << PORTCON_PORTC_PU_C4_SHIFT) #define PORTCON_PORTC_PU_C4_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C4_BITS_ENABLE (PORTCON_PORTC_PU_C4_VALUE_ENABLE << PORTCON_PORTC_PU_C4_SHIFT) #define PORTCON_PORTC_PU_C5_SHIFT 5 #define PORTCON_PORTC_PU_C5_WIDTH 1 #define PORTCON_PORTC_PU_C5_MASK (((1U << PORTCON_PORTC_PU_C5_WIDTH) - 1U) << PORTCON_PORTC_PU_C5_SHIFT) #define PORTCON_PORTC_PU_C5_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C5_BITS_DISABLE (PORTCON_PORTC_PU_C5_VALUE_DISABLE << PORTCON_PORTC_PU_C5_SHIFT) #define PORTCON_PORTC_PU_C5_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C5_BITS_ENABLE (PORTCON_PORTC_PU_C5_VALUE_ENABLE << PORTCON_PORTC_PU_C5_SHIFT) #define PORTCON_PORTC_PU_C6_SHIFT 6 #define PORTCON_PORTC_PU_C6_WIDTH 1 #define PORTCON_PORTC_PU_C6_MASK (((1U << PORTCON_PORTC_PU_C6_WIDTH) - 1U) << PORTCON_PORTC_PU_C6_SHIFT) #define PORTCON_PORTC_PU_C6_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C6_BITS_DISABLE (PORTCON_PORTC_PU_C6_VALUE_DISABLE << PORTCON_PORTC_PU_C6_SHIFT) #define PORTCON_PORTC_PU_C6_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C6_BITS_ENABLE (PORTCON_PORTC_PU_C6_VALUE_ENABLE << PORTCON_PORTC_PU_C6_SHIFT) #define PORTCON_PORTC_PU_C7_SHIFT 7 #define PORTCON_PORTC_PU_C7_WIDTH 1 #define PORTCON_PORTC_PU_C7_MASK (((1U << PORTCON_PORTC_PU_C7_WIDTH) - 1U) << PORTCON_PORTC_PU_C7_SHIFT) #define PORTCON_PORTC_PU_C7_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C7_BITS_DISABLE (PORTCON_PORTC_PU_C7_VALUE_DISABLE << PORTCON_PORTC_PU_C7_SHIFT) #define PORTCON_PORTC_PU_C7_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C7_BITS_ENABLE (PORTCON_PORTC_PU_C7_VALUE_ENABLE << PORTCON_PORTC_PU_C7_SHIFT) #define PORTCON_PORTC_PU_C8_SHIFT 8 #define PORTCON_PORTC_PU_C8_WIDTH 1 #define PORTCON_PORTC_PU_C8_MASK (((1U << PORTCON_PORTC_PU_C8_WIDTH) - 1U) << PORTCON_PORTC_PU_C8_SHIFT) #define PORTCON_PORTC_PU_C8_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C8_BITS_DISABLE (PORTCON_PORTC_PU_C8_VALUE_DISABLE << PORTCON_PORTC_PU_C8_SHIFT) #define PORTCON_PORTC_PU_C8_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C8_BITS_ENABLE (PORTCON_PORTC_PU_C8_VALUE_ENABLE << PORTCON_PORTC_PU_C8_SHIFT) #define PORTCON_PORTC_PU_C9_SHIFT 9 #define PORTCON_PORTC_PU_C9_WIDTH 1 #define PORTCON_PORTC_PU_C9_MASK (((1U << PORTCON_PORTC_PU_C9_WIDTH) - 1U) << PORTCON_PORTC_PU_C9_SHIFT) #define PORTCON_PORTC_PU_C9_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C9_BITS_DISABLE (PORTCON_PORTC_PU_C9_VALUE_DISABLE << PORTCON_PORTC_PU_C9_SHIFT) #define PORTCON_PORTC_PU_C9_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C9_BITS_ENABLE (PORTCON_PORTC_PU_C9_VALUE_ENABLE << PORTCON_PORTC_PU_C9_SHIFT) #define PORTCON_PORTC_PU_C10_SHIFT 10 #define PORTCON_PORTC_PU_C10_WIDTH 1 #define PORTCON_PORTC_PU_C10_MASK (((1U << PORTCON_PORTC_PU_C10_WIDTH) - 1U) << PORTCON_PORTC_PU_C10_SHIFT) #define PORTCON_PORTC_PU_C10_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C10_BITS_DISABLE (PORTCON_PORTC_PU_C10_VALUE_DISABLE << PORTCON_PORTC_PU_C10_SHIFT) #define PORTCON_PORTC_PU_C10_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C10_BITS_ENABLE (PORTCON_PORTC_PU_C10_VALUE_ENABLE << PORTCON_PORTC_PU_C10_SHIFT) #define PORTCON_PORTC_PU_C11_SHIFT 11 #define PORTCON_PORTC_PU_C11_WIDTH 1 #define PORTCON_PORTC_PU_C11_MASK (((1U << PORTCON_PORTC_PU_C11_WIDTH) - 1U) << PORTCON_PORTC_PU_C11_SHIFT) #define PORTCON_PORTC_PU_C11_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C11_BITS_DISABLE (PORTCON_PORTC_PU_C11_VALUE_DISABLE << PORTCON_PORTC_PU_C11_SHIFT) #define PORTCON_PORTC_PU_C11_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C11_BITS_ENABLE (PORTCON_PORTC_PU_C11_VALUE_ENABLE << PORTCON_PORTC_PU_C11_SHIFT) #define PORTCON_PORTC_PU_C12_SHIFT 12 #define PORTCON_PORTC_PU_C12_WIDTH 1 #define PORTCON_PORTC_PU_C12_MASK (((1U << PORTCON_PORTC_PU_C12_WIDTH) - 1U) << PORTCON_PORTC_PU_C12_SHIFT) #define PORTCON_PORTC_PU_C12_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C12_BITS_DISABLE (PORTCON_PORTC_PU_C12_VALUE_DISABLE << PORTCON_PORTC_PU_C12_SHIFT) #define PORTCON_PORTC_PU_C12_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C12_BITS_ENABLE (PORTCON_PORTC_PU_C12_VALUE_ENABLE << PORTCON_PORTC_PU_C12_SHIFT) #define PORTCON_PORTC_PU_C13_SHIFT 13 #define PORTCON_PORTC_PU_C13_WIDTH 1 #define PORTCON_PORTC_PU_C13_MASK (((1U << PORTCON_PORTC_PU_C13_WIDTH) - 1U) << PORTCON_PORTC_PU_C13_SHIFT) #define PORTCON_PORTC_PU_C13_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C13_BITS_DISABLE (PORTCON_PORTC_PU_C13_VALUE_DISABLE << PORTCON_PORTC_PU_C13_SHIFT) #define PORTCON_PORTC_PU_C13_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C13_BITS_ENABLE (PORTCON_PORTC_PU_C13_VALUE_ENABLE << PORTCON_PORTC_PU_C13_SHIFT) #define PORTCON_PORTC_PU_C14_SHIFT 14 #define PORTCON_PORTC_PU_C14_WIDTH 1 #define PORTCON_PORTC_PU_C14_MASK (((1U << PORTCON_PORTC_PU_C14_WIDTH) - 1U) << PORTCON_PORTC_PU_C14_SHIFT) #define PORTCON_PORTC_PU_C14_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C14_BITS_DISABLE (PORTCON_PORTC_PU_C14_VALUE_DISABLE << PORTCON_PORTC_PU_C14_SHIFT) #define PORTCON_PORTC_PU_C14_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C14_BITS_ENABLE (PORTCON_PORTC_PU_C14_VALUE_ENABLE << PORTCON_PORTC_PU_C14_SHIFT) #define PORTCON_PORTC_PU_C15_SHIFT 15 #define PORTCON_PORTC_PU_C15_WIDTH 1 #define PORTCON_PORTC_PU_C15_MASK (((1U << PORTCON_PORTC_PU_C15_WIDTH) - 1U) << PORTCON_PORTC_PU_C15_SHIFT) #define PORTCON_PORTC_PU_C15_VALUE_DISABLE 0U #define PORTCON_PORTC_PU_C15_BITS_DISABLE (PORTCON_PORTC_PU_C15_VALUE_DISABLE << PORTCON_PORTC_PU_C15_SHIFT) #define PORTCON_PORTC_PU_C15_VALUE_ENABLE 1U #define PORTCON_PORTC_PU_C15_BITS_ENABLE (PORTCON_PORTC_PU_C15_VALUE_ENABLE << PORTCON_PORTC_PU_C15_SHIFT) #define PORTCON_PORTA_PD_ADDR (PORTCON_BASE_ADDR + 0x0300U) #define PORTCON_PORTA_PD (*(volatile uint32_t *)PORTCON_PORTA_PD_ADDR) #define PORTCON_PORTA_PD_A0_SHIFT 0 #define PORTCON_PORTA_PD_A0_WIDTH 1 #define PORTCON_PORTA_PD_A0_MASK (((1U << PORTCON_PORTA_PD_A0_WIDTH) - 1U) << PORTCON_PORTA_PD_A0_SHIFT) #define PORTCON_PORTA_PD_A0_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A0_BITS_DISABLE (PORTCON_PORTA_PD_A0_VALUE_DISABLE << PORTCON_PORTA_PD_A0_SHIFT) #define PORTCON_PORTA_PD_A0_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A0_BITS_ENABLE (PORTCON_PORTA_PD_A0_VALUE_ENABLE << PORTCON_PORTA_PD_A0_SHIFT) #define PORTCON_PORTA_PD_A1_SHIFT 1 #define PORTCON_PORTA_PD_A1_WIDTH 1 #define PORTCON_PORTA_PD_A1_MASK (((1U << PORTCON_PORTA_PD_A1_WIDTH) - 1U) << PORTCON_PORTA_PD_A1_SHIFT) #define PORTCON_PORTA_PD_A1_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A1_BITS_DISABLE (PORTCON_PORTA_PD_A1_VALUE_DISABLE << PORTCON_PORTA_PD_A1_SHIFT) #define PORTCON_PORTA_PD_A1_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A1_BITS_ENABLE (PORTCON_PORTA_PD_A1_VALUE_ENABLE << PORTCON_PORTA_PD_A1_SHIFT) #define PORTCON_PORTA_PD_A2_SHIFT 2 #define PORTCON_PORTA_PD_A2_WIDTH 1 #define PORTCON_PORTA_PD_A2_MASK (((1U << PORTCON_PORTA_PD_A2_WIDTH) - 1U) << PORTCON_PORTA_PD_A2_SHIFT) #define PORTCON_PORTA_PD_A2_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A2_BITS_DISABLE (PORTCON_PORTA_PD_A2_VALUE_DISABLE << PORTCON_PORTA_PD_A2_SHIFT) #define PORTCON_PORTA_PD_A2_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A2_BITS_ENABLE (PORTCON_PORTA_PD_A2_VALUE_ENABLE << PORTCON_PORTA_PD_A2_SHIFT) #define PORTCON_PORTA_PD_A3_SHIFT 3 #define PORTCON_PORTA_PD_A3_WIDTH 1 #define PORTCON_PORTA_PD_A3_MASK (((1U << PORTCON_PORTA_PD_A3_WIDTH) - 1U) << PORTCON_PORTA_PD_A3_SHIFT) #define PORTCON_PORTA_PD_A3_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A3_BITS_DISABLE (PORTCON_PORTA_PD_A3_VALUE_DISABLE << PORTCON_PORTA_PD_A3_SHIFT) #define PORTCON_PORTA_PD_A3_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A3_BITS_ENABLE (PORTCON_PORTA_PD_A3_VALUE_ENABLE << PORTCON_PORTA_PD_A3_SHIFT) #define PORTCON_PORTA_PD_A4_SHIFT 4 #define PORTCON_PORTA_PD_A4_WIDTH 1 #define PORTCON_PORTA_PD_A4_MASK (((1U << PORTCON_PORTA_PD_A4_WIDTH) - 1U) << PORTCON_PORTA_PD_A4_SHIFT) #define PORTCON_PORTA_PD_A4_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A4_BITS_DISABLE (PORTCON_PORTA_PD_A4_VALUE_DISABLE << PORTCON_PORTA_PD_A4_SHIFT) #define PORTCON_PORTA_PD_A4_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A4_BITS_ENABLE (PORTCON_PORTA_PD_A4_VALUE_ENABLE << PORTCON_PORTA_PD_A4_SHIFT) #define PORTCON_PORTA_PD_A5_SHIFT 5 #define PORTCON_PORTA_PD_A5_WIDTH 1 #define PORTCON_PORTA_PD_A5_MASK (((1U << PORTCON_PORTA_PD_A5_WIDTH) - 1U) << PORTCON_PORTA_PD_A5_SHIFT) #define PORTCON_PORTA_PD_A5_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A5_BITS_DISABLE (PORTCON_PORTA_PD_A5_VALUE_DISABLE << PORTCON_PORTA_PD_A5_SHIFT) #define PORTCON_PORTA_PD_A5_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A5_BITS_ENABLE (PORTCON_PORTA_PD_A5_VALUE_ENABLE << PORTCON_PORTA_PD_A5_SHIFT) #define PORTCON_PORTA_PD_A6_SHIFT 6 #define PORTCON_PORTA_PD_A6_WIDTH 1 #define PORTCON_PORTA_PD_A6_MASK (((1U << PORTCON_PORTA_PD_A6_WIDTH) - 1U) << PORTCON_PORTA_PD_A6_SHIFT) #define PORTCON_PORTA_PD_A6_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A6_BITS_DISABLE (PORTCON_PORTA_PD_A6_VALUE_DISABLE << PORTCON_PORTA_PD_A6_SHIFT) #define PORTCON_PORTA_PD_A6_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A6_BITS_ENABLE (PORTCON_PORTA_PD_A6_VALUE_ENABLE << PORTCON_PORTA_PD_A6_SHIFT) #define PORTCON_PORTA_PD_A7_SHIFT 7 #define PORTCON_PORTA_PD_A7_WIDTH 1 #define PORTCON_PORTA_PD_A7_MASK (((1U << PORTCON_PORTA_PD_A7_WIDTH) - 1U) << PORTCON_PORTA_PD_A7_SHIFT) #define PORTCON_PORTA_PD_A7_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A7_BITS_DISABLE (PORTCON_PORTA_PD_A7_VALUE_DISABLE << PORTCON_PORTA_PD_A7_SHIFT) #define PORTCON_PORTA_PD_A7_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A7_BITS_ENABLE (PORTCON_PORTA_PD_A7_VALUE_ENABLE << PORTCON_PORTA_PD_A7_SHIFT) #define PORTCON_PORTA_PD_A8_SHIFT 8 #define PORTCON_PORTA_PD_A8_WIDTH 1 #define PORTCON_PORTA_PD_A8_MASK (((1U << PORTCON_PORTA_PD_A8_WIDTH) - 1U) << PORTCON_PORTA_PD_A8_SHIFT) #define PORTCON_PORTA_PD_A8_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A8_BITS_DISABLE (PORTCON_PORTA_PD_A8_VALUE_DISABLE << PORTCON_PORTA_PD_A8_SHIFT) #define PORTCON_PORTA_PD_A8_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A8_BITS_ENABLE (PORTCON_PORTA_PD_A8_VALUE_ENABLE << PORTCON_PORTA_PD_A8_SHIFT) #define PORTCON_PORTA_PD_A9_SHIFT 9 #define PORTCON_PORTA_PD_A9_WIDTH 1 #define PORTCON_PORTA_PD_A9_MASK (((1U << PORTCON_PORTA_PD_A9_WIDTH) - 1U) << PORTCON_PORTA_PD_A9_SHIFT) #define PORTCON_PORTA_PD_A9_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A9_BITS_DISABLE (PORTCON_PORTA_PD_A9_VALUE_DISABLE << PORTCON_PORTA_PD_A9_SHIFT) #define PORTCON_PORTA_PD_A9_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A9_BITS_ENABLE (PORTCON_PORTA_PD_A9_VALUE_ENABLE << PORTCON_PORTA_PD_A9_SHIFT) #define PORTCON_PORTA_PD_A10_SHIFT 10 #define PORTCON_PORTA_PD_A10_WIDTH 1 #define PORTCON_PORTA_PD_A10_MASK (((1U << PORTCON_PORTA_PD_A10_WIDTH) - 1U) << PORTCON_PORTA_PD_A10_SHIFT) #define PORTCON_PORTA_PD_A10_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A10_BITS_DISABLE (PORTCON_PORTA_PD_A10_VALUE_DISABLE << PORTCON_PORTA_PD_A10_SHIFT) #define PORTCON_PORTA_PD_A10_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A10_BITS_ENABLE (PORTCON_PORTA_PD_A10_VALUE_ENABLE << PORTCON_PORTA_PD_A10_SHIFT) #define PORTCON_PORTA_PD_A11_SHIFT 11 #define PORTCON_PORTA_PD_A11_WIDTH 1 #define PORTCON_PORTA_PD_A11_MASK (((1U << PORTCON_PORTA_PD_A11_WIDTH) - 1U) << PORTCON_PORTA_PD_A11_SHIFT) #define PORTCON_PORTA_PD_A11_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A11_BITS_DISABLE (PORTCON_PORTA_PD_A11_VALUE_DISABLE << PORTCON_PORTA_PD_A11_SHIFT) #define PORTCON_PORTA_PD_A11_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A11_BITS_ENABLE (PORTCON_PORTA_PD_A11_VALUE_ENABLE << PORTCON_PORTA_PD_A11_SHIFT) #define PORTCON_PORTA_PD_A12_SHIFT 12 #define PORTCON_PORTA_PD_A12_WIDTH 1 #define PORTCON_PORTA_PD_A12_MASK (((1U << PORTCON_PORTA_PD_A12_WIDTH) - 1U) << PORTCON_PORTA_PD_A12_SHIFT) #define PORTCON_PORTA_PD_A12_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A12_BITS_DISABLE (PORTCON_PORTA_PD_A12_VALUE_DISABLE << PORTCON_PORTA_PD_A12_SHIFT) #define PORTCON_PORTA_PD_A12_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A12_BITS_ENABLE (PORTCON_PORTA_PD_A12_VALUE_ENABLE << PORTCON_PORTA_PD_A12_SHIFT) #define PORTCON_PORTA_PD_A13_SHIFT 13 #define PORTCON_PORTA_PD_A13_WIDTH 1 #define PORTCON_PORTA_PD_A13_MASK (((1U << PORTCON_PORTA_PD_A13_WIDTH) - 1U) << PORTCON_PORTA_PD_A13_SHIFT) #define PORTCON_PORTA_PD_A13_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A13_BITS_DISABLE (PORTCON_PORTA_PD_A13_VALUE_DISABLE << PORTCON_PORTA_PD_A13_SHIFT) #define PORTCON_PORTA_PD_A13_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A13_BITS_ENABLE (PORTCON_PORTA_PD_A13_VALUE_ENABLE << PORTCON_PORTA_PD_A13_SHIFT) #define PORTCON_PORTA_PD_A14_SHIFT 14 #define PORTCON_PORTA_PD_A14_WIDTH 1 #define PORTCON_PORTA_PD_A14_MASK (((1U << PORTCON_PORTA_PD_A14_WIDTH) - 1U) << PORTCON_PORTA_PD_A14_SHIFT) #define PORTCON_PORTA_PD_A14_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A14_BITS_DISABLE (PORTCON_PORTA_PD_A14_VALUE_DISABLE << PORTCON_PORTA_PD_A14_SHIFT) #define PORTCON_PORTA_PD_A14_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A14_BITS_ENABLE (PORTCON_PORTA_PD_A14_VALUE_ENABLE << PORTCON_PORTA_PD_A14_SHIFT) #define PORTCON_PORTA_PD_A15_SHIFT 15 #define PORTCON_PORTA_PD_A15_WIDTH 1 #define PORTCON_PORTA_PD_A15_MASK (((1U << PORTCON_PORTA_PD_A15_WIDTH) - 1U) << PORTCON_PORTA_PD_A15_SHIFT) #define PORTCON_PORTA_PD_A15_VALUE_DISABLE 0U #define PORTCON_PORTA_PD_A15_BITS_DISABLE (PORTCON_PORTA_PD_A15_VALUE_DISABLE << PORTCON_PORTA_PD_A15_SHIFT) #define PORTCON_PORTA_PD_A15_VALUE_ENABLE 1U #define PORTCON_PORTA_PD_A15_BITS_ENABLE (PORTCON_PORTA_PD_A15_VALUE_ENABLE << PORTCON_PORTA_PD_A15_SHIFT) #define PORTCON_PORTB_PD_ADDR (PORTCON_BASE_ADDR + 0x0304U) #define PORTCON_PORTB_PD (*(volatile uint32_t *)PORTCON_PORTB_PD_ADDR) #define PORTCON_PORTB_PD_B0_SHIFT 0 #define PORTCON_PORTB_PD_B0_WIDTH 1 #define PORTCON_PORTB_PD_B0_MASK (((1U << PORTCON_PORTB_PD_B0_WIDTH) - 1U) << PORTCON_PORTB_PD_B0_SHIFT) #define PORTCON_PORTB_PD_B0_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B0_BITS_DISABLE (PORTCON_PORTB_PD_B0_VALUE_DISABLE << PORTCON_PORTB_PD_B0_SHIFT) #define PORTCON_PORTB_PD_B0_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B0_BITS_ENABLE (PORTCON_PORTB_PD_B0_VALUE_ENABLE << PORTCON_PORTB_PD_B0_SHIFT) #define PORTCON_PORTB_PD_B1_SHIFT 1 #define PORTCON_PORTB_PD_B1_WIDTH 1 #define PORTCON_PORTB_PD_B1_MASK (((1U << PORTCON_PORTB_PD_B1_WIDTH) - 1U) << PORTCON_PORTB_PD_B1_SHIFT) #define PORTCON_PORTB_PD_B1_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B1_BITS_DISABLE (PORTCON_PORTB_PD_B1_VALUE_DISABLE << PORTCON_PORTB_PD_B1_SHIFT) #define PORTCON_PORTB_PD_B1_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B1_BITS_ENABLE (PORTCON_PORTB_PD_B1_VALUE_ENABLE << PORTCON_PORTB_PD_B1_SHIFT) #define PORTCON_PORTB_PD_B2_SHIFT 2 #define PORTCON_PORTB_PD_B2_WIDTH 1 #define PORTCON_PORTB_PD_B2_MASK (((1U << PORTCON_PORTB_PD_B2_WIDTH) - 1U) << PORTCON_PORTB_PD_B2_SHIFT) #define PORTCON_PORTB_PD_B2_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B2_BITS_DISABLE (PORTCON_PORTB_PD_B2_VALUE_DISABLE << PORTCON_PORTB_PD_B2_SHIFT) #define PORTCON_PORTB_PD_B2_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B2_BITS_ENABLE (PORTCON_PORTB_PD_B2_VALUE_ENABLE << PORTCON_PORTB_PD_B2_SHIFT) #define PORTCON_PORTB_PD_B3_SHIFT 3 #define PORTCON_PORTB_PD_B3_WIDTH 1 #define PORTCON_PORTB_PD_B3_MASK (((1U << PORTCON_PORTB_PD_B3_WIDTH) - 1U) << PORTCON_PORTB_PD_B3_SHIFT) #define PORTCON_PORTB_PD_B3_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B3_BITS_DISABLE (PORTCON_PORTB_PD_B3_VALUE_DISABLE << PORTCON_PORTB_PD_B3_SHIFT) #define PORTCON_PORTB_PD_B3_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B3_BITS_ENABLE (PORTCON_PORTB_PD_B3_VALUE_ENABLE << PORTCON_PORTB_PD_B3_SHIFT) #define PORTCON_PORTB_PD_B4_SHIFT 4 #define PORTCON_PORTB_PD_B4_WIDTH 1 #define PORTCON_PORTB_PD_B4_MASK (((1U << PORTCON_PORTB_PD_B4_WIDTH) - 1U) << PORTCON_PORTB_PD_B4_SHIFT) #define PORTCON_PORTB_PD_B4_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B4_BITS_DISABLE (PORTCON_PORTB_PD_B4_VALUE_DISABLE << PORTCON_PORTB_PD_B4_SHIFT) #define PORTCON_PORTB_PD_B4_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B4_BITS_ENABLE (PORTCON_PORTB_PD_B4_VALUE_ENABLE << PORTCON_PORTB_PD_B4_SHIFT) #define PORTCON_PORTB_PD_B5_SHIFT 5 #define PORTCON_PORTB_PD_B5_WIDTH 1 #define PORTCON_PORTB_PD_B5_MASK (((1U << PORTCON_PORTB_PD_B5_WIDTH) - 1U) << PORTCON_PORTB_PD_B5_SHIFT) #define PORTCON_PORTB_PD_B5_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B5_BITS_DISABLE (PORTCON_PORTB_PD_B5_VALUE_DISABLE << PORTCON_PORTB_PD_B5_SHIFT) #define PORTCON_PORTB_PD_B5_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B5_BITS_ENABLE (PORTCON_PORTB_PD_B5_VALUE_ENABLE << PORTCON_PORTB_PD_B5_SHIFT) #define PORTCON_PORTB_PD_B6_SHIFT 6 #define PORTCON_PORTB_PD_B6_WIDTH 1 #define PORTCON_PORTB_PD_B6_MASK (((1U << PORTCON_PORTB_PD_B6_WIDTH) - 1U) << PORTCON_PORTB_PD_B6_SHIFT) #define PORTCON_PORTB_PD_B6_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B6_BITS_DISABLE (PORTCON_PORTB_PD_B6_VALUE_DISABLE << PORTCON_PORTB_PD_B6_SHIFT) #define PORTCON_PORTB_PD_B6_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B6_BITS_ENABLE (PORTCON_PORTB_PD_B6_VALUE_ENABLE << PORTCON_PORTB_PD_B6_SHIFT) #define PORTCON_PORTB_PD_B7_SHIFT 7 #define PORTCON_PORTB_PD_B7_WIDTH 1 #define PORTCON_PORTB_PD_B7_MASK (((1U << PORTCON_PORTB_PD_B7_WIDTH) - 1U) << PORTCON_PORTB_PD_B7_SHIFT) #define PORTCON_PORTB_PD_B7_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B7_BITS_DISABLE (PORTCON_PORTB_PD_B7_VALUE_DISABLE << PORTCON_PORTB_PD_B7_SHIFT) #define PORTCON_PORTB_PD_B7_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B7_BITS_ENABLE (PORTCON_PORTB_PD_B7_VALUE_ENABLE << PORTCON_PORTB_PD_B7_SHIFT) #define PORTCON_PORTB_PD_B8_SHIFT 8 #define PORTCON_PORTB_PD_B8_WIDTH 1 #define PORTCON_PORTB_PD_B8_MASK (((1U << PORTCON_PORTB_PD_B8_WIDTH) - 1U) << PORTCON_PORTB_PD_B8_SHIFT) #define PORTCON_PORTB_PD_B8_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B8_BITS_DISABLE (PORTCON_PORTB_PD_B8_VALUE_DISABLE << PORTCON_PORTB_PD_B8_SHIFT) #define PORTCON_PORTB_PD_B8_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B8_BITS_ENABLE (PORTCON_PORTB_PD_B8_VALUE_ENABLE << PORTCON_PORTB_PD_B8_SHIFT) #define PORTCON_PORTB_PD_B9_SHIFT 9 #define PORTCON_PORTB_PD_B9_WIDTH 1 #define PORTCON_PORTB_PD_B9_MASK (((1U << PORTCON_PORTB_PD_B9_WIDTH) - 1U) << PORTCON_PORTB_PD_B9_SHIFT) #define PORTCON_PORTB_PD_B9_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B9_BITS_DISABLE (PORTCON_PORTB_PD_B9_VALUE_DISABLE << PORTCON_PORTB_PD_B9_SHIFT) #define PORTCON_PORTB_PD_B9_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B9_BITS_ENABLE (PORTCON_PORTB_PD_B9_VALUE_ENABLE << PORTCON_PORTB_PD_B9_SHIFT) #define PORTCON_PORTB_PD_B10_SHIFT 10 #define PORTCON_PORTB_PD_B10_WIDTH 1 #define PORTCON_PORTB_PD_B10_MASK (((1U << PORTCON_PORTB_PD_B10_WIDTH) - 1U) << PORTCON_PORTB_PD_B10_SHIFT) #define PORTCON_PORTB_PD_B10_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B10_BITS_DISABLE (PORTCON_PORTB_PD_B10_VALUE_DISABLE << PORTCON_PORTB_PD_B10_SHIFT) #define PORTCON_PORTB_PD_B10_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B10_BITS_ENABLE (PORTCON_PORTB_PD_B10_VALUE_ENABLE << PORTCON_PORTB_PD_B10_SHIFT) #define PORTCON_PORTB_PD_B11_SHIFT 11 #define PORTCON_PORTB_PD_B11_WIDTH 1 #define PORTCON_PORTB_PD_B11_MASK (((1U << PORTCON_PORTB_PD_B11_WIDTH) - 1U) << PORTCON_PORTB_PD_B11_SHIFT) #define PORTCON_PORTB_PD_B11_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B11_BITS_DISABLE (PORTCON_PORTB_PD_B11_VALUE_DISABLE << PORTCON_PORTB_PD_B11_SHIFT) #define PORTCON_PORTB_PD_B11_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B11_BITS_ENABLE (PORTCON_PORTB_PD_B11_VALUE_ENABLE << PORTCON_PORTB_PD_B11_SHIFT) #define PORTCON_PORTB_PD_B12_SHIFT 12 #define PORTCON_PORTB_PD_B12_WIDTH 1 #define PORTCON_PORTB_PD_B12_MASK (((1U << PORTCON_PORTB_PD_B12_WIDTH) - 1U) << PORTCON_PORTB_PD_B12_SHIFT) #define PORTCON_PORTB_PD_B12_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B12_BITS_DISABLE (PORTCON_PORTB_PD_B12_VALUE_DISABLE << PORTCON_PORTB_PD_B12_SHIFT) #define PORTCON_PORTB_PD_B12_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B12_BITS_ENABLE (PORTCON_PORTB_PD_B12_VALUE_ENABLE << PORTCON_PORTB_PD_B12_SHIFT) #define PORTCON_PORTB_PD_B13_SHIFT 13 #define PORTCON_PORTB_PD_B13_WIDTH 1 #define PORTCON_PORTB_PD_B13_MASK (((1U << PORTCON_PORTB_PD_B13_WIDTH) - 1U) << PORTCON_PORTB_PD_B13_SHIFT) #define PORTCON_PORTB_PD_B13_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B13_BITS_DISABLE (PORTCON_PORTB_PD_B13_VALUE_DISABLE << PORTCON_PORTB_PD_B13_SHIFT) #define PORTCON_PORTB_PD_B13_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B13_BITS_ENABLE (PORTCON_PORTB_PD_B13_VALUE_ENABLE << PORTCON_PORTB_PD_B13_SHIFT) #define PORTCON_PORTB_PD_B14_SHIFT 14 #define PORTCON_PORTB_PD_B14_WIDTH 1 #define PORTCON_PORTB_PD_B14_MASK (((1U << PORTCON_PORTB_PD_B14_WIDTH) - 1U) << PORTCON_PORTB_PD_B14_SHIFT) #define PORTCON_PORTB_PD_B14_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B14_BITS_DISABLE (PORTCON_PORTB_PD_B14_VALUE_DISABLE << PORTCON_PORTB_PD_B14_SHIFT) #define PORTCON_PORTB_PD_B14_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B14_BITS_ENABLE (PORTCON_PORTB_PD_B14_VALUE_ENABLE << PORTCON_PORTB_PD_B14_SHIFT) #define PORTCON_PORTB_PD_B15_SHIFT 15 #define PORTCON_PORTB_PD_B15_WIDTH 1 #define PORTCON_PORTB_PD_B15_MASK (((1U << PORTCON_PORTB_PD_B15_WIDTH) - 1U) << PORTCON_PORTB_PD_B15_SHIFT) #define PORTCON_PORTB_PD_B15_VALUE_DISABLE 0U #define PORTCON_PORTB_PD_B15_BITS_DISABLE (PORTCON_PORTB_PD_B15_VALUE_DISABLE << PORTCON_PORTB_PD_B15_SHIFT) #define PORTCON_PORTB_PD_B15_VALUE_ENABLE 1U #define PORTCON_PORTB_PD_B15_BITS_ENABLE (PORTCON_PORTB_PD_B15_VALUE_ENABLE << PORTCON_PORTB_PD_B15_SHIFT) #define PORTCON_PORTC_PD_ADDR (PORTCON_BASE_ADDR + 0x0308U) #define PORTCON_PORTC_PD (*(volatile uint32_t *)PORTCON_PORTC_PD_ADDR) #define PORTCON_PORTC_PD_C0_SHIFT 0 #define PORTCON_PORTC_PD_C0_WIDTH 1 #define PORTCON_PORTC_PD_C0_MASK (((1U << PORTCON_PORTC_PD_C0_WIDTH) - 1U) << PORTCON_PORTC_PD_C0_SHIFT) #define PORTCON_PORTC_PD_C0_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C0_BITS_DISABLE (PORTCON_PORTC_PD_C0_VALUE_DISABLE << PORTCON_PORTC_PD_C0_SHIFT) #define PORTCON_PORTC_PD_C0_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C0_BITS_ENABLE (PORTCON_PORTC_PD_C0_VALUE_ENABLE << PORTCON_PORTC_PD_C0_SHIFT) #define PORTCON_PORTC_PD_C1_SHIFT 1 #define PORTCON_PORTC_PD_C1_WIDTH 1 #define PORTCON_PORTC_PD_C1_MASK (((1U << PORTCON_PORTC_PD_C1_WIDTH) - 1U) << PORTCON_PORTC_PD_C1_SHIFT) #define PORTCON_PORTC_PD_C1_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C1_BITS_DISABLE (PORTCON_PORTC_PD_C1_VALUE_DISABLE << PORTCON_PORTC_PD_C1_SHIFT) #define PORTCON_PORTC_PD_C1_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C1_BITS_ENABLE (PORTCON_PORTC_PD_C1_VALUE_ENABLE << PORTCON_PORTC_PD_C1_SHIFT) #define PORTCON_PORTC_PD_C2_SHIFT 2 #define PORTCON_PORTC_PD_C2_WIDTH 1 #define PORTCON_PORTC_PD_C2_MASK (((1U << PORTCON_PORTC_PD_C2_WIDTH) - 1U) << PORTCON_PORTC_PD_C2_SHIFT) #define PORTCON_PORTC_PD_C2_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C2_BITS_DISABLE (PORTCON_PORTC_PD_C2_VALUE_DISABLE << PORTCON_PORTC_PD_C2_SHIFT) #define PORTCON_PORTC_PD_C2_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C2_BITS_ENABLE (PORTCON_PORTC_PD_C2_VALUE_ENABLE << PORTCON_PORTC_PD_C2_SHIFT) #define PORTCON_PORTC_PD_C3_SHIFT 3 #define PORTCON_PORTC_PD_C3_WIDTH 1 #define PORTCON_PORTC_PD_C3_MASK (((1U << PORTCON_PORTC_PD_C3_WIDTH) - 1U) << PORTCON_PORTC_PD_C3_SHIFT) #define PORTCON_PORTC_PD_C3_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C3_BITS_DISABLE (PORTCON_PORTC_PD_C3_VALUE_DISABLE << PORTCON_PORTC_PD_C3_SHIFT) #define PORTCON_PORTC_PD_C3_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C3_BITS_ENABLE (PORTCON_PORTC_PD_C3_VALUE_ENABLE << PORTCON_PORTC_PD_C3_SHIFT) #define PORTCON_PORTC_PD_C4_SHIFT 4 #define PORTCON_PORTC_PD_C4_WIDTH 1 #define PORTCON_PORTC_PD_C4_MASK (((1U << PORTCON_PORTC_PD_C4_WIDTH) - 1U) << PORTCON_PORTC_PD_C4_SHIFT) #define PORTCON_PORTC_PD_C4_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C4_BITS_DISABLE (PORTCON_PORTC_PD_C4_VALUE_DISABLE << PORTCON_PORTC_PD_C4_SHIFT) #define PORTCON_PORTC_PD_C4_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C4_BITS_ENABLE (PORTCON_PORTC_PD_C4_VALUE_ENABLE << PORTCON_PORTC_PD_C4_SHIFT) #define PORTCON_PORTC_PD_C5_SHIFT 5 #define PORTCON_PORTC_PD_C5_WIDTH 1 #define PORTCON_PORTC_PD_C5_MASK (((1U << PORTCON_PORTC_PD_C5_WIDTH) - 1U) << PORTCON_PORTC_PD_C5_SHIFT) #define PORTCON_PORTC_PD_C5_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C5_BITS_DISABLE (PORTCON_PORTC_PD_C5_VALUE_DISABLE << PORTCON_PORTC_PD_C5_SHIFT) #define PORTCON_PORTC_PD_C5_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C5_BITS_ENABLE (PORTCON_PORTC_PD_C5_VALUE_ENABLE << PORTCON_PORTC_PD_C5_SHIFT) #define PORTCON_PORTC_PD_C6_SHIFT 6 #define PORTCON_PORTC_PD_C6_WIDTH 1 #define PORTCON_PORTC_PD_C6_MASK (((1U << PORTCON_PORTC_PD_C6_WIDTH) - 1U) << PORTCON_PORTC_PD_C6_SHIFT) #define PORTCON_PORTC_PD_C6_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C6_BITS_DISABLE (PORTCON_PORTC_PD_C6_VALUE_DISABLE << PORTCON_PORTC_PD_C6_SHIFT) #define PORTCON_PORTC_PD_C6_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C6_BITS_ENABLE (PORTCON_PORTC_PD_C6_VALUE_ENABLE << PORTCON_PORTC_PD_C6_SHIFT) #define PORTCON_PORTC_PD_C7_SHIFT 7 #define PORTCON_PORTC_PD_C7_WIDTH 1 #define PORTCON_PORTC_PD_C7_MASK (((1U << PORTCON_PORTC_PD_C7_WIDTH) - 1U) << PORTCON_PORTC_PD_C7_SHIFT) #define PORTCON_PORTC_PD_C7_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C7_BITS_DISABLE (PORTCON_PORTC_PD_C7_VALUE_DISABLE << PORTCON_PORTC_PD_C7_SHIFT) #define PORTCON_PORTC_PD_C7_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C7_BITS_ENABLE (PORTCON_PORTC_PD_C7_VALUE_ENABLE << PORTCON_PORTC_PD_C7_SHIFT) #define PORTCON_PORTC_PD_C8_SHIFT 8 #define PORTCON_PORTC_PD_C8_WIDTH 1 #define PORTCON_PORTC_PD_C8_MASK (((1U << PORTCON_PORTC_PD_C8_WIDTH) - 1U) << PORTCON_PORTC_PD_C8_SHIFT) #define PORTCON_PORTC_PD_C8_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C8_BITS_DISABLE (PORTCON_PORTC_PD_C8_VALUE_DISABLE << PORTCON_PORTC_PD_C8_SHIFT) #define PORTCON_PORTC_PD_C8_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C8_BITS_ENABLE (PORTCON_PORTC_PD_C8_VALUE_ENABLE << PORTCON_PORTC_PD_C8_SHIFT) #define PORTCON_PORTC_PD_C9_SHIFT 9 #define PORTCON_PORTC_PD_C9_WIDTH 1 #define PORTCON_PORTC_PD_C9_MASK (((1U << PORTCON_PORTC_PD_C9_WIDTH) - 1U) << PORTCON_PORTC_PD_C9_SHIFT) #define PORTCON_PORTC_PD_C9_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C9_BITS_DISABLE (PORTCON_PORTC_PD_C9_VALUE_DISABLE << PORTCON_PORTC_PD_C9_SHIFT) #define PORTCON_PORTC_PD_C9_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C9_BITS_ENABLE (PORTCON_PORTC_PD_C9_VALUE_ENABLE << PORTCON_PORTC_PD_C9_SHIFT) #define PORTCON_PORTC_PD_C10_SHIFT 10 #define PORTCON_PORTC_PD_C10_WIDTH 1 #define PORTCON_PORTC_PD_C10_MASK (((1U << PORTCON_PORTC_PD_C10_WIDTH) - 1U) << PORTCON_PORTC_PD_C10_SHIFT) #define PORTCON_PORTC_PD_C10_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C10_BITS_DISABLE (PORTCON_PORTC_PD_C10_VALUE_DISABLE << PORTCON_PORTC_PD_C10_SHIFT) #define PORTCON_PORTC_PD_C10_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C10_BITS_ENABLE (PORTCON_PORTC_PD_C10_VALUE_ENABLE << PORTCON_PORTC_PD_C10_SHIFT) #define PORTCON_PORTC_PD_C11_SHIFT 11 #define PORTCON_PORTC_PD_C11_WIDTH 1 #define PORTCON_PORTC_PD_C11_MASK (((1U << PORTCON_PORTC_PD_C11_WIDTH) - 1U) << PORTCON_PORTC_PD_C11_SHIFT) #define PORTCON_PORTC_PD_C11_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C11_BITS_DISABLE (PORTCON_PORTC_PD_C11_VALUE_DISABLE << PORTCON_PORTC_PD_C11_SHIFT) #define PORTCON_PORTC_PD_C11_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C11_BITS_ENABLE (PORTCON_PORTC_PD_C11_VALUE_ENABLE << PORTCON_PORTC_PD_C11_SHIFT) #define PORTCON_PORTC_PD_C12_SHIFT 12 #define PORTCON_PORTC_PD_C12_WIDTH 1 #define PORTCON_PORTC_PD_C12_MASK (((1U << PORTCON_PORTC_PD_C12_WIDTH) - 1U) << PORTCON_PORTC_PD_C12_SHIFT) #define PORTCON_PORTC_PD_C12_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C12_BITS_DISABLE (PORTCON_PORTC_PD_C12_VALUE_DISABLE << PORTCON_PORTC_PD_C12_SHIFT) #define PORTCON_PORTC_PD_C12_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C12_BITS_ENABLE (PORTCON_PORTC_PD_C12_VALUE_ENABLE << PORTCON_PORTC_PD_C12_SHIFT) #define PORTCON_PORTC_PD_C13_SHIFT 13 #define PORTCON_PORTC_PD_C13_WIDTH 1 #define PORTCON_PORTC_PD_C13_MASK (((1U << PORTCON_PORTC_PD_C13_WIDTH) - 1U) << PORTCON_PORTC_PD_C13_SHIFT) #define PORTCON_PORTC_PD_C13_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C13_BITS_DISABLE (PORTCON_PORTC_PD_C13_VALUE_DISABLE << PORTCON_PORTC_PD_C13_SHIFT) #define PORTCON_PORTC_PD_C13_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C13_BITS_ENABLE (PORTCON_PORTC_PD_C13_VALUE_ENABLE << PORTCON_PORTC_PD_C13_SHIFT) #define PORTCON_PORTC_PD_C14_SHIFT 14 #define PORTCON_PORTC_PD_C14_WIDTH 1 #define PORTCON_PORTC_PD_C14_MASK (((1U << PORTCON_PORTC_PD_C14_WIDTH) - 1U) << PORTCON_PORTC_PD_C14_SHIFT) #define PORTCON_PORTC_PD_C14_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C14_BITS_DISABLE (PORTCON_PORTC_PD_C14_VALUE_DISABLE << PORTCON_PORTC_PD_C14_SHIFT) #define PORTCON_PORTC_PD_C14_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C14_BITS_ENABLE (PORTCON_PORTC_PD_C14_VALUE_ENABLE << PORTCON_PORTC_PD_C14_SHIFT) #define PORTCON_PORTC_PD_C15_SHIFT 15 #define PORTCON_PORTC_PD_C15_WIDTH 1 #define PORTCON_PORTC_PD_C15_MASK (((1U << PORTCON_PORTC_PD_C15_WIDTH) - 1U) << PORTCON_PORTC_PD_C15_SHIFT) #define PORTCON_PORTC_PD_C15_VALUE_DISABLE 0U #define PORTCON_PORTC_PD_C15_BITS_DISABLE (PORTCON_PORTC_PD_C15_VALUE_DISABLE << PORTCON_PORTC_PD_C15_SHIFT) #define PORTCON_PORTC_PD_C15_VALUE_ENABLE 1U #define PORTCON_PORTC_PD_C15_BITS_ENABLE (PORTCON_PORTC_PD_C15_VALUE_ENABLE << PORTCON_PORTC_PD_C15_SHIFT) #define PORTCON_PORTA_OD_ADDR (PORTCON_BASE_ADDR + 0x0400U) #define PORTCON_PORTA_OD (*(volatile uint32_t *)PORTCON_PORTA_OD_ADDR) #define PORTCON_PORTA_OD_A0_SHIFT 0 #define PORTCON_PORTA_OD_A0_WIDTH 1 #define PORTCON_PORTA_OD_A0_MASK (((1U << PORTCON_PORTA_OD_A0_WIDTH) - 1U) << PORTCON_PORTA_OD_A0_SHIFT) #define PORTCON_PORTA_OD_A0_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A0_BITS_DISABLE (PORTCON_PORTA_OD_A0_VALUE_DISABLE << PORTCON_PORTA_OD_A0_SHIFT) #define PORTCON_PORTA_OD_A0_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A0_BITS_ENABLE (PORTCON_PORTA_OD_A0_VALUE_ENABLE << PORTCON_PORTA_OD_A0_SHIFT) #define PORTCON_PORTA_OD_A1_SHIFT 1 #define PORTCON_PORTA_OD_A1_WIDTH 1 #define PORTCON_PORTA_OD_A1_MASK (((1U << PORTCON_PORTA_OD_A1_WIDTH) - 1U) << PORTCON_PORTA_OD_A1_SHIFT) #define PORTCON_PORTA_OD_A1_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A1_BITS_DISABLE (PORTCON_PORTA_OD_A1_VALUE_DISABLE << PORTCON_PORTA_OD_A1_SHIFT) #define PORTCON_PORTA_OD_A1_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A1_BITS_ENABLE (PORTCON_PORTA_OD_A1_VALUE_ENABLE << PORTCON_PORTA_OD_A1_SHIFT) #define PORTCON_PORTA_OD_A2_SHIFT 2 #define PORTCON_PORTA_OD_A2_WIDTH 1 #define PORTCON_PORTA_OD_A2_MASK (((1U << PORTCON_PORTA_OD_A2_WIDTH) - 1U) << PORTCON_PORTA_OD_A2_SHIFT) #define PORTCON_PORTA_OD_A2_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A2_BITS_DISABLE (PORTCON_PORTA_OD_A2_VALUE_DISABLE << PORTCON_PORTA_OD_A2_SHIFT) #define PORTCON_PORTA_OD_A2_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A2_BITS_ENABLE (PORTCON_PORTA_OD_A2_VALUE_ENABLE << PORTCON_PORTA_OD_A2_SHIFT) #define PORTCON_PORTA_OD_A3_SHIFT 3 #define PORTCON_PORTA_OD_A3_WIDTH 1 #define PORTCON_PORTA_OD_A3_MASK (((1U << PORTCON_PORTA_OD_A3_WIDTH) - 1U) << PORTCON_PORTA_OD_A3_SHIFT) #define PORTCON_PORTA_OD_A3_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A3_BITS_DISABLE (PORTCON_PORTA_OD_A3_VALUE_DISABLE << PORTCON_PORTA_OD_A3_SHIFT) #define PORTCON_PORTA_OD_A3_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A3_BITS_ENABLE (PORTCON_PORTA_OD_A3_VALUE_ENABLE << PORTCON_PORTA_OD_A3_SHIFT) #define PORTCON_PORTA_OD_A4_SHIFT 4 #define PORTCON_PORTA_OD_A4_WIDTH 1 #define PORTCON_PORTA_OD_A4_MASK (((1U << PORTCON_PORTA_OD_A4_WIDTH) - 1U) << PORTCON_PORTA_OD_A4_SHIFT) #define PORTCON_PORTA_OD_A4_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A4_BITS_DISABLE (PORTCON_PORTA_OD_A4_VALUE_DISABLE << PORTCON_PORTA_OD_A4_SHIFT) #define PORTCON_PORTA_OD_A4_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A4_BITS_ENABLE (PORTCON_PORTA_OD_A4_VALUE_ENABLE << PORTCON_PORTA_OD_A4_SHIFT) #define PORTCON_PORTA_OD_A5_SHIFT 5 #define PORTCON_PORTA_OD_A5_WIDTH 1 #define PORTCON_PORTA_OD_A5_MASK (((1U << PORTCON_PORTA_OD_A5_WIDTH) - 1U) << PORTCON_PORTA_OD_A5_SHIFT) #define PORTCON_PORTA_OD_A5_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A5_BITS_DISABLE (PORTCON_PORTA_OD_A5_VALUE_DISABLE << PORTCON_PORTA_OD_A5_SHIFT) #define PORTCON_PORTA_OD_A5_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A5_BITS_ENABLE (PORTCON_PORTA_OD_A5_VALUE_ENABLE << PORTCON_PORTA_OD_A5_SHIFT) #define PORTCON_PORTA_OD_A6_SHIFT 6 #define PORTCON_PORTA_OD_A6_WIDTH 1 #define PORTCON_PORTA_OD_A6_MASK (((1U << PORTCON_PORTA_OD_A6_WIDTH) - 1U) << PORTCON_PORTA_OD_A6_SHIFT) #define PORTCON_PORTA_OD_A6_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A6_BITS_DISABLE (PORTCON_PORTA_OD_A6_VALUE_DISABLE << PORTCON_PORTA_OD_A6_SHIFT) #define PORTCON_PORTA_OD_A6_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A6_BITS_ENABLE (PORTCON_PORTA_OD_A6_VALUE_ENABLE << PORTCON_PORTA_OD_A6_SHIFT) #define PORTCON_PORTA_OD_A7_SHIFT 7 #define PORTCON_PORTA_OD_A7_WIDTH 1 #define PORTCON_PORTA_OD_A7_MASK (((1U << PORTCON_PORTA_OD_A7_WIDTH) - 1U) << PORTCON_PORTA_OD_A7_SHIFT) #define PORTCON_PORTA_OD_A7_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A7_BITS_DISABLE (PORTCON_PORTA_OD_A7_VALUE_DISABLE << PORTCON_PORTA_OD_A7_SHIFT) #define PORTCON_PORTA_OD_A7_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A7_BITS_ENABLE (PORTCON_PORTA_OD_A7_VALUE_ENABLE << PORTCON_PORTA_OD_A7_SHIFT) #define PORTCON_PORTA_OD_A8_SHIFT 8 #define PORTCON_PORTA_OD_A8_WIDTH 1 #define PORTCON_PORTA_OD_A8_MASK (((1U << PORTCON_PORTA_OD_A8_WIDTH) - 1U) << PORTCON_PORTA_OD_A8_SHIFT) #define PORTCON_PORTA_OD_A8_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A8_BITS_DISABLE (PORTCON_PORTA_OD_A8_VALUE_DISABLE << PORTCON_PORTA_OD_A8_SHIFT) #define PORTCON_PORTA_OD_A8_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A8_BITS_ENABLE (PORTCON_PORTA_OD_A8_VALUE_ENABLE << PORTCON_PORTA_OD_A8_SHIFT) #define PORTCON_PORTA_OD_A9_SHIFT 9 #define PORTCON_PORTA_OD_A9_WIDTH 1 #define PORTCON_PORTA_OD_A9_MASK (((1U << PORTCON_PORTA_OD_A9_WIDTH) - 1U) << PORTCON_PORTA_OD_A9_SHIFT) #define PORTCON_PORTA_OD_A9_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A9_BITS_DISABLE (PORTCON_PORTA_OD_A9_VALUE_DISABLE << PORTCON_PORTA_OD_A9_SHIFT) #define PORTCON_PORTA_OD_A9_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A9_BITS_ENABLE (PORTCON_PORTA_OD_A9_VALUE_ENABLE << PORTCON_PORTA_OD_A9_SHIFT) #define PORTCON_PORTA_OD_A10_SHIFT 10 #define PORTCON_PORTA_OD_A10_WIDTH 1 #define PORTCON_PORTA_OD_A10_MASK (((1U << PORTCON_PORTA_OD_A10_WIDTH) - 1U) << PORTCON_PORTA_OD_A10_SHIFT) #define PORTCON_PORTA_OD_A10_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A10_BITS_DISABLE (PORTCON_PORTA_OD_A10_VALUE_DISABLE << PORTCON_PORTA_OD_A10_SHIFT) #define PORTCON_PORTA_OD_A10_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A10_BITS_ENABLE (PORTCON_PORTA_OD_A10_VALUE_ENABLE << PORTCON_PORTA_OD_A10_SHIFT) #define PORTCON_PORTA_OD_A11_SHIFT 11 #define PORTCON_PORTA_OD_A11_WIDTH 1 #define PORTCON_PORTA_OD_A11_MASK (((1U << PORTCON_PORTA_OD_A11_WIDTH) - 1U) << PORTCON_PORTA_OD_A11_SHIFT) #define PORTCON_PORTA_OD_A11_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A11_BITS_DISABLE (PORTCON_PORTA_OD_A11_VALUE_DISABLE << PORTCON_PORTA_OD_A11_SHIFT) #define PORTCON_PORTA_OD_A11_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A11_BITS_ENABLE (PORTCON_PORTA_OD_A11_VALUE_ENABLE << PORTCON_PORTA_OD_A11_SHIFT) #define PORTCON_PORTA_OD_A12_SHIFT 12 #define PORTCON_PORTA_OD_A12_WIDTH 1 #define PORTCON_PORTA_OD_A12_MASK (((1U << PORTCON_PORTA_OD_A12_WIDTH) - 1U) << PORTCON_PORTA_OD_A12_SHIFT) #define PORTCON_PORTA_OD_A12_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A12_BITS_DISABLE (PORTCON_PORTA_OD_A12_VALUE_DISABLE << PORTCON_PORTA_OD_A12_SHIFT) #define PORTCON_PORTA_OD_A12_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A12_BITS_ENABLE (PORTCON_PORTA_OD_A12_VALUE_ENABLE << PORTCON_PORTA_OD_A12_SHIFT) #define PORTCON_PORTA_OD_A13_SHIFT 13 #define PORTCON_PORTA_OD_A13_WIDTH 1 #define PORTCON_PORTA_OD_A13_MASK (((1U << PORTCON_PORTA_OD_A13_WIDTH) - 1U) << PORTCON_PORTA_OD_A13_SHIFT) #define PORTCON_PORTA_OD_A13_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A13_BITS_DISABLE (PORTCON_PORTA_OD_A13_VALUE_DISABLE << PORTCON_PORTA_OD_A13_SHIFT) #define PORTCON_PORTA_OD_A13_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A13_BITS_ENABLE (PORTCON_PORTA_OD_A13_VALUE_ENABLE << PORTCON_PORTA_OD_A13_SHIFT) #define PORTCON_PORTA_OD_A14_SHIFT 14 #define PORTCON_PORTA_OD_A14_WIDTH 1 #define PORTCON_PORTA_OD_A14_MASK (((1U << PORTCON_PORTA_OD_A14_WIDTH) - 1U) << PORTCON_PORTA_OD_A14_SHIFT) #define PORTCON_PORTA_OD_A14_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A14_BITS_DISABLE (PORTCON_PORTA_OD_A14_VALUE_DISABLE << PORTCON_PORTA_OD_A14_SHIFT) #define PORTCON_PORTA_OD_A14_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A14_BITS_ENABLE (PORTCON_PORTA_OD_A14_VALUE_ENABLE << PORTCON_PORTA_OD_A14_SHIFT) #define PORTCON_PORTA_OD_A15_SHIFT 15 #define PORTCON_PORTA_OD_A15_WIDTH 1 #define PORTCON_PORTA_OD_A15_MASK (((1U << PORTCON_PORTA_OD_A15_WIDTH) - 1U) << PORTCON_PORTA_OD_A15_SHIFT) #define PORTCON_PORTA_OD_A15_VALUE_DISABLE 0U #define PORTCON_PORTA_OD_A15_BITS_DISABLE (PORTCON_PORTA_OD_A15_VALUE_DISABLE << PORTCON_PORTA_OD_A15_SHIFT) #define PORTCON_PORTA_OD_A15_VALUE_ENABLE 1U #define PORTCON_PORTA_OD_A15_BITS_ENABLE (PORTCON_PORTA_OD_A15_VALUE_ENABLE << PORTCON_PORTA_OD_A15_SHIFT) #define PORTCON_PORTB_OD_ADDR (PORTCON_BASE_ADDR + 0x0404U) #define PORTCON_PORTB_OD (*(volatile uint32_t *)PORTCON_PORTB_OD_ADDR) #define PORTCON_PORTB_OD_B0_SHIFT 0 #define PORTCON_PORTB_OD_B0_WIDTH 1 #define PORTCON_PORTB_OD_B0_MASK (((1U << PORTCON_PORTB_OD_B0_WIDTH) - 1U) << PORTCON_PORTB_OD_B0_SHIFT) #define PORTCON_PORTB_OD_B0_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B0_BITS_DISABLE (PORTCON_PORTB_OD_B0_VALUE_DISABLE << PORTCON_PORTB_OD_B0_SHIFT) #define PORTCON_PORTB_OD_B0_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B0_BITS_ENABLE (PORTCON_PORTB_OD_B0_VALUE_ENABLE << PORTCON_PORTB_OD_B0_SHIFT) #define PORTCON_PORTB_OD_B1_SHIFT 1 #define PORTCON_PORTB_OD_B1_WIDTH 1 #define PORTCON_PORTB_OD_B1_MASK (((1U << PORTCON_PORTB_OD_B1_WIDTH) - 1U) << PORTCON_PORTB_OD_B1_SHIFT) #define PORTCON_PORTB_OD_B1_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B1_BITS_DISABLE (PORTCON_PORTB_OD_B1_VALUE_DISABLE << PORTCON_PORTB_OD_B1_SHIFT) #define PORTCON_PORTB_OD_B1_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B1_BITS_ENABLE (PORTCON_PORTB_OD_B1_VALUE_ENABLE << PORTCON_PORTB_OD_B1_SHIFT) #define PORTCON_PORTB_OD_B2_SHIFT 2 #define PORTCON_PORTB_OD_B2_WIDTH 1 #define PORTCON_PORTB_OD_B2_MASK (((1U << PORTCON_PORTB_OD_B2_WIDTH) - 1U) << PORTCON_PORTB_OD_B2_SHIFT) #define PORTCON_PORTB_OD_B2_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B2_BITS_DISABLE (PORTCON_PORTB_OD_B2_VALUE_DISABLE << PORTCON_PORTB_OD_B2_SHIFT) #define PORTCON_PORTB_OD_B2_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B2_BITS_ENABLE (PORTCON_PORTB_OD_B2_VALUE_ENABLE << PORTCON_PORTB_OD_B2_SHIFT) #define PORTCON_PORTB_OD_B3_SHIFT 3 #define PORTCON_PORTB_OD_B3_WIDTH 1 #define PORTCON_PORTB_OD_B3_MASK (((1U << PORTCON_PORTB_OD_B3_WIDTH) - 1U) << PORTCON_PORTB_OD_B3_SHIFT) #define PORTCON_PORTB_OD_B3_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B3_BITS_DISABLE (PORTCON_PORTB_OD_B3_VALUE_DISABLE << PORTCON_PORTB_OD_B3_SHIFT) #define PORTCON_PORTB_OD_B3_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B3_BITS_ENABLE (PORTCON_PORTB_OD_B3_VALUE_ENABLE << PORTCON_PORTB_OD_B3_SHIFT) #define PORTCON_PORTB_OD_B4_SHIFT 4 #define PORTCON_PORTB_OD_B4_WIDTH 1 #define PORTCON_PORTB_OD_B4_MASK (((1U << PORTCON_PORTB_OD_B4_WIDTH) - 1U) << PORTCON_PORTB_OD_B4_SHIFT) #define PORTCON_PORTB_OD_B4_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B4_BITS_DISABLE (PORTCON_PORTB_OD_B4_VALUE_DISABLE << PORTCON_PORTB_OD_B4_SHIFT) #define PORTCON_PORTB_OD_B4_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B4_BITS_ENABLE (PORTCON_PORTB_OD_B4_VALUE_ENABLE << PORTCON_PORTB_OD_B4_SHIFT) #define PORTCON_PORTB_OD_B5_SHIFT 5 #define PORTCON_PORTB_OD_B5_WIDTH 1 #define PORTCON_PORTB_OD_B5_MASK (((1U << PORTCON_PORTB_OD_B5_WIDTH) - 1U) << PORTCON_PORTB_OD_B5_SHIFT) #define PORTCON_PORTB_OD_B5_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B5_BITS_DISABLE (PORTCON_PORTB_OD_B5_VALUE_DISABLE << PORTCON_PORTB_OD_B5_SHIFT) #define PORTCON_PORTB_OD_B5_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B5_BITS_ENABLE (PORTCON_PORTB_OD_B5_VALUE_ENABLE << PORTCON_PORTB_OD_B5_SHIFT) #define PORTCON_PORTB_OD_B6_SHIFT 6 #define PORTCON_PORTB_OD_B6_WIDTH 1 #define PORTCON_PORTB_OD_B6_MASK (((1U << PORTCON_PORTB_OD_B6_WIDTH) - 1U) << PORTCON_PORTB_OD_B6_SHIFT) #define PORTCON_PORTB_OD_B6_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B6_BITS_DISABLE (PORTCON_PORTB_OD_B6_VALUE_DISABLE << PORTCON_PORTB_OD_B6_SHIFT) #define PORTCON_PORTB_OD_B6_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B6_BITS_ENABLE (PORTCON_PORTB_OD_B6_VALUE_ENABLE << PORTCON_PORTB_OD_B6_SHIFT) #define PORTCON_PORTB_OD_B7_SHIFT 7 #define PORTCON_PORTB_OD_B7_WIDTH 1 #define PORTCON_PORTB_OD_B7_MASK (((1U << PORTCON_PORTB_OD_B7_WIDTH) - 1U) << PORTCON_PORTB_OD_B7_SHIFT) #define PORTCON_PORTB_OD_B7_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B7_BITS_DISABLE (PORTCON_PORTB_OD_B7_VALUE_DISABLE << PORTCON_PORTB_OD_B7_SHIFT) #define PORTCON_PORTB_OD_B7_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B7_BITS_ENABLE (PORTCON_PORTB_OD_B7_VALUE_ENABLE << PORTCON_PORTB_OD_B7_SHIFT) #define PORTCON_PORTB_OD_B8_SHIFT 8 #define PORTCON_PORTB_OD_B8_WIDTH 1 #define PORTCON_PORTB_OD_B8_MASK (((1U << PORTCON_PORTB_OD_B8_WIDTH) - 1U) << PORTCON_PORTB_OD_B8_SHIFT) #define PORTCON_PORTB_OD_B8_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B8_BITS_DISABLE (PORTCON_PORTB_OD_B8_VALUE_DISABLE << PORTCON_PORTB_OD_B8_SHIFT) #define PORTCON_PORTB_OD_B8_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B8_BITS_ENABLE (PORTCON_PORTB_OD_B8_VALUE_ENABLE << PORTCON_PORTB_OD_B8_SHIFT) #define PORTCON_PORTB_OD_B9_SHIFT 9 #define PORTCON_PORTB_OD_B9_WIDTH 1 #define PORTCON_PORTB_OD_B9_MASK (((1U << PORTCON_PORTB_OD_B9_WIDTH) - 1U) << PORTCON_PORTB_OD_B9_SHIFT) #define PORTCON_PORTB_OD_B9_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B9_BITS_DISABLE (PORTCON_PORTB_OD_B9_VALUE_DISABLE << PORTCON_PORTB_OD_B9_SHIFT) #define PORTCON_PORTB_OD_B9_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B9_BITS_ENABLE (PORTCON_PORTB_OD_B9_VALUE_ENABLE << PORTCON_PORTB_OD_B9_SHIFT) #define PORTCON_PORTB_OD_B10_SHIFT 10 #define PORTCON_PORTB_OD_B10_WIDTH 1 #define PORTCON_PORTB_OD_B10_MASK (((1U << PORTCON_PORTB_OD_B10_WIDTH) - 1U) << PORTCON_PORTB_OD_B10_SHIFT) #define PORTCON_PORTB_OD_B10_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B10_BITS_DISABLE (PORTCON_PORTB_OD_B10_VALUE_DISABLE << PORTCON_PORTB_OD_B10_SHIFT) #define PORTCON_PORTB_OD_B10_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B10_BITS_ENABLE (PORTCON_PORTB_OD_B10_VALUE_ENABLE << PORTCON_PORTB_OD_B10_SHIFT) #define PORTCON_PORTB_OD_B11_SHIFT 11 #define PORTCON_PORTB_OD_B11_WIDTH 1 #define PORTCON_PORTB_OD_B11_MASK (((1U << PORTCON_PORTB_OD_B11_WIDTH) - 1U) << PORTCON_PORTB_OD_B11_SHIFT) #define PORTCON_PORTB_OD_B11_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B11_BITS_DISABLE (PORTCON_PORTB_OD_B11_VALUE_DISABLE << PORTCON_PORTB_OD_B11_SHIFT) #define PORTCON_PORTB_OD_B11_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B11_BITS_ENABLE (PORTCON_PORTB_OD_B11_VALUE_ENABLE << PORTCON_PORTB_OD_B11_SHIFT) #define PORTCON_PORTB_OD_B12_SHIFT 12 #define PORTCON_PORTB_OD_B12_WIDTH 1 #define PORTCON_PORTB_OD_B12_MASK (((1U << PORTCON_PORTB_OD_B12_WIDTH) - 1U) << PORTCON_PORTB_OD_B12_SHIFT) #define PORTCON_PORTB_OD_B12_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B12_BITS_DISABLE (PORTCON_PORTB_OD_B12_VALUE_DISABLE << PORTCON_PORTB_OD_B12_SHIFT) #define PORTCON_PORTB_OD_B12_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B12_BITS_ENABLE (PORTCON_PORTB_OD_B12_VALUE_ENABLE << PORTCON_PORTB_OD_B12_SHIFT) #define PORTCON_PORTB_OD_B13_SHIFT 13 #define PORTCON_PORTB_OD_B13_WIDTH 1 #define PORTCON_PORTB_OD_B13_MASK (((1U << PORTCON_PORTB_OD_B13_WIDTH) - 1U) << PORTCON_PORTB_OD_B13_SHIFT) #define PORTCON_PORTB_OD_B13_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B13_BITS_DISABLE (PORTCON_PORTB_OD_B13_VALUE_DISABLE << PORTCON_PORTB_OD_B13_SHIFT) #define PORTCON_PORTB_OD_B13_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B13_BITS_ENABLE (PORTCON_PORTB_OD_B13_VALUE_ENABLE << PORTCON_PORTB_OD_B13_SHIFT) #define PORTCON_PORTB_OD_B14_SHIFT 14 #define PORTCON_PORTB_OD_B14_WIDTH 1 #define PORTCON_PORTB_OD_B14_MASK (((1U << PORTCON_PORTB_OD_B14_WIDTH) - 1U) << PORTCON_PORTB_OD_B14_SHIFT) #define PORTCON_PORTB_OD_B14_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B14_BITS_DISABLE (PORTCON_PORTB_OD_B14_VALUE_DISABLE << PORTCON_PORTB_OD_B14_SHIFT) #define PORTCON_PORTB_OD_B14_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B14_BITS_ENABLE (PORTCON_PORTB_OD_B14_VALUE_ENABLE << PORTCON_PORTB_OD_B14_SHIFT) #define PORTCON_PORTB_OD_B15_SHIFT 15 #define PORTCON_PORTB_OD_B15_WIDTH 1 #define PORTCON_PORTB_OD_B15_MASK (((1U << PORTCON_PORTB_OD_B15_WIDTH) - 1U) << PORTCON_PORTB_OD_B15_SHIFT) #define PORTCON_PORTB_OD_B15_VALUE_DISABLE 0U #define PORTCON_PORTB_OD_B15_BITS_DISABLE (PORTCON_PORTB_OD_B15_VALUE_DISABLE << PORTCON_PORTB_OD_B15_SHIFT) #define PORTCON_PORTB_OD_B15_VALUE_ENABLE 1U #define PORTCON_PORTB_OD_B15_BITS_ENABLE (PORTCON_PORTB_OD_B15_VALUE_ENABLE << PORTCON_PORTB_OD_B15_SHIFT) #define PORTCON_PORTC_OD_ADDR (PORTCON_BASE_ADDR + 0x0408U) #define PORTCON_PORTC_OD (*(volatile uint32_t *)PORTCON_PORTC_OD_ADDR) #define PORTCON_PORTC_OD_C0_SHIFT 0 #define PORTCON_PORTC_OD_C0_WIDTH 1 #define PORTCON_PORTC_OD_C0_MASK (((1U << PORTCON_PORTC_OD_C0_WIDTH) - 1U) << PORTCON_PORTC_OD_C0_SHIFT) #define PORTCON_PORTC_OD_C0_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C0_BITS_DISABLE (PORTCON_PORTC_OD_C0_VALUE_DISABLE << PORTCON_PORTC_OD_C0_SHIFT) #define PORTCON_PORTC_OD_C0_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C0_BITS_ENABLE (PORTCON_PORTC_OD_C0_VALUE_ENABLE << PORTCON_PORTC_OD_C0_SHIFT) #define PORTCON_PORTC_OD_C1_SHIFT 1 #define PORTCON_PORTC_OD_C1_WIDTH 1 #define PORTCON_PORTC_OD_C1_MASK (((1U << PORTCON_PORTC_OD_C1_WIDTH) - 1U) << PORTCON_PORTC_OD_C1_SHIFT) #define PORTCON_PORTC_OD_C1_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C1_BITS_DISABLE (PORTCON_PORTC_OD_C1_VALUE_DISABLE << PORTCON_PORTC_OD_C1_SHIFT) #define PORTCON_PORTC_OD_C1_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C1_BITS_ENABLE (PORTCON_PORTC_OD_C1_VALUE_ENABLE << PORTCON_PORTC_OD_C1_SHIFT) #define PORTCON_PORTC_OD_C2_SHIFT 2 #define PORTCON_PORTC_OD_C2_WIDTH 1 #define PORTCON_PORTC_OD_C2_MASK (((1U << PORTCON_PORTC_OD_C2_WIDTH) - 1U) << PORTCON_PORTC_OD_C2_SHIFT) #define PORTCON_PORTC_OD_C2_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C2_BITS_DISABLE (PORTCON_PORTC_OD_C2_VALUE_DISABLE << PORTCON_PORTC_OD_C2_SHIFT) #define PORTCON_PORTC_OD_C2_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C2_BITS_ENABLE (PORTCON_PORTC_OD_C2_VALUE_ENABLE << PORTCON_PORTC_OD_C2_SHIFT) #define PORTCON_PORTC_OD_C3_SHIFT 3 #define PORTCON_PORTC_OD_C3_WIDTH 1 #define PORTCON_PORTC_OD_C3_MASK (((1U << PORTCON_PORTC_OD_C3_WIDTH) - 1U) << PORTCON_PORTC_OD_C3_SHIFT) #define PORTCON_PORTC_OD_C3_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C3_BITS_DISABLE (PORTCON_PORTC_OD_C3_VALUE_DISABLE << PORTCON_PORTC_OD_C3_SHIFT) #define PORTCON_PORTC_OD_C3_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C3_BITS_ENABLE (PORTCON_PORTC_OD_C3_VALUE_ENABLE << PORTCON_PORTC_OD_C3_SHIFT) #define PORTCON_PORTC_OD_C4_SHIFT 4 #define PORTCON_PORTC_OD_C4_WIDTH 1 #define PORTCON_PORTC_OD_C4_MASK (((1U << PORTCON_PORTC_OD_C4_WIDTH) - 1U) << PORTCON_PORTC_OD_C4_SHIFT) #define PORTCON_PORTC_OD_C4_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C4_BITS_DISABLE (PORTCON_PORTC_OD_C4_VALUE_DISABLE << PORTCON_PORTC_OD_C4_SHIFT) #define PORTCON_PORTC_OD_C4_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C4_BITS_ENABLE (PORTCON_PORTC_OD_C4_VALUE_ENABLE << PORTCON_PORTC_OD_C4_SHIFT) #define PORTCON_PORTC_OD_C5_SHIFT 5 #define PORTCON_PORTC_OD_C5_WIDTH 1 #define PORTCON_PORTC_OD_C5_MASK (((1U << PORTCON_PORTC_OD_C5_WIDTH) - 1U) << PORTCON_PORTC_OD_C5_SHIFT) #define PORTCON_PORTC_OD_C5_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C5_BITS_DISABLE (PORTCON_PORTC_OD_C5_VALUE_DISABLE << PORTCON_PORTC_OD_C5_SHIFT) #define PORTCON_PORTC_OD_C5_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C5_BITS_ENABLE (PORTCON_PORTC_OD_C5_VALUE_ENABLE << PORTCON_PORTC_OD_C5_SHIFT) #define PORTCON_PORTC_OD_C6_SHIFT 6 #define PORTCON_PORTC_OD_C6_WIDTH 1 #define PORTCON_PORTC_OD_C6_MASK (((1U << PORTCON_PORTC_OD_C6_WIDTH) - 1U) << PORTCON_PORTC_OD_C6_SHIFT) #define PORTCON_PORTC_OD_C6_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C6_BITS_DISABLE (PORTCON_PORTC_OD_C6_VALUE_DISABLE << PORTCON_PORTC_OD_C6_SHIFT) #define PORTCON_PORTC_OD_C6_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C6_BITS_ENABLE (PORTCON_PORTC_OD_C6_VALUE_ENABLE << PORTCON_PORTC_OD_C6_SHIFT) #define PORTCON_PORTC_OD_C7_SHIFT 7 #define PORTCON_PORTC_OD_C7_WIDTH 1 #define PORTCON_PORTC_OD_C7_MASK (((1U << PORTCON_PORTC_OD_C7_WIDTH) - 1U) << PORTCON_PORTC_OD_C7_SHIFT) #define PORTCON_PORTC_OD_C7_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C7_BITS_DISABLE (PORTCON_PORTC_OD_C7_VALUE_DISABLE << PORTCON_PORTC_OD_C7_SHIFT) #define PORTCON_PORTC_OD_C7_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C7_BITS_ENABLE (PORTCON_PORTC_OD_C7_VALUE_ENABLE << PORTCON_PORTC_OD_C7_SHIFT) #define PORTCON_PORTC_OD_C8_SHIFT 8 #define PORTCON_PORTC_OD_C8_WIDTH 1 #define PORTCON_PORTC_OD_C8_MASK (((1U << PORTCON_PORTC_OD_C8_WIDTH) - 1U) << PORTCON_PORTC_OD_C8_SHIFT) #define PORTCON_PORTC_OD_C8_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C8_BITS_DISABLE (PORTCON_PORTC_OD_C8_VALUE_DISABLE << PORTCON_PORTC_OD_C8_SHIFT) #define PORTCON_PORTC_OD_C8_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C8_BITS_ENABLE (PORTCON_PORTC_OD_C8_VALUE_ENABLE << PORTCON_PORTC_OD_C8_SHIFT) #define PORTCON_PORTC_OD_C9_SHIFT 9 #define PORTCON_PORTC_OD_C9_WIDTH 1 #define PORTCON_PORTC_OD_C9_MASK (((1U << PORTCON_PORTC_OD_C9_WIDTH) - 1U) << PORTCON_PORTC_OD_C9_SHIFT) #define PORTCON_PORTC_OD_C9_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C9_BITS_DISABLE (PORTCON_PORTC_OD_C9_VALUE_DISABLE << PORTCON_PORTC_OD_C9_SHIFT) #define PORTCON_PORTC_OD_C9_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C9_BITS_ENABLE (PORTCON_PORTC_OD_C9_VALUE_ENABLE << PORTCON_PORTC_OD_C9_SHIFT) #define PORTCON_PORTC_OD_C10_SHIFT 10 #define PORTCON_PORTC_OD_C10_WIDTH 1 #define PORTCON_PORTC_OD_C10_MASK (((1U << PORTCON_PORTC_OD_C10_WIDTH) - 1U) << PORTCON_PORTC_OD_C10_SHIFT) #define PORTCON_PORTC_OD_C10_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C10_BITS_DISABLE (PORTCON_PORTC_OD_C10_VALUE_DISABLE << PORTCON_PORTC_OD_C10_SHIFT) #define PORTCON_PORTC_OD_C10_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C10_BITS_ENABLE (PORTCON_PORTC_OD_C10_VALUE_ENABLE << PORTCON_PORTC_OD_C10_SHIFT) #define PORTCON_PORTC_OD_C11_SHIFT 11 #define PORTCON_PORTC_OD_C11_WIDTH 1 #define PORTCON_PORTC_OD_C11_MASK (((1U << PORTCON_PORTC_OD_C11_WIDTH) - 1U) << PORTCON_PORTC_OD_C11_SHIFT) #define PORTCON_PORTC_OD_C11_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C11_BITS_DISABLE (PORTCON_PORTC_OD_C11_VALUE_DISABLE << PORTCON_PORTC_OD_C11_SHIFT) #define PORTCON_PORTC_OD_C11_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C11_BITS_ENABLE (PORTCON_PORTC_OD_C11_VALUE_ENABLE << PORTCON_PORTC_OD_C11_SHIFT) #define PORTCON_PORTC_OD_C12_SHIFT 12 #define PORTCON_PORTC_OD_C12_WIDTH 1 #define PORTCON_PORTC_OD_C12_MASK (((1U << PORTCON_PORTC_OD_C12_WIDTH) - 1U) << PORTCON_PORTC_OD_C12_SHIFT) #define PORTCON_PORTC_OD_C12_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C12_BITS_DISABLE (PORTCON_PORTC_OD_C12_VALUE_DISABLE << PORTCON_PORTC_OD_C12_SHIFT) #define PORTCON_PORTC_OD_C12_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C12_BITS_ENABLE (PORTCON_PORTC_OD_C12_VALUE_ENABLE << PORTCON_PORTC_OD_C12_SHIFT) #define PORTCON_PORTC_OD_C13_SHIFT 13 #define PORTCON_PORTC_OD_C13_WIDTH 1 #define PORTCON_PORTC_OD_C13_MASK (((1U << PORTCON_PORTC_OD_C13_WIDTH) - 1U) << PORTCON_PORTC_OD_C13_SHIFT) #define PORTCON_PORTC_OD_C13_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C13_BITS_DISABLE (PORTCON_PORTC_OD_C13_VALUE_DISABLE << PORTCON_PORTC_OD_C13_SHIFT) #define PORTCON_PORTC_OD_C13_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C13_BITS_ENABLE (PORTCON_PORTC_OD_C13_VALUE_ENABLE << PORTCON_PORTC_OD_C13_SHIFT) #define PORTCON_PORTC_OD_C14_SHIFT 14 #define PORTCON_PORTC_OD_C14_WIDTH 1 #define PORTCON_PORTC_OD_C14_MASK (((1U << PORTCON_PORTC_OD_C14_WIDTH) - 1U) << PORTCON_PORTC_OD_C14_SHIFT) #define PORTCON_PORTC_OD_C14_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C14_BITS_DISABLE (PORTCON_PORTC_OD_C14_VALUE_DISABLE << PORTCON_PORTC_OD_C14_SHIFT) #define PORTCON_PORTC_OD_C14_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C14_BITS_ENABLE (PORTCON_PORTC_OD_C14_VALUE_ENABLE << PORTCON_PORTC_OD_C14_SHIFT) #define PORTCON_PORTC_OD_C15_SHIFT 15 #define PORTCON_PORTC_OD_C15_WIDTH 1 #define PORTCON_PORTC_OD_C15_MASK (((1U << PORTCON_PORTC_OD_C15_WIDTH) - 1U) << PORTCON_PORTC_OD_C15_SHIFT) #define PORTCON_PORTC_OD_C15_VALUE_DISABLE 0U #define PORTCON_PORTC_OD_C15_BITS_DISABLE (PORTCON_PORTC_OD_C15_VALUE_DISABLE << PORTCON_PORTC_OD_C15_SHIFT) #define PORTCON_PORTC_OD_C15_VALUE_ENABLE 1U #define PORTCON_PORTC_OD_C15_BITS_ENABLE (PORTCON_PORTC_OD_C15_VALUE_ENABLE << PORTCON_PORTC_OD_C15_SHIFT) #endif ================================================ FILE: bsp/dp32g030/pwmplus.h ================================================ #ifndef HARDWARE_DP32G030_PWMPLUS_H #define HARDWARE_DP32G030_PWMPLUS_H #define PWM_PLUS0_BASE_ADDR 0x400B4000U //--------------- #define PWMPLUS_CFG 0x00U #define PWMPLUS_CFG_COUNTER_EN_SHIFT 0U #define PWMPLUS_CFG_COUNTER_EN_WIDTH 1U #define PWMPLUS_CFG_COUNTER_EN_MASK (((1U << PWMPLUS_CFG_COUNTER_EN_WIDTH) - 1U) << PWMPLUS_CFG_COUNTER_EN_SHIFT) #define PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE 1U #define PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE (PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE << PWMPLUS_CFG_COUNTER_EN_SHIFT) #define PWMPLUS_CFG_CNT_TYPE_SHIFT 1U #define PWMPLUS_CFG_CNT_REP_SHIFT 2U #define PWMPLUS_CFG_CNT_REP_WIDTH 1U #define PWMPLUS_CFG_CNT_REP_VALUE_ENABLE 1U #define PWMPLUS_CFG_CNT_REP_BITS_ENABLE (PWMPLUS_CFG_CNT_REP_VALUE_ENABLE << PWMPLUS_CFG_CNT_REP_SHIFT) #define PWMPLUS_CFG_OUT_MODE_SHIFT 3U #define PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE 1U #define PWMPLUS_CFG_OUT_MODE_BITS_ENABLE (PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE << PWMPLUS_CFG_OUT_MODE_SHIFT) #define PWMPLUS_CFG_AUTO_RELOAD_SHIFT 8U //--------------- #define PWMPLUS_GEN 0x04U #define PWMPLUS_GEN_CH0_OE_SHIFT 24U #define PWMPLUS_GEN_CH0_OE_WIDTH 1U #define PWMPLUS_GEN_CH0_OE_VALUE_ENABLE 1U #define PWMPLUS_GEN_CH0_OE_BITS_ENABLE (PWMPLUS_GEN_CH0_OE_VALUE_ENABLE << PWMPLUS_GEN_CH0_OE_SHIFT) #define PWMPLUS_GEN_CH0_OUTINV_SHIFT 16U #define PWMPLUS_GEN_CH0_OUTINV_WIDTH 1U #define PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE 1U #define PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE (PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE << PWMPLUS_GEN_CH0_OUTINV_SHIFT) #define PWMPLUS_GEN_CH0_START_SHIFT 8U #define PWMPLUS_GEN_CH0_START_WIDTH 1U #define PWMPLUS_GEN_CH0_START_VALUE_ENABLE 1U #define PWMPLUS_GEN_CH0_START_BITS_ENABLE (PWMPLUS_GEN_CH0_START_VALUE_ENABLE << PWMPLUS_GEN_CH0_START_SHIFT) #define PWMPLUS_GEN_CH0_IDLE_SHIFT 0U #define PWMPLUS_GEN_CH0_IDLE_WIDTH 1U #define PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE 1U #define PWMPLUS_GEN_CH0_IDLE_BITS_ENABLE (PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE << PWMPLUS_GEN_CH0_IDLE_SHIFT) //--------------- #define PWMPLUS_CLKSRC 0x08U #define PWMPLUS_BRAKE_CFG 0x0CU #define PWMPLUS_MASK_LEV 0x10U #define PWMPLUS_PERIOD 0x1CU #define PWMPLUS_CH0_COMP 0x20U #define PWMPLUS_CH1_COMP 0x24U #define PWMPLUS_CH2_COMP 0x28U #define PWMPLUS_CH0_DT 0x30U #define PWMPLUS_CH1_DT 0x34U #define PWMPLUS_CH2_DT 0x38U #define PWMPLUS_TRIG_COMP 0x40U #define PWMPLUS_TRIG_CFG 0x44U #define PWMPLUS_IE 0x60U #define PWMPLUS_IF 0x64U #define PWMPLUS_SWLOAD 0x84U #define PWMPLUS_MASK_EN 0x88 #define PWMPLUS_CNT_ST 0xE0 #define PWMPLUS_BRAKE_ST 0xE4 #define PWM_PLUS0_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CFG) #define PWM_PLUS0_CFG (*(volatile uint32_t *)PWM_PLUS0_CFG_ADDR) #define PWM_PLUS0_GEN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_GEN) #define PWM_PLUS0_GEN (*(volatile uint32_t *)PWM_PLUS0_GEN_ADDR) #define PWM_PLUS0_CLKSRC_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CLKSRC) #define PWM_PLUS0_CLKSRC (*(volatile uint32_t *)PWM_PLUS0_CLKSRC_ADDR) #define PWM_PLUS0_BRAKE_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_CFG) #define PWM_PLUS0_BRAKE_CFG (*(volatile uint32_t *)PWM_PLUS0_BRAKE_CFG_ADDR) #define PWM_PLUS0_MASK_LEV_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_LEV) #define PWM_PLUS0_MASK_LEV (*(volatile uint32_t *)PWM_PLUS0_MASK_LEV_ADDR) #define PWM_PLUS0_PERIOD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_PERIOD) #define PWM_PLUS0_PERIOD (*(volatile uint32_t *)PWM_PLUS0_PERIOD_ADDR) #define PWM_PLUS0_CH0_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_COMP) #define PWM_PLUS0_CH0_COMP (*(volatile uint32_t *)PWM_PLUS0_CH0_COMP_ADDR) #define PWM_PLUS0_CH1_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_COMP) #define PWM_PLUS0_CH1_COMP (*(volatile uint32_t *)PWM_PLUS0_CH1_COMP_ADDR) #define PWM_PLUS0_CH2_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_COMP) #define PWM_PLUS0_CH2_COMP (*(volatile uint32_t *)PWM_PLUS0_CH2_COMP_ADDR) #define PWM_PLUS0_CH0_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_DT) #define PWM_PLUS0_CH0_DT (*(volatile uint32_t *)PWM_PLUS0_CH0_DT_ADDR) #define PWM_PLUS0_CH1_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_DT) #define PWM_PLUS0_CH1_DT (*(volatile uint32_t *)PWM_PLUS0_CH1_DT_ADDR) #define PWM_PLUS0_CH2_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_DT) #define PWM_PLUS0_CH2_DT (*(volatile uint32_t *)PWM_PLUS0_CH2_DT_ADDR) #define PWM_PLUS0_TRIG_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_COMP) #define PWM_PLUS0_TRIG_COMP (*(volatile uint32_t *)PWM_PLUS0_TRIG_COMP_ADDR) #define PWM_PLUS0_TRIG_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_CFG) #define PWM_PLUS0_TRIG_CFG (*(volatile uint32_t *)PWM_PLUS0_TRIG_CFG_ADDR) #define PWM_PLUS0_IE_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IE) #define PWM_PLUS0_IE (*(volatile uint32_t *)PWM_PLUS0_IE_ADDR) #define PWM_PLUS0_IF_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IF) #define PWM_PLUS0_IF (*(volatile uint32_t *)PWM_PLUS0_IF_ADDR) #define PWM_PLUS0_SWLOAD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_SWLOAD) #define PWM_PLUS0_SWLOAD (*(volatile uint32_t *)PWM_PLUS0_SWLOAD_ADDR) #define PWM_PLUS0_MASK_EN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_EN) #define PWM_PLUS0_MASK_EN (*(volatile uint32_t *)PWM_PLUS0_MASK_EN_ADDR) #define PWM_PLUS0_CNT_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CNT_ST) #define PWM_PLUS0_CNT_ST (*(volatile uint32_t *)PWM_PLUS0_CNT_ST_ADDR) #define PWM_PLUS0_BRAKE_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_ST) #define PWM_PLUS0_BRAKE_ST (*(volatile uint32_t *)PWM_PLUS0_BRAKE_ST_ADDR) #endif ================================================ FILE: bsp/dp32g030/rtc.h ================================================ // // Created by RUPC on 2024/1/30. // #ifndef HARDWARE_DP32G030_RTC_H #define HARDWARE_DP32G030_RTC_H #include //RCLF 32768HZ #define RTC_BASE_ADD 0x40069000 #define RTC_CFG_ADD (0x00+RTC_BASE_ADD) //配置寄存器 #define RTC_IE_ADD (0x04+RTC_BASE_ADD) //中断使能寄存器 #define RTC_IF_ADD (0x08+RTC_BASE_ADD)// 状态寄存器 #define RTC_PRE_ADD (0x10+RTC_BASE_ADD) // 预分频寄存器 #define RTC_TR_ADD (0x14+RTC_BASE_ADD) //时间寄存器 #define RTC_DR_ADD (0x18+RTC_BASE_ADD) // 日期寄存器 #define RTC_AR_ADD (0x1C+RTC_BASE_ADD) //闹钟寄存器 #define RTC_TSTR_ADD (0x20+RTC_BASE_ADD) //当前时间寄存器 #define RTC_TSDR_ADD (0x24+RTC_BASE_ADD) // 当前日期寄存器 #define RTC_CNT_ADD (0x28+RTC_BASE_ADD) // 秒标当前计数值 #define RTC_VALID_ADD (0x2C+RTC_BASE_ADD) //当前时间有效标志寄存器 #define RTC_CFG (*(volatile uint32_t *)RTC_CFG_ADD) //配置寄存器 #define RTC_IE (*(volatile uint32_t *)RTC_IE_ADD) //中断使能寄存器 #define RTC_IF (*(volatile uint32_t *)RTC_IF_ADD)// 状态寄存器 #define RTC_PRE (*(volatile uint32_t *)RTC_PRE_ADD) // 预分频寄存器 #define RTC_TR (*(volatile uint32_t *)RTC_TR_ADD) //时间寄存器 #define RTC_DR (*(volatile uint32_t *)RTC_DR_ADD) // 日期寄存器 #define RTC_AR (*(volatile uint32_t *)RTC_AR_ADD) //闹钟寄存器 #define RTC_TSTR (*(volatile uint32_t *)RTC_TSTR_ADD) //当前时间寄存器 #define RTC_TSDR (*(volatile uint32_t *)RTC_TSDR_ADD) // 当前日期寄存器 #define RTC_CNT (*(volatile uint32_t *)RTC_CNT_ADD) // 秒标当前计数值 #define RTC_VALID (*(volatile uint32_t *)RTC_VALID_ADD) //当前时间有效标志寄存器 #define RC_FREQ_DELTA (*(volatile uint32_t *)(0x40000000u+0x78u)) #define TRIM_RCLF (*(volatile uint32_t *)(0x40000800u+0x34u)) #define TEMP1 (*(volatile uint32_t *)(0x40000800u+0x20u)) #define TEMP2 (*(volatile uint32_t *)(0x40000800u+0x24u)) void RTC_INIT(void); void RTC_Set( ); void RTC_Get(); extern uint8_t time[6]; #endif ================================================ FILE: bsp/dp32g030/saradc.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_SARADC_H #define HARDWARE_DP32G030_SARADC_H #if !defined(__ASSEMBLY__) #include #endif /* -------- SARADC -------- */ #define SARADC_BASE_ADDR 0x400BA000U #define SARADC_BASE_SIZE 0x00000800U #define SARADC_CFG_ADDR (SARADC_BASE_ADDR + 0x0000U) #define SARADC_CFG (*(volatile uint32_t *)SARADC_CFG_ADDR) #define SARADC_CFG_CH_SEL_SHIFT 0 #define SARADC_CFG_CH_SEL_WIDTH 15 #define SARADC_CFG_CH_SEL_MASK (((1U << SARADC_CFG_CH_SEL_WIDTH) - 1U) << SARADC_CFG_CH_SEL_SHIFT) #define SARADC_CFG_AVG_SHIFT 16 #define SARADC_CFG_AVG_WIDTH 2 #define SARADC_CFG_AVG_MASK (((1U << SARADC_CFG_AVG_WIDTH) - 1U) << SARADC_CFG_AVG_SHIFT) #define SARADC_CFG_AVG_VALUE_1_SAMPLE 0U #define SARADC_CFG_AVG_BITS_1_SAMPLE (SARADC_CFG_AVG_VALUE_1_SAMPLE << SARADC_CFG_AVG_SHIFT) #define SARADC_CFG_AVG_VALUE_2_SAMPLE 1U #define SARADC_CFG_AVG_BITS_2_SAMPLE (SARADC_CFG_AVG_VALUE_2_SAMPLE << SARADC_CFG_AVG_SHIFT) #define SARADC_CFG_AVG_VALUE_4_SAMPLE 2U #define SARADC_CFG_AVG_BITS_4_SAMPLE (SARADC_CFG_AVG_VALUE_4_SAMPLE << SARADC_CFG_AVG_SHIFT) #define SARADC_CFG_AVG_VALUE_8_SAMPLE 3U #define SARADC_CFG_AVG_BITS_8_SAMPLE (SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT) #define SARADC_CFG_CONT_SHIFT 18 #define SARADC_CFG_CONT_WIDTH 1 #define SARADC_CFG_CONT_MASK (((1U << SARADC_CFG_CONT_WIDTH) - 1U) << SARADC_CFG_CONT_SHIFT) #define SARADC_CFG_CONT_VALUE_SINGLE 0U #define SARADC_CFG_CONT_BITS_SINGLE (SARADC_CFG_CONT_VALUE_SINGLE << SARADC_CFG_CONT_SHIFT) #define SARADC_CFG_CONT_VALUE_CONTINUOUS 1U #define SARADC_CFG_CONT_BITS_CONTINUOUS (SARADC_CFG_CONT_VALUE_CONTINUOUS << SARADC_CFG_CONT_SHIFT) #define SARADC_CFG_SMPL_SETUP_SHIFT 19 #define SARADC_CFG_SMPL_SETUP_WIDTH 3 #define SARADC_CFG_SMPL_SETUP_MASK (((1U << SARADC_CFG_SMPL_SETUP_WIDTH) - 1U) << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE 0U #define SARADC_CFG_SMPL_SETUP_BITS_1_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE 1U #define SARADC_CFG_SMPL_SETUP_BITS_2_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE 2U #define SARADC_CFG_SMPL_SETUP_BITS_4_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE 3U #define SARADC_CFG_SMPL_SETUP_BITS_8_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE 4U #define SARADC_CFG_SMPL_SETUP_BITS_16_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE 5U #define SARADC_CFG_SMPL_SETUP_BITS_32_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE 6U #define SARADC_CFG_SMPL_SETUP_BITS_64_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE 7U #define SARADC_CFG_SMPL_SETUP_BITS_128_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) #define SARADC_CFG_MEM_MODE_SHIFT 22 #define SARADC_CFG_MEM_MODE_WIDTH 1 #define SARADC_CFG_MEM_MODE_MASK (((1U << SARADC_CFG_MEM_MODE_WIDTH) - 1U) << SARADC_CFG_MEM_MODE_SHIFT) #define SARADC_CFG_MEM_MODE_VALUE_FIFO 0U #define SARADC_CFG_MEM_MODE_BITS_FIFO (SARADC_CFG_MEM_MODE_VALUE_FIFO << SARADC_CFG_MEM_MODE_SHIFT) #define SARADC_CFG_MEM_MODE_VALUE_CHANNEL 1U #define SARADC_CFG_MEM_MODE_BITS_CHANNEL (SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT) #define SARADC_CFG_SMPL_CLK_SHIFT 23 #define SARADC_CFG_SMPL_CLK_WIDTH 1 #define SARADC_CFG_SMPL_CLK_MASK (((1U << SARADC_CFG_SMPL_CLK_WIDTH) - 1U) << SARADC_CFG_SMPL_CLK_SHIFT) #define SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL 0U #define SARADC_CFG_SMPL_CLK_BITS_EXTERNAL (SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL << SARADC_CFG_SMPL_CLK_SHIFT) #define SARADC_CFG_SMPL_CLK_VALUE_INTERNAL 1U #define SARADC_CFG_SMPL_CLK_BITS_INTERNAL (SARADC_CFG_SMPL_CLK_VALUE_INTERNAL << SARADC_CFG_SMPL_CLK_SHIFT) #define SARADC_CFG_SMPL_WIN_SHIFT 24 #define SARADC_CFG_SMPL_WIN_WIDTH 3 #define SARADC_CFG_SMPL_WIN_MASK (((1U << SARADC_CFG_SMPL_WIN_WIDTH) - 1U) << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE 0U #define SARADC_CFG_SMPL_WIN_BITS_1_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE 1U #define SARADC_CFG_SMPL_WIN_BITS_3_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE 2U #define SARADC_CFG_SMPL_WIN_BITS_5_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE 3U #define SARADC_CFG_SMPL_WIN_BITS_7_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE 4U #define SARADC_CFG_SMPL_WIN_BITS_9_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE 5U #define SARADC_CFG_SMPL_WIN_BITS_11_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE 6U #define SARADC_CFG_SMPL_WIN_BITS_13_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE 7U #define SARADC_CFG_SMPL_WIN_BITS_15_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) #define SARADC_CFG_ADC_EN_SHIFT 27 #define SARADC_CFG_ADC_EN_WIDTH 1 #define SARADC_CFG_ADC_EN_MASK (((1U << SARADC_CFG_ADC_EN_WIDTH) - 1U) << SARADC_CFG_ADC_EN_SHIFT) #define SARADC_CFG_ADC_EN_VALUE_DISABLE 0U #define SARADC_CFG_ADC_EN_BITS_DISABLE (SARADC_CFG_ADC_EN_VALUE_DISABLE << SARADC_CFG_ADC_EN_SHIFT) #define SARADC_CFG_ADC_EN_VALUE_ENABLE 1U #define SARADC_CFG_ADC_EN_BITS_ENABLE (SARADC_CFG_ADC_EN_VALUE_ENABLE << SARADC_CFG_ADC_EN_SHIFT) #define SARADC_CFG_ADC_TRIG_SHIFT 28 #define SARADC_CFG_ADC_TRIG_WIDTH 1 #define SARADC_CFG_ADC_TRIG_MASK (((1U << SARADC_CFG_ADC_TRIG_WIDTH) - 1U) << SARADC_CFG_ADC_TRIG_SHIFT) #define SARADC_CFG_ADC_TRIG_VALUE_CPU 0U #define SARADC_CFG_ADC_TRIG_BITS_CPU (SARADC_CFG_ADC_TRIG_VALUE_CPU << SARADC_CFG_ADC_TRIG_SHIFT) #define SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL 1U #define SARADC_CFG_ADC_TRIG_BITS_EXTERNAL (SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL << SARADC_CFG_ADC_TRIG_SHIFT) #define SARADC_CFG_DMA_EN_SHIFT 29 #define SARADC_CFG_DMA_EN_WIDTH 1 #define SARADC_CFG_DMA_EN_MASK (((1U << SARADC_CFG_DMA_EN_WIDTH) - 1U) << SARADC_CFG_DMA_EN_SHIFT) #define SARADC_CFG_DMA_EN_VALUE_DISABLE 0U #define SARADC_CFG_DMA_EN_BITS_DISABLE (SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT) #define SARADC_CFG_DMA_EN_VALUE_ENABLE 1U #define SARADC_CFG_DMA_EN_BITS_ENABLE (SARADC_CFG_DMA_EN_VALUE_ENABLE << SARADC_CFG_DMA_EN_SHIFT) #define SARADC_START_ADDR (SARADC_BASE_ADDR + 0x0004U) #define SARADC_START (*(volatile uint32_t *)SARADC_START_ADDR) #define SARADC_START_START_SHIFT 0 #define SARADC_START_START_WIDTH 1 #define SARADC_START_START_MASK (((1U << SARADC_START_START_WIDTH) - 1U) << SARADC_START_START_SHIFT) #define SARADC_START_START_VALUE_DISABLE 0U #define SARADC_START_START_BITS_DISABLE (SARADC_START_START_VALUE_DISABLE << SARADC_START_START_SHIFT) #define SARADC_START_START_VALUE_ENABLE 1U #define SARADC_START_START_BITS_ENABLE (SARADC_START_START_VALUE_ENABLE << SARADC_START_START_SHIFT) #define SARADC_START_SOFT_RESET_SHIFT 2 #define SARADC_START_SOFT_RESET_WIDTH 1 #define SARADC_START_SOFT_RESET_MASK (((1U << SARADC_START_SOFT_RESET_WIDTH) - 1U) << SARADC_START_SOFT_RESET_SHIFT) #define SARADC_START_SOFT_RESET_VALUE_ASSERT 0U #define SARADC_START_SOFT_RESET_BITS_ASSERT (SARADC_START_SOFT_RESET_VALUE_ASSERT << SARADC_START_SOFT_RESET_SHIFT) #define SARADC_START_SOFT_RESET_VALUE_DEASSERT 1U #define SARADC_START_SOFT_RESET_BITS_DEASSERT (SARADC_START_SOFT_RESET_VALUE_DEASSERT << SARADC_START_SOFT_RESET_SHIFT) #define SARADC_IE_ADDR (SARADC_BASE_ADDR + 0x0008U) #define SARADC_IE (*(volatile uint32_t *)SARADC_IE_ADDR) #define SARADC_IE_CHx_EOC_SHIFT 0 #define SARADC_IE_CHx_EOC_WIDTH 16 #define SARADC_IE_CHx_EOC_MASK (((1U << SARADC_IE_CHx_EOC_WIDTH) - 1U) << SARADC_IE_CHx_EOC_SHIFT) #define SARADC_IE_CHx_EOC_VALUE_NONE 0U #define SARADC_IE_CHx_EOC_BITS_NONE (SARADC_IE_CHx_EOC_VALUE_NONE << SARADC_IE_CHx_EOC_SHIFT) #define SARADC_IE_CHx_EOC_VALUE_ALL 65535U #define SARADC_IE_CHx_EOC_BITS_ALL (SARADC_IE_CHx_EOC_VALUE_ALL << SARADC_IE_CHx_EOC_SHIFT) #define SARADC_IE_FIFO_FULL_SHIFT 16 #define SARADC_IE_FIFO_FULL_WIDTH 1 #define SARADC_IE_FIFO_FULL_MASK (((1U << SARADC_IE_FIFO_FULL_WIDTH) - 1U) << SARADC_IE_FIFO_FULL_SHIFT) #define SARADC_IE_FIFO_FULL_VALUE_DISABLE 0U #define SARADC_IE_FIFO_FULL_BITS_DISABLE (SARADC_IE_FIFO_FULL_VALUE_DISABLE << SARADC_IE_FIFO_FULL_SHIFT) #define SARADC_IE_FIFO_FULL_VALUE_ENABLE 1U #define SARADC_IE_FIFO_FULL_BITS_ENABLE (SARADC_IE_FIFO_FULL_VALUE_ENABLE << SARADC_IE_FIFO_FULL_SHIFT) #define SARADC_IE_FIFO_HFULL_SHIFT 17 #define SARADC_IE_FIFO_HFULL_WIDTH 1 #define SARADC_IE_FIFO_HFULL_MASK (((1U << SARADC_IE_FIFO_HFULL_WIDTH) - 1U) << SARADC_IE_FIFO_HFULL_SHIFT) #define SARADC_IE_FIFO_HFULL_VALUE_DISABLE 0U #define SARADC_IE_FIFO_HFULL_BITS_DISABLE (SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT) #define SARADC_IE_FIFO_HFULL_VALUE_ENABLE 1U #define SARADC_IE_FIFO_HFULL_BITS_ENABLE (SARADC_IE_FIFO_HFULL_VALUE_ENABLE << SARADC_IE_FIFO_HFULL_SHIFT) #define SARADC_IF_ADDR (SARADC_BASE_ADDR + 0x000CU) #define SARADC_IF (*(volatile uint32_t *)SARADC_IF_ADDR) #define SARADC_IF_CHx_EOC_SHIFT 0 #define SARADC_IF_CHx_EOC_WIDTH 16 #define SARADC_IF_CHx_EOC_MASK (((1U << SARADC_IF_CHx_EOC_WIDTH) - 1U) << SARADC_IF_CHx_EOC_SHIFT) #define SARADC_IF_FIFO_FULL_SHIFT 16 #define SARADC_IF_FIFO_FULL_WIDTH 1 #define SARADC_IF_FIFO_FULL_MASK (((1U << SARADC_IF_FIFO_FULL_WIDTH) - 1U) << SARADC_IF_FIFO_FULL_SHIFT) #define SARADC_IF_FIFO_FULL_VALUE_NOT_SET 0U #define SARADC_IF_FIFO_FULL_BITS_NOT_SET (SARADC_IF_FIFO_FULL_VALUE_NOT_SET << SARADC_IF_FIFO_FULL_SHIFT) #define SARADC_IF_FIFO_FULL_VALUE_SET 1U #define SARADC_IF_FIFO_FULL_BITS_SET (SARADC_IF_FIFO_FULL_VALUE_SET << SARADC_IF_FIFO_FULL_SHIFT) #define SARADC_IF_FIFO_HFULL_SHIFT 17 #define SARADC_IF_FIFO_HFULL_WIDTH 1 #define SARADC_IF_FIFO_HFULL_MASK (((1U << SARADC_IF_FIFO_HFULL_WIDTH) - 1U) << SARADC_IF_FIFO_HFULL_SHIFT) #define SARADC_IF_FIFO_HFULL_VALUE_NOT_SET 0U #define SARADC_IF_FIFO_HFULL_BITS_NOT_SET (SARADC_IF_FIFO_HFULL_VALUE_NOT_SET << SARADC_IF_FIFO_HFULL_SHIFT) #define SARADC_IF_FIFO_HFULL_VALUE_SET 1U #define SARADC_IF_FIFO_HFULL_BITS_SET (SARADC_IF_FIFO_HFULL_VALUE_SET << SARADC_IF_FIFO_HFULL_SHIFT) #define SARADC_CH0_ADDR (SARADC_BASE_ADDR + 0x0010U) #define SARADC_CH0 (*(volatile uint32_t *)SARADC_CH0_ADDR) #define SARADC_EXTTRIG_SEL_ADDR (SARADC_BASE_ADDR + 0x00B0U) #define SARADC_EXTTRIG_SEL (*(volatile uint32_t *)SARADC_EXTTRIG_SEL_ADDR) #define SARADC_CALIB_OFFSET_ADDR (SARADC_BASE_ADDR + 0x00F0U) #define SARADC_CALIB_OFFSET (*(volatile uint32_t *)SARADC_CALIB_OFFSET_ADDR) #define SARADC_CALIB_OFFSET_OFFSET_SHIFT 0 #define SARADC_CALIB_OFFSET_OFFSET_WIDTH 8 #define SARADC_CALIB_OFFSET_OFFSET_MASK (((1U << SARADC_CALIB_OFFSET_OFFSET_WIDTH) - 1U) << SARADC_CALIB_OFFSET_OFFSET_SHIFT) #define SARADC_CALIB_OFFSET_VALID_SHIFT 16 #define SARADC_CALIB_OFFSET_VALID_WIDTH 1 #define SARADC_CALIB_OFFSET_VALID_MASK (((1U << SARADC_CALIB_OFFSET_VALID_WIDTH) - 1U) << SARADC_CALIB_OFFSET_VALID_SHIFT) #define SARADC_CALIB_OFFSET_VALID_VALUE_NO 0U #define SARADC_CALIB_OFFSET_VALID_BITS_NO (SARADC_CALIB_OFFSET_VALID_VALUE_NO << SARADC_CALIB_OFFSET_VALID_SHIFT) #define SARADC_CALIB_OFFSET_VALID_VALUE_YES 1U #define SARADC_CALIB_OFFSET_VALID_BITS_YES (SARADC_CALIB_OFFSET_VALID_VALUE_YES << SARADC_CALIB_OFFSET_VALID_SHIFT) #define SARADC_CALIB_KD_ADDR (SARADC_BASE_ADDR + 0x00F4U) #define SARADC_CALIB_KD (*(volatile uint32_t *)SARADC_CALIB_KD_ADDR) #define SARADC_CALIB_KD_KD_SHIFT 0 #define SARADC_CALIB_KD_KD_WIDTH 8 #define SARADC_CALIB_KD_KD_MASK (((1U << SARADC_CALIB_KD_KD_WIDTH) - 1U) << SARADC_CALIB_KD_KD_SHIFT) #define SARADC_CALIB_KD_VALID_SHIFT 16 #define SARADC_CALIB_KD_VALID_WIDTH 1 #define SARADC_CALIB_KD_VALID_MASK (((1U << SARADC_CALIB_KD_VALID_WIDTH) - 1U) << SARADC_CALIB_KD_VALID_SHIFT) #define SARADC_CALIB_KD_VALID_VALUE_NO 0U #define SARADC_CALIB_KD_VALID_BITS_NO (SARADC_CALIB_KD_VALID_VALUE_NO << SARADC_CALIB_KD_VALID_SHIFT) #define SARADC_CALIB_KD_VALID_VALUE_YES 1U #define SARADC_CALIB_KD_VALID_BITS_YES (SARADC_CALIB_KD_VALID_VALUE_YES << SARADC_CALIB_KD_VALID_SHIFT) /* -------- ADC_CHx -------- */ typedef struct { uint32_t STAT; uint32_t DATA; } ADC_Channel_t; #define ADC_CHx_STAT_EOC_SHIFT 0 #define ADC_CHx_STAT_EOC_WIDTH 1 #define ADC_CHx_STAT_EOC_MASK (((1U << ADC_CHx_STAT_EOC_WIDTH) - 1U) << ADC_CHx_STAT_EOC_SHIFT) #define ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE 0U #define ADC_CHx_STAT_EOC_BITS_NOT_COMPLETE (ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE << ADC_CHx_STAT_EOC_SHIFT) #define ADC_CHx_STAT_EOC_VALUE_COMPLETE 1U #define ADC_CHx_STAT_EOC_BITS_COMPLETE (ADC_CHx_STAT_EOC_VALUE_COMPLETE << ADC_CHx_STAT_EOC_SHIFT) #define ADC_CHx_DATA_DATA_SHIFT 0 #define ADC_CHx_DATA_DATA_WIDTH 12 #define ADC_CHx_DATA_DATA_MASK (((1U << ADC_CHx_DATA_DATA_WIDTH) - 1U) << ADC_CHx_DATA_DATA_SHIFT) #define ADC_CHx_DATA_NUM_SHIFT 12 #define ADC_CHx_DATA_NUM_WIDTH 4 #define ADC_CHx_DATA_NUM_MASK (((1U << ADC_CHx_DATA_NUM_WIDTH) - 1U) << ADC_CHx_DATA_NUM_SHIFT) #endif ================================================ FILE: bsp/dp32g030/spi.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_SPI_H #define HARDWARE_DP32G030_SPI_H #if !defined(__ASSEMBLY__) #include #endif /* -------- SPI0 -------- */ #define SPI0_BASE_ADDR 0x400B8000U #define SPI0_BASE_SIZE 0x00000800U #define SPI0 ((volatile SPI_Port_t *)SPI0_BASE_ADDR) /* -------- SPI1 -------- */ #define SPI1_BASE_ADDR 0x400B8800U #define SPI1_BASE_SIZE 0x00000800U #define SPI1 ((volatile SPI_Port_t *)SPI1_BASE_ADDR) /* -------- SPI -------- */ typedef struct { uint32_t CR; uint32_t WDR; uint32_t RDR; uint32_t Reserved_000C[1]; uint32_t IE; uint32_t IF; uint32_t FIFOST; } SPI_Port_t; #define SPI_CR_SPR_SHIFT 0 #define SPI_CR_SPR_WIDTH 3 #define SPI_CR_SPR_MASK (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_4 0U #define SPI_CR_SPR_BITS_FPCLK_DIV_4 (SPI_CR_SPR_VALUE_FPCLK_DIV_4 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_8 1U #define SPI_CR_SPR_BITS_FPCLK_DIV_8 (SPI_CR_SPR_VALUE_FPCLK_DIV_8 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_16 2U #define SPI_CR_SPR_BITS_FPCLK_DIV_16 (SPI_CR_SPR_VALUE_FPCLK_DIV_16 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_32 3U #define SPI_CR_SPR_BITS_FPCLK_DIV_32 (SPI_CR_SPR_VALUE_FPCLK_DIV_32 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_64 4U #define SPI_CR_SPR_BITS_FPCLK_DIV_64 (SPI_CR_SPR_VALUE_FPCLK_DIV_64 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_128 5U #define SPI_CR_SPR_BITS_FPCLK_DIV_128 (SPI_CR_SPR_VALUE_FPCLK_DIV_128 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_256 6U #define SPI_CR_SPR_BITS_FPCLK_DIV_256 (SPI_CR_SPR_VALUE_FPCLK_DIV_256 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPR_VALUE_FPCLK_DIV_512 7U #define SPI_CR_SPR_BITS_FPCLK_DIV_512 (SPI_CR_SPR_VALUE_FPCLK_DIV_512 << SPI_CR_SPR_SHIFT) #define SPI_CR_SPE_SHIFT 3 #define SPI_CR_SPE_WIDTH 1 #define SPI_CR_SPE_MASK (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT) #define SPI_CR_SPE_VALUE_DISABLE 0U #define SPI_CR_SPE_BITS_DISABLE (SPI_CR_SPE_VALUE_DISABLE << SPI_CR_SPE_SHIFT) #define SPI_CR_SPE_VALUE_ENABLE 1U #define SPI_CR_SPE_BITS_ENABLE (SPI_CR_SPE_VALUE_ENABLE << SPI_CR_SPE_SHIFT) #define SPI_CR_CPHA_SHIFT 4 #define SPI_CR_CPHA_WIDTH 1 #define SPI_CR_CPHA_MASK (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT) #define SPI_CR_CPOL_SHIFT 5 #define SPI_CR_CPOL_WIDTH 1 #define SPI_CR_CPOL_MASK (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT) #define SPI_CR_MSTR_SHIFT 6 #define SPI_CR_MSTR_WIDTH 1 #define SPI_CR_MSTR_MASK (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT) #define SPI_CR_LSB_SHIFT 7 #define SPI_CR_LSB_WIDTH 1 #define SPI_CR_LSB_MASK (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT) #define SPI_CR_CPHA_DATA_HOLD_S_SHIFT 8 #define SPI_CR_CPHA_DATA_HOLD_S_WIDTH 4 #define SPI_CR_CPHA_DATA_HOLD_S_MASK (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT) #define SPI_CR_MSR_SSN_SHIFT 12 #define SPI_CR_MSR_SSN_WIDTH 1 #define SPI_CR_MSR_SSN_MASK (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT) #define SPI_CR_MSR_SSN_VALUE_DISABLE 0U #define SPI_CR_MSR_SSN_BITS_DISABLE (SPI_CR_MSR_SSN_VALUE_DISABLE << SPI_CR_MSR_SSN_SHIFT) #define SPI_CR_MSR_SSN_VALUE_ENABLE 1U #define SPI_CR_MSR_SSN_BITS_ENABLE (SPI_CR_MSR_SSN_VALUE_ENABLE << SPI_CR_MSR_SSN_SHIFT) #define SPI_CR_RXDMAEN_SHIFT 13 #define SPI_CR_RXDMAEN_WIDTH 1 #define SPI_CR_RXDMAEN_MASK (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT) #define SPI_CR_TXDMAEN_SHIFT 14 #define SPI_CR_TXDMAEN_WIDTH 1 #define SPI_CR_TXDMAEN_MASK (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT) #define SPI_CR_RF_CLR_SHIFT 15 #define SPI_CR_RF_CLR_WIDTH 1 #define SPI_CR_RF_CLR_MASK (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT) #define SPI_CR_TF_CLR_SHIFT 16 #define SPI_CR_TF_CLR_WIDTH 1 #define SPI_CR_TF_CLR_MASK (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT) #define SPI_IE_RXFIFO_OVF_SHIFT 0 #define SPI_IE_RXFIFO_OVF_WIDTH 1 #define SPI_IE_RXFIFO_OVF_MASK (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT) #define SPI_IE_RXFIFO_OVF_VALUE_DISABLE 0U #define SPI_IE_RXFIFO_OVF_BITS_DISABLE (SPI_IE_RXFIFO_OVF_VALUE_DISABLE << SPI_IE_RXFIFO_OVF_SHIFT) #define SPI_IE_RXFIFO_OVF_VALUE_ENABLE 1U #define SPI_IE_RXFIFO_OVF_BITS_ENABLE (SPI_IE_RXFIFO_OVF_VALUE_ENABLE << SPI_IE_RXFIFO_OVF_SHIFT) #define SPI_IE_RXFIFO_FULL_SHIFT 1 #define SPI_IE_RXFIFO_FULL_WIDTH 1 #define SPI_IE_RXFIFO_FULL_MASK (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT) #define SPI_IE_RXFIFO_FULL_VALUE_DISABLE 0U #define SPI_IE_RXFIFO_FULL_BITS_DISABLE (SPI_IE_RXFIFO_FULL_VALUE_DISABLE << SPI_IE_RXFIFO_FULL_SHIFT) #define SPI_IE_RXFIFO_FULL_VALUE_ENABLE 1U #define SPI_IE_RXFIFO_FULL_BITS_ENABLE (SPI_IE_RXFIFO_FULL_VALUE_ENABLE << SPI_IE_RXFIFO_FULL_SHIFT) #define SPI_IE_RXFIFO_HFULL_SHIFT 2 #define SPI_IE_RXFIFO_HFULL_WIDTH 1 #define SPI_IE_RXFIFO_HFULL_MASK (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT) #define SPI_IE_RXFIFO_HFULL_VALUE_DISABLE 0U #define SPI_IE_RXFIFO_HFULL_BITS_DISABLE (SPI_IE_RXFIFO_HFULL_VALUE_DISABLE << SPI_IE_RXFIFO_HFULL_SHIFT) #define SPI_IE_RXFIFO_HFULL_VALUE_ENABLE 1U #define SPI_IE_RXFIFO_HFULL_BITS_ENABLE (SPI_IE_RXFIFO_HFULL_VALUE_ENABLE << SPI_IE_RXFIFO_HFULL_SHIFT) #define SPI_IE_TXFIFO_EMPTY_SHIFT 3 #define SPI_IE_TXFIFO_EMPTY_WIDTH 1 #define SPI_IE_TXFIFO_EMPTY_MASK (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT) #define SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE 0U #define SPI_IE_TXFIFO_EMPTY_BITS_DISABLE (SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) #define SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE 1U #define SPI_IE_TXFIFO_EMPTY_BITS_ENABLE (SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) #define SPI_IE_TXFIFO_HFULL_SHIFT 4 #define SPI_IE_TXFIFO_HFULL_WIDTH 1 #define SPI_IE_TXFIFO_HFULL_MASK (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT) #define SPI_IE_TXFIFO_HFULL_VALUE_DISABLE 0U #define SPI_IE_TXFIFO_HFULL_BITS_DISABLE (SPI_IE_TXFIFO_HFULL_VALUE_DISABLE << SPI_IE_TXFIFO_HFULL_SHIFT) #define SPI_IE_TXFIFO_HFULL_VALUE_ENABLE 1U #define SPI_IE_TXFIFO_HFULL_BITS_ENABLE (SPI_IE_TXFIFO_HFULL_VALUE_ENABLE << SPI_IE_TXFIFO_HFULL_SHIFT) #define SPI_FIFOST_RFE_SHIFT 0 #define SPI_FIFOST_RFE_WIDTH 1 #define SPI_FIFOST_RFE_MASK (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT) #define SPI_FIFOST_RFE_VALUE_NOT_EMPTY 0U #define SPI_FIFOST_RFE_BITS_NOT_EMPTY (SPI_FIFOST_RFE_VALUE_NOT_EMPTY << SPI_FIFOST_RFE_SHIFT) #define SPI_FIFOST_RFE_VALUE_EMPTY 1U #define SPI_FIFOST_RFE_BITS_EMPTY (SPI_FIFOST_RFE_VALUE_EMPTY << SPI_FIFOST_RFE_SHIFT) #define SPI_FIFOST_RFF_SHIFT 1 #define SPI_FIFOST_RFF_WIDTH 1 #define SPI_FIFOST_RFF_MASK (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT) #define SPI_FIFOST_RFF_VALUE_NOT_FULL 0U #define SPI_FIFOST_RFF_BITS_NOT_FULL (SPI_FIFOST_RFF_VALUE_NOT_FULL << SPI_FIFOST_RFF_SHIFT) #define SPI_FIFOST_RFF_VALUE_FULL 1U #define SPI_FIFOST_RFF_BITS_FULL (SPI_FIFOST_RFF_VALUE_FULL << SPI_FIFOST_RFF_SHIFT) #define SPI_FIFOST_RFHF_SHIFT 2 #define SPI_FIFOST_RFHF_WIDTH 1 #define SPI_FIFOST_RFHF_MASK (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT) #define SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL 0U #define SPI_FIFOST_RFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) #define SPI_FIFOST_RFHF_VALUE_HALF_FULL 1U #define SPI_FIFOST_RFHF_BITS_HALF_FULL (SPI_FIFOST_RFHF_VALUE_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) #define SPI_FIFOST_TFE_SHIFT 3 #define SPI_FIFOST_TFE_WIDTH 1 #define SPI_FIFOST_TFE_MASK (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT) #define SPI_FIFOST_TFE_VALUE_NOT_EMPTY 0U #define SPI_FIFOST_TFE_BITS_NOT_EMPTY (SPI_FIFOST_TFE_VALUE_NOT_EMPTY << SPI_FIFOST_TFE_SHIFT) #define SPI_FIFOST_TFE_VALUE_EMPTY 1U #define SPI_FIFOST_TFE_BITS_EMPTY (SPI_FIFOST_TFE_VALUE_EMPTY << SPI_FIFOST_TFE_SHIFT) #define SPI_FIFOST_TFF_SHIFT 4 #define SPI_FIFOST_TFF_WIDTH 1 #define SPI_FIFOST_TFF_MASK (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT) #define SPI_FIFOST_TFF_VALUE_NOT_FULL 0U #define SPI_FIFOST_TFF_BITS_NOT_FULL (SPI_FIFOST_TFF_VALUE_NOT_FULL << SPI_FIFOST_TFF_SHIFT) #define SPI_FIFOST_TFF_VALUE_FULL 1U #define SPI_FIFOST_TFF_BITS_FULL (SPI_FIFOST_TFF_VALUE_FULL << SPI_FIFOST_TFF_SHIFT) #define SPI_FIFOST_TFHF_SHIFT 5 #define SPI_FIFOST_TFHF_WIDTH 1 #define SPI_FIFOST_TFHF_MASK (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT) #define SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL 0U #define SPI_FIFOST_TFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) #define SPI_FIFOST_TFHF_VALUE_HALF_FULL 1U #define SPI_FIFOST_TFHF_BITS_HALF_FULL (SPI_FIFOST_TFHF_VALUE_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) #define SPI_FIFOST_RF_LEVEL_SHIFT 6 #define SPI_FIFOST_RF_LEVEL_WIDTH 3 #define SPI_FIFOST_RF_LEVEL_MASK (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE 0U #define SPI_FIFOST_RF_LEVEL_BITS_0_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE 1U #define SPI_FIFOST_RF_LEVEL_BITS_1_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE 2U #define SPI_FIFOST_RF_LEVEL_BITS_2_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE 3U #define SPI_FIFOST_RF_LEVEL_BITS_3_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE 4U #define SPI_FIFOST_RF_LEVEL_BITS_4_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE 5U #define SPI_FIFOST_RF_LEVEL_BITS_5_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE 6U #define SPI_FIFOST_RF_LEVEL_BITS_6_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE 7U #define SPI_FIFOST_RF_LEVEL_BITS_7_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_SHIFT 9 #define SPI_FIFOST_TF_LEVEL_WIDTH 3 #define SPI_FIFOST_TF_LEVEL_MASK (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE 0U #define SPI_FIFOST_TF_LEVEL_BITS_0_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE 1U #define SPI_FIFOST_TF_LEVEL_BITS_1_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE 2U #define SPI_FIFOST_TF_LEVEL_BITS_2_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE 3U #define SPI_FIFOST_TF_LEVEL_BITS_3_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE 4U #define SPI_FIFOST_TF_LEVEL_BITS_4_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE 5U #define SPI_FIFOST_TF_LEVEL_BITS_5_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE 6U #define SPI_FIFOST_TF_LEVEL_BITS_6_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #define SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE 7U #define SPI_FIFOST_TF_LEVEL_BITS_7_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) #endif ================================================ FILE: bsp/dp32g030/syscon.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_SYSCON_H #define HARDWARE_DP32G030_SYSCON_H #if !defined(__ASSEMBLY__) #include #endif /* -------- SYSCON -------- */ #define SYSCON_BASE_ADDR 0x40000000U #define SYSCON_BASE_SIZE 0x00000800U #define SYSCON_CLK_SEL_ADDR (SYSCON_BASE_ADDR + 0x0000U) #define SYSCON_CLK_SEL (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR) #define SYSCON_CLK_SEL_SYS_SHIFT 0 #define SYSCON_CLK_SEL_SYS_WIDTH 1 #define SYSCON_CLK_SEL_SYS_MASK (((1U << SYSCON_CLK_SEL_SYS_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_SHIFT) #define SYSCON_CLK_SEL_SYS_VALUE_RCHF 0U #define SYSCON_CLK_SEL_SYS_BITS_RCHF (SYSCON_CLK_SEL_SYS_VALUE_RCHF << SYSCON_CLK_SEL_SYS_SHIFT) #define SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK 1U #define SYSCON_CLK_SEL_SYS_BITS_DIV_CLK (SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK << SYSCON_CLK_SEL_SYS_SHIFT) #define SYSCON_CLK_SEL_DIV_SHIFT 1 #define SYSCON_CLK_SEL_DIV_WIDTH 3 #define SYSCON_CLK_SEL_DIV_MASK (((1U << SYSCON_CLK_SEL_DIV_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_1 0U #define SYSCON_CLK_SEL_DIV_BITS_1 (SYSCON_CLK_SEL_DIV_VALUE_1 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_2 1U #define SYSCON_CLK_SEL_DIV_BITS_2 (SYSCON_CLK_SEL_DIV_VALUE_2 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_4 2U #define SYSCON_CLK_SEL_DIV_BITS_4 (SYSCON_CLK_SEL_DIV_VALUE_4 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_8 3U #define SYSCON_CLK_SEL_DIV_BITS_8 (SYSCON_CLK_SEL_DIV_VALUE_8 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_16 4U #define SYSCON_CLK_SEL_DIV_BITS_16 (SYSCON_CLK_SEL_DIV_VALUE_16 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_DIV_VALUE_32 5U #define SYSCON_CLK_SEL_DIV_BITS_32 (SYSCON_CLK_SEL_DIV_VALUE_32 << SYSCON_CLK_SEL_DIV_SHIFT) #define SYSCON_CLK_SEL_SRC_SHIFT 4 #define SYSCON_CLK_SEL_SRC_WIDTH 3 #define SYSCON_CLK_SEL_SRC_MASK (((1U << SYSCON_CLK_SEL_SRC_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_SRC_VALUE_RCHF 0U #define SYSCON_CLK_SEL_SRC_BITS_RCHF (SYSCON_CLK_SEL_SRC_VALUE_RCHF << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_SRC_VALUE_RCLF 1U #define SYSCON_CLK_SEL_SRC_BITS_RCLF (SYSCON_CLK_SEL_SRC_VALUE_RCLF << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_SRC_VALUE_XTAH 2U #define SYSCON_CLK_SEL_SRC_BITS_XTAH (SYSCON_CLK_SEL_SRC_VALUE_XTAH << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_SRC_VALUE_XTAL 3U #define SYSCON_CLK_SEL_SRC_BITS_XTAL (SYSCON_CLK_SEL_SRC_VALUE_XTAL << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_SRC_VALUE_PLL 4U #define SYSCON_CLK_SEL_SRC_BITS_PLL (SYSCON_CLK_SEL_SRC_VALUE_PLL << SYSCON_CLK_SEL_SRC_SHIFT) #define SYSCON_CLK_SEL_W_PLL_SHIFT 7 #define SYSCON_CLK_SEL_W_PLL_WIDTH 1 #define SYSCON_CLK_SEL_W_PLL_MASK (((1U << SYSCON_CLK_SEL_W_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_PLL_SHIFT) #define SYSCON_CLK_SEL_W_PLL_VALUE_RCHF 0U #define SYSCON_CLK_SEL_W_PLL_BITS_RCHF (SYSCON_CLK_SEL_W_PLL_VALUE_RCHF << SYSCON_CLK_SEL_W_PLL_SHIFT) #define SYSCON_CLK_SEL_W_PLL_VALUE_XTAH 1U #define SYSCON_CLK_SEL_W_PLL_BITS_XTAH (SYSCON_CLK_SEL_W_PLL_VALUE_XTAH << SYSCON_CLK_SEL_W_PLL_SHIFT) #define SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT 9 #define SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH 2 #define SYSCON_CLK_SEL_R_SARADC_SMPL_MASK (((1U << SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1 0U #define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV1 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2 1U #define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV2 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4 2U #define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV4 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8 3U #define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV8 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT 10 #define SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH 2 #define SYSCON_CLK_SEL_W_SARADC_SMPL_MASK (((1U << SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1 0U #define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV1 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 1U #define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV2 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4 2U #define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV4 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8 3U #define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV8 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) #define SYSCON_CLK_SEL_R_PLL_SHIFT 11 #define SYSCON_CLK_SEL_R_PLL_WIDTH 1 #define SYSCON_CLK_SEL_R_PLL_MASK (((1U << SYSCON_CLK_SEL_R_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_PLL_SHIFT) #define SYSCON_CLK_SEL_R_PLL_VALUE_RCHF 0U #define SYSCON_CLK_SEL_R_PLL_BITS_RCHF (SYSCON_CLK_SEL_R_PLL_VALUE_RCHF << SYSCON_CLK_SEL_R_PLL_SHIFT) #define SYSCON_CLK_SEL_R_PLL_VALUE_XTAH 1U #define SYSCON_CLK_SEL_R_PLL_BITS_XTAH (SYSCON_CLK_SEL_R_PLL_VALUE_XTAH << SYSCON_CLK_SEL_R_PLL_SHIFT) #define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U) #define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR) #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 0 #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1 #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE 0U #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE 1U #define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_ENABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) #define SYSCON_DEV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0008U) #define SYSCON_DEV_CLK_GATE (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR) #define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT 0 #define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH 1 #define SYSCON_DEV_CLK_GATE_GPIOA_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_GPIOA_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT 1 #define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH 1 #define SYSCON_DEV_CLK_GATE_GPIOB_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_GPIOB_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT 2 #define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH 1 #define SYSCON_DEV_CLK_GATE_GPIOC_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_GPIOC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) #define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC0_SHIFT 4 #define SYSCON_DEV_CLK_GATE_IIC0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_IIC0_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_IIC0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_IIC0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC1_SHIFT 5 #define SYSCON_DEV_CLK_GATE_IIC1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_IIC1_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_IIC1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) #define SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_IIC1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) #define SYSCON_DEV_CLK_GATE_UART0_SHIFT 6 #define SYSCON_DEV_CLK_GATE_UART0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_UART0_MASK (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT) #define SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_UART0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) #define SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_UART0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) #define SYSCON_DEV_CLK_GATE_UART1_SHIFT 7 #define SYSCON_DEV_CLK_GATE_UART1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_UART1_MASK (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT) #define SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_UART1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) #define SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) #define SYSCON_DEV_CLK_GATE_UART2_SHIFT 8 #define SYSCON_DEV_CLK_GATE_UART2_WIDTH 1 #define SYSCON_DEV_CLK_GATE_UART2_MASK (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT) #define SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_UART2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) #define SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_UART2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI0_SHIFT 10 #define SYSCON_DEV_CLK_GATE_SPI0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_SPI0_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_SPI0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI1_SHIFT 11 #define SYSCON_DEV_CLK_GATE_SPI1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_SPI1_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_SPI1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) #define SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT 12 #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT 13 #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT 14 #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH 1 #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT 15 #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT 16 #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT 17 #define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT 18 #define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT 20 #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH 1 #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT 21 #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH 1 #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) #define SYSCON_DEV_CLK_GATE_RTC_SHIFT 22 #define SYSCON_DEV_CLK_GATE_RTC_WIDTH 1 #define SYSCON_DEV_CLK_GATE_RTC_MASK (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT) #define SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_RTC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) #define SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_RTC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) #define SYSCON_DEV_CLK_GATE_IWDT_SHIFT 23 #define SYSCON_DEV_CLK_GATE_IWDT_WIDTH 1 #define SYSCON_DEV_CLK_GATE_IWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_IWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_IWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_WWDT_SHIFT 24 #define SYSCON_DEV_CLK_GATE_WWDT_WIDTH 1 #define SYSCON_DEV_CLK_GATE_WWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_WWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_WWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) #define SYSCON_DEV_CLK_GATE_SARADC_SHIFT 25 #define SYSCON_DEV_CLK_GATE_SARADC_WIDTH 1 #define SYSCON_DEV_CLK_GATE_SARADC_MASK (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) #define SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_SARADC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) #define SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) #define SYSCON_DEV_CLK_GATE_CRC_SHIFT 27 #define SYSCON_DEV_CLK_GATE_CRC_WIDTH 1 #define SYSCON_DEV_CLK_GATE_CRC_MASK (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT) #define SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_CRC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) #define SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) #define SYSCON_DEV_CLK_GATE_AES_SHIFT 28 #define SYSCON_DEV_CLK_GATE_AES_WIDTH 1 #define SYSCON_DEV_CLK_GATE_AES_MASK (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT) #define SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE 0U #define SYSCON_DEV_CLK_GATE_AES_BITS_DISABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) #define SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE 1U #define SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) #define SYSCON_RC_FREQ_DELTA_ADDR (SYSCON_BASE_ADDR + 0x0078U) #define SYSCON_RC_FREQ_DELTA (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR) #define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT 0 #define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH 10 #define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT) #define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT 10 #define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH 1 #define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT) #define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT 11 #define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH 20 #define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT) #define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT 31 #define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH 1 #define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT) #define SYSCON_VREF_VOLT_DELTA_ADDR (SYSCON_BASE_ADDR + 0x007CU) #define SYSCON_VREF_VOLT_DELTA (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR) #define SYSCON_CHIP_ID0_ADDR (SYSCON_BASE_ADDR + 0x0080U) #define SYSCON_CHIP_ID0 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR) #define SYSCON_CHIP_ID1_ADDR (SYSCON_BASE_ADDR + 0x0084U) #define SYSCON_CHIP_ID1 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR) #define SYSCON_CHIP_ID2_ADDR (SYSCON_BASE_ADDR + 0x0088U) #define SYSCON_CHIP_ID2 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR) #define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) #define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) #endif ================================================ FILE: bsp/dp32g030/timer.h ================================================ // // Created by RUPC on 2024/1/8. // #ifndef HARDWARE_DP32G030_TIMER_H #define HARDWARE_DP32G030_TIMER_H #include #define TIMERBASE0_ADD 0x40064000 //TIMER0 #define TIMERBASE0_EN_ADD (0X00+TIMERBASE0_ADD) #define TIMERBASE0_DIV_ADD (0X04+TIMERBASE0_ADD) #define TIMERBASE0_IE_ADD (0X10+TIMERBASE0_ADD) #define TIMERBASE0_IF_ADD (0X14+TIMERBASE0_ADD) #define TIMERBASE0_HIGH_LOAD_ADD (0X20+TIMERBASE0_ADD) #define TIMERBASE0_HIGH_CNT_ADD (0X24+TIMERBASE0_ADD) #define TIMERBASE0_LOW_LOAD_ADD (0X30+TIMERBASE0_ADD) #define TIMERBASE0_LOW_CNT_ADD (0X34+TIMERBASE0_ADD) #define TIMERBASE0_EN (*(volatile uint32_t *)TIMERBASE0_EN_ADD) #define TIMERBASE0_DIV (*(volatile uint32_t *)TIMERBASE0_DIV_ADD) #define TIMERBASE0_IE (*(volatile uint32_t *)TIMERBASE0_IE_ADD) #define TIMERBASE0_IF (*(volatile uint32_t *)TIMERBASE0_IF_ADD) #define TIMERBASE0_HIGH_LOAD (*(volatile uint32_t *)TIMERBASE0_HIGH_LOAD_ADD) #define TIMERBASE0_HIGH_CNT (*(volatile uint32_t *)TIMERBASE0_HIGH_CNT_ADD) #define TIMERBASE0_LOW_LOAD (*(volatile uint32_t *)TIMERBASE0_LOW_LOAD_ADD) #define TIMERBASE0_LOW_CNT (*(volatile uint32_t *)TIMERBASE0_LOW_CNT_ADD) extern uint32_t TIM0_CNT; void TIM0_INIT(); #endif //UV_K5_FIRMWARE_CUSTOM_0_17_TIMER_H ================================================ FILE: bsp/dp32g030/uart.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef HARDWARE_DP32G030_UART_H #define HARDWARE_DP32G030_UART_H #if !defined(__ASSEMBLY__) #include #endif /* -------- UART0 -------- */ #define UART0_BASE_ADDR 0x4006B000U #define UART0_BASE_SIZE 0x00000800U #define UART0 ((volatile UART_Port_t *)UART0_BASE_ADDR) /* -------- UART1 -------- */ #define UART1_BASE_ADDR 0x4006B800U #define UART1_BASE_SIZE 0x00000800U #define UART1 ((volatile UART_Port_t *)UART1_BASE_ADDR) /* -------- UART2 -------- */ #define UART2_BASE_ADDR 0x4006C000U #define UART2_BASE_SIZE 0x00000800U #define UART2 ((volatile UART_Port_t *)UART2_BASE_ADDR) /* -------- UART -------- */ typedef struct { uint32_t CTRL; uint32_t BAUD; uint32_t TDR; uint32_t RDR; uint32_t IE; uint32_t IF; uint32_t FIFO; uint32_t FC; uint32_t RXTO; } UART_Port_t; #define UART_CTRL_UARTEN_SHIFT 0 #define UART_CTRL_UARTEN_WIDTH 1 #define UART_CTRL_UARTEN_MASK (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT) #define UART_CTRL_UARTEN_VALUE_DISABLE 0U #define UART_CTRL_UARTEN_BITS_DISABLE (UART_CTRL_UARTEN_VALUE_DISABLE << UART_CTRL_UARTEN_SHIFT) #define UART_CTRL_UARTEN_VALUE_ENABLE 1U #define UART_CTRL_UARTEN_BITS_ENABLE (UART_CTRL_UARTEN_VALUE_ENABLE << UART_CTRL_UARTEN_SHIFT) #define UART_CTRL_RXEN_SHIFT 1 #define UART_CTRL_RXEN_WIDTH 1 #define UART_CTRL_RXEN_MASK (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT) #define UART_CTRL_RXEN_VALUE_DISABLE 0U #define UART_CTRL_RXEN_BITS_DISABLE (UART_CTRL_RXEN_VALUE_DISABLE << UART_CTRL_RXEN_SHIFT) #define UART_CTRL_RXEN_VALUE_ENABLE 1U #define UART_CTRL_RXEN_BITS_ENABLE (UART_CTRL_RXEN_VALUE_ENABLE << UART_CTRL_RXEN_SHIFT) #define UART_CTRL_TXEN_SHIFT 2 #define UART_CTRL_TXEN_WIDTH 1 #define UART_CTRL_TXEN_MASK (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT) #define UART_CTRL_TXEN_VALUE_DISABLE 0U #define UART_CTRL_TXEN_BITS_DISABLE (UART_CTRL_TXEN_VALUE_DISABLE << UART_CTRL_TXEN_SHIFT) #define UART_CTRL_TXEN_VALUE_ENABLE 1U #define UART_CTRL_TXEN_BITS_ENABLE (UART_CTRL_TXEN_VALUE_ENABLE << UART_CTRL_TXEN_SHIFT) #define UART_CTRL_RXDMAEN_SHIFT 3 #define UART_CTRL_RXDMAEN_WIDTH 1 #define UART_CTRL_RXDMAEN_MASK (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT) #define UART_CTRL_RXDMAEN_VALUE_DISABLE 0U #define UART_CTRL_RXDMAEN_BITS_DISABLE (UART_CTRL_RXDMAEN_VALUE_DISABLE << UART_CTRL_RXDMAEN_SHIFT) #define UART_CTRL_RXDMAEN_VALUE_ENABLE 1U #define UART_CTRL_RXDMAEN_BITS_ENABLE (UART_CTRL_RXDMAEN_VALUE_ENABLE << UART_CTRL_RXDMAEN_SHIFT) #define UART_CTRL_TXDMAEN_SHIFT 4 #define UART_CTRL_TXDMAEN_WIDTH 1 #define UART_CTRL_TXDMAEN_MASK (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT) #define UART_CTRL_TXDMAEN_VALUE_DISABLE 0U #define UART_CTRL_TXDMAEN_BITS_DISABLE (UART_CTRL_TXDMAEN_VALUE_DISABLE << UART_CTRL_TXDMAEN_SHIFT) #define UART_CTRL_TXDMAEN_VALUE_ENABLE 1U #define UART_CTRL_TXDMAEN_BITS_ENABLE (UART_CTRL_TXDMAEN_VALUE_ENABLE << UART_CTRL_TXDMAEN_SHIFT) #define UART_CTRL_NINEBIT_SHIFT 5 #define UART_CTRL_NINEBIT_WIDTH 1 #define UART_CTRL_NINEBIT_MASK (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT) #define UART_CTRL_NINEBIT_VALUE_DISABLE 0U #define UART_CTRL_NINEBIT_BITS_DISABLE (UART_CTRL_NINEBIT_VALUE_DISABLE << UART_CTRL_NINEBIT_SHIFT) #define UART_CTRL_NINEBIT_VALUE_ENABLE 1U #define UART_CTRL_NINEBIT_BITS_ENABLE (UART_CTRL_NINEBIT_VALUE_ENABLE << UART_CTRL_NINEBIT_SHIFT) #define UART_CTRL_PAREN_SHIFT 6 #define UART_CTRL_PAREN_WIDTH 1 #define UART_CTRL_PAREN_MASK (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT) #define UART_CTRL_PAREN_VALUE_DISABLE 0U #define UART_CTRL_PAREN_BITS_DISABLE (UART_CTRL_PAREN_VALUE_DISABLE << UART_CTRL_PAREN_SHIFT) #define UART_CTRL_PAREN_VALUE_ENABLE 1U #define UART_CTRL_PAREN_BITS_ENABLE (UART_CTRL_PAREN_VALUE_ENABLE << UART_CTRL_PAREN_SHIFT) #define UART_IE_TXDONE_SHIFT 2 #define UART_IE_TXDONE_WIDTH 1 #define UART_IE_TXDONE_MASK (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT) #define UART_IE_TXDONE_VALUE_DISABLE 0U #define UART_IE_TXDONE_BITS_DISABLE (UART_IE_TXDONE_VALUE_DISABLE << UART_IE_TXDONE_SHIFT) #define UART_IE_TXDONE_VALUE_ENABLE 1U #define UART_IE_TXDONE_BITS_ENABLE (UART_IE_TXDONE_VALUE_ENABLE << UART_IE_TXDONE_SHIFT) #define UART_IE_PARITYE_SHIFT 3 #define UART_IE_PARITYE_WIDTH 1 #define UART_IE_PARITYE_MASK (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT) #define UART_IE_PARITYE_VALUE_DISABLE 0U #define UART_IE_PARITYE_BITS_DISABLE (UART_IE_PARITYE_VALUE_DISABLE << UART_IE_PARITYE_SHIFT) #define UART_IE_PARITYE_VALUE_ENABLE 1U #define UART_IE_PARITYE_BITS_ENABLE (UART_IE_PARITYE_VALUE_ENABLE << UART_IE_PARITYE_SHIFT) #define UART_IE_STOPE_SHIFT 4 #define UART_IE_STOPE_WIDTH 1 #define UART_IE_STOPE_MASK (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT) #define UART_IE_STOPE_VALUE_DISABLE 0U #define UART_IE_STOPE_BITS_DISABLE (UART_IE_STOPE_VALUE_DISABLE << UART_IE_STOPE_SHIFT) #define UART_IE_STOPE_VALUE_ENABLE 1U #define UART_IE_STOPE_BITS_ENABLE (UART_IE_STOPE_VALUE_ENABLE << UART_IE_STOPE_SHIFT) #define UART_IE_RXTO_SHIFT 5 #define UART_IE_RXTO_WIDTH 1 #define UART_IE_RXTO_MASK (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT) #define UART_IE_RXTO_VALUE_DISABLE 0U #define UART_IE_RXTO_BITS_DISABLE (UART_IE_RXTO_VALUE_DISABLE << UART_IE_RXTO_SHIFT) #define UART_IE_RXTO_VALUE_ENABLE 1U #define UART_IE_RXTO_BITS_ENABLE (UART_IE_RXTO_VALUE_ENABLE << UART_IE_RXTO_SHIFT) #define UART_IE_RXFIFO_SHIFT 6 #define UART_IE_RXFIFO_WIDTH 1 #define UART_IE_RXFIFO_MASK (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT) #define UART_IE_RXFIFO_VALUE_DISABLE 0U #define UART_IE_RXFIFO_BITS_DISABLE (UART_IE_RXFIFO_VALUE_DISABLE << UART_IE_RXFIFO_SHIFT) #define UART_IE_RXFIFO_VALUE_ENABLE 1U #define UART_IE_RXFIFO_BITS_ENABLE (UART_IE_RXFIFO_VALUE_ENABLE << UART_IE_RXFIFO_SHIFT) #define UART_IE_TXFIFO_SHIFT 7 #define UART_IE_TXFIFO_WIDTH 1 #define UART_IE_TXFIFO_MASK (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT) #define UART_IE_TXFIFO_VALUE_DISABLE 0U #define UART_IE_TXFIFO_BITS_DISABLE (UART_IE_TXFIFO_VALUE_DISABLE << UART_IE_TXFIFO_SHIFT) #define UART_IE_TXFIFO_VALUE_ENABLE 1U #define UART_IE_TXFIFO_BITS_ENABLE (UART_IE_TXFIFO_VALUE_ENABLE << UART_IE_TXFIFO_SHIFT) #define UART_IE_RXFIFO_OVF_SHIFT 8 #define UART_IE_RXFIFO_OVF_WIDTH 1 #define UART_IE_RXFIFO_OVF_MASK (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT) #define UART_IE_RXFIFO_OVF_VALUE_DISABLE 0U #define UART_IE_RXFIFO_OVF_BITS_DISABLE (UART_IE_RXFIFO_OVF_VALUE_DISABLE << UART_IE_RXFIFO_OVF_SHIFT) #define UART_IE_RXFIFO_OVF_VALUE_ENABLE 1U #define UART_IE_RXFIFO_OVF_BITS_ENABLE (UART_IE_RXFIFO_OVF_VALUE_ENABLE << UART_IE_RXFIFO_OVF_SHIFT) #define UART_IE_ABRD_OVF_SHIFT 9 #define UART_IE_ABRD_OVF_WIDTH 1 #define UART_IE_ABRD_OVF_MASK (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT) #define UART_IE_ABRD_OVF_VALUE_DISABLE 0U #define UART_IE_ABRD_OVF_BITS_DISABLE (UART_IE_ABRD_OVF_VALUE_DISABLE << UART_IE_ABRD_OVF_SHIFT) #define UART_IE_ABRD_OVF_VALUE_ENABLE 1U #define UART_IE_ABRD_OVF_BITS_ENABLE (UART_IE_ABRD_OVF_VALUE_ENABLE << UART_IE_ABRD_OVF_SHIFT) #define UART_IF_TXDONE_SHIFT 2 #define UART_IF_TXDONE_WIDTH 1 #define UART_IF_TXDONE_MASK (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT) #define UART_IF_TXDONE_VALUE_NOT_SET 0U #define UART_IF_TXDONE_BITS_NOT_SET (UART_IF_TXDONE_VALUE_NOT_SET << UART_IF_TXDONE_SHIFT) #define UART_IF_TXDONE_VALUE_SET 1U #define UART_IF_TXDONE_BITS_SET (UART_IF_TXDONE_VALUE_SET << UART_IF_TXDONE_SHIFT) #define UART_IF_PARITYE_SHIFT 3 #define UART_IF_PARITYE_WIDTH 1 #define UART_IF_PARITYE_MASK (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT) #define UART_IF_PARITYE_VALUE_NOT_SET 0U #define UART_IF_PARITYE_BITS_NOT_SET (UART_IF_PARITYE_VALUE_NOT_SET << UART_IF_PARITYE_SHIFT) #define UART_IF_PARITYE_VALUE_SET 1U #define UART_IF_PARITYE_BITS_SET (UART_IF_PARITYE_VALUE_SET << UART_IF_PARITYE_SHIFT) #define UART_IF_STOPE_SHIFT 4 #define UART_IF_STOPE_WIDTH 1 #define UART_IF_STOPE_MASK (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT) #define UART_IF_STOPE_VALUE_NOT_SET 0U #define UART_IF_STOPE_BITS_NOT_SET (UART_IF_STOPE_VALUE_NOT_SET << UART_IF_STOPE_SHIFT) #define UART_IF_STOPE_VALUE_SET 1U #define UART_IF_STOPE_BITS_SET (UART_IF_STOPE_VALUE_SET << UART_IF_STOPE_SHIFT) #define UART_IF_RXTO_SHIFT 5 #define UART_IF_RXTO_WIDTH 1 #define UART_IF_RXTO_MASK (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT) #define UART_IF_RXTO_VALUE_NOT_SET 0U #define UART_IF_RXTO_BITS_NOT_SET (UART_IF_RXTO_VALUE_NOT_SET << UART_IF_RXTO_SHIFT) #define UART_IF_RXTO_VALUE_SET 1U #define UART_IF_RXTO_BITS_SET (UART_IF_RXTO_VALUE_SET << UART_IF_RXTO_SHIFT) #define UART_IF_RXFIFO_SHIFT 6 #define UART_IF_RXFIFO_WIDTH 1 #define UART_IF_RXFIFO_MASK (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT) #define UART_IF_RXFIFO_VALUE_NOT_SET 0U #define UART_IF_RXFIFO_BITS_NOT_SET (UART_IF_RXFIFO_VALUE_NOT_SET << UART_IF_RXFIFO_SHIFT) #define UART_IF_RXFIFO_VALUE_SET 1U #define UART_IF_RXFIFO_BITS_SET (UART_IF_RXFIFO_VALUE_SET << UART_IF_RXFIFO_SHIFT) #define UART_IF_TXFIFO_SHIFT 7 #define UART_IF_TXFIFO_WIDTH 1 #define UART_IF_TXFIFO_MASK (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT) #define UART_IF_TXFIFO_VALUE_NOT_SET 0U #define UART_IF_TXFIFO_BITS_NOT_SET (UART_IF_TXFIFO_VALUE_NOT_SET << UART_IF_TXFIFO_SHIFT) #define UART_IF_TXFIFO_VALUE_SET 1U #define UART_IF_TXFIFO_BITS_SET (UART_IF_TXFIFO_VALUE_SET << UART_IF_TXFIFO_SHIFT) #define UART_IF_RXFIFO_OVF_SHIFT 8 #define UART_IF_RXFIFO_OVF_WIDTH 1 #define UART_IF_RXFIFO_OVF_MASK (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT) #define UART_IF_RXFIFO_OVF_VALUE_NOT_SET 0U #define UART_IF_RXFIFO_OVF_BITS_NOT_SET (UART_IF_RXFIFO_OVF_VALUE_NOT_SET << UART_IF_RXFIFO_OVF_SHIFT) #define UART_IF_RXFIFO_OVF_VALUE_SET 1U #define UART_IF_RXFIFO_OVF_BITS_SET (UART_IF_RXFIFO_OVF_VALUE_SET << UART_IF_RXFIFO_OVF_SHIFT) #define UART_IF_ABRD_OVF_SHIFT 9 #define UART_IF_ABRD_OVF_WIDTH 1 #define UART_IF_ABRD_OVF_MASK (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT) #define UART_IF_ABRD_OVF_VALUE_NOT_SET 0U #define UART_IF_ABRD_OVF_BITS_NOT_SET (UART_IF_ABRD_OVF_VALUE_NOT_SET << UART_IF_ABRD_OVF_SHIFT) #define UART_IF_ABRD_OVF_VALUE_SET 1U #define UART_IF_ABRD_OVF_BITS_SET (UART_IF_ABRD_OVF_VALUE_SET << UART_IF_ABRD_OVF_SHIFT) #define UART_IF_RXFIFO_EMPTY_SHIFT 10 #define UART_IF_RXFIFO_EMPTY_WIDTH 1 #define UART_IF_RXFIFO_EMPTY_MASK (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT) #define UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET 0U #define UART_IF_RXFIFO_EMPTY_BITS_NOT_SET (UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_RXFIFO_EMPTY_SHIFT) #define UART_IF_RXFIFO_EMPTY_VALUE_SET 1U #define UART_IF_RXFIFO_EMPTY_BITS_SET (UART_IF_RXFIFO_EMPTY_VALUE_SET << UART_IF_RXFIFO_EMPTY_SHIFT) #define UART_IF_RXFIFO_FULL_SHIFT 11 #define UART_IF_RXFIFO_FULL_WIDTH 1 #define UART_IF_RXFIFO_FULL_MASK (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT) #define UART_IF_RXFIFO_FULL_VALUE_NOT_SET 0U #define UART_IF_RXFIFO_FULL_BITS_NOT_SET (UART_IF_RXFIFO_FULL_VALUE_NOT_SET << UART_IF_RXFIFO_FULL_SHIFT) #define UART_IF_RXFIFO_FULL_VALUE_SET 1U #define UART_IF_RXFIFO_FULL_BITS_SET (UART_IF_RXFIFO_FULL_VALUE_SET << UART_IF_RXFIFO_FULL_SHIFT) #define UART_IF_RXFIFO_HFULL_SHIFT 12 #define UART_IF_RXFIFO_HFULL_WIDTH 1 #define UART_IF_RXFIFO_HFULL_MASK (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT) #define UART_IF_RXFIFO_HFULL_VALUE_NOT_SET 0U #define UART_IF_RXFIFO_HFULL_BITS_NOT_SET (UART_IF_RXFIFO_HFULL_VALUE_NOT_SET << UART_IF_RXFIFO_HFULL_SHIFT) #define UART_IF_RXFIFO_HFULL_VALUE_SET 1U #define UART_IF_RXFIFO_HFULL_BITS_SET (UART_IF_RXFIFO_HFULL_VALUE_SET << UART_IF_RXFIFO_HFULL_SHIFT) #define UART_IF_TXFIFO_EMPTY_SHIFT 13 #define UART_IF_TXFIFO_EMPTY_WIDTH 1 #define UART_IF_TXFIFO_EMPTY_MASK (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT) #define UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET 0U #define UART_IF_TXFIFO_EMPTY_BITS_NOT_SET (UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_TXFIFO_EMPTY_SHIFT) #define UART_IF_TXFIFO_EMPTY_VALUE_SET 1U #define UART_IF_TXFIFO_EMPTY_BITS_SET (UART_IF_TXFIFO_EMPTY_VALUE_SET << UART_IF_TXFIFO_EMPTY_SHIFT) #define UART_IF_TXFIFO_FULL_SHIFT 14 #define UART_IF_TXFIFO_FULL_WIDTH 1 #define UART_IF_TXFIFO_FULL_MASK (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT) #define UART_IF_TXFIFO_FULL_VALUE_NOT_SET 0U #define UART_IF_TXFIFO_FULL_BITS_NOT_SET (UART_IF_TXFIFO_FULL_VALUE_NOT_SET << UART_IF_TXFIFO_FULL_SHIFT) #define UART_IF_TXFIFO_FULL_VALUE_SET 1U #define UART_IF_TXFIFO_FULL_BITS_SET (UART_IF_TXFIFO_FULL_VALUE_SET << UART_IF_TXFIFO_FULL_SHIFT) #define UART_IF_TXFIFO_HFULL_SHIFT 15 #define UART_IF_TXFIFO_HFULL_WIDTH 1 #define UART_IF_TXFIFO_HFULL_MASK (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT) #define UART_IF_TXFIFO_HFULL_VALUE_NOT_SET 0U #define UART_IF_TXFIFO_HFULL_BITS_NOT_SET (UART_IF_TXFIFO_HFULL_VALUE_NOT_SET << UART_IF_TXFIFO_HFULL_SHIFT) #define UART_IF_TXFIFO_HFULL_VALUE_SET 1U #define UART_IF_TXFIFO_HFULL_BITS_SET (UART_IF_TXFIFO_HFULL_VALUE_SET << UART_IF_TXFIFO_HFULL_SHIFT) #define UART_IF_TXBUSY_SHIFT 16 #define UART_IF_TXBUSY_WIDTH 1 #define UART_IF_TXBUSY_MASK (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT) #define UART_IF_TXBUSY_VALUE_NOT_SET 0U #define UART_IF_TXBUSY_BITS_NOT_SET (UART_IF_TXBUSY_VALUE_NOT_SET << UART_IF_TXBUSY_SHIFT) #define UART_IF_TXBUSY_VALUE_SET 1U #define UART_IF_TXBUSY_BITS_SET (UART_IF_TXBUSY_VALUE_SET << UART_IF_TXBUSY_SHIFT) #define UART_IF_RF_LEVEL_SHIFT 17 #define UART_IF_RF_LEVEL_WIDTH 3 #define UART_IF_RF_LEVEL_MASK (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_0_8_BYTE 0U #define UART_IF_RF_LEVEL_BITS_0_8_BYTE (UART_IF_RF_LEVEL_VALUE_0_8_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_1_BYTE 1U #define UART_IF_RF_LEVEL_BITS_1_BYTE (UART_IF_RF_LEVEL_VALUE_1_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_2_BYTE 2U #define UART_IF_RF_LEVEL_BITS_2_BYTE (UART_IF_RF_LEVEL_VALUE_2_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_3_BYTE 3U #define UART_IF_RF_LEVEL_BITS_3_BYTE (UART_IF_RF_LEVEL_VALUE_3_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_4_BYTE 4U #define UART_IF_RF_LEVEL_BITS_4_BYTE (UART_IF_RF_LEVEL_VALUE_4_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_5_BYTE 5U #define UART_IF_RF_LEVEL_BITS_5_BYTE (UART_IF_RF_LEVEL_VALUE_5_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_6_BYTE 6U #define UART_IF_RF_LEVEL_BITS_6_BYTE (UART_IF_RF_LEVEL_VALUE_6_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_RF_LEVEL_VALUE_7_BYTE 7U #define UART_IF_RF_LEVEL_BITS_7_BYTE (UART_IF_RF_LEVEL_VALUE_7_BYTE << UART_IF_RF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_SHIFT 20 #define UART_IF_TF_LEVEL_WIDTH 3 #define UART_IF_TF_LEVEL_MASK (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_0_8_BYTE 0U #define UART_IF_TF_LEVEL_BITS_0_8_BYTE (UART_IF_TF_LEVEL_VALUE_0_8_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_1_BYTE 1U #define UART_IF_TF_LEVEL_BITS_1_BYTE (UART_IF_TF_LEVEL_VALUE_1_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_2_BYTE 2U #define UART_IF_TF_LEVEL_BITS_2_BYTE (UART_IF_TF_LEVEL_VALUE_2_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_3_BYTE 3U #define UART_IF_TF_LEVEL_BITS_3_BYTE (UART_IF_TF_LEVEL_VALUE_3_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_4_BYTE 4U #define UART_IF_TF_LEVEL_BITS_4_BYTE (UART_IF_TF_LEVEL_VALUE_4_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_5_BYTE 5U #define UART_IF_TF_LEVEL_BITS_5_BYTE (UART_IF_TF_LEVEL_VALUE_5_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_6_BYTE 6U #define UART_IF_TF_LEVEL_BITS_6_BYTE (UART_IF_TF_LEVEL_VALUE_6_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_IF_TF_LEVEL_VALUE_7_BYTE 7U #define UART_IF_TF_LEVEL_BITS_7_BYTE (UART_IF_TF_LEVEL_VALUE_7_BYTE << UART_IF_TF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_SHIFT 0 #define UART_FIFO_RF_LEVEL_WIDTH 3 #define UART_FIFO_RF_LEVEL_MASK (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_1_BYTE 0U #define UART_FIFO_RF_LEVEL_BITS_1_BYTE (UART_FIFO_RF_LEVEL_VALUE_1_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_2_BYTE 1U #define UART_FIFO_RF_LEVEL_BITS_2_BYTE (UART_FIFO_RF_LEVEL_VALUE_2_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_3_BYTE 2U #define UART_FIFO_RF_LEVEL_BITS_3_BYTE (UART_FIFO_RF_LEVEL_VALUE_3_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_4_BYTE 3U #define UART_FIFO_RF_LEVEL_BITS_4_BYTE (UART_FIFO_RF_LEVEL_VALUE_4_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_5_BYTE 4U #define UART_FIFO_RF_LEVEL_BITS_5_BYTE (UART_FIFO_RF_LEVEL_VALUE_5_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_6_BYTE 5U #define UART_FIFO_RF_LEVEL_BITS_6_BYTE (UART_FIFO_RF_LEVEL_VALUE_6_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_7_BYTE 6U #define UART_FIFO_RF_LEVEL_BITS_7_BYTE (UART_FIFO_RF_LEVEL_VALUE_7_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_RF_LEVEL_VALUE_8_BYTE 7U #define UART_FIFO_RF_LEVEL_BITS_8_BYTE (UART_FIFO_RF_LEVEL_VALUE_8_BYTE << UART_FIFO_RF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_SHIFT 3 #define UART_FIFO_TF_LEVEL_WIDTH 3 #define UART_FIFO_TF_LEVEL_MASK (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_0_BYTE 0U #define UART_FIFO_TF_LEVEL_BITS_0_BYTE (UART_FIFO_TF_LEVEL_VALUE_0_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_1_BYTE 1U #define UART_FIFO_TF_LEVEL_BITS_1_BYTE (UART_FIFO_TF_LEVEL_VALUE_1_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_2_BYTE 2U #define UART_FIFO_TF_LEVEL_BITS_2_BYTE (UART_FIFO_TF_LEVEL_VALUE_2_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_3_BYTE 3U #define UART_FIFO_TF_LEVEL_BITS_3_BYTE (UART_FIFO_TF_LEVEL_VALUE_3_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_4_BYTE 4U #define UART_FIFO_TF_LEVEL_BITS_4_BYTE (UART_FIFO_TF_LEVEL_VALUE_4_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_5_BYTE 5U #define UART_FIFO_TF_LEVEL_BITS_5_BYTE (UART_FIFO_TF_LEVEL_VALUE_5_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_6_BYTE 6U #define UART_FIFO_TF_LEVEL_BITS_6_BYTE (UART_FIFO_TF_LEVEL_VALUE_6_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_TF_LEVEL_VALUE_7_BYTE 7U #define UART_FIFO_TF_LEVEL_BITS_7_BYTE (UART_FIFO_TF_LEVEL_VALUE_7_BYTE << UART_FIFO_TF_LEVEL_SHIFT) #define UART_FIFO_RF_CLR_SHIFT 6 #define UART_FIFO_RF_CLR_WIDTH 1 #define UART_FIFO_RF_CLR_MASK (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT) #define UART_FIFO_RF_CLR_VALUE_DISABLE 0U #define UART_FIFO_RF_CLR_BITS_DISABLE (UART_FIFO_RF_CLR_VALUE_DISABLE << UART_FIFO_RF_CLR_SHIFT) #define UART_FIFO_RF_CLR_VALUE_ENABLE 1U #define UART_FIFO_RF_CLR_BITS_ENABLE (UART_FIFO_RF_CLR_VALUE_ENABLE << UART_FIFO_RF_CLR_SHIFT) #define UART_FIFO_TF_CLR_SHIFT 7 #define UART_FIFO_TF_CLR_WIDTH 1 #define UART_FIFO_TF_CLR_MASK (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT) #define UART_FIFO_TF_CLR_VALUE_DISABLE 0U #define UART_FIFO_TF_CLR_BITS_DISABLE (UART_FIFO_TF_CLR_VALUE_DISABLE << UART_FIFO_TF_CLR_SHIFT) #define UART_FIFO_TF_CLR_VALUE_ENABLE 1U #define UART_FIFO_TF_CLR_BITS_ENABLE (UART_FIFO_TF_CLR_VALUE_ENABLE << UART_FIFO_TF_CLR_SHIFT) #define UART_FC_CTSEN_SHIFT 0 #define UART_FC_CTSEN_WIDTH 1 #define UART_FC_CTSEN_MASK (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT) #define UART_FC_CTSEN_VALUE_DISABLE 0U #define UART_FC_CTSEN_BITS_DISABLE (UART_FC_CTSEN_VALUE_DISABLE << UART_FC_CTSEN_SHIFT) #define UART_FC_CTSEN_VALUE_ENABLE 1U #define UART_FC_CTSEN_BITS_ENABLE (UART_FC_CTSEN_VALUE_ENABLE << UART_FC_CTSEN_SHIFT) #define UART_FC_RTSEN_SHIFT 1 #define UART_FC_RTSEN_WIDTH 1 #define UART_FC_RTSEN_MASK (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT) #define UART_FC_RTSEN_VALUE_DISABLE 0U #define UART_FC_RTSEN_BITS_DISABLE (UART_FC_RTSEN_VALUE_DISABLE << UART_FC_RTSEN_SHIFT) #define UART_FC_RTSEN_VALUE_ENABLE 1U #define UART_FC_RTSEN_BITS_ENABLE (UART_FC_RTSEN_VALUE_ENABLE << UART_FC_RTSEN_SHIFT) #define UART_FC_CTSPOL_SHIFT 2 #define UART_FC_CTSPOL_WIDTH 1 #define UART_FC_CTSPOL_MASK (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT) #define UART_FC_CTSPOL_VALUE_LOW 0U #define UART_FC_CTSPOL_BITS_LOW (UART_FC_CTSPOL_VALUE_LOW << UART_FC_CTSPOL_SHIFT) #define UART_FC_CTSPOL_VALUE_HIGH 1U #define UART_FC_CTSPOL_BITS_HIGH (UART_FC_CTSPOL_VALUE_HIGH << UART_FC_CTSPOL_SHIFT) #define UART_FC_RTSPOL_SHIFT 3 #define UART_FC_RTSPOL_WIDTH 1 #define UART_FC_RTSPOL_MASK (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT) #define UART_FC_RTSPOL_VALUE_LOW 0U #define UART_FC_RTSPOL_BITS_LOW (UART_FC_RTSPOL_VALUE_LOW << UART_FC_RTSPOL_SHIFT) #define UART_FC_RTSPOL_VALUE_HIGH 1U #define UART_FC_RTSPOL_BITS_HIGH (UART_FC_RTSPOL_VALUE_HIGH << UART_FC_RTSPOL_SHIFT) #define UART_FC_CTS_SIGNAL_SHIFT 4 #define UART_FC_CTS_SIGNAL_WIDTH 1 #define UART_FC_CTS_SIGNAL_MASK (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT) #define UART_FC_CTS_SIGNAL_VALUE_LOW 0U #define UART_FC_CTS_SIGNAL_BITS_LOW (UART_FC_CTS_SIGNAL_VALUE_LOW << UART_FC_CTS_SIGNAL_SHIFT) #define UART_FC_CTS_SIGNAL_VALUE_HIGH 1U #define UART_FC_CTS_SIGNAL_BITS_HIGH (UART_FC_CTS_SIGNAL_VALUE_HIGH << UART_FC_CTS_SIGNAL_SHIFT) #define UART_FC_RTS_SIGNAL_SHIFT 5 #define UART_FC_RTS_SIGNAL_WIDTH 1 #define UART_FC_RTS_SIGNAL_MASK (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT) #define UART_FC_RTS_SIGNAL_VALUE_LOW 0U #define UART_FC_RTS_SIGNAL_BITS_LOW (UART_FC_RTS_SIGNAL_VALUE_LOW << UART_FC_RTS_SIGNAL_SHIFT) #define UART_FC_RTS_SIGNAL_VALUE_HIGH 1U #define UART_FC_RTS_SIGNAL_BITS_HIGH (UART_FC_RTS_SIGNAL_VALUE_HIGH << UART_FC_RTS_SIGNAL_SHIFT) #endif ================================================ FILE: build/.cmake/api/v1/query/client-vscode/query.json ================================================ {"requests":[{"kind":"cache","version":2},{"kind":"codemodel","version":2},{"kind":"toolchains","version":1},{"kind":"cmakeFiles","version":1}]} ================================================ FILE: build/CMakeCache.txt ================================================ # This is the CMakeCache file. # For build in directory: c:/Users/RUPC/Desktop/losehu/uv-k5-firmware-custom/build # It was generated by CMake: C:/Program Files/CMake/bin/cmake.exe # You can edit this file to change values found and used by cmake. # If you do not want to change any of the values, simply exit the editor. # If you do want to change a value, simply edit, save, and exit the editor. # The syntax for the file is as follows: # KEY:TYPE=VALUE # KEY is the name of a variable in the cache. # TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!. # VALUE is the current value for the KEY. ######################## # EXTERNAL cache entries ######################## //No help, variable specified on the command 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CMAKE_ROOT:INTERNAL=C:/Program Files/CMake/share/cmake-3.22 ================================================ FILE: build/CMakeFiles/cmake.check_cache ================================================ # This file is generated by cmake for dependency checking of the CMakeCache.txt file ================================================ FILE: chinese.h ================================================ // // Created by RUPC on 2023/11/30. // #ifndef UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H #define UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H #include "font.h" #if ENABLE_CHINESE_FULL!=4 || defined(ENABLE_ENGLISH) #ifdef ENABLE_ENGLISH #define 步进频率 "Step" #define 接收数字亚音 "RxDCS" #define 接收模拟亚音 "RxCTCS" #define 发送数字亚音 "TxDCS" #define 发送模拟亚音 "TxCTCS" #define 频差方向 "TxODir" #define 频差频率 "TxOffs" #define 加密 "Scramb" #define 遇忙禁发 "BusyCL" #define 压扩 "Compnd" #define 存置信道 "ChSave" #define 删除信道 "ChDele" #define 命名信道 "ChName" #define 信道扫描列表 "SList" #define 扫描列表1 "SList1" #define 扫描列表2 "SList2" #define 搜索恢复模式 "ScnRev" #define 发送超时 "TxTOut" #define 省电模式 "BatSav" #define 麦克风增益 "Mic" #define 信道显示模式 "ChDisp" #define 自动背光 "BackLt" #define 背光亮度 "Light" #define 首尾音 "Roger" #define MDC_ID "MDC ID" #define 尾音消除 "STE" #define 过中继尾音消除 "RP STE" #define 按键即呼 "1 Call" #define DTMF_ID "D ID" #define DTMF上线码 "UPCode" #define DTMF下线码 "DWCode" #define DTMF发送 "PTT ID" #define DTMF侧音 "D ST" #define DTMF响应 "D Resp" #define DTMF复位 "D Hold" #define DTMF预载波 "D Prel" #define DTMF联系人 "D List" #define DTMF显示 "D Live" #define AM自动增益 "AM Fix" #define 收发模式 "RxMode" #define 静噪等级 "Sql" #define 频段解锁 "F Lock" #define 两百M发射 "Tx 200" #define 三百五十M发射 "Tx 350" #define 五百M发射 "Tx 500" #define 三百五十M接收 "350 En" #define 电池调压 "BatCal" #define 电池大小 "BatVol" #define 参数复位 "Reset" #define 发送等于接收 "OFF" #define 发送等于接收加偏移 "+" #define 发送等于接收减偏移 "-" #define 关闭 "OFF" #define 开启 "ON" #define 一级 "1:1" #define 二级 "1:2" #define 三级 "1:3" #define 四级 "1:4" #define 三十秒 "30 sec" #define 一分 "1 min" #define 两分 "2 min" #define 三分 "3 min" #define 四分 "4 min" #define 五分 "5 min" #define 六分 "6 min" #define 七分 "7 min" #define 八分 "8 min" #define 九分 "9 min" #define 十五分 "15 min" #define 主信道接收发射 "MAIN\nONLY" #define 双信道接收 "DUAL RX\nRESPOND" #define 主信道发射副信道接收 "CROSS\nBAND" #define 主信道发射双信道接收 "MAIN TX\nDUAL RX" #define 遇信号5秒后搜索 "TIME" #define 信号停止后搜索 "CARRIER" #define 遇信号后停止搜索 "STOP" #define 频率 "FREQ" #define 信道号 "CHANNEL\nNUMBER" #define 名称 "NAME" #define 名称加频率 "NAME +\nFREQ" #define 不响应 "DO\nNOTHING" #define 本地响铃 "RING" #define 回复响应 "REPLY" #define 本地响铃回复响应 "BOTH" #define 不发送 "OFF" #define 上线码 "UP CODE" #define 下线码 "DOWN CODE" #define 上线加下线码 "UP+DOWN\nCODE" #define Quindar码 "APOLLO\nQUINDAR" #define 关闭 "OFF" #define ROGER尾音 "ROGER" #define MDC尾音 "MDC\nEND" #define MDC首音 "MDC\nBGN" #define MDC首尾音 "MDC\nBOTH" #define MDC首音加ROGER "MDC BGN\n+ROGER" #define 除信道参数 "VFO" #define 全部参数 "ALL" #define 禁用全部 "DISABLE\nALL" #define 解锁全部 "UNLOCK\nALL" #define 五秒 "5 sec" #define 十秒 "10 sec" #define 二十秒 "20 sec" #define 发送时 "TX" #define 接收时 "RX" #define 发送接收时 "TX/RX" #define 全部 "ALL" #define 扫描 "Scan" #define 低电压 "LOW VOL" #define 遇忙 "BUSY" #define 禁止发射 "DISABLE" #define 发送超时 "TxTOut" #define 高电压 "HIGH VOL" #define 按EXIT键 "Press EXIT" #define 存置问 "SAVE?" #define 存置了 "SAVED!" #define 删除问 "DEL?" #define 列表 "List" #define 模拟亚音 "CTCS" #define 数字亚音 "DCS" #define 图片 "PIC" #define 信息 "TxT" #define 侧键1短按 "F1Shrt" #define 侧键1长按 "F1Long" #define 侧键2短按 "F2Shrt" #define 侧键2长按 "F2Long" #define M键长按 "M Long" #define 手电 "LIGHT" #define 切换发射功率 "POWER" #define 监听 "MONITOR" #define 声控发射 "VOX" #define FM收音机 "FM RADIO" #define 锁定按键 "LOCK KEY" #define 切换信道 "SWITCH VFO" #define 切换信道模式 "VFO/MR" #define 切换调制模式 "Demodu" #define DTMF解码 "D Decd" #define 切换宽窄带 "W/N" #define 宽窄带 "W/N" #define 宽带 "WIDE" #define 窄带 "NARROW" #define 主信道发射 "MAIN SEND" #define 副信道发射 "DUAL SEND" #define 开机显示 "POnMsg" #else #define 步进频率 "\x01\x02\x03\x04" #define 接收数字亚音 "\x05\x06\x07\x08\x09\x0B" #define 接收模拟亚音 "\x05\x06\x0C\x0D\x09\x0B" #define 发送数字亚音 "\x0E\x0F\x07\x08\x09\x0B" #define 发送模拟亚音 "\x0E\x0F\x0C\x0D\x09\x0B" #define 频差方向 "\x03\x10\x11\x12" #define 频差频率 "\x03\x10\x03\x04" #define 加密 "\x13\x14" #define 遇忙禁发 "\x15\x16\x17\x0E" #define 压扩 "\x18\x19" #define 存置信道 "\x1A\x1B\x1C\x1D" #define 删除信道 "\x1E\x1F\x1C\x1D" #define 命名信道 "\x7F\x80\x1C\x1D" #define 信道扫描列表 "\x1C\x1D\x81\x82\x83\x84" #define 扫描列表1 "\x81\x82\x83\x84\x31" #define 扫描列表2 "\x81\x82\x83\x84\x32" #define 搜索恢复模式 "\x85\x86\x87\x88\x0C\x89" #define 发送超时 "\x0E\x0F\x8A\x8B" #define 省电模式 "\x8C\x8D\x0C\x89" #define 麦克风增益 "\x8E\x8F\x90\x91\x92" #define 信道显示模式 "\x1C\x1D\x93\x94\x0C\x89" #define 自动背光 "\x95\x96\x97\x98" #define 背光亮度 "\x97\x98\x99\x9A" #define 首尾音 "\x9B\x9C\x0B" #define MDC_ID "\x4D\x44\x43\x20\x49\x44" #define 尾音消除 "\x9C\x0B\x9D\x1F" #define 过中继尾音消除 "\x9E\x9F\xA0\x9C\x0B\x9D\x1F" #define 按键即呼 "\xA1\xA2\xA3\xA4" #define DTMF_ID "\x44\x54\x4D\x46\x20\x49\x44" #define DTMF上线码 "\x44\x54\x4D\x46\xA5\xA6\xA7" #define DTMF下线码 "\x44\x54\x4D\x46\xA8\xA6\xA7" #define DTMF发送 "\x44\x54\x4D\x46\x0E\x0F" #define DTMF侧音 "\x44\x54\x4D\x46\xA9\x0B" #define DTMF响应 "\x44\x54\x4D\x46\xAA\xAB" #define DTMF复位 "\x44\x54\x4D\x46\x88\xAC" #define DTMF预载波 "\x44\x54\x4D\x46\xAD\xAE\xAF" #define DTMF联系人 "\x44\x54\x4D\x46\xB0\xB1\xB2" #define DTMF显示 "\x44\x54\x4D\x46\x93\x94" #define AM自动增益 "\x41\x4D\x95\x96\x91\x92" #define 收发模式 "\x06\x0E\x0C\x89" #define 静噪等级 "\xB3\xB4\xB5\xB6" #define 频段解锁 "\x03\xB7\xB8\xB9" #define 电池调压 "\x8D\xBA\xBB\x18" #define 电池大小 "\x8D\xBA\xBC\xBD" #define 参数复位 "\xBE\x07\x88\xAC" #define 发送等于接收 "\x0E\x0F\x3D\x05\x06" #define 发送等于接收加偏移 "\x0E\x0F\x3D\n\x05\x06\x2B\xBF\xC0" #define 发送等于接收减偏移 "\x0E\x0F\x3D\n\x05\x06\x2D\xBF\xC0" #define 关闭 "\xC1\xC2" #define 开启 "\xC3\xC4" #define 一级 "\x31\x20\xB6" #define 二级 "\x32\x20\xB6" #define 三级 "\x33\x20\xB6" #define 四级 "\x34\x20\xB6" #define 三十秒 "\x33\x30\x20\xC5" #define 一分 "\x31\x20\xC6" #define 两分 "\x32\x20\xC6" #define 三分 "\x33\x20\xC6" #define 四分 "\x34\x20\xC6" #define 五分 "\x35\x20\xC6" #define 六分 "\x36\x20\xC6" #define 七分 "\x37\x20\xC6" #define 八分 "\x38\x20\xC6" #define 九分 "\x39\x20\xC6" #define 十五分 "\x31\x35\x20\xC6" #define 主信道接收发射 "\xC7\x1C\x1D\n\x05\x06\x0E\xC8" #define 双信道接收 "\xC9\x1C\x1D\n\x05\x06" #define 主信道发射副信道接收 "\xC7\x1C\x1D\x0E\xC8\n\xCA\x1C\x1D\x05\x06" #define 主信道发射双信道接收 "\xC7\x1C\x1D\x0E\xC8\n\xC9\x1C\x1D\x05\x06" #define 遇信号5秒后搜索 "\x15\x1C\xCB\n\x35\xC5\xCC\x85\x86" #define 信号停止后搜索 "\x1C\xCB\xCD\xCE\xCC\n\x85\x86" #define 遇信号后停止搜索 "\x15\x1C\xCB\xCC\n\xCD\xCE\x85\x86" #define 频率 "\x03\x04" #define 信道号 "\x1C\x1D\xCB" #define 名称 "\x80\xCF" #define 名称加频率 "\x80\xCF\x2B\n\x03\x04" #define 不响应 "\xD0\xAA\xAB" #define 本地响铃 "\xD1\xD2\xAA\xD3" #define 回复响应 "\xD4\x88\xAA\xAB" #define 本地响铃回复响应 "\xD1\xD2\xAA\xD3\n\xD4\x88\xAA\xAB" #define 不发送 "\xD0\x0E\x0F" #define 上线码 "\xA5\xA6\xA7" #define 下线码 "\xA8\xA6\xA7" #define 上线加下线码 "\xA5\xA6\x2B\xA8\xA6\xA7" #define Quindar码 "\x51\x75\x69\x6E\x64\x61\x72\xA7" #define 关闭 "\xC1\xC2" #define ROGER尾音 "\x52\x4F\x47\x45\x52\x9C\x0B" #define MDC尾音 "\x4D\x44\x43\x9C\x0B" #define MDC首音 "\x4D\x44\x43\x9B\x0B" #define MDC首尾音 "\x4D\x44\x43\x9B\x9C\x0B" #define MDC首音加ROGER "\x4D\x44\x43\x9B\x0B\x2B\n\x52\x4F\x47\x45\x52" #define 除信道参数 "\x1F\x1C\x1D\xBE\x07" #define 全部参数 "\xD5\xD6\xBE\x07" #define 禁用全部 "\x17\xD7\xD5\xD6" #define 解锁全部 "\xB8\xB9\xD5\xD6" #define 五秒 "\x35\x20\xC5" #define 十秒 "\x31\x30\x20\xC5" #define 二十秒 "\x32\x30\x20\xC5" #define 发送时 "\x0E\x0F\x8B" #define 接收时 "\x05\x06\x8B" #define 发送接收时 "\x0E\x0F\x2F\x05\x06\x8B" #define 列表 "\x83\x84" #define 全部 "\xD5\xD6" #define 扫描 "\x81\x82" #define 低电压 "\xD8\x8D\x18" #define 长按井键解锁 "\xD9\xA1\x20\x23\x20\xA2\xB8\xB9" #define 遇忙 "\x15\x16" #define 禁止发射 "\x17\xCE\x0E\xC8" #define 发送超时 "\x0E\x0F\x8A\x8B" #define 高电压 "\xDA\x8D\x18" #define 按EXIT键 "\xA1\x20\x45\x58\x49\x54\x20\xA2" #define 全部按键 "\xD5\xD6\xA1\xA2" #define 解锁 "\xB8\xB9" #define 模拟亚音 "\x0C\x0D\x09\x0B" #define 数字亚音 "\x07\x08\x09\x0B" #define 频率 "\x03\x04" #define 存置问 "\x1A\x1B\x3F" #define 存置了 "\x1A\x1B\x3A" #define 扫描 "\x81\x82" #define 删除问 "\x1E\x1F\x3F" #ifdef ENABLE_CUSTOM_SIDEFUNCTIONS #define 侧键1短按 "\xA9\xA2\x31\xDB\xA1" #define 侧键1长按 "\xA9\xA2\x31\xD9\xA1" #define 侧键2短按 "\xA9\xA2\x32\xDB\xA1" #define 侧键2长按 "\xA9\xA2\x32\xD9\xA1" #define M键长按 "\x4D\xA2\xD9\xA1" #define 手电 "\xDC\x8D" #define 切换发射功率 "\xDD\xDE\x0E\xC8\xDF\x04" #define 监听 "\xE0\xE1" #define 声控发射 "\xE2\xE3\x0E\xC8" #define FM收音机 "\x46\x4D\x06\x0B\xE4" #define 锁定按键 "\xB9\xE5\xA1\xA2" #define 切换信道 "\xDD\xDE\x1C\x1D" #define 切换信道模式 "\xDD\xDE\x1C\x1D\x0C\x89" #define 切换调制模式 "\xDD\xDE\xBB\xE6\x0C\x89" #define DTMF解码 "\x44\x54\x4D\x46\xB8\xA7" #define 切换宽窄带 "\xDD\xDE\xE7\xE8\xE9" #define 宽窄带 "\xE7\xE8\xE9" #define 宽带 "\xE7\xE9" #define 窄带 "\xE8\xE9" #ifdef ENABLE_SIDEFUNCTIONS_SEND #define 主信道发射 "\xC7\x1C\x1D\x0E\xC8" #define 副信道发射 "\xCA\x1C\x1D\x0E\xC8" #endif #endif #endif #elif ENABLE_CHINESE_FULL==4 #define 步进频率 "\xB2\xBD\xBD\xF8\xC6\xB5\xC2\xCA" #define 接收数字亚音 "\xBD\xD3\xCA\xD5\xCA\xFD\xD7\xD6\xD1\xC7\xD2\xF4" #define 接收模拟亚音 "\xBD\xD3\xCA\xD5\xC4\xA3\xC4\xE2\xD1\xC7\xD2\xF4" #define 发送数字亚音 "\xB7\xA2\xCB\xCD\xCA\xFD\xD7\xD6\xD1\xC7\xD2\xF4" #define 发送模拟亚音 "\xB7\xA2\xCB\xCD\xC4\xA3\xC4\xE2\xD1\xC7\xD2\xF4" #define 频差方向 "\xC6\xB5\xB2\xEE\xB7\xBD\xCF\xF2" #define 频差频率 "\xC6\xB5\xB2\xEE\xC6\xB5\xC2\xCA" #define 加密 "\xBC\xD3\xC3\xDC" #define 遇忙禁发 "\xD3\xF6\xC3\xA6\xBD\xFB\xB7\xA2" #define 压扩 "\xD1\xB9\xC0\xA9" #define 存置信道 "\xB1\xA3\xB4\xE6\xD0\xC5\xB5\xC0" #define 删除信道 "\xC9\xBE\xB3\xFD\xD0\xC5\xB5\xC0" #define 命名信道 "\xC3\xFC\xC3\xFB\xD0\xC5\xB5\xC0" #define 信道扫描列表 "\xD0\xC5\xB5\xC0\xC9\xA8\xC3\xE8\xC1\xD0\xB1\xED" #define 扫描列表1 "\xC9\xA8\xC3\xE8\xC1\xD0\xB1\xED\x31" #define 扫描列表2 "\xC9\xA8\xC3\xE8\xC1\xD0\xB1\xED\x32" #define 搜索恢复模式 "\xCB\xD1\xCB\xF7\xBB\xD6\xB8\xB4\xC4\xA3\xCA\xBD" #define 发送超时 "\xB7\xA2\xCB\xCD\xB3\xAC\xCA\xB1" #define 省电模式 "\xCA\xA1\xB5\xE7\xC4\xA3\xCA\xBD" #define 麦克风增益 "\xC2\xF3\xBF\xCB\xB7\xE7\xD4\xF6\xD2\xE6" #define 信道显示模式 "\xD0\xC5\xB5\xC0\xCF\xD4\xCA\xBE\xC4\xA3\xCA\xBD" #define 自动背光 "\xD7\xD4\xB6\xAF\xB1\xB3\xB9\xE2" #define 背光亮度 "\xB1\xB3\xB9\xE2\xC1\xC1\xB6\xC8" #define 首尾音 "\xCA\xD7\xCE\xB2\xD2\xF4" #define MDC_ID "\x4D\x44\x43\x20\x49\x44" #define 尾音消除 "\xCE\xB2\xD2\xF4\xCF\xFB\xB3\xFD" #define 过中继尾音消除 "\xB9\xFD\xD6\xD0\xBC\xCC\xCE\xB2\xD2\xF4\xCF\xFB\xB3\xFD" #define 按键即呼 "\xB0\xB4\xBC\xFC\xBC\xB4\xBA\xF4" #define DTMF_ID "\x44\x54\x4D\x46\x20\x49\x44" #define DTMF上线码 "\x44\x54\x4D\x46\xC9\xCF\xCF\xDF\xC2\xEB" #define DTMF下线码 "\x44\x54\x4D\x46\xCF\xC2\xCF\xDF\xC2\xEB" #define DTMF发送 "\x44\x54\x4D\x46\xB7\xA2\xCB\xCD" #define DTMF侧音 "\x44\x54\x4D\x46\xB2\xE0\xD2\xF4" #define DTMF响应 "\x44\x54\x4D\x46\xCF\xEC\xD3\xA6" #define DTMF复位 "\x44\x54\x4D\x46\xB8\xB4\xCE\xBB" #define DTMF预载波 "\x44\x54\x4D\x46\xD4\xA4\xD4\xD8\xB2\xA8" #define DTMF联系人 "\x44\x54\x4D\x46\xC1\xAA\xCF\xB5\xC8\xCB" #define DTMF显示 "\x44\x54\x4D\x46\xCF\xD4\xCA\xBE" #define AM自动增益 "\x41\x4D\xD7\xD4\xB6\xAF\xD4\xF6\xD2\xE6" #define 收发模式 "\xCA\xD5\xB7\xA2\xC4\xA3\xCA\xBD" #define 静噪等级 "\xBE\xB2\xD4\xEB\xB5\xC8\xBC\xB6" #define 频段解锁 "\xC6\xB5\xB6\xCE\xBD\xE2\xCB\xF8" #define 两百M发射 "\x32\x30\x30\x4D\xB7\xA2\xC9\xE4" #define 三百五十M发射 "\x33\x35\x30\x4D\xB7\xA2\xC9\xE4" #define 五百M发射 "\x35\x30\x30\x4D\xB7\xA2\xC9\xE4" #define 三百五十M接收 "\x33\x35\x30\x4D\xBD\xD3\xCA\xD5" #define 电池调压 "\xB5\xE7\xB3\xD8\xB5\xF7\xD1\xB9" #define 电池大小 "\xB5\xE7\xB3\xD8\xB4\xF3\xD0\xA1" #define 参数复位 "\xB2\xCE\xCA\xFD\xB8\xB4\xCE\xBB" #define 发送等于接收 "\xB7\xA2\xCB\xCD\x3D\xBD\xD3\xCA\xD5" #define 发送等于接收加偏移 "\xB7\xA2\xCB\xCD\x3D\n\xBD\xD3\xCA\xD5\x2B\xC6\xAB\xD2\xC6" #define 发送等于接收减偏移 "\xB7\xA2\xCB\xCD\x3D\n\xBD\xD3\xCA\xD5\x2D\xC6\xAB\xD2\xC6" #define 关闭 "\xB9\xD8\xB1\xD5" #define 开启 "\xBF\xAA\xC6\xF4" #define 一级 "\x31\x20\xBC\xB6" #define 二级 "\x32\x20\xBC\xB6" #define 三级 "\x33\x20\xBC\xB6" #define 四级 "\x34\x20\xBC\xB6" #define 三十秒 "\x33\x30\x20\xC3\xEB" #define 一分 "\x31\x20\xB7\xD6" #define 两分 "\x32\x20\xB7\xD6" #define 三分 "\x33\x20\xB7\xD6" #define 四分 "\x34\x20\xB7\xD6" #define 五分 "\x35\x20\xB7\xD6" #define 六分 "\x36\x20\xB7\xD6" #define 七分 "\x37\x20\xB7\xD6" #define 八分 "\x38\x20\xB7\xD6" #define 九分 "\x39\x20\xB7\xD6" #define 十五分 "\x31\x35\x20\xB7\xD6" #define 主信道接收发射 "\xD6\xF7\xD0\xC5\xB5\xC0\n\xBD\xD3\xCA\xD5\xB7\xA2\xC9\xE4" #define 双信道接收 "\xCB\xAB\xD0\xC5\xB5\xC0\n\xBD\xD3\xCA\xD5" #define 主信道发射副信道接收 "\xD6\xF7\xD0\xC5\xB5\xC0\xB7\xA2\xC9\xE4\n\xB8\xB1\xD0\xC5\xB5\xC0\xBD\xD3\xCA\xD5" #define 主信道发射双信道接收 "\xD6\xF7\xD0\xC5\xB5\xC0\xB7\xA2\xC9\xE4\n\xCB\xAB\xD0\xC5\xB5\xC0\xBD\xD3\xCA\xD5" #define 遇信号5秒后搜索 "\xD3\xF6\xD0\xC5\xBA\xC5\n\x35\xC3\xEB\xBA\xF3\xCB\xD1\xCB\xF7" #define 信号停止后搜索 "\xD0\xC5\xBA\xC5\xCD\xA3\xD6\xB9\xBA\xF3\n\xCB\xD1\xCB\xF7" #define 遇信号后停止搜索 "\xD3\xF6\xD0\xC5\xBA\xC5\xBA\xF3\n\xCD\xA3\xD6\xB9\xCB\xD1\xCB\xF7" #define 频率 "\xC6\xB5\xC2\xCA" #define 信道号 "\xD0\xC5\xB5\xC0\xBA\xC5" #define 名称 "\xC3\xFB\xB3\xC6" #define 名称加频率 "\xC3\xFB\xB3\xC6\x2B\n\xC6\xB5\xC2\xCA" #define 不响应 "\xB2\xBB\xCF\xEC\xD3\xA6" #define 本地响铃 "\xB1\xBE\xB5\xD8\xCF\xEC\xC1\xE5" #define 回复响应 "\xBB\xD8\xB8\xB4\xCF\xEC\xD3\xA6" #define 本地响铃回复响应 "\xB1\xBE\xB5\xD8\xCF\xEC\xC1\xE5\n\xBB\xD8\xB8\xB4\xCF\xEC\xD3\xA6" #define 不发送 "\xB2\xBB\xB7\xA2\xCB\xCD" #define 上线码 "\xC9\xCF\xCF\xDF\xC2\xEB" #define 下线码 "\xCF\xC2\xCF\xDF\xC2\xEB" #define 上线加下线码 "\xC9\xCF\xCF\xDF\x2B\xCF\xC2\xCF\xDF\xC2\xEB" #define Quindar码 "\x51\x75\x69\x6E\x64\x61\x72\xC2\xEB" #define 关闭 "\xB9\xD8\xB1\xD5" #define ROGER尾音 "\x52\x4F\x47\x45\x52\xCE\xB2\xD2\xF4" #define MDC尾音 "\x4D\x44\x43\xCE\xB2\xD2\xF4" #define MDC首音 "\x4D\x44\x43\xCA\xD7\xD2\xF4" #define MDC首尾音 "\x4D\x44\x43\xCA\xD7\xCE\xB2\xD2\xF4" #define MDC首音加ROGER "\x4D\x44\x43\xCA\xD7\xD2\xF4\x2B\n\x52\x4F\x47\x45\x52" #define 除信道参数 "\xB3\xFD\xD0\xC5\xB5\xC0\xB2\xCE\xCA\xFD" #define 全部参数 "\xC8\xAB\xB2\xBF\xB2\xCE\xCA\xFD" #define 禁用全部 "\xBD\xFB\xD3\xC3\xC8\xAB\xB2\xBF" #define 解锁全部 "\xBD\xE2\xCB\xF8\xC8\xAB\xB2\xBF" #define 五秒 "\x35\x20\xC3\xEB" #define 十秒 "\x31\x30\x20\xC3\xEB" #define 二十秒 "\x32\x30\x20\xC3\xEB" #define 发送时 "\xB7\xA2\xCB\xCD\xCA\xB1" #define 接收时 "\xBD\xD3\xCA\xD5\xCA\xB1" #define 发送接收时 "\xB7\xA2\xCB\xCD\x2F\xBD\xD3\xCA\xD5\xCA\xB1" #define 全部 "\xC8\xAB\xB2\xBF" #define 扫描 "\xC9\xA8\xC3\xE8" #define 低电压 "\xB5\xCD\xB5\xE7\xD1\xB9" #define 长按井键解锁 "\xB3\xA4\xB0\xB4\x20\x23\x20\xBC\xFC\xBD\xE2\xCB\xF8" #define 遇忙 "\xD3\xF6\xC3\xA6" #define 禁止发射 "\xBD\xFB\xD6\xB9\xB7\xA2\xC9\xE4" #define 发送超时 "\xB7\xA2\xCB\xCD\xB3\xAC\xCA\xB1" #define 高电压 "\xB8\xDF\xB5\xE7\xD1\xB9" #define 按EXIT键 "\xB0\xB4\x20\x45\x58\x49\x54\x20\xBC\xFC" #define 全部按键 "\xC8\xAB\xB2\xBF\xB0\xB4\xBC\xFC" #define 解锁 "\xBD\xE2\xCB\xF8" #define 存置问 "\xB1\xA3\xB4\xE6\x3F" #define 存置了 "\xB1\xA3\xB4\xE6\x3A" #define 扫描 "\xC9\xA8\xC3\xE8" #define 删除问 "\xC9\xBE\xB3\xFD\x3F" #define 列表 "\xC1\xD0\xB1\xED" #define 模拟亚音 "\xC4\xA3\xC4\xE2\xD1\xC7\xD2\xF4" #define 数字亚音 "\xCA\xFD\xD7\xD6\xD1\xC7\xD2\xF4" #define 图片 "\xCD\xBC\xC6\xAC" #define 信息 "\xD0\xC5\xCF\xA2" #define 侧键1短按 "\xB2\xE0\xBC\xFC\x31\xB6\xCC\xB0\xB4" #define 侧键1长按 "\xB2\xE0\xBC\xFC\x31\xB3\xA4\xB0\xB4" #define 侧键2短按 "\xB2\xE0\xBC\xFC\x32\xB6\xCC\xB0\xB4" #define 侧键2长按 "\xB2\xE0\xBC\xFC\x32\xB3\xA4\xB0\xB4" #define M键长按 "\x4D\xBC\xFC\xB3\xA4\xB0\xB4" #define 手电 "\xCA\xD6\xB5\xE7\xCD\xB2" #define 切换发射功率 "\xC7\xD0\xBB\xBB\xB7\xA2\xC9\xE4\xB9\xA6\xC2\xCA" #define 监听 "\xBC\xE0\xCC\xFD" #define 声控发射 "\xC9\xF9\xBF\xD8\xB7\xA2\xC9\xE4" #define FM收音机 "\x46\x4D\xCA\xD5\xD2\xF4\xBB\xFA" #define 锁定按键 "\xCB\xF8\xB6\xA8\xB0\xB4\xBC\xFC" #define 切换信道 "\xC7\xD0\xBB\xBB\xD0\xC5\xB5\xC0" #define 切换信道模式 "\xC7\xD0\xBB\xBB\xD0\xC5\xB5\xC0\xC4\xA3\xCA\xBD" #define 切换调制模式 "\xC7\xD0\xBB\xBB\xB5\xF7\xD6\xC6\xC4\xA3\xCA\xBD" #define DTMF解码 "\x44\x54\x4D\x46\xBD\xE2\xC2\xEB" #define 切换宽窄带 "\xC7\xD0\xBB\xBB\xBF\xED\xD5\xAD\xB4\xF8" #define 宽窄带 "\xBF\xED\xD5\xAD\xB4\xF8" #define 宽带 "\xBF\xED\xB4\xF8" #define 窄带 "\xD5\xAD\xB4\xF8" #define 主信道发射 "\xD6\xF7\xD0\xC5\xB5\xC0\xB7\xA2\xC9\xE4" #define 副信道发射 "\xB8\xB1\xD0\xC5\xB5\xC0\xB7\xA2\xC9\xE4" #define 开机显示 "\xBF\xAA\xBB\xFA\xCF\xD4\xCA\xBE" #endif #endif //UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H ================================================ FILE: compile-with-docker.bat ================================================ @echo on make clean docker build -t uvk5 . docker run --rm -v %CD%\compiled-firmware:/app/compiled-firmware uvk5 /bin/bash -c "cd /app &&rm -rf compiled&& make clean && make full&& cp *.bin compiled-firmware/" pause ================================================ FILE: compile-with-docker.sh ================================================ #!/bin/sh rm -rf compiled make clean docker build -t uvk5 . docker run --rm -v "$(pwd)/compiled-firmware:/app/compiled-firmware" uvk5 /bin/bash -c "cd /app && rm -rf compiled && make clean && make && cp *.bin compiled-firmware/" ================================================ FILE: dcs.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "driver/eeprom.h" #include "dcs.h" #ifndef ARRAY_SIZE #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) #endif #ifdef TEST_UNDE_CTCSS const uint16_t CTCSS_Options[50] = { 200, 693, 719, 744, 770, 797, 825, 854, 885, 915, 948, 974, 1000, 1035, 1072, 1109, 1148, 1188, 1230, 1273, 1318, 1365, 1413, 1462, 1514, 1567, 1598, 1622, 1655, 1679, 1713, 1738, 1773, 1799, 1835, 1862, 1899, 1928, 1966, 1995, 2035, 2065, 2107, 2181, 2257, 2291, 2336, 2418, 2503, 2541 }; #else //CTCSS Hz * 10 #if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH) const uint16_t CTCSS_Options[50] = { 670, 693, 719, 744, 770, 797, 825, 854, 885, 915, 948, 974, 1000, 1035, 1072, 1109, 1148, 1188, 1230, 1273, 1318, 1365, 1413, 1462, 1514, 1567, 1598, 1622, 1655, 1679, 1713, 1738, 1773, 1799, 1835, 1862, 1899, 1928, 1966, 1995, 2035, 2065, 2107, 2181, 2257, 2291, 2336, 2418, 2503, 2541 }; #endif #endif #if ENABLE_CHINESE_FULL == 0|| defined(ENABLE_ENGLISH) const uint16_t DCS_Options[104] = { 0x0013, 0x0015, 0x0016, 0x0019, 0x001A, 0x001E, 0x0023, 0x0027, 0x0029, 0x002B, 0x002C, 0x0035, 0x0039, 0x003A, 0x003B, 0x003C, 0x004C, 0x004D, 0x004E, 0x0052, 0x0055, 0x0059, 0x005A, 0x005C, 0x0063, 0x0065, 0x006A, 0x006D, 0x006E, 0x0072, 0x0075, 0x007A, 0x007C, 0x0085, 0x008A, 0x0093, 0x0095, 0x0096, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A9, 0x00AA, 0x00AD, 0x00B1, 0x00B3, 0x00B5, 0x00B6, 0x00B9, 0x00BC, 0x00C6, 0x00C9, 0x00CD, 0x00D5, 0x00D9, 0x00DA, 0x00E3, 0x00E6, 0x00E9, 0x00EE, 0x00F4, 0x00F5, 0x00F9, 0x0109, 0x010A, 0x010B, 0x0113, 0x0119, 0x011A, 0x0125, 0x0126, 0x012A, 0x012C, 0x012D, 0x0132, 0x0134, 0x0135, 0x0136, 0x0143, 0x0146, 0x014E, 0x0153, 0x0156, 0x015A, 0x0166, 0x0175, 0x0186, 0x018A, 0x0194, 0x0197, 0x0199, 0x019A, 0x01AC, 0x01B2, 0x01B4, 0x01C3, 0x01CA, 0x01D3, 0x01D9, 0x01DA, 0x01DC, 0x01E3, 0x01EC, }; #endif static uint32_t DCS_CalculateGolay(uint32_t CodeWord) { unsigned int i; uint32_t Word = CodeWord; for (i = 0; i < 12; i++) { Word <<= 1; if (Word & 0x1000) Word ^= 0x08EA; } return CodeWord | ((Word & 0x0FFE) << 11); } uint32_t DCS_GetGolayCodeWord(DCS_CodeType_t CodeType, uint8_t Option) { #if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH) uint32_t Code = DCS_CalculateGolay(DCS_Options[Option] + 0x800U); #else uint8_t read_tmp[2]; EEPROM_ReadBuffer(0x02C64+(Option)*2, read_tmp, 2); uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8); uint32_t Code = DCS_CalculateGolay(DCS_Options_read + 0x800U); #endif // uint32_t Code = DCS_CalculateGolay(DCS_Options[Option] + 0x800U); if (CodeType == CODE_TYPE_REVERSE_DIGITAL) Code ^= 0x7FFFFF; return Code; } uint8_t DCS_GetCdcssCode(uint32_t Code) { unsigned int i; for (i = 0; i < 23; i++) { uint32_t Shift; if (((Code >> 9) & 0x7U) == 4) { unsigned int j; for (j = 0; j < 104; j++) { #if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH) if (DCS_Options[j] == (Code & 0x1FF)) #else uint8_t read_tmp[2]; EEPROM_ReadBuffer(0x02C64+(j)*2, read_tmp, 2); uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8); if (DCS_Options_read == (Code & 0x1FF)) #endif if (DCS_GetGolayCodeWord(2, j) == Code) return j; } } Shift = Code >> 1; if (Code & 1U) Shift |= 0x400000U; Code = Shift; } return 0xFF; } uint8_t DCS_GetCtcssCode(int Code) { unsigned int i; uint8_t Result = 0xFF; int Smallest = 50; for (i = 0; i < 50; i++) { #if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH) int Delta = Code - CTCSS_Options[i]; if (Delta < 0) Delta = -(Code - CTCSS_Options[i]); #else uint8_t read_tmp[2]; EEPROM_ReadBuffer(0x02C00+i*2, read_tmp, 2); uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8); int Delta = Code - CTCSS_Options_read; if (Delta < 0) Delta = -(Code - CTCSS_Options_read); #endif if (Smallest > Delta) { Smallest = Delta; Result = i; } } return Result; } #ifdef TEST_UNDE_CTCSS uint16_t DCS_GetCtcssCode_ALL(int Code) { unsigned int i; uint16_t Result = 0xFFFF; int Smallest = 50; for (i = 0; i <2550; i++) { int Delta = Code - i; if (Delta < 0) Delta = -(Code - i); if (Smallest > Delta) { Smallest = Delta; Result = i; } } return Result; } #endif ================================================ FILE: dcs.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DCS_H #define DCS_H #include enum DCS_CodeType_t { CODE_TYPE_OFF = 0, CODE_TYPE_CONTINUOUS_TONE, CODE_TYPE_DIGITAL, CODE_TYPE_REVERSE_DIGITAL }; typedef enum DCS_CodeType_t DCS_CodeType_t; enum { CDCSS_POSITIVE_CODE = 1U, CDCSS_NEGATIVE_CODE = 2U, }; extern const uint16_t CTCSS_Options[50]; extern const uint16_t DCS_Options[104]; uint32_t DCS_GetGolayCodeWord(DCS_CodeType_t CodeType, uint8_t Option); uint8_t DCS_GetCdcssCode(uint32_t Code); uint8_t DCS_GetCtcssCode(int Code); #ifdef TEST_UNDE_CTCSS uint16_t DCS_GetCtcssCode_ALL(int Code); #endif #endif ================================================ FILE: debugging.h ================================================ #ifndef DEBUGGING_H #define DEBUGGING_H #ifdef ENABLE_UART #include "driver/uart.h" #include "driver/bk4819.h" #include "string.h" #include #include "am_fix.h" static inline void LogUartf(const char* format, ...) { char buffer[128]; va_list va; va_start(va, format); vsnprintf(buffer, (size_t)-1, format, va); va_end(va); UART_Send(buffer, strlen(buffer)); } static inline void LogUart(const char *const str) { UART_Send(str, strlen(str)); } static inline void LogRegUart(uint16_t reg) { uint16_t regVal = BK4819_ReadRegister(reg); char buf[32]; sprintf(buf, "reg%02X: %04X\n", reg, regVal); LogUart(buf); } static inline void LogPrint() { uint16_t rssi = BK4819_GetRSSI(); uint16_t reg7e = BK4819_ReadRegister(0x7E); char buf[32]; sprintf(buf, "reg7E: %d %2d %6d %2d %d rssi: %d\n", (reg7e >> 15), (reg7e >> 12) & 0b111, (reg7e >> 5) & 0b1111111, (reg7e >> 2) & 0b111, (reg7e >> 0) & 0b11, rssi); LogUart(buf); } #endif #endif ================================================ FILE: del_linux.sh ================================================ #!/bin/bash target_directory="./" find "$target_directory" -type f \( -name "*.o" -o -name "*.d" \) -delete echo "Deletion complete." ================================================ FILE: del_win.bat ================================================ @echo off setlocal rem ĿĿ¼ set "target_directory=./" rem 滻ΪĿĿ¼· rem ɾ .o .d ļ for /r "%target_directory%" %%f in (*.o *.d) do ( del "%%f" ) echo Deletion complete. endlocal ================================================ FILE: doc/多普勒eeprom详细说明.txt ================================================ 0x02BA0~0x2BA9 10B,卫星名称,首字符在前,最多9个英文，最后一个为'\0' 0x2BAA 1B,开始过境时间的年份的十位个位，0~99，如:2024即为24 0x2BAB 1B,开始过境时间的月份，1~12 0x2BAC 1B,开始过境时间的日期，1~31 0x2BAD 1B,开始过境时间的时，0~23 0x2BAE 1B,开始过境时间的分，0~59 0x2BAF 1B,开始过境时间的秒，0~59 0x2BB0 1B,离境时间的年份的十位个位，0~99，如:2077即为77 0x2BB1 1B,离境时间的月份，1~12 0x2BB2 1B,离境时间的日期，1~31 0x2BB3 1B,离境时间的时，0~23 0x2BB4 1B,离境时间的分，0~59 0x2BB5 1B,离境时间的秒，0~59 0x2BB6~0x2BB7 2B，总的过境时间（秒），低位在前，高位在后 0x2BB8~0x2BB9 2B，手台的发射亚音，低位在前，高位在后 0x2BBA~0x2BBB 2B，手台的接收亚音，低位在前，高位在后 0x2BBC~0X2BBF ,4B,为开始过境时间的UNIX时间戳与2000年1月1日UNIX时间戳的差,4B，正整数，低位在前，高位在后 0X2BC0~0X2BC5 时间 第n秒的卫星数据共8B，从0x1E200开始存放，2秒更新一次，最多支持(0X20000-0x1E200)/8*2=1920s=32min 也就是说:0B~7B放第1秒卫星的频率（第1秒=开始过境时间） 8B~15B放第3秒卫星的频率 16B~23B放第5秒卫星的频率 8B包括: 上行频率/10（正整数hz）4B、下行频率/10(正整数hz)4B 第1B~4B:上行频率/10,只有正,如:438.5MHZ，那么为438,500,00，都是低位在前，高位在后 第5B~8B:下行频率/10,只有正,如:144.5MHZ，那么为144,500,00，都是低位在前，高位在后 (K5频率精度为10，所以/10方便处理) ================================================ FILE: dp32g030.cfg ================================================ transport select hla_swd reset_config srst_only srst_nogate connect_assert_srst gdb breakpoint_override hard adapter speed 24000 adapter srst delay 100 reset_config srst_nogate set _CHIP_NAME DP32G0xx set CPUTAPID 0x0bb11477 # Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan swd newdap $_CHIP_NAME cpu -enable -expected-id $CPUTAPID # Create the DAP instance, this must be explicitly created according to the OpenOCD docs dap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu # Set up the GDB target for the CPU, cortex_m is the CPU type, target create $_CHIP_NAME.cpu cortex_m -dap $_CHIP_NAME.dap set _SECTOR_SIZE 512 proc uv_clear_flash_sector {sector_number} { echo [format "Erasing sector 0x%02x = offset 0x%04x" [expr {$sector_number}] [expr {$sector_number*256}] ] write_memory 0x4006F000 32 {0x09} ;#set erasing mode write_memory 0x4006F004 32 [expr {$sector_number << 6}] write_memory 0x4006F01c 32 {0xAA} ;#unlock flash write_memory 0x4006F010 32 {0x01} ;#set OPSTART=1 read_memory 0x4006F014 32 1 ;#check status for 0x02 uv_wait_busy write_memory 0x4006F018 32 {0x55} ;#lock flash } proc uv_clear_whole_flash {} { for {set i 0} {$i < 0x100} {incr i} { uv_clear_flash_sector $i } } proc uv_clear_sectors {sectors_count} { for {set i 0} {$i < $sectors_count} {incr i} { uv_clear_flash_sector $i } } proc uv_flash_unlock {} { write_memory 0x4006F01c 32 {0xAA} ;#unlock flash uv_wait_busy } proc uv_flash_lock {} { write_memory 0x4006F018 32 {0x55} ;#lock flash uv_wait_busy } proc uv_flash_write {address value} { write_memory 0x4006F000 32 {0x05} ;#set writing mode write_memory 0x4006F004 32 [expr {($address>>2)+0xC000}] ;#set address in flash write_memory 0x4006F008 32 $value ;#set data write_memory 0x4006F010 32 {0x01} ;#set OPSTART=1 while {1} { set status [read_memory 0x4006F014 32 1] if {($status & 0x4) != 0} { break } } uv_wait_busy } proc uv_wait_busy {} { while {1} { set status [read_memory 0x4006F014 32 1] if {($status & 0x2) == 0} { break } } } proc write_image {filename address} { global _SECTOR_SIZE set fs [file size $filename] set fd [open $filename "rb"] echo "Checking mask" set status [read_memory 0x4006F020 32 1] if {$status != 6} { echo "Changing mask" write_memory 0x4006F020 32 0 uv_wait_busy write_memory 0x4006F020 32 6 uv_wait_busy set status [read_memory 0x4006F020 32 1] if {$status != 6} { echo [format "Cannot set flash mask %d!" $status] close $fd return } } uv_clear_sectors [expr {(($fs+$_SECTOR_SIZE-1)&(0x10000000-$_SECTOR_SIZE))/($_SECTOR_SIZE/2)}] uv_flash_unlock set addr $address while {![eof $fd]} { set data [read $fd 4] if {[string length $data] == 4} { set b0 [scan [string index $data 0] %c] set b1 [scan [string index $data 1] %c] set b2 [scan [string index $data 2] %c] set b3 [scan [string index $data 3] %c] set i_data [expr {$b0 | $b1 << 8 | $b2 << 16 | $b3 << 24}] echo [format "Writing 0x%04x to address 0x%04x (%02d %%)" $i_data $addr [expr {(100*($addr+4)/$fs)}]] uv_flash_write $addr $i_data incr addr 4 } } uv_flash_lock close $fd } # dap init init halt # reset halt ================================================ FILE: driver/adc.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM0.h" #include "adc.h" #include "bsp/dp32g030/irq.h" #include "bsp/dp32g030/saradc.h" #include "bsp/dp32g030/syscon.h" uint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask) { return __builtin_ctz(Mask); } void ADC_Disable(void) { SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_DISABLE; } void ADC_Enable(void) { SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_ENABLE; } void ADC_SoftReset(void) { SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_ASSERT; SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_DEASSERT; } // The firmware thinks W_SARADC_SMPL_CLK_SEL is at [8:7] but the TRM says it's at [10:9] #define FW_R_SARADC_SMPL_SHIFT 7 #define FW_R_SARADC_SMPL_MASK (3U << FW_R_SARADC_SMPL_SHIFT) uint32_t ADC_GetClockConfig(void) { uint32_t Value; Value = SYSCON_CLK_SEL; Value = 0 | (Value & ~(SYSCON_CLK_SEL_R_PLL_MASK | FW_R_SARADC_SMPL_MASK)) | (((Value & SYSCON_CLK_SEL_R_PLL_MASK) >> SYSCON_CLK_SEL_R_PLL_SHIFT) << SYSCON_CLK_SEL_W_PLL_SHIFT) | (((Value & FW_R_SARADC_SMPL_MASK) >> FW_R_SARADC_SMPL_SHIFT) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT); return Value; } void ADC_Configure() { SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE; ADC_Disable(); SYSCON_CLK_SEL = (ADC_GetClockConfig() & ~SYSCON_CLK_SEL_W_SARADC_SMPL_MASK) | ((SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) & SYSCON_CLK_SEL_W_SARADC_SMPL_MASK); SARADC_CFG = 0 | (SARADC_CFG & ~(0 | SARADC_CFG_CH_SEL_MASK | SARADC_CFG_AVG_MASK | SARADC_CFG_CONT_MASK | SARADC_CFG_SMPL_SETUP_MASK | SARADC_CFG_MEM_MODE_MASK | SARADC_CFG_SMPL_CLK_MASK | SARADC_CFG_SMPL_WIN_MASK | SARADC_CFG_ADC_TRIG_MASK | SARADC_CFG_DMA_EN_MASK )) | (((ADC_CH4 | ADC_CH9) << SARADC_CFG_CH_SEL_SHIFT) & SARADC_CFG_CH_SEL_MASK) | ((SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT) & SARADC_CFG_AVG_MASK) | ((SARADC_CFG_CONT_VALUE_SINGLE<< SARADC_CFG_CONT_SHIFT) & SARADC_CFG_CONT_MASK) | ((SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) & SARADC_CFG_SMPL_SETUP_MASK) | ((SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT) & SARADC_CFG_MEM_MODE_MASK) | ((SARADC_CFG_SMPL_CLK_VALUE_INTERNAL<< SARADC_CFG_SMPL_CLK_SHIFT) & SARADC_CFG_SMPL_CLK_MASK) | ((SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) & SARADC_CFG_SMPL_WIN_MASK) | ((SARADC_CFG_ADC_TRIG_VALUE_CPU<< SARADC_CFG_ADC_TRIG_SHIFT) & SARADC_CFG_ADC_TRIG_MASK) | ((SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT) & SARADC_CFG_DMA_EN_MASK); SARADC_EXTTRIG_SEL =0; SARADC_CALIB_OFFSET = (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_YES; SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_YES; SARADC_IF = 0xFFFFFFFF; SARADC_IE = 0 | (SARADC_IE & ~(0 | SARADC_IE_CHx_EOC_MASK | SARADC_IE_FIFO_FULL_MASK | SARADC_IE_FIFO_HFULL_MASK )) | ((SARADC_IE_CHx_EOC_VALUE_NONE<< SARADC_IE_CHx_EOC_SHIFT) & SARADC_IE_CHx_EOC_MASK) | ((SARADC_IE_FIFO_FULL_VALUE_DISABLE<< SARADC_IE_FIFO_FULL_SHIFT) & SARADC_IE_FIFO_FULL_MASK) | ((SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT) & SARADC_IE_FIFO_HFULL_MASK); if (SARADC_IE == 0) { NVIC_DisableIRQ((IRQn_Type) DP32_SARADC_IRQn); } else { NVIC_EnableIRQ((IRQn_Type) DP32_SARADC_IRQn); } } void ADC_Start(void) { SARADC_START = (SARADC_START & ~SARADC_START_START_MASK) | SARADC_START_START_BITS_ENABLE; } bool ADC_CheckEndOfConversion(ADC_CH_MASK Mask) { volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *) &SARADC_CH0; uint8_t Channel = ADC_GetChannelNumber(Mask); return (pChannels[Channel].STAT & ADC_CHx_STAT_EOC_MASK) >> ADC_CHx_STAT_EOC_SHIFT; } uint16_t ADC_GetValue(ADC_CH_MASK Mask) { volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *) &SARADC_CH0; uint8_t Channel = ADC_GetChannelNumber(Mask); SARADC_IF = 1 << Channel; // TODO: Or just use 'Mask' return (pChannels[Channel].DATA & ADC_CHx_DATA_DATA_MASK) >> ADC_CHx_DATA_DATA_SHIFT; } ================================================ FILE: driver/adc.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_ADC_H #define DRIVER_ADC_H #include #include enum ADC_CH_MASK { ADC_CH0 = 0x0001U, ADC_CH1 = 0x0002U, ADC_CH2 = 0x0004U, ADC_CH3 = 0x0008U, ADC_CH4 = 0x0010U, ADC_CH5 = 0x0020U, ADC_CH6 = 0x0040U, ADC_CH7 = 0x0080U, ADC_CH8 = 0x0100U, ADC_CH9 = 0x0200U, ADC_CH10 = 0x0400U, ADC_CH11 = 0x0800U, ADC_CH12 = 0x1000U, ADC_CH13 = 0x2000U, ADC_CH14 = 0x4000U, ADC_CH15 = 0x8000U, }; typedef enum ADC_CH_MASK ADC_CH_MASK; //typedef struct { // uint16_t EXTTRIG_SEL; // uint16_t IE_CHx_EOC; // ADC_CH_MASK CH_SEL; // uint8_t CLK_SEL; // uint8_t AVG; // uint8_t CONT; // uint8_t MEM_MODE; // uint8_t SMPL_CLK; // uint8_t SMPL_SETUP; // uint8_t SMPL_WIN; // uint8_t ADC_TRIG; // uint8_t DMA_EN; // uint8_t IE_FIFO_HFULL; // uint8_t IE_FIFO_FULL; // bool CALIB_OFFSET_VALID; // bool CALIB_KD_VALID; // uint8_t _pad[1]; //} ADC_Config_t; uint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask); void ADC_Disable(void); void ADC_Enable(void); void ADC_SoftReset(void); uint32_t ADC_GetClockConfig(void); void ADC_Configure(); void ADC_Start(void); bool ADC_CheckEndOfConversion(ADC_CH_MASK Mask); uint16_t ADC_GetValue(ADC_CH_MASK Mask); #endif ================================================ FILE: driver/aes.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "bsp/dp32g030/aes.h" #include "driver/aes.h" static void AES_Setup_ENC_CBC(bool IsDecrypt, const void *pKey, const void *pIv) { const uint32_t *pK = (const uint32_t *) pKey; const uint32_t *pI = (const uint32_t *) pIv; (void) IsDecrypt; // unused AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_DISABLE; AES_CR = AES_CR_CHMOD_BITS_CBC; AES_KEYR3 = pK[0]; AES_KEYR2 = pK[1]; AES_KEYR1 = pK[2]; AES_KEYR0 = pK[3]; AES_IVR3 = pI[0]; AES_IVR2 = pI[1]; AES_IVR1 = pI[2]; AES_IVR0 = pI[3]; AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_ENABLE; } static void AES_Transform(const void *pIn, void *pOut) { const uint32_t *pI = (const uint32_t *) pIn; uint32_t *pO = (uint32_t *) pOut; AES_DINR = pI[0]; AES_DINR = pI[1]; AES_DINR = pI[2]; AES_DINR = pI[3]; while ((AES_SR & AES_SR_CCF_MASK) == AES_SR_CCF_BITS_NOT_COMPLETE) { } pO[0] = AES_DOUTR; pO[1] = AES_DOUTR; pO[2] = AES_DOUTR; pO[3] = AES_DOUTR; AES_CR |= AES_CR_CCFC_BITS_SET; } void AES_Encrypt(const void *pKey, const void *pIv, const void *pIn, void *pOut, uint8_t NumBlocks) { const uint8_t *pI = (const uint8_t *) pIn; uint8_t *pO = (uint8_t *) pOut; uint8_t i; AES_Setup_ENC_CBC(0, pKey, pIv); for (i = 0; i < NumBlocks; i++) { AES_Transform(pI + (i * 16), pO + (i * 16)); } } ================================================ FILE: driver/aes.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_AES_H #define DRIVER_AES_H #include void AES_Encrypt(const void *pKey, const void *pIv, const void *pIn, void *pOut, uint8_t NumBlocks); #endif ================================================ FILE: driver/backlight.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "backlight.h" #include "bsp/dp32g030/gpio.h" #include "bsp/dp32g030/pwmplus.h" #include "bsp/dp32g030/portcon.h" #include "driver/gpio.h" #include "settings.h" // this is decremented once every 500ms uint16_t gBacklightCountdown_500ms = 0; bool backlightOn; void BACKLIGHT_InitHardware() { // 48MHz / 94 / 1024 ~ 500Hz const uint32_t PWM_FREQUENCY_HZ = 25000; PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16); PWM_PLUS0_PERIOD = 1023; PORTCON_PORTB_SEL0 &= ~(0 // Back light | PORTCON_PORTB_SEL0_B6_MASK ); PORTCON_PORTB_SEL0 |= 0 // Back light PWM | PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0; PWM_PLUS0_GEN = PWMPLUS_GEN_CH0_OE_BITS_ENABLE | PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE | 0; PWM_PLUS0_CFG = PWMPLUS_CFG_CNT_REP_BITS_ENABLE | PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE | 0; } unsigned short BACKLIGHT_MAP[7]={11,21,41,121,241,481,0}; void BACKLIGHT_TurnOn(void) { if (gEeprom.BACKLIGHT_TIME == 0) { BACKLIGHT_TurnOff(); return; } backlightOn = true; BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX); gBacklightCountdown_500ms = BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1]; } void BACKLIGHT_TurnOff() { #ifdef ENABLE_BLMIN_TMP_OFF register uint8_t tmp; tmp = 0; BACKLIGHT_SetBrightness(tmp); #else BACKLIGHT_SetBrightness(0); #endif gBacklightCountdown_500ms = 0; backlightOn = false; } bool BACKLIGHT_IsOn() { return backlightOn; } static uint8_t currentBrightness; void BACKLIGHT_SetBrightness(uint8_t brigtness) { const uint8_t value[]= {0,3,6,9,15,24,38,62,100,159,255}; currentBrightness = brigtness; PWM_PLUS0_CH0_COMP = value[brigtness]<<2; //PWM_PLUS0_SWLOAD = 1; } uint8_t BACKLIGHT_GetBrightness(void) { return currentBrightness; } ================================================ FILE: driver/backlight.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_BACKLIGHT_H #define DRIVER_BACKLIGHT_H #include #include extern uint16_t gBacklightCountdown_500ms; extern uint8_t gBacklightBrightness; #ifdef ENABLE_BLMIN_TMP_OFF typedef enum { BLMIN_STAT_ON, BLMIN_STAT_OFF, BLMIN_STAT_UNKNOWN } BLMIN_STAT_t; #endif void BACKLIGHT_InitHardware(); void BACKLIGHT_TurnOn(); void BACKLIGHT_TurnOff(); bool BACKLIGHT_IsOn(); void BACKLIGHT_SetBrightness(uint8_t brigtness); uint8_t BACKLIGHT_GetBrightness(void); extern unsigned short BACKLIGHT_MAP[7]; #endif ================================================ FILE: driver/bk1080-regs.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef BK1080_REGS_H #define BK1080_REGS_H enum BK1080_Register_t { BK1080_REG_00 = 0x00U, BK1080_REG_02_POWER_CONFIGURATION = 0x02U, BK1080_REG_03_CHANNEL = 0x03U, BK1080_REG_05_SYSTEM_CONFIGURATION2 = 0x05U, BK1080_REG_07 = 0x07U, BK1080_REG_10 = 0x0AU, BK1080_REG_25_INTERNAL = 0x19U, }; typedef enum BK1080_Register_t BK1080_Register_t; // REG 07 #define BK1080_REG_07_SHIFT_FREQD 4 #define BK1080_REG_07_SHIFT_SNR 0 #define BK1080_REG_07_MASK_FREQD (0xFFFU << BK1080_REG_07_SHIFT_FREQD) #define BK1080_REG_07_MASK_SNR (0x00FU << BK1080_REG_07_SHIFT_SNR) #define BK1080_REG_07_GET_FREQD(x) (((x) & BK1080_REG_07_MASK_FREQD) >> BK1080_REG_07_SHIFT_FREQD) #define BK1080_REG_07_GET_SNR(x) (((x) & BK1080_REG_07_MASK_SNR) >> BK1080_REG_07_SHIFT_SNR) // REG 10 #define BK1080_REG_10_SHIFT_AFCRL 12 #define BK1080_REG_10_SHIFT_RSSI 0 #define BK1080_REG_10_MASK_AFCRL (0x01U << BK1080_REG_10_SHIFT_AFCRL) #define BK1080_REG_10_MASK_RSSI (0xFFU << BK1080_REG_10_SHIFT_RSSI) #define BK1080_REG_10_AFCRL_NOT_RAILED (0U << BK1080_REG_10_SHIFT_AFCRL) #define BK1080_REG_10_AFCRL_RAILED (1U << BK1080_REG_10_SHIFT_AFCRL) #define BK1080_REG_10_GET_RSSI(x) (((x) & BK1080_REG_10_MASK_RSSI) >> BK1080_REG_10_SHIFT_RSSI) #endif ================================================ FILE: driver/bk1080.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "bsp/dp32g030/gpio.h" #include "bk1080.h" #include "driver/gpio.h" #include "driver/i2c.h" #include "driver/system.h" #include "frequencies.h" #include "misc.h" //#define CHAN_SPACING 0u // 200kHz //#define CHAN_SPACING 1u // 100kHz #define CHAN_SPACING 2u // 50kHz #define VOLUME 15u #define SEEK_THRESHOLD 10u const freq_band_table_t FM_RADIO_FREQ_BAND_TABLE[] = { {875, 1080}, // 87.5 ~ 108 MHz {760, 1080}, // 76 ~ 108 MHz {760, 900}, // 76 ~ 90 MHz {640, 760} // 64 ~ 76 MHz }; static const uint16_t BK1080_RegisterTable[] = { 0x0008, // 0x00 0x1080, // 0x01 chip ID (1u << 9) | (1u << 0), // 0x02 0x0201 0000001000000001 0x0000, // 0x03 0x40C0, // 0x04 0100000011000000 (SEEK_THRESHOLD << 8) | (0u << 6) | (CHAN_SPACING << 4) | (VOLUME << 0), // 0x0A1F, // 0x05 00001010 00 01 1111 0x002E, // 0x06 0000000000101110 0x02FF, // 0x07 0000001011111111 0x5B11, // 0x08 0101101100010001 0x0000, // 0x09 0x411E, // 0x0A 0100000100011110 0x0000, // 0x0B 0xCE00, // 0x0C 1100111000000000 0x0000, // 0x0D 0x0000, // 0x0E 0x1000, // 0x0F 1000000000000000 0x3197, // 0x10 0011000110010111 0x0000, // 0x11 0x13FF, // 0x12 0001001111111111 0x9852, // 0x13 1001100001010010 0x0000, // 0x14 0x0000, // 0x15 0x0008, // 0x16 0x0000, // 0x17 0x51E1, // 0x18 0101000111100001 0xA8BC, // 0x19 1010100010111100 0x2645, // 0x1A 0010011001000101 0x00E4, // 0x1B 0000000011100100 0x1CD8, // 0x1C 0001110011011000 0x3A50, // 0x1D 0011101001010000 0xEAE0, // 0x1E 1110101011100000 0x3000, // 0x1F 0011000000000000 0x0200, // 0x20 0010000000000000 0x0000 // 0x21 }; uint16_t BK1080_BaseFrequency; uint16_t BK1080_FrequencyDeviation; bool is_init; uint16_t BK1080_freq_lower; uint16_t BK1080_freq_upper; uint16_t BK1080_freq_base; int16_t BK1080_freq_offset; void BK1080_Init(const uint16_t frequency, const bool initialise) { unsigned int i; // determine the lower and upper frequency limits when multiple bands are used if (!is_init) { BK1080_freq_base = 0; BK1080_freq_offset = 0; BK1080_freq_lower = 0xffff; BK1080_freq_upper = 0; for (i = 0; i < ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE); i++) { const uint16_t lower = FM_RADIO_FREQ_BAND_TABLE[i].lower; const uint16_t upper = FM_RADIO_FREQ_BAND_TABLE[i].upper; if (BK1080_freq_lower > lower) BK1080_freq_lower = lower; if (BK1080_freq_upper < upper) BK1080_freq_upper = upper; } } if (initialise) { // init and enable the chip GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080); if (!is_init) { for (i = 0; i < ARRAY_SIZE(BK1080_RegisterTable); i++) BK1080_WriteRegister(i, BK1080_RegisterTable[i]); SYSTEM_DelayMs(250); BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA83C); // 1010 1000 0011 1100 BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA8BC); // 1010 1000 1011 1100 SYSTEM_DelayMs(60); is_init = true; } else { BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, (1u << 9) | (1u << 0)); } BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, 0x0A5F); // 0000 1010 0101 1111 BK1080_SetFrequency(frequency); } else { // disable the chip BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, (1u << 9) | (1u << 6) | (1u << 0)); // 0x0241); // 0000 0010 0100 0001 GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080); } } uint16_t BK1080_ReadRegister(BK1080_Register_t Register) { uint8_t Value[2]; I2C_Start(); I2C_Write(0x80); I2C_Write((Register << 1) | I2C_READ); I2C_ReadBuffer(Value, sizeof(Value)); I2C_Stop(); return (Value[0] << 8) | Value[1]; } void BK1080_WriteRegister(BK1080_Register_t Register, uint16_t Value) { I2C_Start(); I2C_Write(0x80); I2C_Write((Register << 1) | I2C_WRITE); Value = ((Value >> 8) & 0xFF) | ((Value & 0xFF) << 8); I2C_WriteBuffer(&Value, sizeof(Value)); I2C_Stop(); } void BK1080_Mute(const bool Mute) { BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, (1u << 9) | (1u << 0) | (Mute ? 1u << 14 : 0u)); } void BK1080_SetFrequency(uint16_t Frequency) { int channel; uint16_t band = 0; // determine which band to use for (band = 0; band < ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE); band++) if (Frequency >= FM_RADIO_FREQ_BAND_TABLE[band].lower && Frequency < FM_RADIO_FREQ_BAND_TABLE[band].upper) break; if (band >= ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE)) { Frequency = BK1080_freq_lower; } // channel = (int)Frequency - FM_RADIO_FREQ_BAND_TABLE[band].lower; // 100kHz channel spacing channel = ((int) Frequency - FM_RADIO_FREQ_BAND_TABLE[band].lower) * 2; // 50kHz channel spacing channel = (channel < 0) ? 0 : (channel > 1023) ? 1023 : channel; BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, (SEEK_THRESHOLD << 8) | (band << 6) | (CHAN_SPACING << 4) | (VOLUME << 0)); BK1080_WriteRegister(BK1080_REG_03_CHANNEL, (uint16_t) channel); // SYSTEM_DelayMs(1); BK1080_WriteRegister(BK1080_REG_03_CHANNEL, (uint16_t) channel | (1u << 15)); } int16_t BK1080_get_freq_offset(const uint16_t Frequency) { BK1080_freq_base = Frequency; BK1080_freq_offset = (int16_t) BK1080_ReadRegister(BK1080_REG_07) / 16; return BK1080_freq_offset; } void BK1080_GetFrequencyDeviation(uint16_t Frequency) { BK1080_BaseFrequency = Frequency; BK1080_FrequencyDeviation = BK1080_ReadRegister(BK1080_REG_07) / 16; } ================================================ FILE: driver/bk1080.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_BK1080_H #define DRIVER_BK1080_H #include #include #include "driver/bk1080-regs.h" extern uint16_t BK1080_BaseFrequency; extern uint16_t BK1080_FrequencyDeviation; void BK1080_Init(uint16_t Frequency, bool bDoScan); uint16_t BK1080_ReadRegister(BK1080_Register_t Register); void BK1080_WriteRegister(BK1080_Register_t Register, uint16_t Value); void BK1080_Mute(bool Mute); void BK1080_SetFrequency(uint16_t Frequency); void BK1080_GetFrequencyDeviation(uint16_t Frequency); #endif ================================================ FILE: driver/bk4819-regs.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef BK4819_REGS_H #define BK4819_REGS_H #include typedef struct { const char *name; uint8_t num; uint8_t offset; uint16_t mask; uint16_t inc; } RegisterSpec; static const RegisterSpec afcDisableRegSpec = {"AFC Disable", 0x73, 4, 1, 1}; static const RegisterSpec afOutRegSpec = {"AF Output Select", 0x47, 8, 0xF, 1}; static const RegisterSpec afDacGainRegSpec = {"AF DAC Gain", 0x48, 0, 0xF, 1}; enum BK4819_REGISTER_t { BK4819_REG_00 = 0x00U, BK4819_REG_02 = 0x02U, BK4819_REG_06 = 0x06U, BK4819_REG_07 = 0x07U, BK4819_REG_08 = 0x08U, BK4819_REG_09 = 0x09U, BK4819_REG_0B = 0x0BU, BK4819_REG_0C = 0x0CU, BK4819_REG_0D = 0x0DU, BK4819_REG_0E = 0x0EU, BK4819_REG_10 = 0x10U, BK4819_REG_11 = 0x11U, BK4819_REG_12 = 0x12U, BK4819_REG_13 = 0x13U, BK4819_REG_14 = 0x14U, BK4819_REG_19 = 0x19U, BK4819_REG_1F = 0x1FU, BK4819_REG_20 = 0x20U, BK4819_REG_21 = 0x21U, BK4819_REG_24 = 0x24U, BK4819_REG_28 = 0x28U, BK4819_REG_29 = 0x29U, BK4819_REG_2B = 0x2BU, BK4819_REG_30 = 0x30U, BK4819_REG_31 = 0x31U, BK4819_REG_32 = 0x32U, BK4819_REG_33 = 0x33U, BK4819_REG_36 = 0x36U, BK4819_REG_37 = 0x37U, BK4819_REG_38 = 0x38U, BK4819_REG_39 = 0x39U, BK4819_REG_3A = 0x3AU, BK4819_REG_3B = 0x3BU, BK4819_REG_3C = 0x3CU, BK4819_REG_3D = 0x3DU, BK4819_REG_3E = 0x3EU, BK4819_REG_3F = 0x3FU, BK4819_REG_40 = 0x40U, BK4819_REG_43 = 0x43U, BK4819_REG_46 = 0x46U, BK4819_REG_47 = 0x47U, BK4819_REG_48 = 0x48U, BK4819_REG_49 = 0x49U, BK4819_REG_4D = 0x4DU, BK4819_REG_4E = 0x4EU, BK4819_REG_4F = 0x4FU, BK4819_REG_50 = 0x50U, BK4819_REG_51 = 0x51U, BK4819_REG_52 = 0x52U, BK4819_REG_58 = 0x58U, BK4819_REG_59 = 0x59U, BK4819_REG_5A = 0x5AU, BK4819_REG_5B = 0x5BU, BK4819_REG_5C = 0x5CU, BK4819_REG_5D = 0x5DU, BK4819_REG_5E = 0x5EU, BK4819_REG_5F = 0x5FU, BK4819_REG_63 = 0x63U, BK4819_REG_64 = 0x64U, BK4819_REG_65 = 0x65U, BK4819_REG_67 = 0x67U, BK4819_REG_68 = 0x68U, BK4819_REG_69 = 0x69U, BK4819_REG_6A = 0x6AU, BK4819_REG_6F = 0x6FU, BK4819_REG_70 = 0x70U, BK4819_REG_71 = 0x71U, BK4819_REG_72 = 0x72U, BK4819_REG_78 = 0x78U, BK4819_REG_79 = 0x79U, BK4819_REG_7A = 0x7AU, BK4819_REG_7B = 0x7BU, BK4819_REG_7C = 0x7CU, BK4819_REG_7D = 0x7DU, BK4819_REG_7E = 0x7EU, }; typedef enum BK4819_REGISTER_t BK4819_REGISTER_t; enum BK4819_GPIO_PIN_t { BK4819_GPIO0_PIN28_RX_ENABLE = 0, BK4819_GPIO1_PIN29_PA_ENABLE = 1, BK4819_GPIO3_PIN31_UHF_LNA = 3, BK4819_GPIO4_PIN32_VHF_LNA = 4, BK4819_GPIO5_PIN1_RED = 5, BK4819_GPIO6_PIN2_GREEN = 6, }; typedef enum BK4819_GPIO_PIN_t BK4819_GPIO_PIN_t; // REG 02 #define BK4819_REG_02_SHIFT_FSK_TX_FINISHED 15 #define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY 14 #define BK4819_REG_02_SHIFT_FSK_RX_FINISHED 13 #define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL 12 #define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND 11 #define BK4819_REG_02_SHIFT_CxCSS_TAIL 10 #define BK4819_REG_02_SHIFT_CDCSS_FOUND 9 #define BK4819_REG_02_SHIFT_CDCSS_LOST 8 #define BK4819_REG_02_SHIFT_CTCSS_FOUND 7 #define BK4819_REG_02_SHIFT_CTCSS_LOST 6 #define BK4819_REG_02_SHIFT_VOX_FOUND 5 #define BK4819_REG_02_SHIFT_VOX_LOST 4 #define BK4819_REG_02_SHIFT_SQUELCH_FOUND 3 #define BK4819_REG_02_SHIFT_SQUELCH_LOST 2 #define BK4819_REG_02_SHIFT_FSK_RX_SYNC 1 #define BK4819_REG_02_MASK_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX) #define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY) #define BK4819_REG_02_MASK_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED) #define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL) #define BK4819_REG_02_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND) #define BK4819_REG_02_MASK_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL) #define BK4819_REG_02_MASK_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND) #define BK4819_REG_02_MASK_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST) #define BK4819_REG_02_MASK_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND) #define BK4819_REG_02_MASK_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST) #define BK4819_REG_02_MASK_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND) #define BK4819_REG_02_MASK_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST) #define BK4819_REG_02_MASK_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND) #define BK4819_REG_02_MASK_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST) #define BK4819_REG_02_MASK_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC) #define BK4819_REG_02_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED) #define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY) #define BK4819_REG_02_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED) #define BK4819_REG_02_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL) #define BK4819_REG_02_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND) #define BK4819_REG_02_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL) #define BK4819_REG_02_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND) #define BK4819_REG_02_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST) #define BK4819_REG_02_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND) #define BK4819_REG_02_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST) #define BK4819_REG_02_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND) #define BK4819_REG_02_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST) #define BK4819_REG_02_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND) #define BK4819_REG_02_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST) #define BK4819_REG_02_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC) // REG 07 #define BK4819_REG_07_SHIFT_FREQUENCY_MODE 13 #define BK4819_REG_07_SHIFT_FREQUENCY 0 #define BK4819_REG_07_MASK_FREQUENCY_MODE (0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE) #define BK4819_REG_07_MASK_FREQUENCY (0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY) #define BK4819_REG_07_MODE_CTC1 (0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE) #define BK4819_REG_07_MODE_CTC2 (1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE) #define BK4819_REG_07_MODE_CDCSS (2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE) // REG 24 #define BK4819_REG_24_SHIFT_UNKNOWN_15 15 #define BK4819_REG_24_SHIFT_THRESHOLD 7 #define BK4819_REG_24_SHIFT_UNKNOWN_6 6 #define BK4819_REG_24_SHIFT_ENABLE 5 #define BK4819_REG_24_SHIFT_SELECT 4 #define BK4819_REG_24_SHIFT_MAX_SYMBOLS 0 #define BK4819_REG_24_MASK_THRESHOLD (0x2Fu << BK4819_REG_24_SHIFT_THRESHOLD) #define BK4819_REG_24_MASK_ENABLE (0x01u << BK4819_REG_24_SHIFT_ENABLE) #define BK4819_REG_24_MASK_SELECT (0x04u << BK4819_REG_24_SHIFT_SELECT) #define BK4819_REG_24_MASK_MAX_SYMBOLS (0x0Fu << BK4819_REG_24_SHIFT_MAX_SYMBOLS) #define BK4819_REG_24_ENABLE (1u << BK4819_REG_24_SHIFT_ENABLE) #define BK4819_REG_24_DISABLE (0u << BK4819_REG_24_SHIFT_ENABLE) #define BK4819_REG_24_SELECT_DTMF (1u << BK4819_REG_24_SHIFT_SELECT) #define BK4819_REG_24_SELECT_SELCALL (0u << BK4819_REG_24_SHIFT_SELECT) // REG 30 #define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB 15 #define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN 14 #define BK4819_REG_30_SHIFT_ENABLE_RX_LINK 10 #define BK4819_REG_30_SHIFT_ENABLE_AF_DAC 9 #define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE 8 #define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO 4 #define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN 3 #define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC 2 #define BK4819_REG_30_SHIFT_ENABLE_TX_DSP 1 #define BK4819_REG_30_SHIFT_ENABLE_RX_DSP 0 #define BK4819_REG_30_MASK_ENABLE_VCO_CALIB (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB) #define BK4819_REG_30_MASK_ENABLE_UNKNOWN (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN) #define BK4819_REG_30_MASK_ENABLE_RX_LINK (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK) #define BK4819_REG_30_MASK_ENABLE_AF_DAC (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC) #define BK4819_REG_30_MASK_ENABLE_DISC_MODE (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE) #define BK4819_REG_30_MASK_ENABLE_PLL_VCO (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO) #define BK4819_REG_30_MASK_ENABLE_PA_GAIN (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN) #define BK4819_REG_30_MASK_ENABLE_MIC_ADC (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC) #define BK4819_REG_30_MASK_ENABLE_TX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP) #define BK4819_REG_30_MASK_ENABLE_RX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP) enum { BK4819_REG_30_ENABLE_VCO_CALIB = (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB), BK4819_REG_30_DISABLE_VCO_CALIB = (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB), BK4819_REG_30_ENABLE_UNKNOWN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN), BK4819_REG_30_DISABLE_UNKNOWN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN), BK4819_REG_30_ENABLE_RX_LINK = (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK), BK4819_REG_30_DISABLE_RX_LINK = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK), BK4819_REG_30_ENABLE_AF_DAC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC), BK4819_REG_30_DISABLE_AF_DAC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC), BK4819_REG_30_ENABLE_DISC_MODE = (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE), BK4819_REG_30_DISABLE_DISC_MODE = (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE), BK4819_REG_30_ENABLE_PLL_VCO = (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO), BK4819_REG_30_DISABLE_PLL_VCO = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO), BK4819_REG_30_ENABLE_PA_GAIN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN), BK4819_REG_30_DISABLE_PA_GAIN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN), BK4819_REG_30_ENABLE_MIC_ADC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC), BK4819_REG_30_DISABLE_MIC_ADC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC), BK4819_REG_30_ENABLE_TX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP), BK4819_REG_30_DISABLE_TX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP), BK4819_REG_30_ENABLE_RX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP), BK4819_REG_30_DISABLE_RX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP), }; // REG 3F #define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED 15 #define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY 14 #define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED 13 #define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL 12 #define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND 11 #define BK4819_REG_3F_SHIFT_CxCSS_TAIL 10 #define BK4819_REG_3F_SHIFT_CDCSS_FOUND 9 #define BK4819_REG_3F_SHIFT_CDCSS_LOST 8 #define BK4819_REG_3F_SHIFT_CTCSS_FOUND 7 #define BK4819_REG_3F_SHIFT_CTCSS_LOST 6 #define BK4819_REG_3F_SHIFT_VOX_FOUND 5 #define BK4819_REG_3F_SHIFT_VOX_LOST 4 #define BK4819_REG_3F_SHIFT_SQUELCH_FOUND 3 #define BK4819_REG_3F_SHIFT_SQUELCH_LOST 2 #define BK4819_REG_3F_SHIFT_FSK_RX_SYNC 1 #define BK4819_REG_3F_MASK_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX) #define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY) #define BK4819_REG_3F_MASK_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED) #define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL) #define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND) #define BK4819_REG_3F_MASK_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL) #define BK4819_REG_3F_MASK_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND) #define BK4819_REG_3F_MASK_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST) #define BK4819_REG_3F_MASK_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND) #define BK4819_REG_3F_MASK_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST) #define BK4819_REG_3F_MASK_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND) #define BK4819_REG_3F_MASK_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST) #define BK4819_REG_3F_MASK_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND) #define BK4819_REG_3F_MASK_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST) #define BK4819_REG_3F_MASK_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC) #define BK4819_REG_3F_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED) #define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY) #define BK4819_REG_3F_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED) #define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL) #define BK4819_REG_3F_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND) #define BK4819_REG_3F_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL) #define BK4819_REG_3F_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND) #define BK4819_REG_3F_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST) #define BK4819_REG_3F_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND) #define BK4819_REG_3F_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST) #define BK4819_REG_3F_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND) #define BK4819_REG_3F_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST) #define BK4819_REG_3F_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND) #define BK4819_REG_3F_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST) #define BK4819_REG_3F_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC) // REG 51 #define BK4819_REG_51_SHIFT_ENABLE_CxCSS 15 #define BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT 14 #define BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY 13 #define BK4819_REG_51_SHIFT_CxCSS_MODE 12 #define BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH 11 #define BK4819_REG_51_SHIFT_1050HZ_DETECTION 10 #define BK4819_REG_51_SHIFT_AUTO_CDCSS_BW 9 #define BK4819_REG_51_SHIFT_AUTO_CTCSS_BW 8 #define BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1 0 #define BK4819_REG_51_MASK_ENABLE_CxCSS (0x01U << BK4819_REG_51_SHIFT_ENABLE_CxCSS) #define BK4819_REG_51_MASK_GPIO6_PIN2_INPUT (0x01U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT) #define BK4819_REG_51_MASK_TX_CDCSS_POLARITY (0x01U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY) #define BK4819_REG_51_MASK_CxCSS_MODE (0x01U << BK4819_REG_51_SHIFT_CxCSS_MODE) #define BK4819_REG_51_MASK_CDCSS_BIT_WIDTH (0x01U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH) #define BK4819_REG_51_MASK_1050HZ_DETECTION (0x01U << BK4819_REG_51_SHIFT_1050HZ_DETECTION) #define BK4819_REG_51_MASK_AUTO_CDCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW) #define BK4819_REG_51_MASK_AUTO_CTCSS_BW (0x01U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW) #define BK4819_REG_51_MASK_CxCSS_TX_GAIN1 (0x7FU << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1) enum { BK4819_REG_51_ENABLE_CxCSS = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS), BK4819_REG_51_DISABLE_CxCSS = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS), BK4819_REG_51_GPIO6_PIN2_INPUT = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT), BK4819_REG_51_GPIO6_PIN2_NORMAL = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT), BK4819_REG_51_TX_CDCSS_NEGATIVE = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY), BK4819_REG_51_TX_CDCSS_POSITIVE = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY), BK4819_REG_51_MODE_CTCSS = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE), BK4819_REG_51_MODE_CDCSS = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE), BK4819_REG_51_CDCSS_24_BIT = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH), BK4819_REG_51_CDCSS_23_BIT = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH), BK4819_REG_51_1050HZ_DETECTION = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION), BK4819_REG_51_1050HZ_NO_DETECTION = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION), BK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW), BK4819_REG_51_AUTO_CDCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW), BK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW), BK4819_REG_51_AUTO_CTCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW), }; // REG 70 #define BK4819_REG_70_SHIFT_ENABLE_TONE1 15 #define BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN 8 #define BK4819_REG_70_SHIFT_ENABLE_TONE2 7 #define BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN 0 #define BK4819_REG_70_MASK_ENABLE_TONE1 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE1) #define BK4819_REG_70_MASK_TONE1_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN) #define BK4819_REG_70_MASK_ENABLE_TONE2 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE2) #define BK4819_REG_70_MASK_TONE2_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN) enum { BK4819_REG_70_ENABLE_TONE1 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE1), BK4819_REG_70_ENABLE_TONE2 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE2), }; #endif ================================================ FILE: driver/bk4819.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "app/messenger.h" #include "app/messenger.h" #include #include "app/app.h" #include "ui/ui.h" #include #include "string.h" #include "settings.h" #include "../audio.h" #include "../bsp/dp32g030/gpio.h" #include "../bsp/dp32g030/portcon.h" #include "bk4819.h" #include "gpio.h" #include "app/messenger.h" #include "system.h" #include "systick.h" #ifdef ENABLE_MDC1200 #include "app/mdc1200.h" #endif #include "misc.h" #ifndef ARRAY_SIZE #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) #endif BK4819_FilterBandwidth_t m_bandwidth = BK4819_FILTER_BW_NARROW; static const uint8_t DTMF_TONE1_GAIN = 65; static const uint8_t DTMF_TONE2_GAIN = 93; static uint16_t gBK4819_GpioOutState; bool gRxIdleMode; __inline uint16_t scale_freq(const uint16_t freq) { // return (((uint32_t)freq * 1032444u) + 50000u) / 100000u; // with rounding return (((uint32_t) freq * 1353245u) + (1u << 16)) >> 17; // with rounding } void BK4819_Init(void) { GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); BK4819_WriteRegister(BK4819_REG_00, 0x8000); BK4819_WriteRegister(BK4819_REG_00, 0x0000); BK4819_WriteRegister(BK4819_REG_37, 0x1D0F); BK4819_WriteRegister(BK4819_REG_36, 0x0022); BK4819_InitAGC(false); BK4819_SetAGC(true); BK4819_WriteRegister(BK4819_REG_19, 0b0001000001000001); // <15> MIC AGC 1 = disable 0 = enable BK4819_WriteRegister(BK4819_REG_7D, 0xE940); // REG_48 .. RX AF level // // <15:12> 11 ??? 0 to 15 // // <11:10> 0 AF Rx Gain-1 // 0 = 0dB // 1 = -6dB // 2 = -12dB // 3 = -18dB // // <9:4> 60 AF Rx Gain-2 -26dB ~ 5.5dB 0.5dB/step // 63 = max // 0 = mute // // <3:0> 15 AF DAC Gain (after Gain-1 and Gain-2) approx 2dB/step // 15 = max // 0 = min // BK4819_WriteRegister(BK4819_REG_48, // 0xB3A8); // 1011 00 111010 1000 (11u << 12) | // ??? 0..15 (0u << 10) | // AF Rx Gain-1 (58u << 4) | // AF Rx Gain-2 (8u << 0)); // AF DAC Gain (after Gain-1 and Gain-2) #if 1 const uint8_t dtmf_coeffs[] = {111, 107, 103, 98, 80, 71, 58, 44, 65, 55, 37, 23, 228, 203, 181, 159}; for (unsigned int i = 0; i < ARRAY_SIZE(dtmf_coeffs); i++) BK4819_WriteRegister(BK4819_REG_09, (i << 12) | dtmf_coeffs[i]); #else // original code BK4819_WriteRegister(BK4819_REG_09, 0x006F); // 6F BK4819_WriteRegister(BK4819_REG_09, 0x106B); // 6B BK4819_WriteRegister(BK4819_REG_09, 0x2067); // 67 BK4819_WriteRegister(BK4819_REG_09, 0x3062); // 62 BK4819_WriteRegister(BK4819_REG_09, 0x4050); // 50 BK4819_WriteRegister(BK4819_REG_09, 0x5047); // 47 BK4819_WriteRegister(BK4819_REG_09, 0x603A); // 3A BK4819_WriteRegister(BK4819_REG_09, 0x702C); // 2C BK4819_WriteRegister(BK4819_REG_09, 0x8041); // 41 BK4819_WriteRegister(BK4819_REG_09, 0x9037); // 37 BK4819_WriteRegister(BK4819_REG_09, 0xA025); // 25 BK4819_WriteRegister(BK4819_REG_09, 0xB017); // 17 BK4819_WriteRegister(BK4819_REG_09, 0xC0E4); // E4 BK4819_WriteRegister(BK4819_REG_09, 0xD0CB); // CB BK4819_WriteRegister(BK4819_REG_09, 0xE0B5); // B5 BK4819_WriteRegister(BK4819_REG_09, 0xF09F); // 9F #endif BK4819_WriteRegister(BK4819_REG_1F, 0x5454); BK4819_WriteRegister(BK4819_REG_3E, 0xA037); gBK4819_GpioOutState = 0x9000; BK4819_WriteRegister(BK4819_REG_33, 0x9000); BK4819_WriteRegister(BK4819_REG_3F, 0); } static uint16_t BK4819_ReadU16(void) { unsigned int i; uint16_t Value; PORTCON_PORTC_IE = (PORTCON_PORTC_IE & ~PORTCON_PORTC_IE_C2_MASK) | PORTCON_PORTC_IE_C2_BITS_ENABLE; GPIOC->DIR = (GPIOC->DIR & ~GPIO_DIR_2_MASK) | GPIO_DIR_2_BITS_INPUT; //SYSTICK_DelayUs(1); SYSTICK_Delay250ns(1); Value = 0; for (i = 0; i < 16; i++) { Value <<= 1; Value |= GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); } PORTCON_PORTC_IE = (PORTCON_PORTC_IE & ~PORTCON_PORTC_IE_C2_MASK) | PORTCON_PORTC_IE_C2_BITS_DISABLE; GPIOC->DIR = (GPIOC->DIR & ~GPIO_DIR_2_MASK) | GPIO_DIR_2_BITS_OUTPUT; return Value; } uint16_t BK4819_ReadRegister(BK4819_REGISTER_t Register) { uint16_t Value; GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); BK4819_WriteU8(Register | 0x80); Value = BK4819_ReadU16(); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); SYSTICK_Delay250ns(1); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); return Value; } void BK4819_WriteRegister(BK4819_REGISTER_t Register, uint16_t Data) { GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); BK4819_WriteU8(Register); //SYSTICK_Delay250ns(1); BK4819_WriteU16(Data); //SYSTICK_Delay250ns(1); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN); SYSTICK_Delay250ns(1); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); } void BK4819_WriteU8(uint8_t Data) { unsigned int i; GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); for (i = 0; i < 8; i++) { if ((Data & 0x80) == 0) GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); else GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); SYSTICK_Delay250ns(1); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); Data <<= 1; GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); } } void BK4819_WriteU16(uint16_t Data) { unsigned int i; GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); for (i = 0; i < 16; i++) { if ((Data & 0x8000) == 0) GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); else GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA); SYSTICK_Delay250ns(1); GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); Data <<= 1; SYSTICK_Delay250ns(1); GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL); SYSTICK_Delay250ns(1); } } void BK4819_SetAGC(bool enable) { uint16_t regVal = BK4819_ReadRegister(BK4819_REG_7E); if (!(regVal & (1 << 15)) == enable) return; BK4819_WriteRegister(BK4819_REG_7E, (regVal & ~(1 << 15) & ~(0b111 << 12)) | (!enable << 15) // 0 AGC fix mode | (3u << 12) // 3 AGC fix index ); // if(enable) { // BK4819_WriteRegister(BK4819_REG_7B, 0x8420); // } // else { // BK4819_WriteRegister(BK4819_REG_7B, 0x318C); // BK4819_WriteRegister(BK4819_REG_7C, 0x595E); // BK4819_WriteRegister(BK4819_REG_20, 0x8DEF); // for (uint8_t i = 0; i < 8; i++) { // //BK4819_WriteRegister(BK4819_REG_06, ((i << 13) | 0x2500u) + 0x036u); // BK4819_WriteRegister(BK4819_REG_06, (i & 7) << 13 | 0x4A << 7 | 0x36); // } // } } void BK4819_InitAGC(bool amModulation) { // REG_10, REG_11, REG_12 REG_13, REG_14 // // Rx AGC Gain Table[]. (Index Max->Min is 3,2,1,0,-1) // // <15:10> ??? // // <9:8> LNA Gain Short // 3 = 0dB <<< 1o11 read from spectrum reference manual // 2 = -24dB -19 -11 // 1 = -30dB -24 -16 // 0 = -33dB -28 -19 // // <7:5> LNA Gain // 7 = 0dB // 6 = -2dB // 5 = -4dB // 4 = -6dB // 3 = -9dB // 2 = -14dB <<< // 1 = -19dB // 0 = -24dB // // <4:3> MIXER Gain // 3 = 0dB <<< // 2 = -3dB // 1 = -6dB // 0 = -8dB // // <2:0> PGA Gain // 7 = 0dB // 6 = -3dB <<< // 5 = -6dB // 4 = -9dB // 3 = -15dB // 2 = -21dB // 1 = -27dB // 0 = -33dB // BK4819_WriteRegister(BK4819_REG_13, 0x03BE); // 0x03BE / 000000 11 101 11 110 / -7dB BK4819_WriteRegister(BK4819_REG_12, 0x037B); // 0x037B / 000000 11 011 11 011 / -24dB BK4819_WriteRegister(BK4819_REG_11, 0x027B); // 0x027B / 000000 10 011 11 011 / -43dB BK4819_WriteRegister(BK4819_REG_10, 0x007A); // 0x007A / 000000 00 011 11 010 / -58dB if (amModulation) { BK4819_WriteRegister(BK4819_REG_14, 0x0000); BK4819_WriteRegister(BK4819_REG_49, (0 << 14) | (50 << 7) | (32 << 0)); } else { BK4819_WriteRegister(BK4819_REG_14, 0x0019); // 0x0019 / 000000 00 000 11 001 / -79dB BK4819_WriteRegister(BK4819_REG_49, (0 << 14) | (84 << 7) | (56 << 0)); //0x2A38 / 00 1010100 0111000 / 84, 56 } BK4819_WriteRegister(BK4819_REG_7B, 0x8420); } void BK4819_PlayRoger(void) { #ifdef ENABLE_MESSENGER if(stop_mdc_flag) return; #endif if (gEeprom.ROGER == ROGER_MODE_ROGER || gEeprom.ROGER == ROGER_MODE_MDC_HEAD_ROGER) BK4819_PlayRogerNormal(); #ifdef ENABLE_MDC1200 else if ((gEeprom.ROGER == ROGER_MODE_MDC_END||gEeprom.ROGER==ROGER_MODE_MDC_BOTH) ) { BK4819_send_MDC1200(MDC1200_OP_CODE_POST_ID, 0x00, gEeprom.MDC1200_ID, false); #ifdef ENABLE_MDC1200_SIDE_BEEP BK4819_start_tone(880, 10, true, true); SYSTEM_DelayMs(120); BK4819_stop_tones(true); #endif } #endif } int8_t BK4819_GetRxGain_dB(void) { union { struct { uint16_t pga: 3; uint16_t mixer: 2; uint16_t lna: 3; uint16_t lnaS: 2; }; uint16_t __raw; } agcGainReg; union { struct { uint16_t _: 5; uint16_t agcSigStrength: 7; int16_t gainIdx: 3; uint16_t agcEnab: 1; }; uint16_t __raw; } reg7e; reg7e.__raw = BK4819_ReadRegister(BK4819_REG_7E); uint8_t gainAddr = reg7e.gainIdx < 0 ? BK4819_REG_14 : BK4819_REG_10 + reg7e.gainIdx; agcGainReg.__raw = BK4819_ReadRegister(gainAddr); int8_t lnaShortTab[] = {-28, -24, -19, 0}; int8_t lnaTab[] = {-24, -19, -14, -9, -6, -4, -2, 0}; int8_t mixerTab[] = {-8, -6, -3, 0}; int8_t pgaTab[] = {-33, -27, -21, -15, -9, -6, -3, 0}; return lnaShortTab[agcGainReg.lnaS] + lnaTab[agcGainReg.lna] + mixerTab[agcGainReg.mixer] + pgaTab[agcGainReg.pga]; } int16_t BK4819_GetRSSI_dBm(void) { uint16_t rssi = BK4819_GetRSSI(); return (rssi / 2) - 160;// - BK4819_GetRxGain_dB(); } void BK4819_ToggleGpioOut(BK4819_GPIO_PIN_t Pin, bool bSet) { if (bSet) gBK4819_GpioOutState |= (0x40u >> Pin); else gBK4819_GpioOutState &= ~(0x40u >> Pin); BK4819_WriteRegister(BK4819_REG_33, gBK4819_GpioOutState); } void BK4819_SetCDCSSCodeWord(uint32_t CodeWord) { // REG_51 // // <15> 0 // 1 = Enable TxCTCSS/CDCSS // 0 = Disable // // <14> 0 // 1 = GPIO0Input for CDCSS // 0 = Normal Mode (for BK4819 v3) // // <13> 0 // 1 = Transmit negative CDCSS code // 0 = Transmit positive CDCSS code // // <12> 0 CTCSS/CDCSS mode selection // 1 = CTCSS // 0 = CDCSS // // <11> 0 CDCSS 24/23bit selection // 1 = 24bit // 0 = 23bit // // <10> 0 1050HzDetectionMode // 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz // // <9> 0 Auto CDCSS Bw Mode // 1 = Disable // 0 = Enable // // <8> 0 Auto CTCSS Bw Mode // 0 = Enable // 1 = Disable // // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning // 0 = min // 127 = max // Enable CDCSS // Transmit positive CDCSS code // CDCSS Mode // CDCSS 23bit // Enable Auto CDCSS Bw Mode // Enable Auto CTCSS Bw Mode // CTCSS/CDCSS Tx Gain1 Tuning = 51 // BK4819_WriteRegister(BK4819_REG_51, BK4819_REG_51_ENABLE_CxCSS | BK4819_REG_51_GPIO6_PIN2_NORMAL | BK4819_REG_51_TX_CDCSS_POSITIVE | BK4819_REG_51_MODE_CDCSS | BK4819_REG_51_CDCSS_23_BIT | BK4819_REG_51_1050HZ_NO_DETECTION | BK4819_REG_51_AUTO_CDCSS_BW_ENABLE | BK4819_REG_51_AUTO_CTCSS_BW_ENABLE | (51u << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1)); // REG_07 <15:0> // // When <13> = 0 for CTC1 // <12:0> = CTC1 frequency control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 1 for CTC2 (Tail 55Hz Rx detection) // <12:0> = CTC2 (should below 100Hz) frequency control word = // 25391 / freq(Hz) for XTAL 13M/26M or // 25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 2 for CDCSS 134.4Hz // <12:0> = CDCSS baud rate frequency (134.4Hz) control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // BK4819_WriteRegister(BK4819_REG_07, BK4819_REG_07_MODE_CTC1 | 2775u); // REG_08 <15:0> <15> = 1 for CDCSS high 12bit // <15> = 0 for CDCSS low 12bit // <11:0> = CDCSShigh/low 12bit code // BK4819_WriteRegister(BK4819_REG_08, (0u << 15) | ((CodeWord >> 0) & 0x0FFF)); // LS 12-bits BK4819_WriteRegister(BK4819_REG_08, (1u << 15) | ((CodeWord >> 12) & 0x0FFF)); // MS 12-bits } void BK4819_SetCTCSSFrequency(uint32_t FreqControlWord) { // REG_51 <15> 0 1 = Enable TxCTCSS/CDCSS 0 = Disable // REG_51 <14> 0 1 = GPIO0Input for CDCSS 0 = Normal Mode.(for BK4819v3) // REG_51 <13> 0 1 = Transmit negative CDCSS code 0 = Transmit positive CDCSScode // REG_51 <12> 0 CTCSS/CDCSS mode selection 1 = CTCSS 0 = CDCSS // REG_51 <11> 0 CDCSS 24/23bit selection 1 = 24bit 0 = 23bit // REG_51 <10> 0 1050HzDetectionMode 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz // REG_51 <9> 0 Auto CDCSS Bw Mode 1 = Disable 0 = Enable. // REG_51 <8> 0 Auto CTCSS Bw Mode 0 = Enable 1 = Disable // REG_51 <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning 0 = min 127 = max uint16_t Config; if (FreqControlWord == 2625) { // Enables 1050Hz detection mode // Enable TxCTCSS // CTCSS Mode // 1050/4 Detect Enable // Enable Auto CDCSS Bw Mode // Enable Auto CTCSS Bw Mode // CTCSS/CDCSS Tx Gain1 Tuning = 74 // Config = 0x944A; // 1 0 0 1 0 1 0 0 0 1001010 } else { // Enable TxCTCSS // CTCSS Mode // Enable Auto CDCSS Bw Mode // Enable Auto CTCSS Bw Mode // CTCSS/CDCSS Tx Gain1 Tuning = 74 //亚音 // Config = 0x904A; // 1 0 0 1 0 0 0 0 0 1001010 Config = 0x9033; } BK4819_WriteRegister(BK4819_REG_51, Config); // REG_07 <15:0> // // When <13> = 0 for CTC1 // <12:0> = CTC1 frequency control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 1 for CTC2 (Tail RX detection) // <12:0> = CTC2 (should below 100Hz) frequency control word = // 25391 / freq(Hz) for XTAL 13M/26M or // 25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 2 for CDCSS 134.4Hz // <12:0> = CDCSS baud rate frequency (134.4Hz) control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // BK4819_WriteRegister(BK4819_REG_07, BK4819_REG_07_MODE_CTC1 | (((FreqControlWord * 206488u) + 50000u) / 100000u)); // with rounding } // freq_10Hz is CTCSS Hz * 10 void BK4819_SetTailDetection(const uint32_t freq_10Hz) { // REG_07 <15:0> // // When <13> = 0 for CTC1 // <12:0> = CTC1 frequency control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 1 for CTC2 (Tail RX detection) // <12:0> = CTC2 (should below 100Hz) frequency control word = // 25391 / freq(Hz) for XTAL 13M/26M or // 25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 2 for CDCSS 134.4Hz // <12:0> = CDCSS baud rate frequency (134.4Hz) control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // BK4819_WriteRegister(BK4819_REG_07, BK4819_REG_07_MODE_CTC2 | ((253910 + (freq_10Hz / 2)) / freq_10Hz)); // with rounding } void BK4819_EnableVox(uint16_t VoxEnableThreshold, uint16_t VoxDisableThreshold) { //VOX Algorithm //if (voxamp>VoxEnableThreshold) VOX = 1; //else //if (voxamp 0 ??? // // <14:12> 4 RF filter bandwidth // 0 = 1.7 kHz // 1 = 2.0 kHz // 2 = 2.5 kHz // 3 = 3.0 kHz // 4 = 3.75 kHz // 5 = 4.0 kHz // 6 = 4.25 kHz // 7 = 4.5 kHz // if <5> == 1, RF filter bandwidth * 2 // // <11:9> 0 RF filter bandwidth when signal is weak // 0 = 1.7 kHz // 1 = 2.0 kHz // 2 = 2.5 kHz // 3 = 3.0 kHz // 4 = 3.75 kHz // 5 = 4.0 kHz // 6 = 4.25 kHz // 7 = 4.5 kHz // if <5> == 1, RF filter bandwidth * 2 // // <8:6> 1 AFTxLPF2 filter Band Width // 1 = 2.5 kHz (for 12.5k channel space) // 2 = 2.75 kHz // 0 = 3.0 kHz (for 25k channel space) // 3 = 3.5 kHz // 4 = 4.5 kHz // 5 = 4.25 kHz // 6 = 4.0 kHz // 7 = 3.75 kHz // // <5:4> 0 BW Mode Selection // 0 = 12.5k // 1 = 6.25k // 2 = 25k/20k // // <3> 1 ??? // // <2> 0 Gain after FM Demodulation // 0 = 0dB // 1 = 6dB // // <1:0> 0 ??? uint16_t val; m_bandwidth = Bandwidth; switch (Bandwidth) { default: case BK4819_FILTER_BW_WIDE: // 25kHz if (weak_no_different) { // make the RX bandwidth the same with weak signals val = (0u << 15) | // 0 (4u << 12) | // *3 RF filter bandwidth (4u << 9) | // *0 RF filter bandwidth when signal is weak (6u << 6) | // *0 AFTxLPF2 filter Band Width (2u << 4) | // 2 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 0 Gain after FM Demodulation (0u << 0); // 0 } else { // with weak RX signals the RX bandwidth is reduced val = // 0x3028); // 0 011 000 000 10 1 0 00 (0u << 15) | // 0 (4u << 12) | // *3 RF filter bandwidth (2u << 9) | // *0 RF filter bandwidth when signal is weak (6u << 6) | // *0 AFTxLPF2 filter Band Width (2u << 4) | // 2 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 0 Gain after FM Demodulation (0u << 0); // 0 } break; case BK4819_FILTER_BW_NARROW: // 12.5kHz if (weak_no_different) { val = (0u << 15) | // 0 (4u << 12) | // *4 RF filter bandwidth (4u << 9) | // *0 RF filter bandwidth when signal is weak (0u << 6) | // *1 AFTxLPF2 filter Band Width (0u << 4) | // 0 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 0 Gain after FM Demodulation (0u << 0); // 0 } else { val = // 0x4048); // 0 100 000 001 00 1 0 00 (0u << 15) | // 0 (4u << 12) | // *4 RF filter bandwidth (2u << 9) | // *0 RF filter bandwidth when signal is weak (0u << 6) | // *1 AFTxLPF2 filter Band Width (0u << 4) | // 0 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 0 Gain after FM Demodulation (0u << 0); // 0 } break; case BK4819_FILTER_BW_NARROWER: // 6.25kHz if (weak_no_different) { val = (0u << 15) | // 0 (3u << 12) | // 3 RF filter bandwidth (3u << 9) | // *0 RF filter bandwidth when signal is weak (1u << 6) | // 1 AFTxLPF2 filter Band Width (1u << 4) | // 1 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 0 Gain after FM Demodulation (0u << 0); // 0 } else { val = (0u << 15) | // 0 (3u << 12) | // 3 RF filter bandwidth (0u << 9) | // 0 RF filter bandwidth when signal is weak (1u << 6) | // 1 AFTxLPF2 filter Band Width (1u << 4) | // 1 BW Mode Selection (1u << 3) | // 1 (0u << 2) | // 1 Gain after FM Demodulation (0u << 0); // 0 } break; } BK4819_WriteRegister(BK4819_REG_43, val); } void BK4819_SetupPowerAmplifier(const uint8_t bias, const uint32_t frequency) { // REG_36 <15:8> 0 PA Bias output 0 ~ 3.2V // 255 = 3.2V // 0 = 0V // // REG_36 <7> 0 // 1 = Enable PA-CTL output // 0 = Disable (Output 0 V) // // REG_36 <5:3> 7 PA gain 1 tuning // 7 = max // 0 = min // // REG_36 <2:0> 7 PA gain 2 tuning // 7 = max // 0 = min // // 280MHz gain 1 = 1 gain 2 = 0 gain 1 = 4 gain 2 = 2 const uint8_t gain = (frequency < 28000000) ? (1u << 3) | (0u << 0) : (4u << 3) | (2u << 0); const uint8_t enable = 1; BK4819_WriteRegister(BK4819_REG_36, (bias << 8) | (enable << 7) | (gain << 0)); } void BK4819_SetFrequency(uint32_t Frequency) { BK4819_WriteRegister(BK4819_REG_38, (Frequency >> 0) & 0xFFFF); BK4819_WriteRegister(BK4819_REG_39, (Frequency >> 16) & 0xFFFF); } void BK4819_SetupSquelch( uint8_t SquelchOpenRSSIThresh, uint8_t SquelchCloseRSSIThresh, uint8_t SquelchOpenNoiseThresh, uint8_t SquelchCloseNoiseThresh, uint8_t SquelchCloseGlitchThresh, uint8_t SquelchOpenGlitchThresh) { // REG_70 // // <15> 0 Enable TONE1 // 1 = Enable // 0 = Disable // // <14:8> 0 TONE1 tuning gain // 0 ~ 127 // // <7> 0 Enable TONE2 // 1 = Enable // 0 = Disable // // <6:0> 0 TONE2/FSK tuning gain // 0 ~ 127 // BK4819_WriteRegister(BK4819_REG_70, 0); // Glitch threshold for Squelch = close // // 0 ~ 255 // BK4819_WriteRegister(BK4819_REG_4D, 0xA000 | SquelchCloseGlitchThresh); // REG_4E // // <15:14> 1 ??? // // <13:11> 5 Squelch = open Delay Setting // 0 ~ 7 // // <10:9> 7 Squelch = close Delay Setting // 0 ~ 3 // // <8> 0 ??? // // <7:0> 8 Glitch threshold for Squelch = open // 0 ~ 255 // BK4819_WriteRegister(BK4819_REG_4E, // 01 101 11 1 00000000 // original (*) (1u << 14) | // 1 ??? (5u << 11) | // *5 squelch = open delay .. 0 ~ 7 (6u << 9) | // *3 squelch = close delay .. 0 ~ 3 SquelchOpenGlitchThresh); // 0 ~ 255 // REG_4F // // <14:8> 47 Ex-noise threshold for Squelch = close // 0 ~ 127 // // <7> ??? // // <6:0> 46 Ex-noise threshold for Squelch = open // 0 ~ 127 // BK4819_WriteRegister(BK4819_REG_4F, ((uint16_t) SquelchCloseNoiseThresh << 8) | SquelchOpenNoiseThresh); // REG_78 // // <15:8> 72 RSSI threshold for Squelch = open 0.5dB/step // // <7:0> 70 RSSI threshold for Squelch = close 0.5dB/step // BK4819_WriteRegister(BK4819_REG_78, ((uint16_t) SquelchOpenRSSIThresh << 8) | SquelchCloseRSSIThresh); BK4819_SetAF(BK4819_AF_MUTE); BK4819_RX_TurnOn(); } void BK4819_SetAF(BK4819_AF_Type_t AF) { // AF Output Inverse Mode = Inverse // Undocumented bits 0x2040 // // BK4819_WriteRegister(BK4819_REG_47, 0x6040 | (AF << 8)); BK4819_WriteRegister(BK4819_REG_47, (6u << 12) | (AF << 8) | (1u << 6)); } void BK4819_SetRegValue(RegisterSpec s, uint16_t v) { uint16_t reg = BK4819_ReadRegister(s.num); reg &= ~(s.mask << s.offset); BK4819_WriteRegister(s.num, reg | (v << s.offset)); } void BK4819_RX_TurnOn(void) { // DSP Voltage Setting = 1 // ANA LDO = 2.7v // VCO LDO = 2.7v // RF LDO = 2.7v // PLL LDO = 2.7v // ANA LDO bypass // VCO LDO bypass // RF LDO bypass // PLL LDO bypass // Reserved bit is 1 instead of 0 // Enable DSP // Enable XTAL // Enable Band Gap // BK4819_WriteRegister(BK4819_REG_37, 0x1F0F); // 0001111100001111 // Turn off everything BK4819_WriteRegister(BK4819_REG_30, 0); BK4819_WriteRegister(BK4819_REG_30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_DISABLE_UNKNOWN | BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_DISABLE_PA_GAIN | BK4819_REG_30_DISABLE_MIC_ADC | BK4819_REG_30_DISABLE_TX_DSP | BK4819_REG_30_ENABLE_RX_DSP); } void BK4819_PickRXFilterPathBasedOnFrequency(uint32_t Frequency) { if (Frequency < 28000000) { // VHF BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, true); BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, false); } else if (Frequency == 0xFFFFFFFF) { // OFF BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, false); BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, false); } else { // UHF BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, false); BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, true); } } void BK4819_DisableScramble(void) { const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31); BK4819_WriteRegister(BK4819_REG_31, Value & ~(1u << 1)); } void BK4819_EnableScramble(uint8_t Type) { const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31); BK4819_WriteRegister(BK4819_REG_31, Value | (1u << 1)); BK4819_WriteRegister(BK4819_REG_71, 0x68DC + (Type * 1032)); // 0110 1000 1101 1100 } bool BK4819_CompanderEnabled(void) { return (BK4819_ReadRegister(BK4819_REG_31) & (1u << 3)) ? true : false; } void BK4819_SetCompander(const unsigned int mode) { // mode 0 .. OFF // mode 1 .. TX // mode 2 .. RX // mode 3 .. TX and RX const uint16_t r31 = BK4819_ReadRegister(BK4819_REG_31); if (mode == 0) { // disable BK4819_WriteRegister(BK4819_REG_31, r31 & ~(1u << 3)); return; } // REG_29 // // <15:14> 10 Compress (AF Tx) Ratio // 00 = Disable // 01 = 1.333:1 // 10 = 2:1 // 11 = 4:1 // // <13:7> 86 Compress (AF Tx) 0 dB point (dB) // // <6:0> 64 Compress (AF Tx) noise point (dB) // const uint16_t compress_ratio = (mode == 1 || mode >= 3) ? 2 : 0; // 2:1 const uint16_t compress_0dB = 86; const uint16_t compress_noise_dB = 64; // AB40 10 1010110 1000000 BK4819_WriteRegister(BK4819_REG_29, // (BK4819_ReadRegister(BK4819_REG_29) & ~(3u << 14)) | (compress_ratio << 14)); (compress_ratio << 14) | (compress_0dB << 7) | (compress_noise_dB << 0)); // REG_28 // // <15:14> 01 Expander (AF Rx) Ratio // 00 = Disable // 01 = 1:2 // 10 = 1:3 // 11 = 1:4 // // <13:7> 86 Expander (AF Rx) 0 dB point (dB) // // <6:0> 56 Expander (AF Rx) noise point (dB) // const uint16_t expand_ratio = (mode >= 2) ? 1 : 0; // 1:2 const uint16_t expand_0dB = 86; const uint16_t expand_noise_dB = 56; // 6B38 01 1010110 0111000 BK4819_WriteRegister(BK4819_REG_28, // (BK4819_ReadRegister(BK4819_REG_28) & ~(3u << 14)) | (expand_ratio << 14)); (expand_ratio << 14) | (expand_0dB << 7) | (expand_noise_dB << 0)); // enable BK4819_WriteRegister(BK4819_REG_31, r31 | (1u << 3)); } void BK4819_DisableVox(void) { const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31); BK4819_WriteRegister(BK4819_REG_31, Value & 0xFFFB); } void BK4819_DisableDTMF(void) { BK4819_WriteRegister(BK4819_REG_24, 0); } void BK4819_EnableDTMF(void) { // no idea what this does BK4819_WriteRegister(BK4819_REG_21, 0x06D8); // 0000 0110 1101 1000 // REG_24 // // <15> 1 ??? // // <14:7> 24 Threshold // // <6> 1 ??? // // <5> 0 DTMF/SelCall enable // 1 = Enable // 0 = Disable // // <4> 1 DTMF or SelCall detection mode // 1 = for DTMF // 0 = for SelCall // // <3:0> 14 Max symbol number for SelCall detection // // const uint16_t threshold = 24; // default, but doesn't decode non-QS radios const uint16_t threshold = 130; // but 128 ~ 247 does BK4819_WriteRegister(BK4819_REG_24, // 1 00011000 1 1 1 1110 (1u << BK4819_REG_24_SHIFT_UNKNOWN_15) | (threshold << BK4819_REG_24_SHIFT_THRESHOLD) | // 0 ~ 255 (1u << BK4819_REG_24_SHIFT_UNKNOWN_6) | BK4819_REG_24_ENABLE | BK4819_REG_24_SELECT_DTMF | (15u << BK4819_REG_24_SHIFT_MAX_SYMBOLS)); // 0 ~ 15 } void BK4819_PlayTone(uint16_t Frequency, bool bTuningGainSwitch) { uint16_t ToneConfig = BK4819_REG_70_ENABLE_TONE1; BK4819_EnterTxMute(); BK4819_SetAF(BK4819_AF_BEEP); if (bTuningGainSwitch == 0) ToneConfig |= 96u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN; else ToneConfig |= 28u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN; BK4819_WriteRegister(BK4819_REG_70, ToneConfig); BK4819_WriteRegister(BK4819_REG_30, 0); BK4819_WriteRegister(BK4819_REG_30, BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_TX_DSP); BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency)); } // level 0 ~ 127 void BK4819_PlaySingleTone(const unsigned int tone_Hz, const unsigned int delay, const unsigned int level, const bool play_speaker) { BK4819_EnterTxMute(); if (play_speaker) { AUDIO_AudioPathOn(); BK4819_SetAF(BK4819_AF_BEEP); } else BK4819_SetAF(BK4819_AF_MUTE); BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_ENABLE_TONE1 | ((level & 0x7f) << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)); BK4819_EnableTXLink(); SYSTEM_DelayMs(50); BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone_Hz)); BK4819_ExitTxMute(); SYSTEM_DelayMs(delay); BK4819_EnterTxMute(); if (play_speaker) { AUDIO_AudioPathOff(); BK4819_SetAF(BK4819_AF_MUTE); } BK4819_WriteRegister(BK4819_REG_70, 0x0000); BK4819_WriteRegister(BK4819_REG_30, 0xC1FE); BK4819_ExitTxMute(); } void BK4819_EnterTxMute(void) { BK4819_WriteRegister(BK4819_REG_50, 0xBB20); } void BK4819_ExitTxMute(void) { BK4819_WriteRegister(BK4819_REG_50, 0x3B20); } void BK4819_Sleep(void) { BK4819_WriteRegister(BK4819_REG_30, 0); BK4819_WriteRegister(BK4819_REG_37, 0x1D00); } void BK4819_TurnsOffTones_TurnsOnRX(void) { BK4819_WriteRegister(BK4819_REG_70, 0); BK4819_SetAF(BK4819_AF_MUTE); BK4819_ExitTxMute(); BK4819_WriteRegister(BK4819_REG_30, 0); BK4819_WriteRegister(BK4819_REG_30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_RX_DSP); } #ifdef ENABLE_AIRCOPY void BK4819_SetupAircopy(void) { BK4819_WriteRegister(BK4819_REG_70, 0x00E0); // Enable Tone2, tuning gain 48 BK4819_WriteRegister(BK4819_REG_72, 0x3065); // Tone2 baudrate 1200 BK4819_WriteRegister(BK4819_REG_58, 0x00C1); // FSK Enable, FSK 1.2K RX Bandwidth, Preamble 0xAA or 0x55, RX Gain 0, RX Mode // (FSK1.2K, FSK2.4K Rx and NOAA SAME Rx), TX Mode FSK 1.2K and FSK 2.4K Tx BK4819_WriteRegister(BK4819_REG_5C, 0x5665); // Enable CRC among other things we don't know yet BK4819_WriteRegister(BK4819_REG_5D, 0x4700); // FSK Data Length 72 Bytes (0xabcd + 2 byte length + 64 byte payload + 2 byte CRC + 0xdcba) } #endif void BK4819_ResetFSK(void) { BK4819_WriteRegister(BK4819_REG_3F, 0x0000); // Disable interrupts BK4819_WriteRegister(BK4819_REG_59, 0x0068); // Sync length 4 bytes, 7 byte preamble SYSTEM_DelayMs(30); BK4819_Disable(); } void BK4819_ExitBypass(void) { BK4819_SetAF(BK4819_AF_MUTE); // REG_7E // // <15> 0 AGC fix mode // 1 = fix // 0 = auto // // <14:12> 3 AGC fix index // 3 ( 3) = max // 2 ( 2) // 1 ( 1) // 0 ( 0) // 7 (-1) // 6 (-2) // 5 (-3) // 4 (-4) = min // // <11:6> 0 ??? // // <5:3> 5 DC filter band width for Tx (MIC In) // 0 ~ 7 // 0 = bypass DC filter // // <2:0> 6 DC filter band width for Rx (I.F In) // 0 ~ 7 // 0 = bypass DC filter // uint16_t regVal = BK4819_ReadRegister(BK4819_REG_7E); // 0x302E / 0 011 000000 101 110 BK4819_WriteRegister(BK4819_REG_7E, (regVal & ~(0b111 << 3)) | (5u << 3) // 5 DC Filter band width for Tx (MIC In) ); } void BK4819_PrepareTransmit(void) { BK4819_ExitBypass(); BK4819_ExitTxMute(); BK4819_TxOn_Beep(); } void BK4819_TxOn_Beep(void) { BK4819_WriteRegister(BK4819_REG_37, 0x1D0F); BK4819_WriteRegister(BK4819_REG_52, 0x028F); BK4819_WriteRegister(BK4819_REG_30, 0x0000); BK4819_WriteRegister(BK4819_REG_30, 0xC1FE); } void BK4819_ExitSubAu(void) { // REG_51 // // <15> 0 // 1 = Enable TxCTCSS/CDCSS // 0 = Disable // // <14> 0 // 1 = GPIO0Input for CDCSS // 0 = Normal Mode (for BK4819 v3) // // <13> 0 // 1 = Transmit negative CDCSS code // 0 = Transmit positive CDCSS code // // <12> 0 CTCSS/CDCSS mode selection // 1 = CTCSS // 0 = CDCSS // // <11> 0 CDCSS 24/23bit selection // 1 = 24bit // 0 = 23bit // // <10> 0 1050HzDetectionMode // 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz // // <9> 0 Auto CDCSS Bw Mode // 1 = Disable // 0 = Enable // // <8> 0 Auto CTCSS Bw Mode // 0 = Enable // 1 = Disable // // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning // 0 = min // 127 = max // BK4819_WriteRegister(BK4819_REG_51, 0x0000); } void BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable(void) { if (gRxIdleMode) { BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, true); BK4819_RX_TurnOn(); } } void BK4819_EnterDTMF_TX(bool bLocalLoopback) { BK4819_EnableDTMF(); BK4819_EnterTxMute(); BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE); BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_MASK_ENABLE_TONE1 | (DTMF_TONE1_GAIN << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN) | BK4819_REG_70_MASK_ENABLE_TONE2 | (DTMF_TONE2_GAIN << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)); BK4819_EnableTXLink(); } void BK4819_ExitDTMF_TX(bool bKeep) { BK4819_EnterTxMute(); BK4819_SetAF(BK4819_AF_MUTE); BK4819_WriteRegister(BK4819_REG_70, 0x0000); BK4819_DisableDTMF(); BK4819_WriteRegister(BK4819_REG_30, 0xC1FE); if (!bKeep) BK4819_ExitTxMute(); } void BK4819_EnableTXLink(void) { BK4819_WriteRegister(BK4819_REG_30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_UNKNOWN | BK4819_REG_30_DISABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_PA_GAIN | BK4819_REG_30_DISABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | BK4819_REG_30_DISABLE_RX_DSP); } void BK4819_PlayDTMF(char Code) { struct DTMF_TonePair { uint16_t tone1; uint16_t tone2; }; const struct DTMF_TonePair tones[] = { {941, 1336}, {697, 1209}, {697, 1336}, {697, 1477}, {770, 1209}, {770, 1336}, {770, 1477}, {852, 1209}, {852, 1336}, {852, 1477}, {697, 1633}, {770, 1633}, {852, 1633}, {941, 1633}, {941, 1209}, {941, 1477}, }; const struct DTMF_TonePair *pSelectedTone = NULL; switch (Code) { case '0'...'9': pSelectedTone = &tones[0 + Code - '0']; break; case 'A'...'D': pSelectedTone = &tones[10 + Code - 'A']; break; case '*': pSelectedTone = &tones[14]; break; case '#': pSelectedTone = &tones[15]; break; default: pSelectedTone = NULL; } if (pSelectedTone) { BK4819_WriteRegister(BK4819_REG_71, (((uint32_t) pSelectedTone->tone1 * 103244) + 5000) / 10000); // with rounding BK4819_WriteRegister(BK4819_REG_72, (((uint32_t) pSelectedTone->tone2 * 103244) + 5000) / 10000); // with rounding } } void BK4819_PlayDTMFString(const char *pString, bool bDelayFirst, uint16_t FirstCodePersistTime, uint16_t HashCodePersistTime, uint16_t CodePersistTime, uint16_t CodeInternalTime) { unsigned int i; if (pString == NULL) return; for (i = 0; pString[i]; i++) { uint16_t Delay; BK4819_PlayDTMF(pString[i]); BK4819_ExitTxMute(); if (bDelayFirst && i == 0) Delay = FirstCodePersistTime; else if (pString[i] == '*' || pString[i] == '#') Delay = HashCodePersistTime; else Delay = CodePersistTime; SYSTEM_DelayMs(Delay); BK4819_EnterTxMute(); SYSTEM_DelayMs(CodeInternalTime); } } void BK4819_TransmitTone(bool bLocalLoopback, uint32_t Frequency) { BK4819_EnterTxMute(); // REG_70 // // <15> 0 Enable TONE1 // 1 = Enable // 0 = Disable // // <14:8> 0 TONE1 tuning gain // 0 ~ 127 // // <7> 0 Enable TONE2 // 1 = Enable // 0 = Disable // // <6:0> 0 TONE2/FSK amplitude // 0 ~ 127 // // set the tone amplitude // BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_MASK_ENABLE_TONE1 | (66u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)); BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency)); BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE); BK4819_EnableTXLink(); SYSTEM_DelayMs(50); BK4819_ExitTxMute(); } void BK4819_GenTail(uint8_t Tail) { // REG_52 // // <15> 0 Enable 120/180/240 degree shift CTCSS or 134.4Hz Tail when CDCSS mode // 0 = Normal // 1 = Enable // // <14:13> 0 CTCSS tail mode selection (only valid when REG_52 <15> = 1) // 00 = for 134.4Hz CTCSS Tail when CDCSS mode // 01 = CTCSS0 120° phase shift // 10 = CTCSS0 180° phase shift // 11 = CTCSS0 240° phase shift // // <12> 0 CTCSSDetectionThreshold Mode // 1 = ~0.1% // 0 = 0.1 Hz // // <11:6> 0x0A CTCSS found detect threshold // // <5:0> 0x0F CTCSS lost detect threshold // REG_07 <15:0> // // When <13> = 0 for CTC1 // <12:0> = CTC1 frequency control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 1 for CTC2 (Tail 55Hz Rx detection) // <12:0> = CTC2 (should below 100Hz) frequency control word = // 25391 / freq(Hz) for XTAL 13M/26M or // 25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M // // When <13> = 2 for CDCSS 134.4Hz // <12:0> = CDCSS baud rate frequency (134.4Hz) control word = // freq(Hz) * 20.64888 for XTAL 13M/26M or // freq(Hz)*20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M switch (Tail) { case 0: // 134.4Hz CTCSS Tail BK4819_WriteRegister(BK4819_REG_52, 0x828F); // 1 00 0 001010 001111 break; case 1: // 120° phase shift BK4819_WriteRegister(BK4819_REG_52, 0xA28F); // 1 01 0 001010 001111 break; case 2: // 180° phase shift BK4819_WriteRegister(BK4819_REG_52, 0xC28F); // 1 10 0 001010 001111 break; case 3: // 240° phase shift BK4819_WriteRegister(BK4819_REG_52, 0xE28F); // 1 11 0 001010 001111 break; case 4: // 55Hz tone freq BK4819_WriteRegister(BK4819_REG_07, 0x046f); // 0 00 0 010001 101111 break; } } void BK4819_PlayCDCSSTail(void) { BK4819_GenTail(0); // CTC134 //亚音 // BK4819_WriteRegister(BK4819_REG_51, 0x804A); BK4819_WriteRegister(BK4819_REG_51, 0x8033); } void BK4819_PlayCTCSSTail(void) { #ifdef ENABLE_CTCSS_TAIL_PHASE_SHIFT //BK4819_GenTail(1); // 120° phase shift BK4819_GenTail(2); // 180° phase shift //BK4819_GenTail(3); // 240° phase shift #else BK4819_GenTail(4); // 55Hz tone freq #endif // REG_51 // // <15> 0 // 1 = Enable TxCTCSS/CDCSS // 0 = Disable // // <14> 0 // 1 = GPIO0Input for CDCSS // 0 = Normal Mode (for BK4819 v3) // // <13> 0 // 1 = Transmit negative CDCSS code // 0 = Transmit positive CDCSS code // // <12> 0 CTCSS/CDCSS mode selection // 1 = CTCSS // 0 = CDCSS // // <11> 0 CDCSS 24/23bit selection // 1 = 24bit // 0 = 23bit // // <10> 0 1050HzDetectionMode // 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz // // <9> 0 Auto CDCSS Bw Mode // 1 = Disable // 0 = Enable // // <8> 0 Auto CTCSS Bw Mode // 0 = Enable // 1 = Disable // // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning // 0 = min // 127 = max //亚音 // BK4819_WriteRegister(BK4819_REG_51, 0x904A); // 1 0 0 1 0 0 0 0 0 1001010 BK4819_WriteRegister(BK4819_REG_51, 0x9033); // 1 0 0 1 0 0 0 0 0 1001010 } uint16_t BK4819_GetRSSI(void) { return BK4819_ReadRegister(BK4819_REG_67) & 0x01FF; } uint8_t BK4819_GetGlitchIndicator(void) { return BK4819_ReadRegister(BK4819_REG_63) & 0x00FF; } uint8_t BK4819_GetExNoiceIndicator(void) { return BK4819_ReadRegister(BK4819_REG_65) & 0x007F; } uint16_t BK4819_GetVoiceAmplitudeOut(void) { return BK4819_ReadRegister(BK4819_REG_64); } uint8_t BK4819_GetAfTxRx(void) { return BK4819_ReadRegister(BK4819_REG_6F) & 0x003F; } bool BK4819_GetFrequencyScanResult(uint32_t *pFrequency) { const uint16_t High = BK4819_ReadRegister(BK4819_REG_0D); const bool Finished = (High & 0x8000) == 0; if (Finished) { const uint16_t Low = BK4819_ReadRegister(BK4819_REG_0E); *pFrequency = (uint32_t) ((High & 0x7FF) << 16) | Low; } return Finished; } BK4819_CssScanResult_t BK4819_GetCxCSSScanResult(uint32_t *pCdcssFreq, uint16_t *pCtcssFreq) { uint16_t Low; uint16_t High = BK4819_ReadRegister(BK4819_REG_69); if ((High & 0x8000) == 0) { Low = BK4819_ReadRegister(BK4819_REG_6A); *pCdcssFreq = ((High & 0xFFF) << 12) | (Low & 0xFFF); return BK4819_CSS_RESULT_CDCSS; } Low = BK4819_ReadRegister(BK4819_REG_68); if ((Low & 0x8000) == 0) { *pCtcssFreq = ((Low & 0x1FFF) * 4843) / 10000; return BK4819_CSS_RESULT_CTCSS; } return BK4819_CSS_RESULT_NOT_FOUND; } void BK4819_DisableFrequencyScan(void) { // REG_32 // // <15:14> 0 frequency scan time // 0 = 0.2 sec // 1 = 0.4 sec // 2 = 0.8 sec // 3 = 1.6 sec // // <13:1> ??? // // <0> 0 frequency scan enable // 1 = enable // 0 = disable // BK4819_WriteRegister(BK4819_REG_32, // 0x0244); // 00 0000100100010 0 (0u << 14) | // 0 frequency scan Time (290u << 1) | // ??? (0u << 0)); // 0 frequency scan enable } void BK4819_EnableFrequencyScan(void) { // REG_32 // // <15:14> 0 frequency scan time // 0 = 0.2 sec // 1 = 0.4 sec // 2 = 0.8 sec // 3 = 1.6 sec // // <13:1> ??? // // <0> 0 frequency scan enable // 1 = enable // 0 = disable // BK4819_WriteRegister(BK4819_REG_32, // 0x0245); // 00 0000100100010 1 (0u << 14) | // 0 frequency scan time (290u << 1) | // ??? (1u << 0)); // 1 frequency scan enable } void BK4819_SetScanFrequency(uint32_t Frequency) { BK4819_SetFrequency(Frequency); // REG_51 // // <15> 0 // 1 = Enable TxCTCSS/CDCSS // 0 = Disable // // <14> 0 // 1 = GPIO0Input for CDCSS // 0 = Normal Mode (for BK4819 v3) // // <13> 0 // 1 = Transmit negative CDCSS code // 0 = Transmit positive CDCSS code // // <12> 0 CTCSS/CDCSS mode selection // 1 = CTCSS // 0 = CDCSS // // <11> 0 CDCSS 24/23bit selection // 1 = 24bit // 0 = 23bit // // <10> 0 1050HzDetectionMode // 1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz // // <9> 0 Auto CDCSS Bw Mode // 1 = Disable // 0 = Enable // // <8> 0 Auto CTCSS Bw Mode // 0 = Enable // 1 = Disable // // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning // 0 = min // 127 = max // BK4819_WriteRegister(BK4819_REG_51, BK4819_REG_51_DISABLE_CxCSS | BK4819_REG_51_GPIO6_PIN2_NORMAL | BK4819_REG_51_TX_CDCSS_POSITIVE | BK4819_REG_51_MODE_CDCSS | BK4819_REG_51_CDCSS_23_BIT | BK4819_REG_51_1050HZ_NO_DETECTION | BK4819_REG_51_AUTO_CDCSS_BW_DISABLE | BK4819_REG_51_AUTO_CTCSS_BW_DISABLE); BK4819_RX_TurnOn(); } void BK4819_Disable(void) { BK4819_WriteRegister(BK4819_REG_30, 0); } void BK4819_StopScan(void) { BK4819_DisableFrequencyScan(); BK4819_Disable(); } uint8_t BK4819_GetDTMF_5TONE_Code(void) { return (BK4819_ReadRegister(BK4819_REG_0B) >> 8) & 0x0F; } uint8_t BK4819_GetCDCSSCodeType(void) { return (BK4819_ReadRegister(BK4819_REG_0C) >> 14) & 3u; } uint8_t BK4819_GetCTCShift(void) { return (BK4819_ReadRegister(BK4819_REG_0C) >> 12) & 3u; } uint8_t BK4819_GetCTCType(void) { return (BK4819_ReadRegister(BK4819_REG_0C) >> 10) & 3u; } void BK4819_SendFSKData(uint16_t *pData) { unsigned int i; uint8_t Timeout = 200; SYSTEM_DelayMs(20); BK4819_WriteRegister(BK4819_REG_3F, BK4819_REG_3F_FSK_TX_FINISHED); BK4819_WriteRegister(BK4819_REG_59, 0x8068); BK4819_WriteRegister(BK4819_REG_59, 0x0068); for (i = 0; i < 36; i++) BK4819_WriteRegister(BK4819_REG_5F, pData[i]); SYSTEM_DelayMs(20); BK4819_WriteRegister(BK4819_REG_59, 0x2868); while (Timeout-- && (BK4819_ReadRegister(BK4819_REG_0C) & 1u) == 0) SYSTEM_DelayMs(5); BK4819_WriteRegister(BK4819_REG_02, 0); SYSTEM_DelayMs(20); BK4819_ResetFSK(); } void BK4819_PrepareFSKReceive(void) { BK4819_ResetFSK(); BK4819_WriteRegister(BK4819_REG_02, 0); BK4819_WriteRegister(BK4819_REG_3F, 0); BK4819_RX_TurnOn(); BK4819_WriteRegister(BK4819_REG_3F, 0 | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL); // Clear RX FIFO // FSK Preamble Length 7 bytes // FSK SyncLength Selection BK4819_WriteRegister(BK4819_REG_59, 0x4068); // Enable FSK Scramble // Enable FSK RX // FSK Preamble Length 7 bytes // FSK SyncLength Selection BK4819_WriteRegister(BK4819_REG_59, 0x3068); } void BK4819_PlayRogerNormal(void) { #if 0 const uint32_t tone1_Hz = 500; const uint32_t tone2_Hz = 700; #else // motorola type const uint32_t tone1_Hz = 1540; const uint32_t tone2_Hz = 1310; #endif BK4819_EnterTxMute(); BK4819_SetAF(BK4819_AF_MUTE); BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_ENABLE_TONE1 | (66u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)); BK4819_EnableTXLink(); SYSTEM_DelayMs(50); BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone1_Hz)); BK4819_ExitTxMute(); SYSTEM_DelayMs(80); BK4819_EnterTxMute(); BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone2_Hz)); BK4819_ExitTxMute(); SYSTEM_DelayMs(80); BK4819_EnterTxMute(); BK4819_WriteRegister(BK4819_REG_70, 0x0000); BK4819_WriteRegister(BK4819_REG_30, 0xC1FE); // 1 1 0000 0 1 1111 1 1 1 0 } void BK4819_Enable_AfDac_DiscMode_TxDsp(void) { BK4819_WriteRegister(BK4819_REG_30, 0x0000); BK4819_WriteRegister(BK4819_REG_30, 0x0302); } void BK4819_GetVoxAmp(uint16_t *pResult) { *pResult = BK4819_ReadRegister(BK4819_REG_64) & 0x7FFF; } void BK4819_SetScrambleFrequencyControlWord(uint32_t Frequency) { BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency)); } void BK4819_PlayDTMFEx(bool bLocalLoopback, char Code) { BK4819_EnableDTMF(); BK4819_EnterTxMute(); BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE); BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_MASK_ENABLE_TONE1 | (DTMF_TONE1_GAIN << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN) | BK4819_REG_70_MASK_ENABLE_TONE2 | (DTMF_TONE2_GAIN << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)); BK4819_EnableTXLink(); SYSTEM_DelayMs(50); BK4819_PlayDTMF(Code); BK4819_ExitTxMute(); } #ifdef ENABLE_MDC1200 void BK4819_start_tone(const uint16_t frequency, const unsigned int level, const bool tx, const bool tx_mute) { SYSTEM_DelayMs(1); GPIO_ClearBit(&GPIOC->DATA, 4); SYSTEM_DelayMs(1); // mute TX BK4819_WriteRegister(0x50, (1u << 15) | 0x3B20); BK4819_WriteRegister(0x70, BK4819_REG_70_ENABLE_TONE1 | ((level & 0x7f) << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)); BK4819_WriteRegister(0x30, 0); if (!tx) { BK4819_WriteRegister(0x30, // BK4819_REG_30_ENABLE_VCO_CALIB | // BK4819_REG_30_ENABLE_UNKNOWN | // BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | // BK4819_REG_30_ENABLE_PLL_VCO | // BK4819_REG_30_ENABLE_PA_GAIN | // BK4819_REG_30_ENABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | // BK4819_REG_30_ENABLE_RX_DSP | 0); } else { BK4819_WriteRegister(0x30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_UNKNOWN | // BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_PA_GAIN | // BK4819_REG_30_ENABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | // BK4819_REG_30_ENABLE_RX_DSP | 0); } BK4819_WriteRegister(0x71, scale_freq(frequency)); SYSTEM_DelayMs(1); // BK4819_SetAF(tx ? BK4819_AF_BEEP : 2); BK4819_SetAF(2); // RX // BK4819_SetAF(BK4819_AF_BEEP); // TX if (!tx_mute) BK4819_WriteRegister(0x50, 0x3B20); // 0011 1011 0010 0000 GPIO_SetBit(&GPIOC->DATA, 4); SYSTEM_DelayMs(1); } void BK4819_stop_tones(const bool tx) { SYSTEM_DelayMs(1); GPIO_ClearBit(&GPIOC->DATA, 4); SYSTEM_DelayMs(1); BK4819_SetAF(BK4819_AF_MUTE); // BK4819_EnterTxMute(); SYSTEM_DelayMs(1); BK4819_WriteRegister(0x70, 0); BK4819_WriteRegister(0x30, 0); if (!tx) { BK4819_WriteRegister(0x30, BK4819_REG_30_ENABLE_VCO_CALIB | // BK4819_REG_30_ENABLE_UNKNOWN | BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | // BK4819_REG_30_ENABLE_PA_GAIN | // BK4819_REG_30_ENABLE_MIC_ADC | // BK4819_REG_30_ENABLE_TX_DSP | BK4819_REG_30_ENABLE_RX_DSP | 0); } else { BK4819_WriteRegister(0x30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_UNKNOWN | // BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_PA_GAIN | BK4819_REG_30_ENABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | // BK4819_REG_30_ENABLE_RX_DSP | 0); } SYSTEM_DelayMs(1); BK4819_ExitTxMute(); SYSTEM_DelayMs(1); } void BK4819_send_MDC1200(const uint8_t op, const uint8_t arg, const uint16_t id, const bool long_preamble) { uint16_t fsk_reg59; uint8_t packet[42]; // create the MDC1200 packet const unsigned int size = MDC1200_encode_single_packet(packet, op, arg, id); //BK4819_ExitTxMute(); BK4819_WriteRegister(0x50, 0x3B20); // 0011 1011 0010 0000 BK4819_WriteRegister(0x30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_UNKNOWN | // BK4819_REG_30_ENABLE_RX_LINK | BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_PA_GAIN | // BK4819_REG_30_ENABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | // BK4819_REG_30_ENABLE_RX_DSP | 0); #if 1 GPIO_ClearBit(&GPIOC->DATA, 4); BK4819_SetAF(BK4819_AF_MUTE); #else // let the user hear the FSK being sent BK4819_SetAF(BK4819_AF_BEEP); GPIO_SetBit(&GPIOC->DATA, 4); #endif // SYSTEM_DelayMs(2); // REG_51 // // <15> TxCTCSS/CDCSS 0 = disable 1 = Enable // // turn off CTCSS/CDCSS during FFSK const uint16_t css_val = BK4819_ReadRegister(0x51); BK4819_WriteRegister(0x51, 0); // set the FM deviation level const uint16_t dev_val = BK4819_ReadRegister(0x40); #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG) // UART_printf("tx dev %04X\r\n", dev_val); #endif { uint16_t deviation = 850; switch (m_bandwidth) { case BK4819_FILTER_BW_WIDE: deviation = 1050; break; case BK4819_FILTER_BW_NARROW: deviation = 850; break; case BK4819_FILTER_BW_NARROWER: deviation = 750; break; } //BK4819_WriteRegister(0x40, (3u << 12) | (deviation & 0xfff)); BK4819_WriteRegister(0x40, (dev_val & 0xf000) | (deviation & 0xfff)); } // REG_2B 0 // // <15> 1 Enable CTCSS/CDCSS DC cancellation after FM Demodulation 1 = enable 0 = disable // <14> 1 Enable AF DC cancellation after FM Demodulation 1 = enable 0 = disable // <10> 0 AF RX HPF 300Hz filter 0 = enable 1 = disable // <9> 0 AF RX LPF 3kHz filter 0 = enable 1 = disable // <8> 0 AF RX de-emphasis filter 0 = enable 1 = disable // <2> 0 AF TX HPF 300Hz filter 0 = enable 1 = disable // <1> 0 AF TX LPF filter 0 = enable 1 = disable // <0> 0 AF TX pre-emphasis filter 0 = enable 1 = disable // // disable the 300Hz HPF and FM pre-emphasis filter // const uint16_t filt_val = BK4819_ReadRegister(0x2B); BK4819_WriteRegister(0x2B, (1u << 2) | (1u << 0)); // ******************************************* // setup the FFSK modem as best we can for MDC1200 // MDC1200 uses 1200/1800 Hz FSK tone frequencies 1200 bits/s // BK4819_WriteRegister(0x58, // 0x37C3); // 001 101 11 11 00 001 1 (1u << 13) | // 1 FSK TX mode selection // 0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM // 1 = FFSK 1200/1800 TX // 2 = ??? // 3 = FFSK 1200/2400 TX // 4 = ??? // 5 = NOAA SAME TX // 6 = ??? // 7 = ??? // (7u << 10) | // 0 FSK RX mode selection // 0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM // 1 = ??? // 2 = ??? // 3 = ??? // 4 = FFSK 1200/2400 RX // 5 = ??? // 6 = ??? // 7 = FFSK 1200/1800 RX // (0u << 8) | // 0 FSK RX gain // 0 ~ 3 // (0u << 6) | // 0 ??? // 0 ~ 3 // (0u << 4) | // 0 FSK preamble type selection // 0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0 // 1 = ??? // 2 = 0x55 // 3 = 0xAA // (1u << 1) | // 1 FSK RX bandwidth setting // 0 = FSK 1.2K .. no tones, direct FM // 1 = FFSK 1200/1800 // 2 = NOAA SAME RX // 3 = ??? // 4 = FSK 2.4K and FFSK 1200/2400 // 5 = ??? // 6 = ??? // 7 = ??? // (1u << 0)); // 1 FSK enable // 0 = disable // 1 = enable // REG_72 // // <15:0> 0x2854 TONE-2 / FSK frequency control word // = freq(Hz) * 10.32444 for XTAL 13M / 26M or // = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M // // tone-2 = 1200Hz // BK4819_WriteRegister(0x72, scale_freq(1200)); // REG_70 // // <15> 0 TONE-1 // 1 = enable // 0 = disable // // <14:8> 0 TONE-1 tuning // // <7> 0 TONE-2 // 1 = enable // 0 = disable // // <6:0> 0 TONE-2 / FSK tuning // 0 ~ 127 // // enable tone-2, set gain // BK4819_WriteRegister(0x70, // 0 0000000 1 1100000 ( 0u << 15) | // 0 ( 0u << 8) | // 0 ( 1u << 7) | // 1 (96u << 0)); // 96 // (127u << 0)); // REG_59 // // <15> 0 TX FIFO 1 = clear // <14> 0 RX FIFO 1 = clear // <13> 0 FSK Scramble 1 = Enable // <12> 0 FSK RX 1 = Enable // <11> 0 FSK TX 1 = Enable // <10> 0 FSK data when RX 1 = Invert // <9> 0 FSK data when TX 1 = Invert // <8> 0 ??? // // <7:4> 0 FSK preamble length selection // 0 = 1 byte // 1 = 2 bytes // 2 = 3 bytes // 15 = 16 bytes // // <3> 0 FSK sync length selection // 0 = 2 bytes (FSK Sync Byte 0, 1) // 1 = 4 bytes (FSK Sync Byte 0, 1, 2, 3) // // <2:0> 0 ??? // fsk_reg59 = (0u << 15) | // 0/1 1 = clear TX FIFO (0u << 14) | // 0/1 1 = clear RX FIFO (0u << 13) | // 0/1 1 = scramble (0u << 12) | // 0/1 1 = enable RX (0u << 11) | // 0/1 1 = enable TX (0u << 10) | // 0/1 1 = invert data when RX (0u << 9) | // 0/1 1 = invert data when TX (0u << 8) | // 0/1 ??? (0u << 4) | // 0 ~ 15 preamble length .. bit toggling (1u << 3) | // 0/1 sync length (0u << 0); // 0 ~ 7 ??? fsk_reg59 |= long_preamble ? 15u << 4 : 3u << 4; // Set packet length (not including pre-amble and sync bytes that we can't seem to disable) BK4819_WriteRegister(0x5D, ((size - 1) << 8)); // REG_5A // // <15:8> 0x55 FSK Sync Byte 0 (Sync Byte 0 first, then 1,2,3) // <7:0> 0x55 FSK Sync Byte 1 // BK4819_WriteRegister(0x5A, 0x0000); // bytes 1 & 2 // REG_5B // // <15:8> 0x55 FSK Sync Byte 2 (Sync Byte 0 first, then 1,2,3) // <7:0> 0xAA FSK Sync Byte 3 // BK4819_WriteRegister(0x5B, 0x0000); // bytes 2 & 3 // CRC setting (plus other stuff we don't know what) // // REG_5C // // <15:7> ??? // // <6> 1 CRC option enable 0 = disable 1 = enable // // <5:0> ??? // // disable CRC // // NB, this also affects TX pre-amble in some way // BK4819_WriteRegister(0x5C, 0x5625); // 010101100 0 100101 // BK4819_WriteRegister(0x5C, 0xAA30); // 101010100 0 110000 // BK4819_WriteRegister(0x5C, 0x0030); // 000000000 0 110000 BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's BK4819_WriteRegister(0x59, fsk_reg59); // release the FIFO reset { // load the entire packet data into the TX FIFO buffer unsigned int i; const uint16_t *p = (const uint16_t *)packet; for (i = 0; i < (size / sizeof(p[0])); i++) BK4819_WriteRegister(0x5F, p[i]); // load 16-bits at a time } // enable tx interrupt BK4819_WriteRegister(0x3F, BK4819_REG_3F_FSK_TX_FINISHED); // enable FSK TX BK4819_WriteRegister(0x59, (1u << 11) | fsk_reg59); { // packet time is .. // 173ms for PTT ID, acks, emergency // 266ms for call alert and sel-calls // allow up to 310ms for the TX to complete // if it takes any longer then somethings gone wrong, we shut the TX down unsigned int timeout = 300 / 4; while (timeout-- > 0) { SYSTEM_DelayMs(4); if (BK4819_ReadRegister(0x0C) & (1u << 0)) { // we have interrupt flags BK4819_WriteRegister(0x02, 0); if (BK4819_ReadRegister(0x02) & BK4819_REG_02_FSK_TX_FINISHED) timeout = 0; // TX is complete } } } GPIO_ClearBit(&GPIOC->DATA, 4); // disable FSK BK4819_WriteRegister(0x59, fsk_reg59); BK4819_WriteRegister(0x3F, 0); // disable interrupts BK4819_WriteRegister(0x70, 0); BK4819_WriteRegister(0x58, 0); // restore FM deviation level BK4819_WriteRegister(0x40, dev_val); // restore TX/RX filtering BK4819_WriteRegister(0x2B, filt_val); // restore the CTCSS/CDCSS setting BK4819_WriteRegister(0x51, css_val); //BK4819_EnterTxMute(); BK4819_WriteRegister(0x50, 0xBB20); // 1011 1011 0010 0000 //BK4819_SetAF(BK4819_AF_MUTE); BK4819_WriteRegister(0x47, (1u << 14) | (1u << 13) | (BK4819_AF_MUTE << 8) | (1u << 6)); BK4819_WriteRegister(0x30, BK4819_REG_30_ENABLE_VCO_CALIB | BK4819_REG_30_ENABLE_UNKNOWN | // BK4819_REG_30_ENABLE_RX_LINK | // BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_PLL_VCO | BK4819_REG_30_ENABLE_PA_GAIN | BK4819_REG_30_ENABLE_MIC_ADC | BK4819_REG_30_ENABLE_TX_DSP | // BK4819_REG_30_ENABLE_RX_DSP | 0); //BK4819_ExitTxMute(); BK4819_WriteRegister(0x50, 0x3B20); // 0011 1011 0010 0000 } #endif void enable_msg_rx(const bool enable) { // REG_70 // // <15> 0 TONE-1 // 1 = enable // 0 = disable // // <14:8> 0 TONE-1 gain // // <7> 0 TONE-2 // 1 = enable // 0 = disable // // <6:0> 0 TONE-2 / FSK gain // 0 ~ 127 // // enable tone-2, set gain // REG_72 // // <15:0> 0x2854 TONE-2 / FSK frequency control word // = freq(Hz) * 10.32444 for XTAL 13M / 26M or // = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M // // tone-2 = 1200Hz // REG_58 // // <15:13> 1 FSK TX mode selection // 0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM // 1 = FFSK 1200 / 1800 TX // 2 = ??? // 3 = FFSK 1200 / 2400 TX // 4 = ??? // 5 = NOAA SAME TX // 6 = ??? // 7 = ??? // // <12:10> 0 FSK RX mode selection // 0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM // 1 = ??? // 2 = ??? // 3 = ??? // 4 = FFSK 1200 / 2400 RX // 5 = ??? // 6 = ??? // 7 = FFSK 1200 / 1800 RX // // <9:8> 0 FSK RX gain // 0 ~ 3 // // <7:6> 0 ??? // 0 ~ 3 // // <5:4> 0 FSK preamble type selection // 0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0 // 1 = ??? // 2 = 0x55 // 3 = 0xAA // // <3:1> 1 FSK RX bandwidth setting // 0 = FSK 1.2K .. no tones, direct FM // 1 = FFSK 1200 / 1800 // 2 = NOAA SAME RX // 3 = ??? // 4 = FSK 2.4K and FFSK 1200 / 2400 // 5 = ??? // 6 = ??? // 7 = ??? // // <0> 1 FSK enable // 0 = disable // 1 = enable // REG_5C // // <15:7> ??? // // <6> 1 CRC option enable // 0 = disable // 1 = enable // // <5:0> ??? // // disable CRC // REG_5D // // set the packet size if (enable) { const uint16_t fsk_reg59 = (0u << 15) | // 1 = clear TX FIFO (0u << 14) | // 1 = clear RX FIFO (0u << 13) | // 1 = scramble (0u << 12) | // 1 = enable RX (0u << 11) | // 1 = enable TX (0u << 10) | // 1 = invert data when RX (0u << 9) | // 1 = invert data when TX (0u << 8) | // ??? (0u << 4) | // 0 ~ 15 preamble length selection .. mdc1200 does not send bit reversals :( (1u << 3) | // 0/1 sync length selection (0u << 0); // 0 ~ 7 ??? BK4819_WriteRegister(0x70, (0u << 15) | // 0 (0u << 8) | // 0 (1u << 7) | // 1 (96u << 0)); // 96 BK4819_WriteRegister(0x72, scale_freq(1200)); BK4819_WriteRegister(0x58, (1u << 13) | // 1 FSK TX mode selection // 0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM // 1 = FFSK 1200 / 1800 TX // 2 = ??? // 3 = FFSK 1200 / 2400 TX // 4 = ??? // 5 = NOAA SAME TX // 6 = ??? // 7 = ??? // (7u << 10) | // 0 FSK RX mode selection // 0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM // 1 = ??? // 2 = ??? // 3 = ??? // 4 = FFSK 1200 / 2400 RX // 5 = ??? // 6 = ??? // 7 = FFSK 1200 / 1800 RX // (3u << 8) | // 0 FSK RX gain // 0 ~ 3 // (0u << 6) | // 0 ??? // 0 ~ 3 // (0u << 4) | // 0 FSK preamble type selection // 0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0 // 1 = ??? // 2 = 0x55 // 3 = 0xAA // (1u << 1) | // 1 FSK RX bandwidth setting // 0 = FSK 1.2K .. no tones, direct FM // 1 = FFSK 1200 / 1800 // 2 = NOAA SAME RX // 3 = ??? // 4 = FSK 2.4K and FFSK 1200 / 2400 // 5 = ??? // 6 = ??? // 7 = ??? // (1u << 0)); // 1 FSK enable // 0 = disable // 1 = enable // REG_5A .. bytes 0 & 1 sync pattern // // <15:8> sync byte 0 // < 7:0> sync byte 1 // BK4819_WriteRegister(0x5A, ((uint16_t)mdc1200_sync_suc_xor[0] << 8) | (mdc1200_sync_suc_xor[1] << 0)); BK4819_WriteRegister(0x5A, 0x7240); //0x7240 // REG_5B .. bytes 2 & 3 sync pattern // // <15:8> sync byte 2 // < 7:0> sync byte 3 // BK4819_WriteRegister(0x5B, ((uint16_t)mdc1200_sync_suc_xor[2] << 8) | (mdc1200_sync_suc_xor[3] << 0)); BK4819_WriteRegister(0x5B, 0x99a7);//0x99a7 // disable CRC BK4819_WriteRegister(0x5C, 0x5625); // 01010110 0 0 100101 // BK4819_WriteRegister(0x5C, 0xAA30); // 10101010 0 0 110000 // set the almost full threshold BK4819_WriteRegister(0x5E, (64u << 3) | (1u << 0)); // 0 ~ 127, 0 ~ 7 // { // packet size .. sync + 14 bytes - size of a single mdc1200 packet //// uint16_t size = 1 + (MDC1200_FEC_K * 2); // uint16_t size = 0 + (MDC1200_FEC_K * 2); //// size -= (fsk_reg59 & (1u << 3)) ? 4 : 2; // size = ((size + 1) / 2) * 2; // round up to even, else FSK RX doesn't work // BK4819_WriteRegister(0x5D, ((size - 1) << 8)); // } { // packet size .. sync + 14 bytes - size of a single packet uint16_t size = 52; // size -= (fsk_reg59 & (1u << 3)) ? 4 : 2; size = (((size + 1) / 2) * 2) + 2; // round up to even, else FSK RX doesn't work BK4819_WriteRegister(0x5D, (size << 8)); } // clear FIFO's then enable RX BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); BK4819_WriteRegister(0x59, (1u << 12) | fsk_reg59); // clear interrupt flags BK4819_WriteRegister(0x02, 0); // BK4819_RX_TurnOn(); // enable interrupts // BK4819_WriteRegister(0x3F, BK4819_ReadRegister(0x3F) | BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL); } else { BK4819_WriteRegister(0x70, 0); BK4819_WriteRegister(0x58, 0); } } ================================================ FILE: driver/bk4819.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_BK4819_h #define DRIVER_BK4819_h #include #include #include "driver/bk4819-regs.h" enum BK4819_AF_Type_t { BK4819_AF_MUTE = 0u, // BK4819_AF_FM = 1u, // FM BK4819_AF_ALAM = 2u, // BK4819_AF_BEEP = 3u, // BK4819_AF_BASEBAND1 = 4u, // RAW BK4819_AF_BASEBAND2 = 5u, // USB BK4819_AF_CTCO = 6u, // strange LF audio .. maybe the CTCSS LF line ? BK4819_AF_AM = 7u, // AM BK4819_AF_FSKO = 8u, // nothing BK4819_AF_UNKNOWN3 = 9u, // BYP BK4819_AF_UNKNOWN4 = 10u, // nothing at all BK4819_AF_UNKNOWN5 = 11u, // distorted BK4819_AF_UNKNOWN6 = 12u, // distorted BK4819_AF_UNKNOWN7 = 13u, // interesting BK4819_AF_UNKNOWN8 = 14u, // interesting BK4819_AF_UNKNOWN9 = 15u // not a lot }; typedef enum BK4819_AF_Type_t BK4819_AF_Type_t; enum BK4819_FilterBandwidth_t { BK4819_FILTER_BW_WIDE = 0, BK4819_FILTER_BW_NARROW, BK4819_FILTER_BW_NARROWER }; typedef enum BK4819_FilterBandwidth_t BK4819_FilterBandwidth_t; enum BK4819_CssScanResult_t { BK4819_CSS_RESULT_NOT_FOUND = 0, BK4819_CSS_RESULT_CTCSS, BK4819_CSS_RESULT_CDCSS }; typedef enum BK4819_CssScanResult_t BK4819_CssScanResult_t; // radio is asleep, not listening extern bool gRxIdleMode; void BK4819_Init(void); uint16_t BK4819_ReadRegister(BK4819_REGISTER_t Register); void BK4819_WriteRegister(BK4819_REGISTER_t Register, uint16_t Data); void BK4819_SetRegValue(RegisterSpec s, uint16_t v); void BK4819_WriteU8(uint8_t Data); void BK4819_WriteU16(uint16_t Data); void BK4819_SetAGC(bool enable); void BK4819_InitAGC(bool amModulation); void BK4819_ToggleGpioOut(BK4819_GPIO_PIN_t Pin, bool bSet); int8_t BK4819_GetRxGain_dB(void); int16_t BK4819_GetRSSI_dBm(void); void BK4819_SetCDCSSCodeWord(uint32_t CodeWord); void BK4819_SetCTCSSFrequency(uint32_t BaudRate); void BK4819_SetTailDetection(const uint32_t freq_10Hz); void BK4819_EnableVox(uint16_t Vox1Threshold, uint16_t Vox0Threshold); void BK4819_SetFilterBandwidth(const BK4819_FilterBandwidth_t Bandwidth, const bool weak_no_different); void BK4819_SetupPowerAmplifier(const uint8_t bias, const uint32_t frequency); void BK4819_SetFrequency(uint32_t Frequency); void BK4819_SetupSquelch( uint8_t SquelchOpenRSSIThresh, uint8_t SquelchCloseRSSIThresh, uint8_t SquelchOpenNoiseThresh, uint8_t SquelchCloseNoiseThresh, uint8_t SquelchCloseGlitchThresh, uint8_t SquelchOpenGlitchThresh); void BK4819_SetAF(BK4819_AF_Type_t AF); void BK4819_RX_TurnOn(void); void BK4819_PickRXFilterPathBasedOnFrequency(uint32_t Frequency); void BK4819_DisableScramble(void); void BK4819_EnableScramble(uint8_t Type); bool BK4819_CompanderEnabled(void); void BK4819_SetCompander(const unsigned int mode); void BK4819_DisableVox(void); void BK4819_DisableDTMF(void); void BK4819_EnableDTMF(void); void BK4819_PlayTone(uint16_t Frequency, bool bTuningGainSwitch); void BK4819_PlaySingleTone(const unsigned int tone_Hz, const unsigned int delay, const unsigned int level, const bool play_speaker); void BK4819_EnterTxMute(void); void BK4819_ExitTxMute(void); void BK4819_Sleep(void); void BK4819_TurnsOffTones_TurnsOnRX(void); #ifdef ENABLE_AIRCOPY void BK4819_SetupAircopy(void); #endif void BK4819_ResetFSK(void); void BK4819_ExitBypass(void); void BK4819_PrepareTransmit(void); void BK4819_TxOn_Beep(void); void BK4819_ExitSubAu(void); void BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable(void); void BK4819_EnterDTMF_TX(bool bLocalLoopback); void BK4819_ExitDTMF_TX(bool bKeep); void BK4819_EnableTXLink(void); void BK4819_PlayDTMF(char Code); void BK4819_PlayDTMFString(const char *pString, bool bDelayFirst, uint16_t FirstCodePersistTime, uint16_t HashCodePersistTime, uint16_t CodePersistTime, uint16_t CodeInternalTime); void BK4819_TransmitTone(bool bLocalLoopback, uint32_t Frequency); void BK4819_GenTail(uint8_t Tail); void BK4819_PlayCDCSSTail(void); void BK4819_PlayCTCSSTail(void); uint16_t BK4819_GetRSSI(void); uint8_t BK4819_GetGlitchIndicator(void); uint8_t BK4819_GetExNoiceIndicator(void); uint16_t BK4819_GetVoiceAmplitudeOut(void); uint8_t BK4819_GetAfTxRx(void); bool BK4819_GetFrequencyScanResult(uint32_t *pFrequency); BK4819_CssScanResult_t BK4819_GetCxCSSScanResult(uint32_t *pCdcssFreq, uint16_t *pCtcssFreq); void BK4819_DisableFrequencyScan(void); void BK4819_EnableFrequencyScan(void); void BK4819_SetScanFrequency(uint32_t Frequency); void BK4819_Disable(void); void BK4819_StopScan(void); uint8_t BK4819_GetDTMF_5TONE_Code(void); uint8_t BK4819_GetCDCSSCodeType(void); uint8_t BK4819_GetCTCShift(void); uint8_t BK4819_GetCTCType(void); void BK4819_SendFSKData(uint16_t *pData); void BK4819_PrepareFSKReceive(void); void BK4819_PlayRoger(void); void BK4819_PlayRogerNormal(void); void BK4819_PlayRogerMDC(void); void BK4819_Enable_AfDac_DiscMode_TxDsp(void); void BK4819_GetVoxAmp(uint16_t *pResult); void BK4819_SetScrambleFrequencyControlWord(uint32_t Frequency); void BK4819_PlayDTMFEx(bool bLocalLoopback, char Code); void BK4819_send_MDC1200(const uint8_t op, const uint8_t arg, const uint16_t id, const bool long_preamble); void BK4819_stop_tones(const bool tx); void BK4819_start_tone(const uint16_t frequency, const unsigned int level, const bool tx, const bool tx_mute); void enable_msg_rx(const bool enable); #endif ================================================ FILE: driver/crc.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "../bsp/dp32g030/crc.h" #include "crc.h" void CRC_Init(void) { CRC_CR = CRC_CR_CRC_EN_BITS_DISABLE | CRC_CR_INPUT_REV_BITS_NORMAL | CRC_CR_INPUT_INV_BITS_BIT_INVERTED | CRC_CR_OUTPUT_REV_BITS_REVERSED | CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED | CRC_CR_DATA_WIDTH_BITS_8 | CRC_CR_CRC_SEL_BITS_CRC_16_CCITT; CRC_IV = 0; } #define CRC16_XMODEM_POLY 0x1021 uint16_t CRC_Calculate1(void *pBuffer, uint16_t Size) { uint8_t *pData = (uint8_t *) pBuffer; uint16_t crc = 0; // 初始CRC值为0 while (Size--) { crc ^= (*pData++) << 8; // 将数据字节的最高位与CRC异或 for (uint8_t i = 0; i < 8; i++) { if (crc & 0x8000) { // 检查最高位是否为1 crc = (crc << 1) ^ CRC16_XMODEM_POLY; // 如果最高位为1，执行CRC多项式计算 } else { crc = crc << 1; // 如果最高位为0，继续左移 } } } return crc; } uint16_t compute_crc(const void *data, const unsigned int data_len) { // let the CPU's hardware do some work :) uint16_t crc; CRC_Init(); crc = CRC_Calculate(data, data_len); return crc; } uint16_t CRC_Calculate(const void *buffer, const unsigned int size) { const uint8_t *data = (const uint8_t *) buffer; uint16_t i; uint16_t crc; CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_ENABLE; for (i = 0; i < size; i++) CRC_DATAIN = data[i]; crc = (uint16_t) CRC_DATAOUT; CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_DISABLE; return crc; } ================================================ FILE: driver/crc.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_CRC_H #define DRIVER_CRC_H #include void CRC_Init(void); uint16_t CRC_Calculate(const void *buffer, const unsigned int size); uint16_t CRC_Calculate1( void *pBuffer, uint16_t Size); uint16_t compute_crc(const void *data, const unsigned int data_len) ; // let the CPU's hardware do some work :) void CRC_InitReverse(void); #endif ================================================ FILE: driver/eeprom.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include #include "driver/eeprom.h" #include "driver/i2c.h" #include "driver/system.h" #include "assert.h" #ifdef ENABLE_FLASHLIGHT #include "app/flashlight.h" #endif #include #include #include #include "app/action.h" #ifdef ENABLE_AIRCOPY #include "app/aircopy.h" #endif #include "app/app.h" #include "app/chFrScanner.h" #include "app/dtmf.h" #include "driver/uart.h" #ifdef ENABLE_FMRADIO #include "app/fm.h" #endif #include "app/generic.h" #include "app/main.h" #include "app/menu.h" #include "app/scanner.h" #ifdef ENABLE_UART #include "app/uart.h" #endif #include "ARMCM0.h" #include "audio.h" #include "board.h" #include "bsp/dp32g030/gpio.h" #include "driver/backlight.h" #ifdef ENABLE_FMRADIO #include "driver/bk1080.h" #endif #include "driver/bk4819.h" #include "driver/gpio.h" #include "driver/keyboard.h" #include "driver/st7565.h" #include "driver/system.h" #include "am_fix.h" //#include "external/printf/printf.h" #include "frequencies.h" #include "functions.h" #include "helper/battery.h" #include "misc.h" #include "radio.h" #include "settings.h" #if defined(ENABLE_OVERLAY) #include "sram-overlay.h" #endif #ifdef ENABLE_MESSENGER #include "app/messenger.h" #endif #ifdef ENABLE_DOPPLER #include "app/doppler.h" #endif #include "ui/battery.h" #include "ui/inputbox.h" #include "ui/main.h" #include "ui/menu.h" #include "ui/status.h" #include "ui/ui.h" void EEPROM_ReadBuffer(uint32_t Address, void *pBuffer, uint8_t Size) { __disable_irq(); I2C_Start(); uint8_t IIC_ADD = 0xA0 | Address >> 15 &14; I2C_Write(IIC_ADD); I2C_Write((Address >> 8) & 0xFF); I2C_Write((Address >> 0) & 0xFF); I2C_Start(); I2C_Write(IIC_ADD + 1); I2C_ReadBuffer(pBuffer, Size); I2C_Stop(); __enable_irq(); } void EEPROM_WriteBuffer(uint32_t Address, const void *pBuffer, uint8_t WRITE_SIZE) { // if (pBuffer == NULL) // return; uint8_t buffer[128]; EEPROM_ReadBuffer(Address, buffer, WRITE_SIZE); if (memcmp(pBuffer, buffer, WRITE_SIZE) != 0) { uint8_t IIC_ADD = 0xA0 | Address >> 15 &14; I2C_Start(); I2C_Write(IIC_ADD); I2C_Write((Address >> 8) & 0xFF); I2C_Write((Address) & 0xFF); I2C_WriteBuffer(pBuffer, WRITE_SIZE); I2C_Stop(); } SYSTEM_DelayMs(10); } ================================================ FILE: driver/eeprom.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_EEPROM_H #define DRIVER_EEPROM_H #include void EEPROM_ReadBuffer(uint32_t Address, void *pBuffer, uint8_t Size); void EEPROM_WriteBuffer(uint32_t Address, const void *pBuffer, uint8_t WRITE_SIZE); #endif ================================================ FILE: driver/flash.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "driver/flash.h" #include "sram-overlay.h" void FLASH_Init(FLASH_READ_MODE ReadMode) { overlay_FLASH_Init(ReadMode); } void FLASH_ConfigureTrimValues(void) { overlay_FLASH_ConfigureTrimValues(); } uint32_t FLASH_ReadNvrWord(uint32_t Address) { return overlay_FLASH_ReadNvrWord(Address); } ================================================ FILE: driver/flash.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_FLASH_H #define DRIVER_FLASH_H #include "bsp/dp32g030/flash.h" enum FLASH_READ_MODE { FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_VALUE_1_CYCLE, FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_VALUE_2_CYCLE, }; typedef enum FLASH_READ_MODE FLASH_READ_MODE; enum FLASH_MASK_SELECTION { FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_VALUE_NONE, FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_VALUE_2KB, FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_VALUE_4KB, FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_VALUE_8KB, }; typedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION; enum FLASH_MODE { FLASH_MODE_READ_AHB = FLASH_CFG_MODE_VALUE_READ_AHB, FLASH_MODE_PROGRAM = FLASH_CFG_MODE_VALUE_PROGRAM, FLASH_MODE_ERASE = FLASH_CFG_MODE_VALUE_ERASE, FLASH_MODE_READ_APB = FLASH_CFG_MODE_VALUE_READ_APB, }; typedef enum FLASH_MODE FLASH_MODE; enum FLASH_AREA { FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_VALUE_MAIN, FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_VALUE_NVR, }; typedef enum FLASH_AREA FLASH_AREA; void FLASH_Init(FLASH_READ_MODE ReadMode); void FLASH_ConfigureTrimValues(void); uint32_t FLASH_ReadNvrWord(uint32_t Address); #endif ================================================ FILE: driver/gpio.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ ================================================ FILE: driver/gpio.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_GPIO_H #define DRIVER_GPIO_H #include enum GPIOA_PINS { GPIOA_PIN_KEYBOARD_0 = 3, GPIOA_PIN_KEYBOARD_1 = 4, GPIOA_PIN_KEYBOARD_2 = 5, GPIOA_PIN_KEYBOARD_3 = 6, GPIOA_PIN_KEYBOARD_4 = 10, // Shared with I2C! GPIOA_PIN_KEYBOARD_5 = 11, // Shared with I2C! GPIOA_PIN_KEYBOARD_6 = 12, // Shared with voice chip! GPIOA_PIN_KEYBOARD_7 = 13, // Shared with voice chip! GPIOA_PIN_I2C_SCL = 10, // Shared with keyboard! GPIOA_PIN_I2C_SDA = 11, // Shared with keyboard! GPIOA_PIN_VOICE_0 = 12, // Shared with keyboard! GPIOA_PIN_VOICE_1 = 13 // Shared with keyboard! }; enum GPIOB_PINS { GPIOB_PIN_BACKLIGHT = 6, GPIOB_PIN_ST7565_A0 = 9, GPIOB_PIN_ST7565_RES = 11, // Shared with SWD! GPIOB_PIN_SWD_IO = 11, // Shared with ST7565! GPIOB_PIN_SWD_CLK = 14, GPIOB_PIN_BK1080 = 15 }; enum GPIOC_PINS { GPIOC_PIN_BK4819_SCN = 0, GPIOC_PIN_BK4819_SCL = 1, GPIOC_PIN_BK4819_SDA = 2, GPIOC_PIN_FLASHLIGHT = 3, GPIOC_PIN_AUDIO_PATH = 4, GPIOC_PIN_PTT = 5 }; static inline void GPIO_ClearBit(volatile uint32_t *pReg, uint8_t Bit) { *pReg &= ~(1U << Bit); } static inline uint8_t GPIO_CheckBit(volatile uint32_t *pReg, uint8_t Bit) { return (*pReg >> Bit) & 1U; } static inline void GPIO_FlipBit(volatile uint32_t *pReg, uint8_t Bit) { *pReg ^= 1U << Bit; } static inline void GPIO_SetBit(volatile uint32_t *pReg, uint8_t Bit) { *pReg |= 1U << Bit; } #endif ================================================ FILE: driver/i2c.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "bsp/dp32g030/gpio.h" #include "bsp/dp32g030/portcon.h" #include "driver/gpio.h" #include "driver/i2c.h" #include "driver/systick.h" void I2C_Start(void) { GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); SYSTICK_DelayUs(1); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); } void I2C_Stop(void) { GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); SYSTICK_DelayUs(1); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); SYSTICK_DelayUs(1); } uint8_t I2C_Read(bool bFinal) { uint8_t i, Data; PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE; PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK; GPIOA->DIR &= ~GPIO_DIR_11_MASK; Data = 0; for (i = 0; i < 8; i++) { GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); Data <<= 1; SYSTICK_DelayUs(1); if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA)) { Data |= 1U; } GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); } PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK; PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE; GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT; GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); if (bFinal) { GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); } else { GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); } SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); return Data; } int I2C_Write(uint8_t Data) { uint8_t i; int ret = -1; GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); for (i = 0; i < 8; i++) { if ((Data & 0x80) == 0) { GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); } else { GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); } Data <<= 1; SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); } PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE; PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK; GPIOA->DIR &= ~GPIO_DIR_11_MASK; GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); SYSTICK_DelayUs(1); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); for (i = 0; i < 255; i++) { if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA) == 0) { ret = 0; break; } } GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL); SYSTICK_DelayUs(1); PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK; PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE; GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT; GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA); return ret; } int I2C_ReadBuffer(void *pBuffer, uint8_t Size) { uint8_t *pData = (uint8_t *) pBuffer; uint8_t i; if (Size == 1) { *pData = I2C_Read(true); return 1; } for (i = 0; i < Size - 1; i++) { SYSTICK_DelayUs(1); pData[i] = I2C_Read(false); } SYSTICK_DelayUs(1); pData[i++] = I2C_Read(true); return Size; } int I2C_WriteBuffer(const void *pBuffer, uint8_t Size) { const uint8_t *pData = (const uint8_t *) pBuffer; uint8_t i; for (i = 0; i < Size; i++) { if (I2C_Write(*pData++) < 0) { return -1; } } return 0; } ================================================ FILE: driver/i2c.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_I2C_H #define DRIVER_I2C_H #include #include enum { I2C_WRITE = 0U, I2C_READ = 1U, }; void I2C_Start(void); void I2C_Stop(void); uint8_t I2C_Read(bool bFinal); int I2C_Write(uint8_t Data); int I2C_ReadBuffer(void *pBuffer, uint8_t Size); int I2C_WriteBuffer(const void *pBuffer, uint8_t Size); #endif ================================================ FILE: driver/keyboard.c ================================================ /* Copyright 2023 Manuel Jinger * Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "bsp/dp32g030/gpio.h" #include "driver/gpio.h" #include "driver/keyboard.h" #include "driver/systick.h" #include "driver/i2c.h" #include "misc.h" KEY_Code_t gKeyReading0 = KEY_INVALID; KEY_Code_t gKeyReading1 = KEY_INVALID; uint16_t gDebounceCounter = 0; bool gWasFKeyPressed = false; #ifdef ENABLE_DOCK KEY_Code_t gSimulateKey = KEY_INVALID; KEY_Code_t gSimulateHold = KEY_INVALID; uint8_t gDebounceDefeat = 0; #endif static const struct { // Using a 16 bit pre-calculated shift and invert is cheaper // than using 8 bit and doing shift and invert in code. uint16_t set_to_zero_mask; // We are very fortunate. // The key and pin defines fit together in a single u8, making this very efficient struct { KEY_Code_t key: 5; uint8_t pin: 3; // Pin 6 is highest } pins[4]; } keyboard[] = { { // Zero row // Set to zero to handle special case of nothing pulled down .set_to_zero_mask = 0xffff, .pins = { {.key = KEY_SIDE1, .pin = GPIOA_PIN_KEYBOARD_0}, {.key = KEY_SIDE2, .pin = GPIOA_PIN_KEYBOARD_1}, // Duplicate to fill the array with valid values {.key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1}, {.key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1} } }, { // First row .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_4) & 0xffff, .pins = { {.key = KEY_MENU, .pin = GPIOA_PIN_KEYBOARD_0}, {.key = KEY_1, .pin = GPIOA_PIN_KEYBOARD_1}, {.key = KEY_4, .pin = GPIOA_PIN_KEYBOARD_2}, {.key = KEY_7, .pin = GPIOA_PIN_KEYBOARD_3} } }, { // Second row .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_5) & 0xffff, .pins = { {.key = KEY_UP, .pin = GPIOA_PIN_KEYBOARD_0}, {.key = KEY_2, .pin = GPIOA_PIN_KEYBOARD_1}, {.key = KEY_5, .pin = GPIOA_PIN_KEYBOARD_2}, {.key = KEY_8, .pin = GPIOA_PIN_KEYBOARD_3} } }, { // Third row .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_6) & 0xffff, .pins = { {.key = KEY_DOWN, .pin = GPIOA_PIN_KEYBOARD_0}, {.key = KEY_3, .pin = GPIOA_PIN_KEYBOARD_1}, {.key = KEY_6, .pin = GPIOA_PIN_KEYBOARD_2}, {.key = KEY_9, .pin = GPIOA_PIN_KEYBOARD_3} } }, { // Fourth row .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_7) & 0xffff, .pins = { {.key = KEY_EXIT, .pin = GPIOA_PIN_KEYBOARD_0}, {.key = KEY_STAR, .pin = GPIOA_PIN_KEYBOARD_1}, {.key = KEY_0, .pin = GPIOA_PIN_KEYBOARD_2}, {.key = KEY_F, .pin = GPIOA_PIN_KEYBOARD_3} } } }; KEY_Code_t KEYBOARD_Poll(void) { #ifdef ENABLE_DOCK if(gSimulateKey != KEY_INVALID) { const KEY_Code_t temp = gSimulateKey; if(gDebounceDefeat++ >= 5) gSimulateKey = KEY_INVALID; return temp; } if(gSimulateHold != KEY_INVALID) { return gSimulateHold; } #endif KEY_Code_t Key = KEY_INVALID; // if (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT)) // return KEY_PTT; // ***************** for (unsigned int j = 0; j < ARRAY_SIZE(keyboard); j++) { uint16_t reg; unsigned int i; unsigned int k; // Set all high GPIOA->DATA |= 1u << GPIOA_PIN_KEYBOARD_4 | 1u << GPIOA_PIN_KEYBOARD_5 | 1u << GPIOA_PIN_KEYBOARD_6 | 1u << GPIOA_PIN_KEYBOARD_7; // Clear the pin we are selecting GPIOA->DATA &= keyboard[j].set_to_zero_mask; // Read all 4 GPIO pins at once .. with de-noise, max of 8 sample loops for (i = 0, k = 0, reg = 0; i < 3 && k < 8; i++, k++) { SYSTICK_DelayUs(1); uint16_t reg2 = GPIOA->DATA; i *= reg == reg2; reg = reg2; } if (i < 3) break; // noise is too bad for (unsigned int i = 0; i < ARRAY_SIZE(keyboard[j].pins); i++) { const uint16_t mask = 1u << keyboard[j].pins[i].pin; if (!(reg & mask)) { Key = keyboard[j].pins[i].key; break; } } if (Key != KEY_INVALID) break; } // Create I2C stop condition since we might have toggled I2C pins // This leaves GPIOA_PIN_KEYBOARD_4 and GPIOA_PIN_KEYBOARD_5 high // I2C_Stop(); // Reset VOICE pins GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_6); GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_7); return Key; } KEY_Code_t GetKey() { KEY_Code_t btn = KEYBOARD_Poll(); if (btn == KEY_INVALID && !GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT)) { btn = KEY_PTT; } return btn; } ================================================ FILE: driver/keyboard.h ================================================ /* Copyright 2023 Manuel Jinger * Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_KEYBOARD_H #define DRIVER_KEYBOARD_H #include #include enum KEY_Code_e { KEY_0 = 0, // 0 KEY_1, // 1 KEY_2, // 2 KEY_3, // 3 KEY_4, // 4 KEY_5, // 5 KEY_6, // 6 KEY_7, // 7 KEY_8, // 8 KEY_9, // 9 KEY_MENU, // A KEY_UP, // B KEY_DOWN, // C KEY_EXIT, // D KEY_STAR, // * KEY_F, // # KEY_PTT, // KEY_SIDE2, // KEY_SIDE1, // KEY_INVALID // }; typedef enum KEY_Code_e KEY_Code_t; extern KEY_Code_t gKeyReading0; extern KEY_Code_t gKeyReading1; extern uint16_t gDebounceCounter; extern bool gWasFKeyPressed; KEY_Code_t KEYBOARD_Poll(void); KEY_Code_t GetKey() ; #ifdef ENABLE_DOCK extern KEY_Code_t gSimulateKey; extern KEY_Code_t gSimulateHold; extern uint8_t gDebounceDefeat; #endif #endif ================================================ FILE: driver/rtc.c ================================================ // // Created by RUPC on 2024/1/30. // #include "bsp/dp32g030/rtc.h" #include "ARMCM0.h" #include "driver/eeprom.h" #include "driver/system.h" #include "ui/helper.h" uint8_t time[6]; void RTC_INIT() { uint32_t correct_freq = 32768 - 1 + ((((RC_FREQ_DELTA & 0x400) >> 10) ? 1 : -1) * (RC_FREQ_DELTA & 0x3ff)); // 清空PRE_PERIOD, PRE_DECIMAL 和 PRE_ROUND相关位 RTC_PRE &= ~((0x7fff << 0) | (0xf << 20) | (0x1 << 24)); RTC_PRE |= correct_freq//PRE_ROUND=32768HZ-1 | (0 << 20)//DECIMAL=0 | (0 << 24);//PRE_PERIOD=8s EEPROM_ReadBuffer(0X2BC0, time, 6); RTC_Set(); NVIC_SetPriority(Interrupt2_IRQn, 0); RTC_IF |= (1 << 0);//清除中断标志位 RTC_IE |= (1 << 0);//使能秒中断 RTC_CFG |= //(1 << 2)|//打开设置时间功能 (1 << 0);//RTC使能 NVIC_EnableIRQ(Interrupt2_IRQn); } void RTC_Set() { RTC_DR = (2 << 24)//day 2 | (time[0] / 10 << 20)//YEAR TEN | (time[0] % 10 << 16) //YEAR ONE | (time[1] / 10 << 12)//MONTH TEN | (time[1] % 10 << 8)//MONTH ONE | (time[2] / 10 << 4)//DAY TEN | (time[2] % 10 << 0);//DAY ONE RTC_TR = (time[3] / 10 << 20) //h十位 | (time[3] % 10 << 16)//h个位 | (time[4] / 10 << 12)//min十位 | (time[4] % 10 << 8)//min个位 | (time[5] / 10 << 4)//sec十位 | (time[5] % 10 << 0);//sec个位 RTC_CFG |= (1 << 2);//打开设置时间功能 } void RTC_Get() { time[0] = (RTC_TSDR >> 20 & 0b1111) * 10 + (RTC_TSDR >> 16 & 0b1111); time[1] = (RTC_TSDR >> 12 & 0b1) * 10 + (RTC_TSDR >> 8 & 0b1111); time[2] = (RTC_TSDR >> 4 & 0b1111) * 10 + (RTC_TSDR >> 0 & 0b1111); time[3] = (RTC_TSTR >> 20 & 0b111) * 10 + (RTC_TSTR >> 16 & 0b1111); time[4] = (RTC_TSTR >> 12 & 0b111) * 10 + (RTC_TSTR >> 8 & 0b1111); time[5] = (RTC_TSTR >> 4 & 0b111) * 10 + (RTC_TSTR >> 0 & 0b1111); } ================================================ FILE: driver/si473x.c ================================================ #include "si473x.h" #include "../settings.h" #include "../audio.h" #include "eeprom.h" #include "gpio.h" #include "i2c.h" #include "system.h" #include "systick.h" static const uint8_t SI47XX_I2C_ADDR = 0x22; #define RST_HIGH GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080) #define RST_LOW GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080) RSQStatus rsqStatus; SsbMode currentSsbMode; uint16_t divider = 1000; SI47XX_MODE si4732mode = SI47XX_FM; uint16_t siCurrentFreq = 10210; void SI47XX_ReadBuffer(uint8_t *buf, uint8_t size) { I2C_Start(); I2C_Write(SI47XX_I2C_ADDR + 1); I2C_ReadBuffer(buf, size); I2C_Stop(); } void SI47XX_WriteBuffer(uint8_t *buf, uint8_t size) { I2C_Start(); I2C_Write(SI47XX_I2C_ADDR); I2C_WriteBuffer(buf, size); I2C_Stop(); } bool SI47XX_IsSSB() { return si4732mode == SI47XX_USB || si4732mode == SI47XX_LSB; } void waitToSend() { uint8_t tmp = 0; SI47XX_ReadBuffer((uint8_t *)&tmp, 1); while (!(tmp & STATUS_CTS)) { SYSTICK_DelayUs(1); SI47XX_ReadBuffer((uint8_t *)&tmp, 1); } } void sendProperty(uint16_t prop, uint16_t parameter) { waitToSend(); uint8_t tmp[6] = {CMD_SET_PROPERTY, 0, prop >> 8, prop & 0xff, parameter >> 8, parameter & 0xff}; SI47XX_WriteBuffer(tmp, 6); SYSTEM_DelayMs(10); // irrespective of CTS coming up earlier than that } uint16_t getProperty(uint16_t prop, bool *valid) { uint8_t response[4] = {0}; uint8_t tmp[4] = {CMD_GET_PROPERTY, 0, prop >> 8, prop & 0xff}; waitToSend(); SI47XX_WriteBuffer(tmp, 4); SI47XX_ReadBuffer(response, 4); if (valid) { *valid = !(response[0] & STATUS_ERR); } return (response[2] << 8) | response[3]; } void RSQ_GET() { uint8_t cmd[2] = {CMD_FM_RSQ_STATUS, 0x01}; if (si4732mode != SI47XX_FM) { cmd[0] = CMD_AM_RSQ_STATUS; } waitToSend(); SI47XX_WriteBuffer(cmd, 2); SI47XX_ReadBuffer(rsqStatus.raw, si4732mode == SI47XX_FM ? 8 : 6); } void setVolume(uint8_t volume) { if (volume < 0) volume = 0; if (volume > 63) volume = 63; sendProperty(PROP_RX_VOLUME, volume); } void setAvcAmMaxGain(uint8_t gain) { if (gain < 12 || gain > 90) return; sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, gain * 340); } void enableRDS(void) { // Enable and configure RDS reception if (si4732mode == SI47XX_FM) { sendProperty(PROP_FM_RDS_INT_SOURCE, FLG_RDSRECV); // Set the FIFO high-watermark to 12 RDS blocks, which is safe even for // old chips, yet large enough to improve performance. sendProperty(PROP_FM_RDS_INT_FIFO_COUNT, 12); sendProperty( PROP_FM_RDS_CONFIG, ((FLG_BLETHA_35 | FLG_BLETHB_35 | FLG_BLETHC_35 | FLG_BLETHD_35) << 8) | FLG_RDSEN); }; } void SI47XX_SetAutomaticGainControl(uint8_t AGCDIS, uint8_t AGCIDX) { SI47XX_AgcOverrride agc; uint8_t cmd; if (si4732mode == SI47XX_FM) cmd = CMD_FM_AGC_OVERRIDE; else cmd = CMD_AM_AGC_OVERRIDE; // both for AM and SSB agc.arg.DUMMY = 0; // ARG1: bits 7:1 Always write to 0; agc.arg.AGCDIS = AGCDIS; agc.arg.AGCIDX = AGCIDX; waitToSend(); uint8_t cmd2[] = {cmd, agc.raw[0], agc.raw[1]}; SI47XX_WriteBuffer(cmd2, 3); } bool FreqCheck(uint32_t f) { if (si4732mode == SI47XX_FM) { if (f < 6400000 || f > 10800000) { return false; } } else { if (f < 15000 || f > 3000000) { return false; } } return true; } uint32_t Read_FreqSaved() { uint32_t tmpF; EEPROM_ReadBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t *) &tmpF, 4); if (!FreqCheck(tmpF)) { if (si4732mode == SI47XX_FM) { tmpF=10210000; } else if (si4732mode == SI47XX_AM) { tmpF=720000; } else { tmpF= 711300; } } return tmpF; } void SI47XX_PowerUp() { RST_HIGH; uint8_t cmd[3] = {CMD_POWER_UP, FLG_XOSCEN | FUNC_FM, OUT_ANALOG}; if (si4732mode == SI47XX_AM) { cmd[1] = FLG_XOSCEN | FUNC_AM; } waitToSend(); SI47XX_WriteBuffer(cmd, 3); SYSTEM_DelayMs(500); AUDIO_AudioPathOn(); setVolume(63); if (si4732mode == SI47XX_FM) { enableRDS(); } else if (si4732mode == SI47XX_AM) { SI47XX_SetAutomaticGainControl(1, 0); sendProperty(PROP_AM_SOFT_MUTE_MAX_ATTENUATION, 0); sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, 0x7800); SI47XX_SetSeekAmLimits(1800, 30000); } SI47XX_SetFreq( Read_FreqSaved()/divider); } void SI47XX_SsbSetup(SI47XX_SsbFilterBW AUDIOBW, uint8_t SBCUTFLT, uint8_t AVC_DIVIDER, uint8_t AVCEN, uint8_t SMUTESEL, uint8_t DSP_AFCDIS) { currentSsbMode.param.SBCUTFLT = SBCUTFLT; currentSsbMode.param.AVC_DIVIDER = AVC_DIVIDER; currentSsbMode.param.AVCEN = AVCEN; currentSsbMode.param.SMUTESEL = SMUTESEL; currentSsbMode.param.DSP_AFCDIS = DSP_AFCDIS; currentSsbMode.param.AUDIOBW = AUDIOBW; sendProperty(PROP_SSB_MODE, (currentSsbMode.raw[1] << 8) | currentSsbMode.raw[0]); } bool SI47XX_downloadPatch() { uint8_t buf[248]; // const uint8_t PAGE_SIZE = SETTINGS_GetPageSize(); const uint32_t EEPROM_SIZE = 262144; const uint32_t PATCH_START = EEPROM_SIZE - PATCH_SIZE; for (uint16_t offset = 0; offset < PATCH_SIZE; offset += 248) { uint32_t eepromN = PATCH_SIZE - offset > 248 ? 248 : PATCH_SIZE - offset; EEPROM_ReadBuffer(PATCH_START + offset, buf, eepromN); for (uint8_t i = 0; i < eepromN; i += 8) { waitToSend(); SI47XX_WriteBuffer(buf + i, 8); } } return true; } void SI47XX_PatchPowerUp() { RST_HIGH; uint8_t cmd[3] = {CMD_POWER_UP, 0b00110001, OUT_ANALOG}; waitToSend(); SI47XX_WriteBuffer(cmd, 3); SYSTEM_DelayMs(550); SI47XX_downloadPatch(); SI47XX_SsbSetup(2, 1, 0, 1, 0, 1); AUDIO_AudioPathOn(); setVolume(63); SI47XX_SetFreq(Read_FreqSaved()/divider); sendProperty(PROP_SSB_SOFT_MUTE_MAX_ATTENUATION, 0); sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, 0x7800); } void SI47XX_SetSsbBandwidth(SI47XX_SsbFilterBW bw) { SI47XX_SsbSetup(bw, 1, 0, 1, 0, 1); } void SI47XX_Seek(bool up, bool wrap) { uint8_t seekOpt = (up ? FLG_SEEKUP : 0) | (wrap ? FLG_WRAP : 0); uint8_t cmd[6] = {CMD_FM_SEEK_START, seekOpt, 0x00, 0x00, 0x00, 0x00}; if (si4732mode == SI47XX_AM) { cmd[0] = CMD_AM_SEEK_START; cmd[5] = (siCurrentFreq > 1800) ? 1 : 0; } waitToSend(); SI47XX_WriteBuffer(cmd, si4732mode == SI47XX_FM ? 2 : 6); } uint16_t SI47XX_getFrequency(bool *valid) { uint8_t response[4] = {0}; uint8_t cmd[1] = {CMD_FM_TUNE_STATUS}; if (si4732mode == SI47XX_AM) { cmd[0] = CMD_AM_TUNE_STATUS; } waitToSend(); SI47XX_WriteBuffer(cmd, 1); SI47XX_ReadBuffer(response, 4); if (valid) { *valid = (response[1] & STATUS_VALID); } return (response[2] << 8) | response[3]; } void SI47XX_PowerDown() { AUDIO_AudioPathOff(); uint8_t cmd[1] = {CMD_POWER_DOWN}; waitToSend(); SI47XX_WriteBuffer(cmd, 1); SYSTICK_Delay250ns(10); RST_LOW; } void SI47XX_SwitchMode(SI47XX_MODE mode) { if (si4732mode != mode) { bool wasSSB = SI47XX_IsSSB(); si4732mode = mode; if (mode == SI47XX_USB || mode == SI47XX_LSB) { if (!wasSSB) { SI47XX_PowerDown(); SI47XX_PatchPowerUp(); } } else { SI47XX_PowerDown(); SI47XX_PowerUp(); } } } void SI47XX_SetFreq(uint16_t freq) { uint8_t hb = (freq >> 8) & 0xFF; uint8_t lb = freq & 0xFF; bool isSW = freq > 1800; uint8_t size = 4; uint8_t cmd[6] = {CMD_FM_TUNE_FREQ, 0x00, hb, lb, 0, 0}; if (si4732mode == SI47XX_FM || si4732mode == SI47XX_AM) { cmd[1] = 0x01; // FAST } if (si4732mode == SI47XX_AM) { cmd[0] = CMD_AM_TUNE_FREQ; size = 5; } if (SI47XX_IsSSB()) { cmd[0] = CMD_AM_TUNE_FREQ; // same as AM 0x40 if (si4732mode == SI47XX_USB) { cmd[1] = 0b10000000; } else { cmd[1] = 0b01000000; } size = 6; } if (si4732mode != SI47XX_FM) { if (isSW) { cmd[5] = 1; } } waitToSend(); SI47XX_WriteBuffer(cmd, size); siCurrentFreq = freq; SYSTEM_DelayMs(30); // RSQ_GET(); } void SI47XX_SetAMFrontendAGC(uint8_t minGainIdx, uint8_t attnBackup) { sendProperty(PROP_AM_FRONTEND_AGC_CONTROL, minGainIdx << 8 | attnBackup); } void SI47XX_SetBandwidth(SI47XX_FilterBW AMCHFLT, bool AMPLFLT) { SI47XX_BW_Config cfg = {0}; cfg.param.AMCHFLT = AMCHFLT; cfg.param.AMPLFLT = AMPLFLT; sendProperty(PROP_AM_CHANNEL_FILTER, (cfg.raw[1] << 8) | cfg.raw[0]); } void SI47XX_ReadRDS(uint8_t buf[13]) { uint8_t cmd[2] = {CMD_FM_RDS_STATUS, RDS_STATUS_ARG1_CLEAR_INT}; waitToSend(); SI47XX_WriteBuffer(cmd, 2); SI47XX_ReadBuffer(buf, 13); } void SI47XX_SetSeekFmLimits(uint16_t bottom, uint16_t top) { sendProperty(PROP_FM_SEEK_BAND_BOTTOM, bottom); sendProperty(PROP_FM_SEEK_BAND_TOP, top); } void SI47XX_SetSeekAmLimits(uint16_t bottom, uint16_t top) { sendProperty(PROP_AM_SEEK_BAND_BOTTOM, bottom); sendProperty(PROP_AM_SEEK_BAND_TOP, top); } void SI47XX_SetSeekFmSpacing(uint16_t spacing) { sendProperty(PROP_FM_SEEK_FREQ_SPACING, spacing); } void SI47XX_SetSeekAmSpacing(uint16_t spacing) { sendProperty(PROP_AM_SEEK_FREQ_SPACING, spacing); } void SI47XX_SetSeekFmRssiThreshold(uint16_t value) { sendProperty(PROP_FM_SEEK_TUNE_RSSI_THRESHOLD, value); } void SI47XX_SetSeekAmRssiThreshold(uint16_t value) { sendProperty(PROP_AM_SEEK_TUNE_RSSI_THRESHOLD, value); } void SI47XX_SetBFO(int16_t bfo) { sendProperty(PROP_SSB_BFO, bfo); } ================================================ FILE: driver/si473x.h ================================================ #ifndef SI473X_H #define SI473X_H #include #include typedef enum { SI47XX_FM, SI47XX_AM, SI47XX_LSB, SI47XX_USB, SI47XX_CW, } SI47XX_MODE; typedef enum { SI47XX_BW_6_kHz, SI47XX_BW_4_kHz, SI47XX_BW_3_kHz, SI47XX_BW_2_kHz, SI47XX_BW_1_kHz, SI47XX_BW_1_8_kHz, SI47XX_BW_2_5_kHz, } SI47XX_FilterBW; typedef enum { SI47XX_SSB_BW_1_2_kHz, SI47XX_SSB_BW_2_2_kHz, SI47XX_SSB_BW_3_kHz, SI47XX_SSB_BW_4_kHz, SI47XX_SSB_BW_0_5_kHz, SI47XX_SSB_BW_1_0_kHz, } SI47XX_SsbFilterBW; typedef enum { CMD_POWER_UP = 0x01, CMD_GET_REV = 0x10, CMD_POWER_DOWN = 0x11, CMD_SET_PROPERTY = 0x12, CMD_GET_PROPERTY = 0x13, CMD_GET_INT_STATUS = 0x14, CMD_PATCH_ARGS = 0x15, CMD_PATCH_DATA = 0x16, CMD_FM_TUNE_FREQ = 0x20, CMD_FM_SEEK_START = 0x21, CMD_FM_TUNE_STATUS = 0x22, CMD_FM_RSQ_STATUS = 0x23, CMD_FM_RDS_STATUS = 0x24, CMD_FM_AGC_STATUS = 0x27, CMD_FM_AGC_OVERRIDE = 0x28, CMD_TX_TUNE_FREQ = 0x30, CMD_TX_TUNE_POWER = 0x31, CMD_TX_TUNE_MEASURE = 0x32, CMD_TX_TUNE_STATUS = 0x33, CMD_TX_ASQ_STATUS = 0x34, CMD_TX_RDS_BUF = 0x35, CMD_TX_RDS_PS = 0x36, CMD_AM_TUNE_FREQ = 0x40, CMD_AM_SEEK_START = 0x41, CMD_AM_TUNE_STATUS = 0x42, CMD_AM_RSQ_STATUS = 0x43, CMD_AM_AGC_STATUS = 0x47, CMD_AM_AGC_OVERRIDE = 0x48, CMD_WB_TUNE_FREQ = 0x50, CMD_WB_TUNE_STATUS = 0x52, CMD_WB_RSQ_STATUS = 0x53, CMD_WB_SAME_STATUS = 0x54, CMD_WB_ASQ_STATUS = 0x55, CMD_WB_AGC_STATUS = 0x57, CMD_WB_AGC_OVERRIDE = 0x58, CMD_AUX_ASRC_START = 0x61, CMD_AUX_ASQ_STATUS = 0x65, CMD_GPIO_CTL = 0x80, CMD_GPIO_SET = 0x81, } SI47XX_Commands; typedef enum { FLG_CTSIEN = 0x80, FLG_GPO2IEN = 0x40, FLG_PATCH = 0x20, FLG_XOSCEN = 0x10, FLG_FREEZE = 0x02, FLG_FAST = 0x01, FLG_SEEKUP = 0x08, FLG_WRAP = 0x04, FLG_CANCEL = 0x02, FLG_INTACK = 0x01, FLG_STATUSONLY = 0x04, FLG_MTFIFO = 0x02, FLG_GPO3OEN = 0x08, FLG_GPO2OEN = 0x04, FLG_GPO1OEN = 0x02, FLG_GPO3LEVEL = 0x08, FLG_GPO2LEVEL = 0x04, FLG_GPO1LEVEL = 0x02, FLG_BLETHA_0 = 0x00, FLG_BLETHA_12 = 0x40, FLG_BLETHA_35 = 0x80, FLG_BLETHA_U = FLG_BLETHA_12 | FLG_BLETHA_35, FLG_BLETHB_0 = FLG_BLETHA_0, FLG_BLETHB_12 = 0x10, FLG_BLETHB_35 = 0x20, FLG_BLETHB_U = FLG_BLETHB_12 | FLG_BLETHB_35, FLG_BLETHC_0 = FLG_BLETHA_0, FLG_BLETHC_12 = 0x04, FLG_BLETHC_35 = 0x08, FLG_BLETHC_U = FLG_BLETHC_12 | FLG_BLETHC_35, FLG_BLETHD_0 = FLG_BLETHA_0, FLG_BLETHD_12 = 0x01, FLG_BLETHD_35 = 0x02, FLG_BLETHD_U = FLG_BLETHD_12 | FLG_BLETHD_35, FLG_RDSEN = 0x01, FLG_DEEMPH_NONE = 0x00, FLG_DEEMPH_50 = 0x01, FLG_DEEMPH_75 = 0x02, FLG_RSQREP = 0x08, FLG_RDSREP = 0x04, FLG_STCREP = 0x01, FLG_ERRIEN = 0x40, FLG_RSQIEN = 0x08, FLG_RDSIEN = 0x04, FLG_STCIEN = 0x01, FLG_RDSNEWBLOCKB = 0x20, FLG_RDSNEWBLOCKA = 0x10, FLG_RDSSYNCFOUND = 0x04, FLG_RDSSYNCLOST = 0x02, FLG_RDSRECV = 0x01, FLG_GRPLOST = 0x04, FLG_RDSSYNC = 0x01, FLG_AMPLFLT = 0x01, FLG_AMCHFLT_6KHZ = 0x00, FLG_AMCHFLT_4KHZ = 0x01, FLG_AMCHFLT_3KHZ = 0x02, FLG_AMCHFLT_2KHZ = 0x03, FLG_AMCHFLT_1KHZ = 0x04, FLG_AMCHFLT_1KHZ8 = 0x05, FLG_AMCHFLT_2KHZ5 = 0x06, } SI47XX_Flags; // Define Si4735 Function modes typedef enum { FUNC_FM = 0x00, FUNC_AM = 0x01, FUNC_VER = 0x0F, } SI47XX_FunctionModes; // Define Si4735 Output modes typedef enum { OUT_RDS = 0x00, // RDS only OUT_ANALOG = 0x05, OUT_DIGITAL1 = 0x0B, // DCLK, LOUT/DFS, ROUT/DIO OUT_DIGITAL2 = 0xB0, // DCLK, DFS, DIO OUT_BOTH = OUT_ANALOG | OUT_DIGITAL2, } SI47XX_OutputModes; typedef union { struct { uint8_t AUDIOBW: 4; //!< 0 = 1.2kHz (default); 1=2.2kHz; 2=3kHz; 3=4kHz; //!< 4=500Hz; 5=1kHz uint8_t SBCUTFLT: 4; //!< SSB side band cutoff filter for band passand low //!< pass filter uint8_t AVC_DIVIDER: 4; //!< set 0 for SSB mode; set 3 for SYNC mode; uint8_t AVCEN: 1; //!< SSB Automatic Volume Control (AVC) enable; //!< 0=disable; 1=enable (default); uint8_t SMUTESEL: 1; //!< SSB Soft-mute Based on RSSI or SNR uint8_t DUMMY1: 1; //!< Always write 0; uint8_t DSP_AFCDIS: 1; //!< 0=SYNC MODE, AFC enable; 1=SSB MODE, AFC disable. } param; uint8_t raw[2]; } SsbMode; // Define Si47xx Status flag masks (bits the chip fed us) typedef enum { STATUS_CTS = 0x80, STATUS_ERR = 0x40, STATUS_RSQINT = 0x08, STATUS_RDSINT = 0x04, STATUS_ASQINT = 0x02, STATUS_STCINT = 0x01, STATUS_BLTF = 0x80, STATUS_AFCRL = 0x02, STATUS_VALID = 0x01, STATUS_BLENDINT = 0x80, STATUS_MULTHINT = 0x20, STATUS_MULTLINT = 0x10, STATUS_SNRHINT = 0x08, STATUS_SNRLINT = 0x04, STATUS_RSSIHINT = 0x02, STATUS_RSSILINT = 0x01, STATUS_SMUTE = 0x08, STATUS_PILOT = 0x80, STATUS_OVERMOD = 0x04, STATUS_IALH = 0x02, STATUS_IALL = 0x01, } SI47XX_StatusFlagMasks; // Define Si47xx Property codes typedef enum { PROP_GPO_IEN = (uint16_t) 0x0001, PROP_DIGITAL_INPUT_FORMAT = 0x0101, PROP_DIGITAL_OUTPUT_FORMAT = 0x0102, PROP_DIGITAL_INPUT_SAMPLE_RATE = 0x0103, PROP_DIGITAL_OUTPUT_SAMPLE_RATE = 0x0104, PROP_REFCLK_FREQ = 0x0201, PROP_REFCLK_PRESCALE = 0x0202, PROP_FM_DEEMPHASIS = 0x1100, PROP_FM_CHANNEL_FILTER = 0x1102, PROP_FM_BLEND_STEREO_THRESHOLD = 0x1105, PROP_FM_BLEND_MONO_THRESHOLD = 0x1106, PROP_FM_ANTENNA_INPUT = 0x1107, PROP_FM_MAX_TUNE_ERROR = 0x1108, PROP_FM_RSQ_INT_SOURCE = 0x1200, PROP_FM_RSQ_SNR_HI_THRESHOLD = 0x1201, PROP_FM_RSQ_SNR_LO_THRESHOLD = 0x1202, PROP_FM_RSQ_RSSI_HI_THRESHOLD = 0x1203, PROP_FM_RSQ_RSSI_LO_THRESHOLD = 0x1204, PROP_FM_RSQ_MULTIPATH_HI_THRESHOLD = 0x1205, PROP_FM_RSQ_MULTIPATH_LO_THRESHOLD = 0x1206, PROP_FM_RSQ_BLEND_THRESHOLD = 0x1207, PROP_FM_SOFT_MUTE_RATE = 0x1300, PROP_FM_SOFT_MUTE_SLOPE = 0x1301, PROP_FM_SOFT_MUTE_MAX_ATTENUATION = 0x1302, PROP_FM_SOFT_MUTE_SNR_THRESHOLD = 0x1303, PROP_FM_SOFT_MUTE_RELEASE_RATE = 0x1304, PROP_FM_SOFT_MUTE_ATTACK_RATE = 0x1305, PROP_FM_SEEK_BAND_BOTTOM = 0x1400, PROP_FM_SEEK_BAND_TOP = 0x1401, PROP_FM_SEEK_FREQ_SPACING = 0x1402, PROP_FM_SEEK_TUNE_SNR_THRESHOLD = 0x1403, PROP_FM_SEEK_TUNE_RSSI_THRESHOLD = 0x1404, PROP_FM_RDS_INT_SOURCE = 0x1500, PROP_FM_RDS_INT_FIFO_COUNT = 0x1501, PROP_FM_RDS_CONFIG = 0x1502, PROP_FM_RDS_CONFIDENCE = 0x1503, PROP_FM_AGC_ATTACK_RATE = 0x1700, PROP_FM_AGC_RELEASE_RATE = 0x1701, PROP_FM_BLEND_RSSI_STEREO_THRESHOLD = 0x1800, PROP_FM_BLEND_RSSI_MONO_THRESHOLD = 0x1801, PROP_FM_BLEND_RSSI_ATTACK_RATE = 0x1802, PROP_FM_BLEND_RSSI_RELEASE_RATE = 0x1803, PROP_FM_BLEND_SNR_STEREO_THRESHOLD = 0x1804, PROP_FM_BLEND_SNR_MONO_THRESHOLD = 0x1805, PROP_FM_BLEND_SNR_ATTACK_RATE = 0x1806, PROP_FM_BLEND_SNR_RELEASE_RATE = 0x1807, PROP_FM_BLEND_MULTIPATH_STEREO_THRESHOLD = 0x1808, PROP_FM_BLEND_MULTIPATH_MONO_THRESHOLD = 0x1809, PROP_FM_BLEND_MULTIPATH_ATTACK_RATE = 0x180A, PROP_FM_BLEND_MULTIPATH_RELEASE_RATE = 0x180B, PROP_FM_BLEND_MAX_STEREO_SEPARATION = 0x180C, PROP_FM_NB_DETECT_THRESHOLD = 0x1900, PROP_FM_NB_INTERVAL = 0x1901, PROP_FM_NB_RATE = 0x1902, PROP_FM_NB_IIR_FILTER = 0x1903, PROP_FM_NB_DELAY = 0x1904, PROP_FM_HICUT_SNR_HIGH_THRESHOLD = 0x1A00, PROP_FM_HICUT_SNR_LOW_THRESHOLD = 0x1A01, PROP_FM_HICUT_ATTACK_RATE = 0x1A02, PROP_FM_HICUT_RELEASE_RATE = 0x1A03, PROP_FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD = 0x1A04, PROP_FM_HICUT_MULTIPATH_END_THRESHOLD = 0x1A05, PROP_FM_HICUT_CUTOFF_FREQUENCY = 0x1A06, PROP_TX_COMPONENT_ENABLE = 0x2100, PROP_TX_AUDIO_DEVIATION = 0x2101, PROP_TX_PILOT_DEVIATION = 0x2102, PROP_TX_RDS_DEVIATION = 0x2103, PROP_TX_LINE_INPUT_LEVEL = 0x2104, PROP_TX_LINE_INPUT_MUTE = 0x2105, PROP_TX_PREEMPHASIS = 0x2106, PROP_TX_PILOT_FREQUENCY = 0x2107, PROP_TX_ACOMP_ENABLE = 0x2200, PROP_TX_ACOMP_THRESHOLD = 0x2201, PROP_TX_ACOMP_ATTACK_TIME = 0x2202, PROP_TX_ACOMP_RELEASE_TIME = 0x2203, PROP_TX_ACOMP_GAIN = 0x2204, PROP_TX_LIMITER_RELEASE_TIME = 0x2205, PROP_TX_ASQ_INTERRUPT_SOURCE = 0x2300, PROP_TX_ASQ_LEVEL_LOW = 0x2301, PROP_TX_ASQ_DURATION_LOW = 0x2302, PROP_TX_ASQ_LEVEL_HIGH = 0x2303, PROP_TX_ASQ_DURATION_HIGH = 0x2304, PROP_TX_RDS_INTERRUPT_SOURCE = 0x2C00, PROP_TX_RDS_PI = 0x2C01, PROP_TX_RDS_PS_MIX = 0x2C02, PROP_TX_RDS_PS_MISC = 0x2C03, PROP_TX_RDS_PS_REPEAT_COUNT = 0x2C04, PROP_TX_RDS_PS_MESSAGE_COUNT = 0x2C05, PROP_TX_RDS_PS_AF = 0x2C06, PROP_TX_RDS_FIFO_SIZE = 0x2C07, PROP_AM_DEEMPHASIS = 0x3100, PROP_AM_CHANNEL_FILTER = 0x3102, PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN = 0x3103, PROP_AM_MODE_AFC_SW_PULL_IN_RANGE = 0x3104, PROP_AM_MODE_AFC_SW_LOCK_IN_RANGE = 0x3105, PROP_AM_RSQ_INTERRUPTS = 0x3200, PROP_AM_RSQ_SNR_HIGH_THRESHOLD = 0x3201, PROP_AM_RSQ_SNR_LOW_THRESHOLD = 0x3202, PROP_AM_RSQ_RSSI_HIGH_THRESHOLD = 0x3203, PROP_AM_RSQ_RSSI_LOW_THRESHOLD = 0x3204, PROP_AM_SOFT_MUTE_RATE = 0x3300, PROP_AM_SOFT_MUTE_SLOPE = 0x3301, PROP_AM_SOFT_MUTE_MAX_ATTENUATION = 0x3302, PROP_AM_SOFT_MUTE_SNR_THRESHOLD = 0x3303, PROP_AM_SOFT_MUTE_RELEASE_RATE = 0x3304, PROP_AM_SOFT_MUTE_ATTACK_RATE = 0x3305, PROP_AM_SEEK_BAND_BOTTOM = 0x3400, PROP_AM_SEEK_BAND_TOP = 0x3401, PROP_AM_SEEK_FREQ_SPACING = 0x3402, PROP_AM_SEEK_TUNE_SNR_THRESHOLD = 0x3403, PROP_AM_SEEK_TUNE_RSSI_THRESHOLD = 0x3404, PROP_AM_AGC_ATTACK_RATE = 0x3702, PROP_AM_AGC_RELEASE_RATE = 0x3703, PROP_AM_FRONTEND_AGC_CONTROL = 0x3705, PROP_AM_NB_DETECT_THRESHOLD = 0x3900, PROP_AM_NB_INTERVAL = 0x3901, PROP_AM_NB_RATE = 0x3902, PROP_AM_NB_IIR_FILTER = 0x3903, PROP_AM_NB_DELAY = 0x3904, PROP_RX_VOLUME = 0x4000, PROP_RX_HARD_MUTE = 0x4001, PROP_WB_MAX_TUNE_ERROR = 0x5108, PROP_WB_RSQ_INT_SOURCE = 0x5200, PROP_WB_RSQ_SNR_HI_THRESHOLD = 0x5201, PROP_WB_RSQ_SNR_LO_THRESHOLD = 0x5202, PROP_WB_RSQ_RSSI_HI_THRESHOLD = 0x5203, PROP_WB_RSQ_RSSI_LO_THRESHOLD = 0x5204, PROP_WB_VALID_SNR_THRESHOLD = 0x5403, PROP_WB_VALID_RSSI_THRESHOLD = 0x5404, PROP_WB_SAME_INTERRUPT_SOURCE = 0x5500, PROP_WB_ASQ_INTERRUPT_SOURCE = 0x5600, PROP_AUX_ASQ_INTERRUPT_SOURCE = 0x6600, PROP_DEBUG_CONTROL = 0xFF00, PROP_AM_RSQ_INT_SOURCE = 0x3200, PROP_WB_SAME_INT_SOURCE = 0x5500, // Si4707 only PROP_WB_ASQ_INT_SOURCE = 0x5600, PROP_AUX_ASQ_INT_SOURCE = 0x6600, // AUX mode - Si4735-D60 or later PROP_SSB_BFO = 0x0100, // Sets the Beat Frequency Offset (BFO) under SSB mode. PROP_SSB_MODE = 0x0101, // Sets number of properties of the SSB mode. PROP_SSB_RSQ_INTERRUPTS = 0x3200, // Configure Interrupts related to RSQ PROP_SSB_RSQ_SNR_HI_THRESHOLD = 0x3201, // Sets high threshold for SNR interrupt PROP_SSB_RSQ_SNR_LO_THRESHOLD = 0x3202, // Sets low threshold for SNR interrupt PROP_SSB_RSQ_RSSI_HI_THRESHOLD = 0x3203, // Sets high threshold for RSSI interrupt PROP_SSB_RSQ_RSSI_LO_THRESHOLD = 0x3204, // Sets low threshold for RSSI interrupt PROP_SSB_SOFT_MUTE_RATE = 0x3300, // Sets the attack and decay rates when // entering or leaving soft mute PROP_SSB_SOFT_MUTE_MAX_ATTENUATION = 0x3302, // Sets the maximum attenuation during soft mute (db); 0dB to // disable soft mute; defaul 8dB; PROP_SSB_SOFT_MUTE_SNR_THRESHOLD = 0x3303, // Sets SNR threshould to engage soft mute. Defaul 8dB PROP_SSB_RF_AGC_ATTACK_RATE = 0x3700, // Sets the number of milliseconds the high RF peak detector must // be exceeded before decreasing the gain. Defaul 4. PROP_SSB_RF_AGC_RELEASE_RATE = 0x3701, // Sets the number of milliseconds the low RF peak detector must // be exceeded before increasing the gain. Defaul 24. PROP_SSB_IF_AGC_RELEASE_RATE = 0x3703, // Sets the number of milliseconds the low IF peak detector must // not be exceeded before increasing the gain. Default value is // 140 (approximately 40 dB / s). PROP_SSB_IF_AGC_ATTACK_RATE = 0x3702, // Sets the number of milliseconds the high IF peak detector must // be exceeded before decreasing gain. Default value is 4 // (approximately 1400 dB / s). } SI47XX_PropertyCodes; enum { // POWER_UP /* See POWER_UP_AUDIO_OUT constants above for ARG2. */ POWER_UP_ARG1_CTSIEN = 0b10000000, // CTS interrupt enable POWER_UP_ARG1_GPO2OEN = 0b01000000, // GPO2/INT output enable POWER_UP_ARG1_PATCH = 0b00100000, // Patch enable POWER_UP_ARG1_XOSCEN = 0b00010000, // Enable internal oscillator with external 32768 Hz crystal POWER_UP_ARG1_FUNC_FM = 0x0, // FM receive mode POWER_UP_ARG1_FUNC_AM = 0x1, // AM receive mode POWER_UP_ARG1_FUNC_TX = 0x2, // FM transmit mode - not Si4735 or Si4707 POWER_UP_ARG1_FUNC_WB = 0x3, // WB receive mode - not Si4735 POWER_UP_ARG1_FUNC_AUX = 0x4, // Auxiliary input mode - Si4735-D60 or later POWER_UP_ARG1_FUNC_REV = 0xF, // Query chip's hardware and firmware revisions // FM_TUNE_FREQ, AM_TUNE_FREQ FM_TUNE_FREQ_ARG1_FREEZE = 0b10, TUNE_FREQ_ARG1_FAST = 0b01, // Fast, inaccurate tune // FM_SEEK_START, AM_SEEK_START SEEK_START_ARG1_SEEK_UP = 0b1000, // 1 = Seek up, 0 = Seek down SEEK_START_ARG1_WRAP = 0b0100, // Wrap when band limit reached // FM_TUNE_STATUS, AM_TUNE_STATUS, WB_TUNE_STATUS TUNE_STATUS_ARG1_CANCEL_SEEK = 0b10, // Cancel seek operation - not WB TUNE_STATUS_ARG1_CLEAR_INT = 0b01, // Clear STC interrupt // FM_RSQ_STATUS, AM_RSQ_STATUS, WB_RSQ_STATUS RSQ_STATUS_ARG1_CLEAR_INT = 0b1, // Clear RSQ and related interrupts // FM_RDS_STATUS RDS_STATUS_ARG1_STATUS_ONLY = 0b100, RDS_STATUS_ARG1_CLEAR_FIFO = 0b010, // Clear RDS receive FIFO RDS_STATUS_ARG1_CLEAR_INT = 0b001, // Clear RDS interrupt // WB_SAME_STATUS SAME_STATUS_ARG1_CLEAR_BUFFER = 0b10, // Clear SAME receive buffer SAME_STATUS_ARG1_CLEAR_INT = 0b01, // Clear SAME interrupt // AUX_ASQ_STATUS, WB_ASQ_STATUS ASQ_STATUS_ARG1_CLEAR_INT = 0b1, // Clear ASQ interrupt // FM_AGC_OVERRIDE, AM_AGC_OVERRIDE, WB_AGC_OVERRIDE AGC_OVERRIDE_ARG1_DISABLE_AGC = 0b1, // Disable AGC // GPIO_CTL, GPIO_SET GPIO_ARG1_GPO3 = 0b1000, // GPO3 GPIO_ARG1_GPO2 = 0b0100, // GPO2 GPIO_ARG1_GPO1 = 0b0010, // GPO1 }; // Command responses // Names that begin with FIELD are argument masks. Others are argument // constants. enum { // FM_TUNE_STATUS, AM_TUNE_STATUS, WB_TUNE_STATUS FIELD_TUNE_STATUS_RESP1_SEEK_LIMIT = 0b10000000, // Seek hit search limit - not WB FIELD_TUNE_STATUS_RESP1_AFC_RAILED = 0b10, // AFC railed FIELD_TUNE_STATUS_RESP1_SEEKABLE = 0b01, // Station could currently be found by seek, FIELD_TUNE_STATUS_RESP1_VALID = 0b01, // that is, the station is valid // FM_RSQ_STATUS, AM_RSQ_STATUS, WB_RSQ_STATUS /* See RSQ interrupts above for RESP1. */ FIELD_RSQ_STATUS_RESP2_SOFT_MUTE = 0b1000, // Soft mute active - not WB FIELD_RSQ_STATUS_RESP2_AFC_RAILED = 0b0010, // AFC railed FIELD_RSQ_STATUS_RESP2_SEEKABLE = 0b0001, // Station could currently be found by seek, FIELD_RSQ_STATUS_RESP2_VALID = 0b0001, // that is, the station is valid FIELD_RSQ_STATUS_RESP3_STEREO = 0b10000000, // Stereo pilot found - FM only FIELD_RSQ_STATUS_RESP3_STEREO_BLEND = 0b01111111, // Stereo blend in % (100 = full stereo, 0 = full mono) - FM // only // FM_RDS_STATUS /* See RDS interrupts above for RESP1. */ FIELD_RDS_STATUS_RESP2_FIFO_OVERFLOW = 0b00000100, // FIFO overflowed FIELD_RDS_STATUS_RESP2_SYNC = 0b00000001, // RDS currently synchronized FIELD_RDS_STATUS_RESP12_BLOCK_A = 0b11000000, FIELD_RDS_STATUS_RESP12_BLOCK_B = 0b00110000, FIELD_RDS_STATUS_RESP12_BLOCK_C = 0b00001100, FIELD_RDS_STATUS_RESP12_BLOCK_D = 0b00000011, RDS_STATUS_RESP12_BLOCK_A_NO_ERRORS = 0U << 6, // Block had no errors RDS_STATUS_RESP12_BLOCK_A_2_BIT_ERRORS = 1U << 6, // Block had 1-2 bit errors RDS_STATUS_RESP12_BLOCK_A_5_BIT_ERRORS = 2U << 6, // Block had 3-5 bit errors RDS_STATUS_RESP12_BLOCK_A_UNCORRECTABLE = 3U << 6, // Block was uncorrectable RDS_STATUS_RESP12_BLOCK_B_NO_ERRORS = 0U << 4, RDS_STATUS_RESP12_BLOCK_B_2_BIT_ERRORS = 1U << 4, RDS_STATUS_RESP12_BLOCK_B_5_BIT_ERRORS = 2U << 4, RDS_STATUS_RESP12_BLOCK_B_UNCORRECTABLE = 3U << 4, RDS_STATUS_RESP12_BLOCK_C_NO_ERRORS = 0U << 2, RDS_STATUS_RESP12_BLOCK_C_2_BIT_ERRORS = 1U << 2, RDS_STATUS_RESP12_BLOCK_C_5_BIT_ERRORS = 2U << 2, RDS_STATUS_RESP12_BLOCK_C_UNCORRECTABLE = 3U << 2, RDS_STATUS_RESP12_BLOCK_D_NO_ERRORS = 0U << 0, RDS_STATUS_RESP12_BLOCK_D_2_BIT_ERRORS = 1U << 0, RDS_STATUS_RESP12_BLOCK_D_5_BIT_ERRORS = 2U << 0, RDS_STATUS_RESP12_BLOCK_D_UNCORRECTABLE = 3U << 0, // WB_SAME_STATUS - TODO // AUX_ASQ_STATUS, WB_ASQ_STATUS /* See ASQ interrupts above for RESP1. */ FIELD_AUX_ASQ_STATUS_RESP2_OVERLOAD = 0b1, // Audio input is currently overloading ADC FIELD_WB_ASQ_STATUS_RESP2_ALERT = 0b1, // Alert tone is present // FM_AGC_STATUS, AM_AGC_STATUS, WB_AGC_STATUS FIELD_AGC_STATUS_RESP1_DISABLE_AGC = 0b1, // True if AGC disabled }; typedef union { struct { // status ("RESP0") uint8_t STCINT: 1; uint8_t DUMMY1: 1; uint8_t RDSINT: 1; uint8_t RSQINT: 1; uint8_t DUMMY2: 2; uint8_t ERR: 1; uint8_t CTS: 1; // RESP1 uint8_t RSSIILINT: 1; //!< RSSI Detect Low. uint8_t RSSIHINT: 1; //!< RSSI Detect High. uint8_t SNRLINT: 1; //!< SNR Detect Low. uint8_t SNRHINT: 1; //!< SNR Detect High. uint8_t MULTLINT: 1; //!< Multipath Detect Low uint8_t MULTHINT: 1; //!< Multipath Detect High uint8_t DUMMY3: 1; uint8_t BLENDINT: 1; //!< Blend Detect Interrupt. // RESP2 uint8_t VALID: 1; //!< Valid Channel. uint8_t AFCRL: 1; //!< AFC Rail Indicator. uint8_t DUMMY4: 1; uint8_t SMUTE: 1; //!< Soft Mute Indicator. Indicates soft mute is engaged. uint8_t DUMMY5: 4; // RESP3 uint8_t STBLEND: 7; //!< Indicates amount of stereo blend in% (100 = full //!< stereo, 0 = full mono). uint8_t PILOT: 1; //!< Indicates stereo pilot presence. // RESP4 to RESP7 uint8_t RSSI; //!< RESP4 - Contains the current receive signal strength //!< (0–127 dBμV). uint8_t SNR; //!< RESP5 - Contains the current SNR metric (0–127 dB). uint8_t MULT; //!< RESP6 - Contains the current multipath metric. (0 = no //!< multipath; 100 = full multipath) uint8_t FREQOFF; //!< RESP7 - Signed frequency offset (kHz). } resp; uint8_t raw[8]; } RSQStatus; typedef union { struct { // ARG1 uint8_t AGCDIS: 1; // if set to 1 indicates if the AGC is disabled. 0 = AGC // enabled; 1 = AGC disabled. uint8_t DUMMY: 7; // ARG2 uint8_t AGCIDX; // AGC Index; If AMAGCDIS = 1, this byte forces the AGC gain // index; 0 = Minimum attenuation (max gain) } arg; uint8_t raw[2]; } SI47XX_AgcOverrride; typedef union { struct { uint8_t FAST: 1; //!< ARG1 - FAST Tuning. If set, executes fast and //!< invalidated tune. The tune status will not be accurate. uint8_t FREEZE: 1; //!< Valid only for FM (Must be 0 to AM) uint8_t DUMMY1: 4; //!< Always set 0 uint8_t USBLSB: 2; //!< SSB Upper Side Band (USB) and Lower Side Band (LSB) //!< Selection. 10 = USB is selected; 01 = LSB is selected. uint8_t FREQH; //!< ARG2 - Tune Frequency High byte. uint8_t FREQL; //!< ARG3 - Tune Frequency Low byte. uint8_t ANTCAPH; //!< ARG4 - Antenna Tuning Capacitor High byte. uint8_t ANTCAPL; //!< ARG5 - Antenna Tuning Capacitor Low byte. Note used //!< for FM. } arg; uint8_t raw[5]; } SI47XX_SetFrequency; typedef union { struct { uint8_t AMCHFLT: 4; //!< Selects the bandwidth of the AM channel filter. uint8_t DUMMY1: 4; uint8_t AMPLFLT: 1; //!< Enables the AM Power Line Noise Rejection Filter. uint8_t DUMMY2: 7; } param; uint8_t raw[2]; } SI47XX_BW_Config; // AM_CHANNEL_FILTER void SI47XX_PowerUp(); void SI47XX_PowerDown(); void SI47XX_SetFreq(uint16_t freq); void SI47XX_ReadRDS(uint8_t buf[13]); void SI47XX_SwitchMode(SI47XX_MODE mode); bool SI47XX_IsSSB(); void RSQ_GET(); void SI47XX_SetAutomaticGainControl(uint8_t AGCDIS, uint8_t AGCIDX); void SI47XX_Seek(bool up, bool wrap); uint16_t SI47XX_getFrequency(bool *valid); void SI47XX_SetBandwidth(SI47XX_FilterBW AMCHFLT, bool AMPLFLT); void SI47XX_SetSsbBandwidth(SI47XX_SsbFilterBW bw); void SI47XX_SetSeekFmLimits(uint16_t bottom, uint16_t top); void SI47XX_SetSeekAmLimits(uint16_t bottom, uint16_t top); void SI47XX_SetSeekFmSpacing(uint16_t spacing); void SI47XX_SetSeekAmSpacing(uint16_t spacing); void SI47XX_SetSeekFmRssiThreshold(uint16_t value); void SI47XX_SetSeekAmRssiThreshold(uint16_t value); void SI47XX_SetBFO(int16_t bfo); void SI47XX_SetSsbCapacitor(uint16_t v); uint32_t Read_FreqSaved(); bool FreqCheck(uint32_t f); void setVolume(uint8_t volume) ; extern SI47XX_MODE si4732mode; extern RSQStatus rsqStatus; extern uint16_t siCurrentFreq; extern uint16_t divider; #define PATCH_SIZE 15832 #define SI4732_FREQ_ADD 0X01FE0 #endif /* end of include guard: SI473X_H */ ================================================ FILE: driver/spi.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM0.h" #include "bsp/dp32g030/spi.h" #include "bsp/dp32g030/syscon.h" #include "bsp/dp32g030/irq.h" #include "driver/spi.h" void SPI0_Init(void) { SPI_Config_t Config; SPI_Disable(&SPI0->CR); Config.TXFIFO_EMPTY = 0; Config.RXFIFO_HFULL = 0; Config.RXFIFO_FULL = 0; Config.RXFIFO_OVF = 0; Config.MSTR = 1; Config.SPR = 2; Config.CPHA = 1; Config.CPOL = 1; Config.LSB = 0; Config.TF_CLR = 0; Config.RF_CLR = 0; Config.TXFIFO_HFULL = 0; SPI_Configure(SPI0, &Config); SPI_Enable(&SPI0->CR); } void SPI_WaitForUndocumentedTxFifoStatusBit(void) { uint32_t Timeout; Timeout = 0; do { // Undocumented bit! if ((SPI0->IF & 0x20) == 0) { break; } Timeout++; } while (Timeout <= 100000); } void SPI_Disable(volatile uint32_t *pCR) { *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE; } void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig) { if (pPort == SPI0) { SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE; } else if (pPort == SPI1) { SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE; } SPI_Disable(&pPort->CR); pPort->CR = 0 | (pPort->CR & ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK | SPI_CR_RF_CLR_MASK)) | ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK) | ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK) | ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK) | ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK) | ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK) | ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK) | ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK); pPort->IE = 0 | ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK) | ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK) | ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK) | ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK) | ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK); if (pPort->IE) { if (pPort == SPI0) { NVIC_EnableIRQ((IRQn_Type) DP32_SPI0_IRQn); } else if (pPort == SPI1) { NVIC_EnableIRQ((IRQn_Type) DP32_SPI1_IRQn); } } } void SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster) { if (bIsMaster) { *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE; } else { *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE; } } void SPI_Enable(volatile uint32_t *pCR) { *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE; } ================================================ FILE: driver/spi.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_SPI_H #define DRIVER_SPI_H #include #include typedef struct { uint8_t MSTR; uint8_t SPR; uint8_t CPHA; uint8_t CPOL; uint8_t LSB; uint8_t TF_CLR; uint8_t RF_CLR; uint8_t TXFIFO_HFULL; uint8_t TXFIFO_EMPTY; uint8_t RXFIFO_HFULL; uint8_t RXFIFO_FULL; uint8_t RXFIFO_OVF; } SPI_Config_t; void SPI0_Init(void); void SPI_WaitForUndocumentedTxFifoStatusBit(void); void SPI_Disable(volatile uint32_t *pCR); void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig); void SPI_ToggleMasterMode(volatile uint32_t *pCr, bool bIsMaster); void SPI_Enable(volatile uint32_t *pCR); #endif ================================================ FILE: driver/st7565.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include // NULL #include "bsp/dp32g030/gpio.h" #include "bsp/dp32g030/spi.h" #include "driver/gpio.h" #include "driver/spi.h" #include "driver/st7565.h" #include "driver/system.h" #include "misc.h" uint8_t gStatusLine[LCD_WIDTH]; uint8_t gFrameBuffer[FRAME_LINES][LCD_WIDTH]; static void DrawLine(uint8_t column, uint8_t line, const uint8_t *lineBuffer, unsigned size_defVal) { ST7565_SelectColumnAndLine(column + 4, line); GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0); for (unsigned i = 0; i < size_defVal; i++) { while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {} SPI0->WDR = lineBuffer ? lineBuffer[i] : size_defVal; } SPI_WaitForUndocumentedTxFifoStatusBit(); } void ST7565_DrawLine(const unsigned int Column, const unsigned int Line, const uint8_t *pBitmap, const unsigned int Size) { SPI_ToggleMasterMode(&SPI0->CR, false); DrawLine(Column, Line, pBitmap, Size); SPI_ToggleMasterMode(&SPI0->CR, true); } void ST7565_BlitFullScreen(void) { SPI_ToggleMasterMode(&SPI0->CR, false); ST7565_WriteByte(0x40); for (unsigned line = 0; line < FRAME_LINES; line++) { DrawLine(0, line + 1, gFrameBuffer[line], LCD_WIDTH); } SPI_ToggleMasterMode(&SPI0->CR, true); } void ST7565_BlitLine(unsigned line) { SPI_ToggleMasterMode(&SPI0->CR, false); ST7565_WriteByte(0x40); // start line ? DrawLine(0, line + 1, gFrameBuffer[line], LCD_WIDTH); SPI_ToggleMasterMode(&SPI0->CR, true); } void ST7565_BlitStatusLine(void) { // the top small text line on the display SPI_ToggleMasterMode(&SPI0->CR, false); ST7565_WriteByte(0x40); // start line ? DrawLine(0, 0, gStatusLine, LCD_WIDTH); SPI_ToggleMasterMode(&SPI0->CR, true); } void ST7565_FillScreen(uint8_t value) { SPI_ToggleMasterMode(&SPI0->CR, false); for (unsigned i = 0; i < 8; i++) { DrawLine(0, i, NULL, value); } SPI_ToggleMasterMode(&SPI0->CR, true); } // Software reset const uint8_t ST7565_CMD_SOFTWARE_RESET = 0xE2; // Bias Select // 1 0 1 0 0 0 1 BS // Select bias setting 0=1/9; 1=1/7 (at 1/65 duty) const uint8_t ST7565_CMD_BIAS_SELECT = 0xA2; // COM Direction // 1 1 0 0 MY - - - // Set output direction of COM // MY=1, reverse direction // MY=0, normal direction const uint8_t ST7565_CMD_COM_DIRECTION = 0xC0; // SEG Direction // 1 0 1 0 0 0 0 MX // Set scan direction of SEG // MX=1, reverse direction // MX=0, normal direction const uint8_t ST7565_CMD_SEG_DIRECTION = 0xA0; // Inverse Display // 1 0 1 0 0 1 1 INV // INV =1, inverse display // INV =0, normal display const uint8_t ST7565_CMD_INVERSE_DISPLAY = 0xA6; // All Pixel ON // 1 0 1 0 0 1 0 AP // AP=1, set all pixel ON // AP=0, normal display const uint8_t ST7565_CMD_ALL_PIXEL_ON = 0xA4; // Regulation Ratio // 0 0 1 0 0 RR2 RR1 RR0 // This instruction controls the regulation ratio of the built-in regulator const uint8_t ST7565_CMD_REGULATION_RATIO = 0x20; // Double command!! Set electronic volume (EV) level // Send next: 0 0 EV5 EV4 EV3 EV2 EV1 EV0 contrast 0-63 const uint8_t ST7565_CMD_SET_EV = 0x81; // Control built-in power circuit ON/OFF - 0 0 1 0 1 VB VR VF // VB: Built-in Booster // VR: Built-in Regulator // VF: Built-in Follower const uint8_t ST7565_CMD_POWER_CIRCUIT = 0x28; // Set display start line 0-63 // 0 0 0 1 S5 S4 S3 S2 S1 S0 const uint8_t ST7565_CMD_SET_START_LINE = 0x40; // Display ON/OFF // 0 0 1 0 1 0 1 1 1 D // D=1, display ON // D=0, display OFF const uint8_t ST7565_CMD_DISPLAY_ON_OFF = 0xAE; uint8_t cmds[] = { ST7565_CMD_BIAS_SELECT | 0, // Select bias setting: 1/9 ST7565_CMD_COM_DIRECTION | (0 << 3), // Set output direction of COM: normal ST7565_CMD_SEG_DIRECTION | 1, // Set scan direction of SEG: reverse ST7565_CMD_INVERSE_DISPLAY | 0, // Inverse Display: false ST7565_CMD_ALL_PIXEL_ON | 0, // All Pixel ON: false - normal display ST7565_CMD_REGULATION_RATIO | (4 << 0), // Regulation Ratio 5.0 ST7565_CMD_SET_EV, // Set contrast 31, ST7565_CMD_POWER_CIRCUIT | 0b111, // Built-in power circuit ON/OFF: VB=1 VR=1 VF=1 ST7565_CMD_SET_START_LINE | 0, // Set Start Line: 0 ST7565_CMD_DISPLAY_ON_OFF | 1, // Display ON/OFF: ON }; void ST7565_Init(void) { SPI0_Init(); ST7565_HardwareReset(); SPI_ToggleMasterMode(&SPI0->CR, false); ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET); // software reset SYSTEM_DelayMs(120); for (uint8_t i = 0; i < 8; i++) ST7565_WriteByte(cmds[i]); ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b011); // VB=0 VR=1 VF=1 SYSTEM_DelayMs(1); ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b110); // VB=1 VR=1 VF=0 SYSTEM_DelayMs(1); for (uint8_t i = 0; i < 4; i++) // why 4 times? ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b111); // VB=1 VR=1 VF=1 SYSTEM_DelayMs(40); ST7565_WriteByte(ST7565_CMD_SET_START_LINE | 0); // line 0 ST7565_WriteByte(ST7565_CMD_DISPLAY_ON_OFF | 1); // D=1 SPI_WaitForUndocumentedTxFifoStatusBit(); SPI_ToggleMasterMode(&SPI0->CR, true); ST7565_FillScreen(0x00); } void ST7565_FixInterfGlitch(void) { SPI_ToggleMasterMode(&SPI0->CR, false); for (uint8_t i = 0; i < ARRAY_SIZE(cmds); i++) ST7565_WriteByte(cmds[i]); SPI_WaitForUndocumentedTxFifoStatusBit(); SPI_ToggleMasterMode(&SPI0->CR, true); } void ST7565_HardwareReset(void) { GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES); SYSTEM_DelayMs(1); GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES); SYSTEM_DelayMs(20); GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES); SYSTEM_DelayMs(120); } void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line) { GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0); while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {} SPI0->WDR = Line + 176; while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {} SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10; while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {} SPI0->WDR = ((Column >> 0) & 0x0F); SPI_WaitForUndocumentedTxFifoStatusBit(); } void ST7565_WriteByte(uint8_t Value) { GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0); while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {} SPI0->WDR = Value; } ================================================ FILE: driver/st7565.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_ST7565_H #define DRIVER_ST7565_H #include #include #define LCD_WIDTH 128 #define LCD_HEIGHT 64 #define FRAME_LINES 7 extern uint8_t gStatusLine[LCD_WIDTH]; extern uint8_t gFrameBuffer[FRAME_LINES][LCD_WIDTH]; void ST7565_DrawLine(const unsigned int Column, const unsigned int Line, const uint8_t *pBitmap, const unsigned int Size); void ST7565_BlitFullScreen(void); void ST7565_BlitLine(unsigned line); void ST7565_BlitStatusLine(void); void ST7565_FillScreen(uint8_t Value); void ST7565_Init(void); void ST7565_FixInterfGlitch(void); void ST7565_HardwareReset(void); void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line); void ST7565_WriteByte(uint8_t Value); #endif ================================================ FILE: driver/system.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "../bsp/dp32g030/pmu.h" #include "../bsp/dp32g030/syscon.h" #include "system.h" #include "systick.h" void SYSTEM_DelayMs(uint32_t Delay) { SYSTICK_DelayUs(Delay * 1000); } void SYSTEM_ConfigureClocks(void) { // Set source clock from external crystal PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) | PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ | PMU_SRC_CFG_RCHF_EN_BITS_ENABLE; // Divide by 2 SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2; // Disable division clock gate SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE; } ================================================ FILE: driver/system.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_SYSTEM_H #define DRIVER_SYSTEM_H #include void SYSTEM_DelayMs(uint32_t Delay); void SYSTEM_ConfigureClocks(void); #endif ================================================ FILE: driver/systick.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM0.h" #include "systick.h" #include "../misc.h" // 0x20000324 static uint32_t gTickMultiplier; void SYSTICK_Init(void) { SysTick_Config(480000); gTickMultiplier = 48; } void SYSTICK_DelayUs(uint32_t Delay) { const uint32_t ticks = Delay * gTickMultiplier; uint32_t elapsed_ticks = 0; uint32_t Start = SysTick->LOAD; uint32_t Previous = SysTick->VAL; do { uint32_t Current; do { Current = SysTick->VAL; } while (Current == Previous); uint32_t Delta = ((Current < Previous) ? -Current : Start - Current); elapsed_ticks += Delta + Previous; Previous = Current; } while (elapsed_ticks < ticks); } void SYSTICK_Delay250ns(const uint32_t Delay) { const uint32_t ticks = (Delay * gTickMultiplier) >> 2; uint32_t i = 0; uint32_t Start = SysTick->LOAD; uint32_t Previous = SysTick->VAL; do { uint32_t Delta; uint32_t Current; do Current = SysTick->VAL; while (Current == Previous); Delta = (Current < Previous) ? -Current : Start - Current; i += Delta + Previous; Previous = Current; } while (i < ticks); } ================================================ FILE: driver/systick.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DRIVER_SYSTICK_H #define DRIVER_SYSTICK_H #include void SYSTICK_Init(void); void SYSTICK_DelayUs(uint32_t Delay); void SYSTICK_Delay250ns(const uint32_t Delay); #endif ================================================ FILE: driver/timer.c ================================================ // // Created by RUPC on 2024/1/8. // #include "bsp/dp32g030/timer.h" #include "ARMCM0.h" void TIM0_INIT() { TIMERBASE0_DIV = 4800; TIMERBASE0_LOW_LOAD = 10000; //1s NVIC_SetPriority(Interrupt5_IRQn, 0); /* set Priority for Systick Interrupt */ TIMERBASE0_IF |= 0x01; // 写1清零 清除定时器中断状态 TIMERBASE0_IE |= 0x01; TIMERBASE0_EN |= 0x01; NVIC_EnableIRQ(Interrupt5_IRQn); } uint32_t TIM0_CNT = 0; void TIM0Handler(void); void TIM0Handler(void) { TIM0_CNT++; TIMERBASE0_IF |= 0x01; } ================================================ FILE: driver/uart.c ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "bsp/dp32g030/dma.h" #include "bsp/dp32g030/syscon.h" #include "bsp/dp32g030/uart.h" #include "driver/uart.h" static bool UART_IsLogEnabled; uint8_t UART_DMA_Buffer[256]; void UART_Init(void) { uint32_t Delta; uint32_t Positive; uint32_t Frequency; UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE; Delta = SYSCON_RC_FREQ_DELTA; Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT; Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT; if (Positive) { Frequency += 48000000U; } else { Frequency = 48000000U - Frequency; } UART1->BAUD = Frequency / 39053U; UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE; UART1->RXTO = 4; UART1->FC = 0; UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE; UART1->IE = 0; DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE; DMA_CH0->MSADDR = (uint32_t) (uintptr_t) &UART1->RDR; DMA_CH0->MDADDR = (uint32_t) (uintptr_t) UART_DMA_Buffer; DMA_CH0->MOD = 0 // Source | DMA_CH_MOD_MS_ADDMOD_BITS_NONE | DMA_CH_MOD_MS_SIZE_BITS_8BIT | DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1 // Destination | DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT | DMA_CH_MOD_MD_SIZE_BITS_8BIT | DMA_CH_MOD_MD_SEL_BITS_SRAM; DMA_INTEN = 0; DMA_INTST = 0 | DMA_INTST_CH0_TC_INTST_BITS_SET | DMA_INTST_CH1_TC_INTST_BITS_SET | DMA_INTST_CH2_TC_INTST_BITS_SET | DMA_INTST_CH3_TC_INTST_BITS_SET | DMA_INTST_CH0_THC_INTST_BITS_SET | DMA_INTST_CH1_THC_INTST_BITS_SET | DMA_INTST_CH2_THC_INTST_BITS_SET | DMA_INTST_CH3_THC_INTST_BITS_SET; DMA_CH0->CTR = 0 | DMA_CH_CTR_CH_EN_BITS_ENABLE | ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK) | DMA_CH_CTR_LOOP_BITS_ENABLE | DMA_CH_CTR_PRI_BITS_MEDIUM; UART1->IF = UART_IF_RXTO_BITS_SET; DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE; UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE; } void UART_Send(const void *pBuffer, uint32_t Size) { const uint8_t *pData = (const uint8_t *) pBuffer; uint32_t i; for (i = 0; i < Size; i++) { UART1->TDR = pData[i]; while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) { } } } void UART_LogSend(const void *pBuffer, uint32_t Size) { if (UART_IsLogEnabled) { UART_Send(pBuffer, Size); } } ================================================ FILE: driver/uart.h ================================================ /* Copyright 2023 Dual Tachyon * https://github.com/DualTachyon * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * */ #ifndef DRIVER_UART_H #define DRIVER_UART_H #include extern uint8_t UART_DMA_Buffer[256]; void UART_Init(void); void UART_Send(const void *pBuffer, uint32_t Size); #endif ================================================ FILE: external/CMSIS_5/.gitattributes ================================================ # Set the default behavior, in case people don't have core.autocrlf set. * text=auto # Explicitly declare text files you want to always be normalized and converted # to native line endings on checkout. *.c text *.h text *.txt text *.xsd text *.pdsc text *.svd text *.bat text # Declare files that will always have CRLF line endings on checkout. *.uvproj text eol=crlf *.uvproj text eol=crlf # Denote all files that are truly binary and should not be modified. *.png binary *.jpg binary # Script files *.py text eol=lf *.sh text eol=lf ================================================ FILE: external/CMSIS_5/.github/fileheader.json ================================================ { "problemMatcher": [ { "owner": "fileheader", "severity": "error", "pattern": [ { "regexp": "^(.*):(\\d+):(.*)$", "file": 1, "line": 2, "message": 3 } ] } ] } ================================================ FILE: external/CMSIS_5/.github/linkchecker.json ================================================ { "problemMatcher": [ { "owner": "fileheader", "severity": "error", "pattern": [ { "regexp": "^(.*):(\\d+);(.*);(.*)$", "file": 1, "line": 2, "message": 4 } ] } ] } ================================================ FILE: external/CMSIS_5/.github/workflows/caller-corevalidation.yml ================================================ name: Caller CoreValidation on: push: branches: [ main ] pull_request: paths: - .github/workflows/caller-corevalidation.yml - CMSIS/Core/**/* - CMSIS/Core_A/**/* - CMSIS/CoreValidation/**/* - Device/ARM/**/* workflow_dispatch: jobs: upload_pr_number: runs-on: ubuntu-latest steps: - name: Save PR number env: PR_NUMBER: ${{ github.event.number }} run: | mkdir -p ./pr echo -n $PR_NUMBER > ./pr/pr_number - uses: actions/upload-artifact@v3 with: name: pr_number path: pr/ ================================================ FILE: external/CMSIS_5/.github/workflows/codeql-analysis.yml ================================================ name: "CodeQL" on: workflow_dispatch: push: branches: [ develop ] paths: - 'CMSIS/Core/**' - 'CMSIS/Core_A/**' - 'CMSIS/CoreValidation/**' - 'Device/ARM/**' pull_request: branches: [ develop ] paths: - '.github/workflows/codeql-analysis.yml' - 'CMSIS/Core/**' - 'CMSIS/Core_A/**' - 'CMSIS/CoreValidation/**' - 'Device/ARM/**' jobs: analyze: name: Analyze runs-on: ubuntu-latest permissions: actions: read contents: read security-events: write env: CMSIS_PACK_ROOT: /tmp/.packs-${{ github.run_id }} steps: - name: Checkout repository uses: actions/checkout@v3 - name: Install build dependencies run: | sudo apt install gcc-arm-none-eabi ninja-build cmake - name: Cache pack folder id: cache-packs uses: actions/cache@v3 with: key: packs-${{ github.run_id }} restore-keys: | packs- path: /tmp/.packs-${{ github.run_id }} - name: Install CMSIS-Toolbox run: | wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh chmod +x cmsis-toolbox.sh sudo ./cmsis-toolbox.sh </dev/null)) EOI echo "/opt/ctools/bin" >> $GITHUB_PATH echo "cpackget : $(which cpackget)" echo "csolution: $(which csolution)" echo "cbuild : $(which cbuild)" - name: Initialize packs folder if: steps.cache-packs.outputs.cache-hit != 'true' run: cpackget init https://www.keil.com/pack/index.pidx - name: Update pack index if: steps.cache-packs.outputs.cache-hit == 'true' run: cpackget update-index - name: Install build.py requirements run: pip install -r requirements.txt working-directory: CMSIS/CoreValidation/Project # Initializes the CodeQL tools for scanning. - name: Initialize CodeQL uses: github/codeql-action/init@v2 with: languages: cpp queries: security-and-quality - name: Build projects working-directory: CMSIS/CoreValidation/Project run: | pip install -r requirements.txt cpackget add -a -f cpacklist.txt python build.py --verbose -c GCC -d "CM[047]*" -d "CM[23]3*" -o low build || echo "Something failed!" - name: Perform CodeQL Analysis uses: github/codeql-action/analyze@v2 ================================================ FILE: external/CMSIS_5/.github/workflows/corevalidation-report.yml ================================================ name: Publish CoreValidation Test Results on: workflow_run: workflows: ["CoreValidation"] branches-ignore: ["develop"] types: - completed jobs: publish-test-results: name: Publish CoreValidation Test Results runs-on: ubuntu-latest permissions: contents: read issues: read checks: write pull-requests: write if: github.event.workflow_run.conclusion != 'skipped' steps: - name: Download test results env: GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}} run: | mkdir -p artifacts && cd artifacts artifacts_url=${{ github.event.workflow_run.artifacts_url }} gh api "$artifacts_url" -q '.artifacts[] | select(.name=="tests" or .name=="EventFile") | [.name, .archive_download_url] | @tsv' | \ while read artifact; do IFS=$'\t' read name url <<< "$artifact" gh api $url > "$name.zip" unzip -d "$name" "$name.zip" done - name: Publish Test Results uses: EnricoMi/publish-unit-test-result-action@v2 with: commit: ${{ github.event.workflow_run.head_sha }} event_file: artifacts/EventFile/event.json report_individual_runs: true event_name: ${{ github.event.workflow_run.event }} junit_files: "artifacts/**/*.junit" ================================================ FILE: external/CMSIS_5/.github/workflows/corevalidation.yml ================================================ # This workflow is triggered whenever "Caller CoreValidation" workflow is completed (which is called by PR). # This workflow ideally should be triggered also by PR, but forked PR has limited permissions which does not # allow to use `configure-aws-credentials` actions and using secrets. # It will update its status back to the caller PR as "CoreValidation" check name name: CoreValidation on: workflow_run: workflows: - Caller CoreValidation types: - completed # The env variables relate to an ARM AWS account for CMSIS_5 # If you are forking CMSIS_5 repo, please use your own info. env: AWS_ASSUME_ROLE: ${{ secrets.AWS_ASSUME_ROLE }} AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }} AWS_IAM_PROFILE: ${{ secrets.AWS_IAM_PROFILE }} AWS_S3_BUCKET_NAME: ${{ secrets.AWS_S3_BUCKET_NAME }} AWS_SECURITY_GROUP_ID: ${{ secrets.AWS_SECURITY_GROUP_ID }} AWS_SUBNET_ID: ${{ secrets.AWS_SUBNET_ID }} jobs: set_pending_status_to_pr: runs-on: ubuntu-latest steps: - name: Set a pending status to the PR env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | curl --request POST \ --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \ --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ --header 'content-type: application/json' \ --data '{ "state": "pending", "context": "CoreValidation", "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}" }' \ --fail ci_test: runs-on: ubuntu-latest needs: set_pending_status_to_pr permissions: id-token: write contents: read outputs: avhresult: ${{ steps.avh.conclusion }} testbadge: ${{ steps.avh.outputs.badge }} steps: - name: Download workflow artifact uses: dawidd6/action-download-artifact@v2 with: github_token: ${{ secrets.GITHUB_TOKEN }} workflow: caller-corevalidation.yml run_id: ${{ github.event.workflow_run.id }} - name: Read the pr_num file id: pr_num_reader uses: juliangruber/read-file-action@v1.1.6 with: path: ./pr_number/pr_number trim: true - name: Clone this repo uses: actions/checkout@v3 with: fetch-depth: 0 - name: Checkout PR env: GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}} run: | gh pr checkout ${{ steps.pr_num_reader.outputs.content }} - name: Set up Python 3.10 uses: actions/setup-python@v4 with: python-version: '3.10' - name: Install AVH Client for Python run: | pip install git+https://github.com/ARM-software/avhclient.git@v0.1 - uses: ammaraskar/gcc-problem-matcher@master - name: Configure AWS Credentials uses: aws-actions/configure-aws-credentials@v1-node16 with: role-to-assume: ${{ env.AWS_ASSUME_ROLE }} aws-region: ${{ env.AWS_DEFAULT_REGION }} - name: Run tests id: avh run: | avhclient -b aws execute --specfile CMSIS/CoreValidation/Project/avh.yml - name: Archive build results uses: actions/upload-artifact@v3 with: name: builds path: CMSIS/CoreValidation/Project/Core_Validation-*.zip retention-days: 1 if-no-files-found: error if: always() - name: Archive test results uses: actions/upload-artifact@v3 with: name: tests path: CMSIS/CoreValidation/Project/Core_Validation-*.junit retention-days: 1 if-no-files-found: error if: always() - name: Archive event file uses: actions/upload-artifact@v3 with: name: EventFile path: ${{ github.event_path }} set_success_status_to_pr: runs-on: ubuntu-latest needs: ci_test if: ${{ success() }} steps: - name: Set success status to the PR env: GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}} run: | curl --request POST \ --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \ --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ --header 'content-type: application/json' \ --data '{ "state": "success", "context": "CoreValidation", "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}" }' \ --fail set_failure_status_to_pr: runs-on: ubuntu-latest needs: ci_test if: ${{ failure() }} steps: - name: Set failure status to the PR env: GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}} run: | curl --request POST \ --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \ --header "authorization: Bearer ${{ secrets.GITHUB_TOKEN }}" \ --header 'content-type: application/json' \ --data '{ "state": "failure", "context": "CoreValidation", "target_url": "https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}" }' \ --fail ================================================ FILE: external/CMSIS_5/.github/workflows/fileheader.yml ================================================ name: File header on: pull_request: branches: [ develop ] paths: - 'CMSIS/Core/**' - 'CMSIS/Core_A/**' - 'CMSIS/RTOS2/Include/**' - 'CMSIS/RTOS2/Source/**' - 'Device/**' permissions: contents: read pull-requests: write jobs: check: name: Check file header runs-on: ubuntu-latest steps: - name: Calculate depth id: depth run: | echo ::set-output name=GIT_COMMITS::$((${{ github.event.pull_request.commits }} + 1)) - name: Checkout repository uses: actions/checkout@v2 with: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: ${{ steps.depth.outputs.GIT_COMMITS }} - id: files uses: jitterbit/get-changed-files@v1 - name: Check changed files run: | echo "GIT_COMMITS=${{ steps.depth.outputs.GIT_COMMITS }}" echo "::add-matcher::.github/fileheader.json" RC=0 for changed_file in ${{ steps.files.outputs.added_modified }}; do ./CMSIS/Utilities/check_header.sh -v -b HEAD~${{ github.event.pull_request.commits }} ${changed_file} || RC=1 done echo "::remove-matcher owner=fileheader::" exit $RC ================================================ FILE: external/CMSIS_5/.github/workflows/gh-pages.yaml ================================================ name: Publish Documentation on: workflow_dispatch: pull_request: branches: [ develop ] paths: - '.github/workflows/gh-pages.yaml' - 'CMSIS/Utilities/check_links.sh' - 'CMSIS/DoxyGen/**' push: branches: [ develop ] paths: - '.github/workflows/gh-pages.yaml' - 'CMSIS/Utilities/check_links.sh' - 'CMSIS/DoxyGen/**' jobs: docs: name: Build develop documentation runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - uses: actions/setup-node@v1 - name: Install Doxygen 1.8.6 run: | wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb sudo dpkg -i doxygen_1.8.6-2_amd64.deb - name: Install mscgen 0.20 run: | sudo apt-get update sudo apt-get install --no-install-recommends -y mscgen=0.20-12 - name: Install linkchecker run: | sudo pip install LinkChecker - name: Generate doxygen run: CMSIS/DoxyGen/gen_doc.sh - name: Run linkchecker run: | echo "::add-matcher::.github/linkchecker.json" CMSIS/Utilities/check_links.sh CMSIS/Documentation/index.html - name: Upload documentation if: ${{ github.event_name == 'pull_request' }} uses: actions/upload-artifact@v2 with: path: CMSIS/Documentation/** - name: Archive documentation if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }} run: | cd CMSIS/Documentation tar -cvjf /tmp/doc.tbz2 . - uses: actions/checkout@v2 if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }} with: ref: gh-pages - name: Publish documentation if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }} run: | rm -r develop mkdir develop cd develop tar -xvjf /tmp/doc.tbz2 git config user.name github-actions git config user.email github-actions@github.com git add . git commit -m "Update develop documentation" git push ================================================ FILE: external/CMSIS_5/.github/workflows/packdesc.yml ================================================ name: Pack Description on: pull_request: branches: [ develop ] paths: - 'ARM.CMSIS.pdsc' permissions: contents: read pull-requests: write jobs: check: name: Check pack description schema runs-on: ubuntu-latest steps: - name: Install xmllint run: | sudo apt-get update sudo apt-get install libxml2-utils - name: Checkout repository uses: actions/checkout@v2 with: ref: ${{ github.event.pull_request.head.sha }} - name: Run xmllint run: | curl https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/main/schema/PACK.xsd -o CMSIS/Utilities/PACK.xsd echo "::add-matcher::.github/xmllint.json" xmllint --noout --schema "$(realpath -m ./CMSIS/Utilities/PACK.xsd)" "ARM.CMSIS.pdsc" echo "::remove-matcher owner=xmllint::" ================================================ FILE: external/CMSIS_5/.github/workflows/release.yaml ================================================ name: Release Documentation on: release: types: [published] jobs: docs: name: Build release documentation runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - uses: actions/setup-node@v1 - name: Install Doxygen 1.8.6 run: | wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb sudo dpkg -i doxygen_1.8.6-2_amd64.deb - name: Install mscgen 0.20 run: | sudo apt-get update sudo apt-get install --no-install-recommends -y mscgen=0.20-12 - name: Generate doxygen run: CMSIS/DoxyGen/gen_doc.sh - name: Archive documentation run: | cd CMSIS/Documentation tar -cvjf /tmp/doc.tbz2 . - uses: actions/checkout@v2 with: ref: gh-pages - name: Publish documentation run: | RELEASE=$(echo $GITHUB_REF | sed 's/refs\/tags\///') mkdir ${RELEASE} rm latest ln -s ${RELEASE} latest cd ${RELEASE} tar -xvjf /tmp/doc.tbz2 git config user.name github-actions git config user.email github-actions@github.com git add . ../latest git commit -m "Update documentation for release ${RELEASE}" git push ================================================ FILE: external/CMSIS_5/.github/xmllint.json ================================================ { "problemMatcher": [ { "owner": "xmllint", "severity": "error", "pattern": [ { "regexp": "^(.*):(\\d+):(.*)$", "file": 1, "line": 2, "message": 3 } ] } ] } ================================================ FILE: external/CMSIS_5/.gitignore ================================================ *.breadcrumb *.junit **/__pycache__ Local_Release/ CMSIS/Documentation/ CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.* CMSIS/CoreValidation/Project/*.zip CMSIS/CoreValidation/Project/*.junit CMSIS/CoreValidation/Project/Validation.*/ CMSIS/CoreValidation/Project/Bootloader.*/ *.uvguix.* *.uvmpw.uvgui.* *.zip docker/dependenciesFiles CMSIS/RTOS/RTX/LIB/**/*.a CMSIS/RTOS/RTX/LIB/**/*.lib CMSIS/RTOS2/RTX/Library/**/*.a CMSIS/RTOS2/RTX/Library/**/*.lib output .DS_Store internal.cp310-win_amd64.pyd CMSIS/Utilities/Darwin64 CMSIS/Utilities/Linux64 CMSIS/Utilities/Win32 ================================================ FILE: external/CMSIS_5/ARM.CMSIS.pdsc ================================================ CMSIS CMSIS (Common Microcontroller Software Interface Standard) ARM https://www.keil.com/pack/ Active development ... CMSIS-Core(M): 5.7.0 - Added new compiler macros. CMSIS-DSP: Moved into separate pack! CMSIS-NN: Moved into separate pack! CMSIS-RTOS2: 2.2.0 (see revision history for details) - RTX 5.7.0 (see revision history for details) CMSIS-DAP: 2.1.2 (see revision history for details) - Fix DAP_Transfer handling when transfer fails CMSIS-Core(M): 5.6.0 - Arm Cortex-M85 cpu support - Arm China STAR-MC1 cpu support - Updated system_ARMCM55.c CMSIS-DSP: 1.10.0 (see revision history for details) CMSIS-NN: 3.1.0 (see revision history for details) - Support for int16 convolution and fully connected for reference implementation - Support for DSP extension optimization for int16 convolution and fully connected - Support dilation for int8 convolution - Support dilation for int8 depthwise convolution - Support for int16 depthwise conv for reference implementation including dilation - Support for int16 average and max pooling for reference implementation - Support for elementwise add and mul int16 scalar version - Support for softmax int16 scalar version - Support for SVDF with 8 bit state tensor CMSIS-RTOS2: 2.1.3 (unchanged) - RTX 5.5.4 (see revision history for details) CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack) CMSIS-SVD: 1.3.9 (see revision history for details) CMSIS-DAP: 2.1.1 (see revision history for details) - Allow default clock frequency to use fast clock mode Devices - Support for Cortex-M85 Utilities - SVDConv 3.3.42 - PackChk 1.3.95 CMSIS-Core(M): 5.5.0 (see revision history for details) - Updated GCC LinkerDescription, GCC Assembler startup - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC - Changed C-Startup to default Startup. - Updated Armv8-M Assembler startup to use GAS syntax Note: Updating existing projects may need manual user interaction! CMSIS-Core(A): 1.2.1 (see revision history for details) - Bugfixes for Cortex-A32 CMSIS-DAP: 2.1.0 (see revision history for details) - Enhanced DAP_Info - Added extra UART support CMSIS-DSP: 1.9.0 (see revision history for details) - Purged pre-built libs from Git - Enhanced support for f16 datatype - Fixed couple of GCC issues CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0) - Major interface change for functions compatible with TensorFlow Lite for Microcontroller - Added optimization for SVDF kernel - Improved MVE performance for fully Connected and max pool operator - NULL bias support for fully connected operator in non-MVE case(Can affect performance) - Expanded existing unit test suite along with support for FVP - Removed Examples folder CMSIS-RTOS2: - RTX 5.5.3 (see revision history for details) - CVE-2021-27431 vulnerability mitigation. - Enhanced stack overrun checking. - Various bug fixes and improvements. CMSIS-Pack: 1.7.2 (see revision history for details) - Support for Microchip XC32 compiler - Support for Custom Datapath Extension CMSIS-Build: 0.9.0 (beta) - Draft for CMSIS Project description (CPRJ) CMSIS-Core(M): 5.4.0 (see revision history for details) - Cortex-M55 cpu support - Enhanced MVE support for Armv8.1-MML - Fixed device config define checks. - L1 Cache functions for Armv7-M and later CMSIS-Core(A): 1.2.0 (see revision history for details) - Fixed GIC_SetPendingIRQ to use GICD_SGIR - Added missing DSP intrinsics - Reworked assembly intrinsics: volatile, barriers and clobber CMSIS-DSP: 1.8.0 (see revision history for details) - Added new functions and function groups - Added MVE support CMSIS-NN: 1.3.0 (see revision history for details) - Added MVE support - Further optimizations for kernels using DSP extension CMSIS-RTOS2: - RTX 5.5.2 (see revision history for details) CMSIS-Driver: 2.8.0 - Added VIO API 0.1.0 (Preview) - removed volatile from status related typedefs in APIs - enhanced WiFi Interface API with support for polling Socket Receive/Send CMSIS-Pack: 1.6.3 (see revision history for details) - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema. Devices: - ARMCM55 device - ARMv81MML startup code recognizing __MVE_USED macro - Refactored vector table references for all Cortex-M devices - Reworked ARMCM* C-StartUp files. - Include L1 Cache functions in ARMv8MML/ARMv81MML devices Utilities: Attention: Linux binaries moved to Linux64 folder! - SVDConv 3.3.35 - PackChk 1.3.89 CMSIS-Core(M): 5.3.0 (see revision history for details) - Added provisions for compiler-independent C startup code. CMSIS-Core(A): 1.1.4 (see revision history for details) - Fixed __FPU_Enable. CMSIS-DSP: 1.7.0 (see revision history for details) - New Neon versions of f32 functions - Python wrapper - Preliminary cmake build - Compilation flags for FFTs - Changes to arm_math.h CMSIS-NN: 1.2.0 (see revision history for details) - New function for depthwise convolution with asymmetric quantization. - New support functions for requantization. CMSIS-RTOS: - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) CMSIS-RTOS2: - RTX 5.5.1 (see revision history for details) CMSIS-Driver: 2.7.1 - WiFi Interface API 1.0.0 Devices: - Generalized C startup code for all Cortex-M family devices. - Updated Cortex-A default memory regions and MMU configurations - Moved Cortex-A memory and system config files to avoid include path issues The following folders are deprecated - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) CMSIS-Core(M): 5.2.1 (see revision history for details) - Fixed compilation issue in cmsis_armclang_ltm.h The following folders have been removed: - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) The following folders are deprecated - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) CMSIS-Core(M): 5.2.0 (see revision history for details) - Reworked Stack/Heap configuration for ARM startup files. - Added Cortex-M35P device support. - Added generic Armv8.1-M Mainline device support. CMSIS-Core(A): 1.1.3 (see revision history for details) CMSIS-DSP: 1.6.0 (see revision history for details) - reworked DSP library source files - reworked DSP library documentation - Changed DSP folder structure - moved DSP libraries to folder ./DSP/Lib - ARM DSP Libraries are built with ARMCLANG - Added DSP Libraries Source variant CMSIS-RTOS2: - RTX 5.5.0 (see revision history for details) CMSIS-Driver: 2.7.0 - Added WiFi Interface API 1.0.0-beta - Added components for project specific driver implementations CMSIS-Pack: 1.6.0 (see revision history for details) Devices: - Added Cortex-M35P and ARMv81MML device templates. - Fixed C-Startup Code for GCC (aligned with other compilers) Utilities: - SVDConv 3.3.25 - PackChk 1.3.82 Aligned pack structure with repository. The following folders are deprecated: - CMSIS/Include/ - CMSIS/DSP_Lib/ CMSIS-Core(M): 5.1.2 (see revision history for details) - Added Cortex-M1 support (beta). CMSIS-Core(A): 1.1.2 (see revision history for details) CMSIS-NN: 1.1.0 - Added new math functions. CMSIS-RTOS2: - API 2.1.3 (see revision history for details) - RTX 5.4.0 (see revision history for details) * Updated exception handling on Cortex-A CMSIS-Driver: - Flash Driver API V2.2.0 Utilities: - SVDConv 3.3.21 - PackChk 1.3.71 Updated Arm company brand. CMSIS-Core(M): 5.1.1 (see revision history for details) CMSIS-Core(A): 1.1.1 (see revision history for details) CMSIS-DAP: 2.0.0 (see revision history for details) CMSIS-NN: 1.0.0 - Initial contribution of the bare metal Neural Network Library. CMSIS-RTOS2: - RTX 5.3.0 (see revision history for details) - OS Tick API 1.0.1 CMSIS-Core(M): 5.1.0 (see revision history for details) - Added MPU Functions for ARMv8-M for Cortex-M23/M33. - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. CMSIS-Core(A): 1.1.0 (see revision history for details) - Added compiler_iccarm.h. - Added additional access functions for physical timer. CMSIS-DAP: 1.2.0 (see revision history for details) CMSIS-DSP: 1.5.2 (see revision history for details) CMSIS-Driver: 2.6.0 (see revision history for details) - CAN Driver API V1.2.0 - NAND Driver API V2.3.0 CMSIS-RTOS: - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. CMSIS-RTOS2: - API 2.1.2 (see revision history for details) - RTX 5.2.3 (see revision history for details) Devices: - Added GCC startup and linker script for Cortex-A9. - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. - Added IAR startup code for Cortex-A9 CMSIS-RTOS2: - RTX 5.2.1 (see revision history for details) CMSIS-Core(M): 5.0.2 (see revision history for details) - Changed Version Control macros to be core agnostic. - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. CMSIS-Core(A): 1.0.0 (see revision history for details) - Initial release - IRQ Controller API 1.0.0 CMSIS-Driver: 2.05 (see revision history for details) - All typedefs related to status have been made volatile. CMSIS-RTOS2: - API 2.1.1 (see revision history for details) - RTX 5.2.0 (see revision history for details) - OS Tick API 1.0.0 CMSIS-DSP: 1.5.2 (see revision history for details) - Fixed GNU Compiler specific diagnostics. CMSIS-Pack: 1.5.0 (see revision history for details) - added System Description File (*.SDF) Format CMSIS-Zone: 0.0.1 (Preview) - Initial specification draft Package Description: - added taxonomy for Cclass RTOS CMSIS-RTOS2: - API 2.1 (see revision history for details) - RTX 5.1.0 (see revision history for details) CMSIS-Core: 5.0.1 (see revision history for details) - Added __PACKED_STRUCT macro - Added uVisior support - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ - Updated template for secure main function (main_s.c) - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) CMSIS-DSP: 1.5.1 (see revision history for details) - added ARMv8M DSP libraries. CMSIS-Pack:1.4.9 (see revision history for details) - added Pack Index File specification and schema file Changed open source license to Apache 2.0 CMSIS_Core: - Added support for Cortex-M23 and Cortex-M33. - Added ARMv8-M device configurations for mainline and baseline. - Added CMSE support and thread context management for TrustZone for ARMv8-M - Added cmsis_compiler.h to unify compiler behaviour. - Updated function SCB_EnableICache (for Cortex-M7). - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType CMSIS-RTOS: - bug fix in RTX 4.82 (see revision history for details) CMSIS-RTOS2: - new API including compatibility layer to CMSIS-RTOS - reference implementation based on RTX5 - supports all Cortex-M variants including TrustZone for ARMv8-M CMSIS-SVD: - reworked SVD format documentation - removed SVD file database documentation as SVD files are distributed in packs - updated SVDConv for Win32 and Linux CMSIS-DSP: - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. - Added DSP libraries build projects to CMSIS pack. - CMSIS-Core 4.30.0 (see revision history for details) - CMSIS-DAP 1.1.0 (unchanged) - CMSIS-Driver 2.04.0 (see revision history for details) - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) - CMSIS-Pack 1.4.1 (see revision history for details) - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) - CMSIS-SVD 1.3.1 (see revision history for details) - CMSIS-Core 4.20 (see revision history for details) - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) - CMSIS-RTOS -- API 1.02 (unchanged) -- RTX 4.79 (see revision history for details) - CMSIS-SVD 1.3.0 (see revision history for details) - CMSIS-DAP 1.1.0 (extended with SWO support) - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) - CMSIS-DSP 1.4.5 (see revision history for details) - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) - CMSIS-RTOS -- API 1.02 (unchanged) -- RTX 4.78 (see revision history for details) - CMSIS-SVD 1.2 (unchanged) Adding Cortex-M7 support - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) - CMSIS-SVD 1.2 (Cortex-M7 extensions) - CMSIS-RTOS RTX 4.75 (see revision history for details) - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices - CMSIS-Driver 2.02 (incompatible update) - CMSIS-Pack 1.3 (see revision history for details) - CMSIS-DSP 1.4.2 (unchanged) - CMSIS-Core 3.30 (unchanged) - CMSIS-RTOS RTX 4.74 (unchanged) - CMSIS-RTOS API 1.02 (unchanged) - CMSIS-SVD 1.10 (unchanged) PACK: - removed G++ specific files from PACK - added Component Startup variant "C Startup" - added Pack Checking Utility - updated conditions to reflect tool-chain dependency - added Taxonomy for Graphics - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" - CMSIS-RTOS 4.74 (see revision history for details) - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. Software components for audio processing Generic Interfaces for Evaluation and Development Boards Drivers that support an external component available on an evaluation board Compiler Software Extensions Cortex Microcontroller Software Interface Components Unified Device Drivers compliant to CMSIS-Driver Specifications Startup, System Setup Data exchange or data formatter Drivers that support an extension board or shield File Drive Support and File System IoT cloud client connector IoT specific services IoT specific software utility Graphical User Interface Network Stack using Internet Protocols Real-time Operating System Encryption for secure communication or storage Universal Serial Bus Stack Generic software utility components The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling - upward compatibility with the rest of the Cortex-M processor family. The Arm Cortex-M23 is based on the Armv8-M baseline architecture. It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller class processor based on the Armv8-M mainline architecture with Arm TrustZone security. no DSP Instructions, no Floating Point Unit, no TrustZone no DSP Instructions, no Floating Point Unit, TrustZone DSP Instructions, Single Precision Floating Point Unit, no TrustZone DSP Instructions, Single Precision Floating Point Unit, TrustZone The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. no DSP Instructions, no Floating Point Unit, no TrustZone no DSP Instructions, no Floating Point Unit, TrustZone DSP Instructions, Single Precision Floating Point Unit, no TrustZone DSP Instructions, Single Precision Floating Point Unit, TrustZone The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology. It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance. The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption. Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE). The processor also supports previous Armv8-M architectural features. The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning. The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption. Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: - simple, easy-to-use programmers model - highly efficient ultra-low power operation - excellent code density - deterministic, high-performance interrupt handling Armv8-M Baseline based device with TrustZone Armv8-M Mainline based device with TrustZone no DSP Instructions, no Floating Point Unit, TrustZone DSP Instructions, no Floating Point Unit, TrustZone no DSP Instructions, Single Precision Floating Point Unit, TrustZone DSP Instructions, Single Precision Floating Point Unit, TrustZone no DSP Instructions, Double Precision Floating Point Unit, TrustZone DSP Instructions, Double Precision Floating Point Unit, TrustZone Armv8.1-M Mainline based device with TrustZone and MVE Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, an optional integrated GIC, and an optional L2 cache controller. The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle state. Device interrupt controller interface RTOS Kernel system tick timer interface CMSIS-RTOS API for Cortex-M, SC000, and SC300 CMSIS-RTOS API for Cortex-M, SC000, and SC300 USART Driver API for Cortex-M SPI Driver API for Cortex-M SAI Driver API for Cortex-M I2C Driver API for Cortex-M CAN Driver API for Cortex-M Flash Driver API for Cortex-M MCI Driver API for Cortex-M NAND Flash Driver API for Cortex-M Ethernet MAC and PHY Driver API for Cortex-M Ethernet MAC Driver API for Cortex-M Ethernet PHY Driver API for Cortex-M USB Device Driver API for Cortex-M USB Host Driver API for Cortex-M WiFi driver Virtual I/O Armv6-M architecture based device Armv7-M architecture based device Armv8-M base line architecture based device Armv8-M main line architecture based device Armv8.1-M main line architecture based device Armv8-M/Armv8.1-M architecture based device Armv8-M architecture based device Armv6_7-M architecture based device Armv6_7_8-M architecture based device Armv7-A architecture based device No TrustZone TrustZone TrustZone (Disabled) TrustZone (Secure) TrustZone (Non-secure) Armv8-M architecture based device without TrustZone Armv8-M architecture based device with TrustZone (Disabled) Armv8-M architecture based device with TrustZone (Secure) Armv8-M architecture based device with TrustZone (Non-secure) Startup files for Arm Compiler 6 targeting TrustZone secure mode Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode Generic Arm Cortex-M0 device startup and depends on CMSIS Core Generic Arm Cortex-M0+ device startup and depends on CMSIS Core Generic Arm Cortex-M1 device startup and depends on CMSIS Core Generic Arm Cortex-M3 device startup and depends on CMSIS Core Generic Arm Cortex-M4 device startup and depends on CMSIS Core Generic Arm Cortex-M7 device startup and depends on CMSIS Core Generic Arm Cortex-M23 device startup and depends on CMSIS Core Generic Arm Cortex-M33 device startup and depends on CMSIS Core Generic Arm Cortex-M35P device startup and depends on CMSIS Core Generic Arm Cortex-M55 device startup and depends on CMSIS Core Generic Arm Cortex-M85 device startup and depends on CMSIS Core Generic Arm SC000 device startup and depends on CMSIS Core Generic Arm SC300 device startup and depends on CMSIS Core Generic Armv8-M Baseline device startup and depends on CMSIS Core Generic Armv8-M Mainline device startup and depends on CMSIS Core Generic Armv8.1-M Mainline device startup and depends on CMSIS Core Generic Arm Cortex-A5 device startup and depends on CMSIS Core Generic Arm Cortex-A7 device startup and depends on CMSIS Core Generic Arm Cortex-A9 device startup and depends on CMSIS Core Components required for RTOS RTX Components required for RTOS RTX IFX Components required for RTOS RTX5 Components required for RTOS2 RTX5 Components required for RTOS2 RTX5 on Armv7-A Components required for RTOS2 RTX5 in Non-Secure Domain Arm Compiler for Armv6-M architecture (little endian) Arm Compiler for Armv6-M architecture (big endian) Arm Compiler for Armv7-M architecture without FPU (little endian) Arm Compiler for Armv7-M architecture without FPU (big endian) Arm Compiler for Armv7-M architecture with FPU (little endian) Arm Compiler for Armv7-M architecture with FPU (big endian) Arm Compiler for Armv8-M base line architecture (little endian) Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) GNU Compiler for Armv6-M architecture (little endian) GNU Compiler for Armv6-M architecture (big endian) GNU Compiler for Armv7-M architecture without FPU (little endian) GNU Compiler for Armv7-M architecture without FPU (big endian) GNU Compiler for Armv7-M architecture with FPU (little endian) GNU Compiler for Armv7-M architecture with FPU (big endian) GNU Compiler for Armv8-M base line architecture (little endian) GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian) GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian) IAR Compiler for Armv6-M architecture (little endian) IAR Compiler for Armv6-M architecture (big endian) IAR Compiler for Armv7-M architecture without FPU (little endian) IAR Compiler for Armv7-M architecture without FPU (big endian) IAR Compiler for Armv7-M architecture with FPU (little endian) IAR Compiler for Armv7-M architecture with FPU (big endian) IAR Compiler for Armv8-M base line architecture (little endian) IAR Compiler for Armv8-M main line architecture without FPU (little endian) IAR Compiler for Armv8-M main line architecture with FPU (little endian) IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian) IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian) Arm Assembler for Armv6-M architecture GNU Assembler for Armv6-M architecture IAR Assembler for Armv6-M architecture Arm Assembler for Armv7-M architecture GNU Assembler for Armv7-M architecture IAR Assembler for Armv7-M architecture GNU Assembler for Armv8-M base line architecture GNU Assembler for Armv8-M/Armv8.1-M main line architecture IAR Assembler for Armv8-M base line architecture IAR Assembler for Armv8-M main line architecture Arm Assembler for Armv7-A architecture GNU Assembler for Armv7-A architecture IAR Assembler for Armv7-A architecture Components required for OS Tick Private Timer Components required for OS Tick Generic Physical Timer CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M CMSIS-CORE for Cortex-A System and Startup for Generic Arm Cortex-M0 device DEPRECATED: System and Startup for Generic Arm Cortex-M0 device System and Startup for Generic Arm Cortex-M0+ device DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device System and Startup for Generic Arm Cortex-M1 device DEPRECATED: System and Startup for Generic Arm Cortex-M1 device System and Startup for Generic Arm Cortex-M3 device DEPRECATED: System and Startup for Generic Arm Cortex-M3 device System and Startup for Generic Arm Cortex-M4 device DEPRECATED: System and Startup for Generic Arm Cortex-M4 device System and Startup for Generic Arm Cortex-M7 device DEPRECATED: System and Startup for Generic Arm Cortex-M7 device System and Startup for Generic Arm Cortex-M23 device DEPRECATED: System and Startup for Generic Arm Cortex-M23 device System and Startup for Generic Arm Cortex-M33 device DEPRECATED: System and Startup for Generic Arm Cortex-M33 device System and Startup for Generic Arm Cortex-M35P device DEPRECATED: System and Startup for Generic Arm Cortex-M35P device System and Startup for Generic Cortex-M55 device System and Startup for Generic Cortex-M85 device System and Startup for Generic Arm SC000 device DEPRECATED: System and Startup for Generic Arm SC000 device System and Startup for Generic Arm SC300 device DEPRECATED: System and Startup for Generic Arm SC300 device System and Startup for Generic Armv8-M Baseline device DEPRECATED: System and Startup for Generic Armv8-M Baseline device System and Startup for Generic Armv8-M Mainline device DEPRECATED: System and Startup for Generic Armv8-M Mainline device System and Startup for Generic Armv8.1-M Mainline device System and Startup for Generic Arm Cortex-A5 device System and Startup for Generic Arm Cortex-A7 device System and Startup for Generic Arm Cortex-A9 device IRQ Controller implementation using GIC OS Tick implementation using Private Timer OS Tick implementation using Generic Physical Timer CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 #define RTE_CMSIS_RTOS /* CMSIS-RTOS */ #define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ CMSIS-RTOS2 RTX5 for Armv7-A (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source) #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ Access to #include Driver_USART.h file and code template for custom implementation Access to #include Driver_SPI.h file and code template for custom implementation Access to #include Driver_SAI.h file and code template for custom implementation Access to #include Driver_I2C.h file and code template for custom implementation Access to #include Driver_CAN.h file and code template for custom implementation Access to #include Driver_Flash.h file and code template for custom implementation Access to #include Driver_MCI.h file and code template for custom implementation Access to #include Driver_NAND.h file and code template for custom implementation Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation Access to #include Driver_ETH_MAC.h file and code template for custom implementation Access to #include Driver_ETH_PHY.h file and code template for custom implementation Access to #include Driver_USBD.h file and code template for custom implementation Access to #include Driver_USBH.h file and code template for custom implementation Access to #include Driver_WiFi.h file Virtual I/O custom implementation template Virtual I/O implementation using memory only uVision Simulator EWARM Simulator CMSIS-RTOS2 Blinky example Getting Started CMSIS-RTOS2 mixed API v1 and v2 Getting Started CMSIS-RTOS2 Message Queue Example Getting Started CMSIS-RTOS2 Memory Pool Example Getting Started Bare-metal secure/non-secure example without RTOS Getting Started Secure/non-secure RTOS example with thread context management Getting Started Secure/non-secure RTOS example with security test cases and system recovery Getting Started CMSIS-RTOS2 Blinky example Getting Started CMSIS-RTOS2 Message Queue Example Getting Started ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h ================================================ /****************************************************************************** * @file cachel1_armv7.h * @brief CMSIS Level 1 Cache API for Armv7-M and later * @version V1.0.3 * @date 17. March 2023 ******************************************************************************/ /* * Copyright (c) 2020-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_CACHEL1_ARMV7_H #define ARM_CACHEL1_ARMV7_H /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) #ifndef __SCB_DCACHE_LINE_SIZE #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ #endif #ifndef __SCB_ICACHE_LINE_SIZE #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ #endif /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_FORCEINLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief I-Cache Invalidate by address \details Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] isize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if ( isize > 0 ) { int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_ICACHE_LINE_SIZE; op_size -= __SCB_ICACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_FORCEINLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) struct { uint32_t ccsidr; uint32_t sets; uint32_t ways; } locals #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) __ALIGNED(__SCB_DCACHE_LINE_SIZE) #endif ; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); #if !defined(__OPTIMIZE__) /* * For the endless loop issue with no optimization builds. * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 * * The issue only happens when local variables are in stack. If * local variables are saved in general purpose register, then the function * is OK. * * When local variables are in stack, after disabling the cache, flush the * local variables cache line for data consistency. */ /* Clean and invalidate the local variable cache. */ #if defined(__ICCARM__) /* As we can't align the stack to the cache line size, invalidate each of the variables */ SCB->DCCIMVAC = (uint32_t)&locals.sets; SCB->DCCIMVAC = (uint32_t)&locals.ways; SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; #else SCB->DCCIMVAC = (uint32_t)&locals; #endif __DSB(); __ISB(); #endif locals.ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); do { locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); do { SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (locals.ways-- != 0U); } while(locals.sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /*@} end of CMSIS_Core_CacheFunctions */ #endif /* ARM_CACHEL1_ARMV7_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h ================================================ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file * @version V5.4.0 * @date 20. January 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) #define __ARM_ARCH_6M__ 1 #endif #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) #define __ARM_ARCH_7M__ 1 #endif #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) #define __ARM_ARCH_7EM__ 1 #endif /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ /* __ARM_ARCH_8_1M_MAIN__ not applicable */ /* CMSIS compiler control DSP macros */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __ARM_FEATURE_DSP 1 #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __memory_changed() #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"), zero_init)) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; __ISB(); } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.5.0 * @date 20. January 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #ifndef __STACK_SEAL #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base #endif #ifndef __TZ_STACK_SEAL_SIZE #define __TZ_STACK_SEAL_SIZE 8U #endif #ifndef __TZ_STACK_SEAL_VALUE #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** @}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } #endif /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } #endif /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); __ISB(); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); __ISB(); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(fpscr) ((void)(fpscr)) #endif /** @} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 #define __UADD8 __builtin_arm_uadd8 #define __UQADD8 __builtin_arm_uqadd8 #define __UHADD8 __builtin_arm_uhadd8 #define __SSUB8 __builtin_arm_ssub8 #define __QSUB8 __builtin_arm_qsub8 #define __SHSUB8 __builtin_arm_shsub8 #define __USUB8 __builtin_arm_usub8 #define __UQSUB8 __builtin_arm_uqsub8 #define __UHSUB8 __builtin_arm_uhsub8 #define __SADD16 __builtin_arm_sadd16 #define __QADD16 __builtin_arm_qadd16 #define __SHADD16 __builtin_arm_shadd16 #define __UADD16 __builtin_arm_uadd16 #define __UQADD16 __builtin_arm_uqadd16 #define __UHADD16 __builtin_arm_uhadd16 #define __SSUB16 __builtin_arm_ssub16 #define __QSUB16 __builtin_arm_qsub16 #define __SHSUB16 __builtin_arm_shsub16 #define __USUB16 __builtin_arm_usub16 #define __UQSUB16 __builtin_arm_uqsub16 #define __UHSUB16 __builtin_arm_uhsub16 #define __SASX __builtin_arm_sasx #define __QASX __builtin_arm_qasx #define __SHASX __builtin_arm_shasx #define __UASX __builtin_arm_uasx #define __UQASX __builtin_arm_uqasx #define __UHASX __builtin_arm_uhasx #define __SSAX __builtin_arm_ssax #define __QSAX __builtin_arm_qsax #define __SHSAX __builtin_arm_shsax #define __USAX __builtin_arm_usax #define __UQSAX __builtin_arm_uqsax #define __UHSAX __builtin_arm_uhsax #define __USAD8 __builtin_arm_usad8 #define __USADA8 __builtin_arm_usada8 #define __SSAT16 __builtin_arm_ssat16 #define __USAT16 __builtin_arm_usat16 #define __UXTB16 __builtin_arm_uxtb16 #define __UXTAB16 __builtin_arm_uxtab16 #define __SXTB16 __builtin_arm_sxtb16 #define __SXTAB16 __builtin_arm_sxtab16 #define __SMUAD __builtin_arm_smuad #define __SMUADX __builtin_arm_smuadx #define __SMLAD __builtin_arm_smlad #define __SMLADX __builtin_arm_smladx #define __SMLALD __builtin_arm_smlald #define __SMLALDX __builtin_arm_smlaldx #define __SMUSD __builtin_arm_smusd #define __SMUSDX __builtin_arm_smusdx #define __SMLSD __builtin_arm_smlsd #define __SMLSDX __builtin_arm_smlsdx #define __SMLSLD __builtin_arm_smlsld #define __SMLSLDX __builtin_arm_smlsldx #define __SEL __builtin_arm_sel #define __QADD __builtin_arm_qadd #define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /** @} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h ================================================ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V1.6.0 * @date 20. January 2023 ******************************************************************************/ /* * Copyright (c) 2018-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #ifndef __STACK_SEAL #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base #endif #ifndef __TZ_STACK_SEAL_SIZE #define __TZ_STACK_SEAL_SIZE 8U #endif #ifndef __TZ_STACK_SEAL_VALUE #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } #endif /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } #endif /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); __ISB(); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); __ISB(); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.3.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6.6 LTM (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #include "cmsis_armclang_ltm.h" /* * Arm Compiler above 6.10.1 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" /* * TI Arm Clang Compiler (tiarmclang) */ #elif defined (__ti__) #include "cmsis_tiarmclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include /* * TI Arm Compiler (armcl) */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.4.2 * @date 17. December 2022 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START /** \brief Initializes data and bss sections \details This default implementations initialized all data and additional bss sections relying on .copy.table and .zero.table specified properly in the used linker script. */ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { extern void _start(void) __NO_RETURN; typedef struct __copy_table { uint32_t const* src; uint32_t* dest; uint32_t wlen; } __copy_table_t; typedef struct __zero_table { uint32_t* dest; uint32_t wlen; } __zero_table_t; extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_end__; extern const __zero_table_t __zero_table_start__; extern const __zero_table_t __zero_table_end__; for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = pTable->src[i]; } } for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = 0u; } } _start(); } #define __PROGRAM_START __cmsis_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP __StackTop #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT __StackLimit #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #ifndef __STACK_SEAL #define __STACK_SEAL __StackSeal #endif #ifndef __TZ_STACK_SEAL_SIZE #define __TZ_STACK_SEAL_SIZE 8U #endif #ifndef __TZ_STACK_SEAL_VALUE #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi":::"memory") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe":::"memory") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1, ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1, ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); __ISB(); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); __ISB(); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #define STACK_SIZE 0x80 // ջС128ֽڣ #define STACK_END 0x20004000 // ջַ __STATIC_FORCEINLINE void ClearStack(void) { uint32_t *stack_ptr = (uint32_t *)STACK_END; // ջַ uint32_t stack_bottom = (uint32_t)stack_ptr - STACK_SIZE; // ջʼַ while ((uint32_t)stack_ptr > stack_bottom) { stack_ptr--; *stack_ptr = 0; // ջ } } __STATIC_FORCEINLINE uint32_t __get_PC(void) { uint32_t result; __ASM volatile ( "MOV %0, r15\n" : "=r" (result) ); return result; } __STATIC_FORCEINLINE void __set_PC(uint32_t pc) { __ASM volatile ( "MOV r15, %0\n" : : "r" (pc) ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1, ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) #define __USAT16(ARG1, ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) { uint32_t result; if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); } else { result = __SXTB16(__ROR(op1, rotate)) ; } return result; } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) { uint32_t result; if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); } else { result = __SXTAB16(op1, __ROR(op2, rotate)); } return result; } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h ================================================ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.4.0 * @date 20. January 2023 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2021 IAR Systems // Copyright (c) 2017-2023 Arm Limited. All rights reserved. // // SPDX-License-Identifier: Apache-2.0 // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #if __ICCARM_V8 #define __RESTRICT __restrict #else /* Needs IAR language extensions */ #define __RESTRICT restrict #endif #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #undef __WEAK /* undo the definition from DLib_Defaults.h */ #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __PROGRAM_START #define __PROGRAM_START __iar_program_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP CSTACK$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT CSTACK$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __vector_table #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE @".intvec" #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #ifndef __STACK_SEAL #define __STACK_SEAL STACKSEAL$$Base #endif #ifndef __TZ_STACK_SEAL_SIZE #define __TZ_STACK_SEAL_SIZE 8U #endif #ifndef __TZ_STACK_SEAL_VALUE #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __arm_wsr("CONTROL", control); __iar_builtin_ISB(); } #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __arm_wsr("CONTROL_NS", control); __iar_builtin_ISB(); } #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __TZ_get_PSPLIM_NS() (0U) #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) #else #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #endif #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; } #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); return(result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); __iar_builtin_ISB(); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); #endif return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_tiarmclang.h ================================================ /**************************************************************************//** * @file cmsis_tiarmclang.h * @brief CMSIS compiler tiarmclang header file * @version V1.0.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_TIARMCLANG_H #define __CMSIS_TIARMCLANG_H #pragma clang system_header /* treat file as system include file */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __NO_INIT #define __NO_INIT __attribute__ ((section (".bss.noinit"))) #endif #ifndef __ALIAS #define __ALIAS(x) __attribute__ ((alias(x))) #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START _c_int00 #endif #ifndef __INITIAL_SP #define __INITIAL_SP __STACK_END #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT __STACK_SIZE #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #ifndef __STACK_SEAL #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base #endif #ifndef __TZ_STACK_SEAL_SIZE #define __TZ_STACK_SEAL_SIZE 8U #endif #ifndef __TZ_STACK_SEAL_VALUE #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** @}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } #endif /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ #ifndef __ARM_COMPAT_H __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } #endif /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); __ISB(); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); __ISB(); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(fpscr) ((void)(fpscr)) #endif /** @} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 #define __UADD8 __builtin_arm_uadd8 #define __UQADD8 __builtin_arm_uqadd8 #define __UHADD8 __builtin_arm_uhadd8 #define __SSUB8 __builtin_arm_ssub8 #define __QSUB8 __builtin_arm_qsub8 #define __SHSUB8 __builtin_arm_shsub8 #define __USUB8 __builtin_arm_usub8 #define __UQSUB8 __builtin_arm_uqsub8 #define __UHSUB8 __builtin_arm_uhsub8 #define __SADD16 __builtin_arm_sadd16 #define __QADD16 __builtin_arm_qadd16 #define __SHADD16 __builtin_arm_shadd16 #define __UADD16 __builtin_arm_uadd16 #define __UQADD16 __builtin_arm_uqadd16 #define __UHADD16 __builtin_arm_uhadd16 #define __SSUB16 __builtin_arm_ssub16 #define __QSUB16 __builtin_arm_qsub16 #define __SHSUB16 __builtin_arm_shsub16 #define __USUB16 __builtin_arm_usub16 #define __UQSUB16 __builtin_arm_uqsub16 #define __UHSUB16 __builtin_arm_uhsub16 #define __SASX __builtin_arm_sasx #define __QASX __builtin_arm_qasx #define __SHASX __builtin_arm_shasx #define __UASX __builtin_arm_uasx #define __UQASX __builtin_arm_uqasx #define __UHASX __builtin_arm_uhasx #define __SSAX __builtin_arm_ssax #define __QSAX __builtin_arm_qsax #define __SHSAX __builtin_arm_shsax #define __USAX __builtin_arm_usax #define __UQSAX __builtin_arm_uqsax #define __UHSAX __builtin_arm_uhsax #define __USAD8 __builtin_arm_usad8 #define __USADA8 __builtin_arm_usada8 #define __SSAT16 __builtin_arm_ssat16 #define __USAT16 __builtin_arm_usat16 #define __UXTB16 __builtin_arm_uxtb16 #define __UXTAB16 __builtin_arm_uxtab16 #define __SXTB16 __builtin_arm_sxtb16 #define __SXTAB16 __builtin_arm_sxtab16 #define __SMUAD __builtin_arm_smuad #define __SMUADX __builtin_arm_smuadx #define __SMLAD __builtin_arm_smlad #define __SMLADX __builtin_arm_smladx #define __SMLALD __builtin_arm_smlald #define __SMLALDX __builtin_arm_smlaldx #define __SMUSD __builtin_arm_smusd #define __SMUSDX __builtin_arm_smusdx #define __SMLSD __builtin_arm_smlsd #define __SMLSDX __builtin_arm_smlsdx #define __SMLSLD __builtin_arm_smlsld #define __SMLSLDX __builtin_arm_smlsldx #define __SEL __builtin_arm_sel #define __QADD __builtin_arm_qadd #define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /** @} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_TIARMCLANG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/cmsis_version.h ================================================ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.5 * @date 02. February 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h ================================================ /**************************************************************************//** * @file core_armv81mml.h * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File * @version V1.5.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2018-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV81MML_H_GENERIC #define __CORE_ARMV81MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMV81MML @{ */ #include "cmsis_version.h" /* CMSIS ARMV81MML definitions */ #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #error Legacy Arm Compiler does not support Armv8.1-M target architecture. #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV81MML_H_DEPENDANT #define __CORE_ARMV81MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv81MML_REV #define __ARMv81MML_REV 0x0000U #warning "__ARMv81MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #if __FPU_PRESENT != 0U #ifndef __FPU_DP #define __FPU_DP 0U #warning "__FPU_DP not defined in device header file; using default!" #endif #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __PMU_PRESENT #define __PMU_PRESENT 0U #warning "__PMU_PRESENT not defined in device header file; using default!" #endif #if __PMU_PRESENT != 0U #ifndef __PMU_NUM_EVENTCNT #define __PMU_NUM_EVENTCNT 2U #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ #endif #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv81MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ uint32_t RESERVED4[14U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ /* SCB Debug Feature Register 0 Definitions */ #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB RAS Fault Status Register Definitions */ #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[3U]; __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) \brief Type definitions for the Performance Monitoring Unit (PMU) @{ */ /** \brief Structure type to access the Performance Monitoring Unit (PMU). */ typedef struct { __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ uint32_t RESERVED1[224]; __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ uint32_t RESERVED3[480]; __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ uint32_t RESERVED4[7]; __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ uint32_t RESERVED5[7]; __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ uint32_t RESERVED6[7]; __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ uint32_t RESERVED7[7]; __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ uint32_t RESERVED8[7]; __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ uint32_t RESERVED9[7]; __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ uint32_t RESERVED10[79]; __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ uint32_t RESERVED11[108]; __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ uint32_t RESERVED12[3]; __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ uint32_t RESERVED13[3]; __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ } PMU_Type; /** \brief PMU Event Counter Registers (0-30) Definitions */ #define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ /** \brief PMU Event Type and Filter Registers (0-30) Definitions */ #define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ /** \brief PMU Count Enable Set Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ /** \brief PMU Count Enable Clear Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ /** \brief PMU Interrupt Enable Set Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ /** \brief PMU Interrupt Enable Clear Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ /** \brief PMU Overflow Flag Status Set Register Definitions */ #define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ #define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ #define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ #define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ #define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ #define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ #define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ #define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ #define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ #define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ #define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ #define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ #define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ #define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ #define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ #define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ #define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ #define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ #define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ #define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ #define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ #define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ #define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ #define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ #define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ #define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ #define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ #define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ #define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ #define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ #define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ /** \brief PMU Overflow Flag Status Clear Register Definitions */ #define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ #define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ #define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ #define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ #define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ #define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ #define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ #define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ #define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ #define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ #define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ #define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ #define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ #define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ #define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ #define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ #define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ #define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ #define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ #define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ #define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ #define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ #define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ #define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ #define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ #define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ #define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ #define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ #define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ #define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ #define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ /** \brief PMU Software Increment Counter */ #define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ #define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ #define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ #define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ #define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ #define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ #define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ #define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ #define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ #define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ #define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ #define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ #define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ #define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ #define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ #define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ #define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ #define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ #define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ #define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ #define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ #define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ #define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ #define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ #define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ #define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ #define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ #define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ #define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ #define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ #define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ /** \brief PMU Control Register Definitions */ #define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ #define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ #define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ #define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ #define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ /** \brief PMU Type Register Definitions */ #define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ #define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ /** \brief PMU Authentication Status Register Definitions */ #define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ /*@} end of group CMSIS_PMU */ #endif #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ #define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ #define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Set Clear Exception and Monitor Control Register Definitions */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ #define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ #define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ #define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## PMU functions and events #################################### */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #include "pmu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## MVE functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_MveFunctions MVE Functions \brief Function that provides MVE type. @{ */ /** \brief get MVE type \details returns the MVE type \returns - \b 0: No Vector Extension (MVE) - \b 1: Integer Vector Extension (MVE-I) - \b 2: Floating-point Vector Extension (MVE-F) */ __STATIC_INLINE uint32_t SCB_GetMVEType(void) { const uint32_t mvfr1 = FPU->MVFR1; if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) { return 2U; } else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) { return 1U; } else { return 0U; } } /*@} end of CMSIS_Core_MveFunctions */ /* ########################## Cache functions #################################### */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) #include "cachel1_armv7.h" #endif /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h ================================================ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File * @version V5.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined (__ARM_FP) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h ================================================ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File * @version V5.3.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ #include "cmsis_version.h" /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (80U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /** @} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /** @} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /** @} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /** @} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /** @} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /** @} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /** @}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /** @}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /** @}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /** @} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /** @} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /** @} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /** @} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /** @} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /** @} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /** @} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /** @} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /** @} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) #include "cachel1_armv7.h" #endif /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** @} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /** @} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /** @} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ #include "cmsis_version.h" /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ #include "cmsis_version.h" /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; #else uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ #endif /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; #else uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ #endif } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm1.h ================================================ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File * @version V1.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM1_H_GENERIC #define __CORE_CM1_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M1 @{ */ #include "cmsis_version.h" /* CMSIS CM1 definitions */ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (1U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM1_H_DEPENDANT #define __CORE_CM1_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM1_REV #define __CM1_REV 0x0100U #warning "__CM1_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M1 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M1 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm23.h ================================================ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ #endif /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ /* Capitalize ITM_TCR Register Definitions */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos) /*!< \deprecated ITM_TCR_TraceBusID_Pos */ #define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk) /*!< \deprecated ITM_TCR_TraceBusID_Msk */ #define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos) /*!< \deprecated ITM_TCR_TSPrescale_Pos */ #define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk) /*!< \deprecated ITM_TCR_TSPrescale_Msk */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos) /*!< \deprecated ITM_LSR_ByteAcc_Pos */ #define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk) /*!< \deprecated ITM_LSR_ByteAcc_Msk */ #define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos) /*!< \deprecated ITM_LSR_Access_Pos */ #define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk) /*!< \deprecated ITM_LSR_Access_Msk */ #define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos) /*!< \deprecated ITM_LSR_Present_Pos */ #define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk) /*!< \deprecated ITM_LSR_Present_Msk */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm33.h ================================================ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.3.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ #include "cmsis_version.h" /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm35p.h ================================================ /**************************************************************************//** * @file core_cm35p.h * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File * @version V1.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2018-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM35P_H_GENERIC #define __CORE_CM35P_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M35P @{ */ #include "cmsis_version.h" /* CMSIS CM35P definitions */ #define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (35U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM35P_H_DEPENDANT #define __CORE_CM35P_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM35P_REV #define __CM35P_REV 0x0000U #warning "__CM35P_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M35P */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ #include "cmsis_version.h" /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ /* Capitalize ITM_TCR Register Definitions */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos) /*!< \deprecated ITM_TCR_TraceBusID_Pos */ #define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk) /*!< \deprecated ITM_TCR_TraceBusID_Msk */ #define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos) /*!< \deprecated ITM_TCR_TSPrescale_Pos */ #define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk) /*!< \deprecated ITM_TCR_TSPrescale_Msk */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos) /*!< \deprecated ITM_LSR_ByteAcc_Pos */ #define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk) /*!< \deprecated ITM_LSR_ByteAcc_Msk */ #define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos) /*!< \deprecated ITM_LSR_Access_Pos */ #define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk) /*!< \deprecated ITM_LSR_Access_Msk */ #define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos) /*!< \deprecated ITM_LSR_Present_Pos */ #define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk) /*!< \deprecated ITM_LSR_Present_Msk */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm55.h ================================================ /**************************************************************************//** * @file core_cm55.h * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File * @version V1.5.2 * @date 19. April 2023 ******************************************************************************/ /* * Copyright (c) 2018-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM55_H_GENERIC #define __CORE_CM55_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M55 @{ */ #include "cmsis_version.h" /* CMSIS CM55 definitions */ #define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (55U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #error Legacy Arm Compiler does not support Armv8.1-M target architecture. #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM55_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM55_H_DEPENDANT #define __CORE_CM55_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM55_REV #define __CM55_REV 0x0000U #warning "__CM55_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #if __FPU_PRESENT != 0U #ifndef __FPU_DP #define __FPU_DP 0U #warning "__FPU_DP not defined in device header file; using default!" #endif #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __PMU_PRESENT #define __PMU_PRESENT 0U #warning "__PMU_PRESENT not defined in device header file; using default!" #endif #if __PMU_PRESENT != 0U #ifndef __PMU_NUM_EVENTCNT #define __PMU_NUM_EVENTCNT 8U #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ #endif #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M55 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core EWIC Register - Core EWIC Interrupt Status Access Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core PMU Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ uint32_t RESERVED4[14U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ /* SCB Debug Feature Register 0 Definitions */ #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB RAS Fault Status Register Definitions */ #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ICB Implementation Control Block register (ICB) \brief Type definitions for the Implementation Control Block Register @{ */ /** \brief Structure type to access the Implementation Control Block (ICB). */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } ICB_Type; /* Auxiliary Control Register Definitions */ #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ #define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ #define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ #define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ #define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ #define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ #define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ #define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ #define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ #define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ #define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ #define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ #define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ #define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ #define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ #define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ #define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ #define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ #define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ #define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ #define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ #define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ /* Interrupt Controller Type Register Definitions */ #define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_ICB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[27U]; __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) ITM Integration Read Register */ uint32_t RESERVED4[1U]; __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ uint32_t RESERVED5[1U]; __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED6[46U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED7[3U]; __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Read Register Definitions */ #define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ #define ITM_ITREAD_AFVALID_Msk (0x1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ #define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ #define ITM_ITREAD_ATREADY_Msk (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ /* ITM Integration Write Register Definitions */ #define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ #define ITM_ITWRITE_AFVALID_Msk (0x1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ #define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ #define ITM_ITWRITE_ATREADY_Msk (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ #define ITM_ITCTRL_IME_Msk (0x1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED4[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED6[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED14[968U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ uint32_t RESERVED15[3U]; __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) @{ */ /** \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). */ typedef struct { __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ uint32_t RESERVED1[2U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ uint32_t RESERVED2[313U]; __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ uint32_t RESERVED3[2U]; __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ uint32_t RESERVED4[44U]; __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ uint32_t RESERVED5[2U]; __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ } MemSysCtl_Type; /* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ #define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ #define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ #define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ #define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ #define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ #define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ #define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ #define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ #define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ #define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ #define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ #define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ #define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ #define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ #define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ #define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ /* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ #define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ #define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ #define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ #define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ #define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ #define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ #define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ #define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ /* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ #define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ #define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ #define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ #define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ /* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ #define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ #define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ #define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ #define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ /* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ #define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ #define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ #define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ #define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ /* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ #define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ #define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ #define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ #define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ /* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ #define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ #define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ #define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ #define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ /* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ #define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ #define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ #define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ #define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ /* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ #define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ #define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ #define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ #define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ /*@}*/ /* end of group MemSysCtl_Type */ /** \ingroup CMSIS_core_register \defgroup PwrModCtl_Type Power Mode Control Registers \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) @{ */ /** \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). */ typedef struct { __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ } PwrModCtl_Type; /* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ /* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ /*@}*/ /* end of group PwrModCtl_Type */ /** \ingroup CMSIS_core_register \defgroup EWIC_Type External Wakeup Interrupt Controller Registers \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) @{ */ /** \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). */ typedef struct { __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ uint32_t RESERVED0[124U]; __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ uint32_t RESERVED1[112U]; __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ uint32_t RESERVED2[112U]; __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ } EWIC_Type; /* EWIC Control (EWIC_CR) Register Definitions */ #define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ #define EWIC_EWIC_CR_EN_Msk (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ /* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */ #define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ #define EWIC_EWIC_ASCR_ASPU_Msk (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ #define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ #define EWIC_EWIC_ASCR_ASPD_Msk (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ /* EWIC Event Number ID (EWIC_NUMID) Register Definitions */ #define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ #define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ /* EWIC Mask A (EWIC_MASKA) Register Definitions */ #define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ #define EWIC_EWIC_MASKA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ #define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ #define EWIC_EWIC_MASKA_NMI_Msk (0x1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ #define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ #define EWIC_EWIC_MASKA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ /* EWIC Mask n (EWIC_MASKn) Register Definitions */ #define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ #define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ /* EWIC Pend A (EWIC_PENDA) Register Definitions */ #define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ #define EWIC_EWIC_PENDA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ #define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ #define EWIC_EWIC_PENDA_NMI_Msk (0x1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ #define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ #define EWIC_EWIC_PENDA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ /* EWIC Pend n (EWIC_PENDn) Register Definitions */ #define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ #define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ /* EWIC Pend Summary (EWIC_PSR) Register Definitions */ #define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ #define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ #define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ #define EWIC_EWIC_PSR_NZA_Msk (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ /*@}*/ /* end of group EWIC_Type */ /** \ingroup CMSIS_core_register \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) @{ */ /** \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). */ typedef struct { __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ uint32_t RESERVED0[31U]; __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ } EWIC_ISA_Type; /* EWIC_ISA Event Set Pending (EVENTSPR) Register Definitions */ #define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ #define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ #define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ #define EWIC_ISA_EVENTSPR_NMI_Msk (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ #define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ #define EWIC_ISA_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ /* EWIC_ISA Event Mask A (EVENTMASKA) Register Definitions */ #define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ #define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ #define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ #define EWIC_ISA_EVENTMASKA_NMI_Msk (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ #define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ #define EWIC_ISA_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ /* EWIC_ISA Event Mask n (EVENTMASKn) Register Definitions */ #define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ #define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ /*@}*/ /* end of group EWIC_ISA_Type */ /** \ingroup CMSIS_core_register \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Error Banking Registers (ERRBNK) @{ */ /** \brief Structure type to access the Error Banking Registers (ERRBNK). */ typedef struct { __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ uint32_t RESERVED0[2U]; __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ uint32_t RESERVED1[2U]; __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ } ErrBnk_Type; /* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ #define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ #define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ #define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ #define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ #define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ /* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ #define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ #define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ #define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ #define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ #define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ /* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ #define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ #define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ #define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ #define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ #define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ #define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ /* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ #define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ #define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ #define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ #define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ #define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ #define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ /* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ #define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ #define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ #define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ #define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ #define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ #define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ #define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ #define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ /* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ #define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ #define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ #define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ #define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ #define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ #define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ #define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ #define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ /*@}*/ /* end of group ErrBnk_Type */ /** \ingroup CMSIS_core_register \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) @{ */ /** \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). */ typedef struct { __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ } PrcCfgInf_Type; /* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ /* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ /*@}*/ /* end of group PrcCfgInf_Type */ /** \ingroup CMSIS_core_register \defgroup STL_Type Software Test Library Observation Registers \brief Type definitions for the Software Test Library Observation Registerss (STL) @{ */ /** \brief Structure type to access the Software Test Library Observation Registerss (STL). */ typedef struct { __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ uint32_t RESERVED0[2U]; __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ } STL_Type; /* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ #define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ #define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ #define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ #define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ #define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ #define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ #define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ #define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ /* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ #define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ #define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ #define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ #define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ #define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ #define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ #define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ #define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ /* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ #define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ #define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ #define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ #define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ #define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ #define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ /* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ #define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ #define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ #define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ #define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ /* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ #define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ #define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ #define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ #define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ /* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ #define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ #define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ #define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ #define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ /*@}*/ /* end of group STL_Type */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) \brief Type definitions for the Performance Monitoring Unit (PMU) @{ */ /** \brief Structure type to access the Performance Monitoring Unit (PMU). */ typedef struct { __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ uint32_t RESERVED1[224]; __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ uint32_t RESERVED3[480]; __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ uint32_t RESERVED4[7]; __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ uint32_t RESERVED5[7]; __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ uint32_t RESERVED6[7]; __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ uint32_t RESERVED7[7]; __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ uint32_t RESERVED8[7]; __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ uint32_t RESERVED9[7]; __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ uint32_t RESERVED10[79]; __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ uint32_t RESERVED11[108]; __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ uint32_t RESERVED12[3]; __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ uint32_t RESERVED13[3]; __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ } PMU_Type; /** \brief PMU Event Counter Registers (0-30) Definitions */ #define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ /** \brief PMU Event Type and Filter Registers (0-30) Definitions */ #define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ /** \brief PMU Count Enable Set Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ /** \brief PMU Count Enable Clear Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ /** \brief PMU Interrupt Enable Set Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ /** \brief PMU Interrupt Enable Clear Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ /** \brief PMU Overflow Flag Status Set Register Definitions */ #define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ #define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ #define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ #define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ #define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ #define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ #define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ #define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ #define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ #define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ #define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ #define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ #define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ #define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ #define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ #define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ #define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ #define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ #define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ #define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ #define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ #define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ #define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ #define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ #define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ #define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ #define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ #define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ #define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ #define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ #define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ /** \brief PMU Overflow Flag Status Clear Register Definitions */ #define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ #define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ #define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ #define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ #define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ #define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ #define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ #define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ #define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ #define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ #define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ #define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ #define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ #define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ #define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ #define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ #define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ #define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ #define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ #define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ #define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ #define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ #define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ #define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ #define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ #define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ #define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ #define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ #define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ #define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ #define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ /** \brief PMU Software Increment Counter */ #define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ #define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ #define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ #define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ #define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ #define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ #define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ #define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ #define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ #define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ #define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ #define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ #define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ #define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ #define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ #define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ #define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ #define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ #define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ #define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ #define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ #define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ #define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ #define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ #define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ #define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ #define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ #define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ #define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ #define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ #define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ /** \brief PMU Control Register Definitions */ #define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ #define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ #define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ #define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ #define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ /** \brief PMU Type Register Definitions */ #define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ #define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ /** \brief PMU Authentication Status Register Definitions */ #define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ /*@} end of group CMSIS_PMU */ #endif #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ #define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ #define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Set Clear Exception and Monitor Control Register Definitions */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ #define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ #define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { uint32_t RESERVED0[2U]; __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ uint32_t RESERVED1[3U]; __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ } DIB_Type; /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ #define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ /* 'SCnSCB' is deprecated and replaced by 'ICB' */ typedef ICB_Type SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) #define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) #define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) #define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) #define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) #define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) #define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) #define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) #define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) #define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) #define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) #define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) #define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) #define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) #define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) #define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) #define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) #define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) #define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) #define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) #define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) #define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) #define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) #define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) #define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) #define SCnSCB (ICB) #define SCnSCB_NS (ICB_NS) /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## PMU functions and events #################################### */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #include "pmu_armv8.h" /** \brief Cortex-M55 PMU events \note Architectural PMU events can be found in pmu_armv8.h */ #define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ #define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ #define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ #define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ #define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ #define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ #define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ #define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ #define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ #define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ #define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ #define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ #define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ #define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ #define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ #define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ #define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ #define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ #define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ #define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ #define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ #define ARMCM55_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ #define ARMCM55_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ #define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ #define ARMCM55_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ #define ARMCM55_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ #define ARMCM55_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ #define ARMCM55_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ #define ARMCM55_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ #define ARMCM55_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ #define ARMCM55_PMU_PF_LF_LA_1 0xC41C /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */ #define ARMCM55_PMU_PF_LF_LA_2 0xC41D /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */ #define ARMCM55_PMU_PF_LF_LA_3 0xC41E /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */ #define ARMCM55_PMU_PF_LF_LA_4 0xC41F /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */ #define ARMCM55_PMU_PF_LF_LA_5 0xC420 /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */ #define ARMCM55_PMU_PF_LF_LA_6 0xC421 /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */ #define ARMCM55_PMU_PF_BUFFER_FULL 0xC422 /*!< A data prefetcher request is made while the buffer is full. */ #define ARMCM55_PMU_PF_BUFFER_MISS 0xC423 /*!< A load requires a line-fill which misses in the data prefetcher buffer. */ #define ARMCM55_PMU_PF_BUFFER_HIT 0xC424 /*!< A load access hits in the data prefetcher buffer. */ #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## MVE functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_MveFunctions MVE Functions \brief Function that provides MVE type. @{ */ /** \brief get MVE type \details returns the MVE type \returns - \b 0: No Vector Extension (MVE) - \b 1: Integer Vector Extension (MVE-I) - \b 2: Floating-point Vector Extension (MVE-F) */ __STATIC_INLINE uint32_t SCB_GetMVEType(void) { const uint32_t mvfr1 = FPU->MVFR1; if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) { return 2U; } else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) { return 1U; } else { return 0U; } } /*@} end of CMSIS_Core_MveFunctions */ /* ########################## Cache functions #################################### */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) #include "cachel1_armv7.h" #endif /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM55_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm7.h ================================================ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.2.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ #include "cmsis_version.h" /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ uint32_t RESERVED7[5U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ #define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ #define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ #define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ #define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ /* Capitalize ITM_TCR Register Definitions */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos) /*!< \deprecated ITM_TCR_TraceBusID_Pos */ #define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk) /*!< \deprecated ITM_TCR_TraceBusID_Msk */ #define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos) /*!< \deprecated ITM_TCR_TSPrescale_Pos */ #define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk) /*!< \deprecated ITM_TCR_TSPrescale_Msk */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos) /*!< \deprecated ITM_LSR_ByteAcc_Pos */ #define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk) /*!< \deprecated ITM_LSR_ByteAcc_Msk */ #define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos) /*!< \deprecated ITM_LSR_Access_Pos */ #define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk) /*!< \deprecated ITM_LSR_Access_Msk */ #define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos) /*!< \deprecated ITM_LSR_Present_Pos */ #define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk) /*!< \deprecated ITM_LSR_Present_Msk */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) #include "cachel1_armv7.h" #endif /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_cm85.h ================================================ /**************************************************************************//** * @file core_cm85.h * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File * @version V1.3.1 * @date 19. April 2023 ******************************************************************************/ /* * Copyright (c) 2022-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM85_H_GENERIC #define __CORE_CM85_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M85 @{ */ #include "cmsis_version.h" /* CMSIS CM85 definitions */ #define __CORTEX_M (85U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #error Legacy Arm Compiler does not support Armv8.1-M target architecture. #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM85_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM85_H_DEPENDANT #define __CORE_CM85_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM85_REV #define __CM85_REV 0x0001U #warning "__CM85_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #if __FPU_PRESENT != 0U #ifndef __FPU_DP #define __FPU_DP 0U #warning "__FPU_DP not defined in device header file; using default!" #endif #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __PMU_PRESENT #define __PMU_PRESENT 0U #warning "__PMU_PRESENT not defined in device header file; using default!" #endif #if __PMU_PRESENT != 0U #ifndef __PMU_NUM_EVENTCNT #define __PMU_NUM_EVENTCNT 8U #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ #endif #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M85 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core EWIC Register - Core EWIC Interrupt Status Access Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core PMU Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:1; /*!< bit: 20 Reserved */ uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_B_Pos 21U /*!< xPSR: B Position */ #define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ #define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ #define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ #define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ #define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ #define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ #define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ #define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED7[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ uint32_t RESERVED4[14U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ /* SCB Debug Feature Register 0 Definitions */ #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB RAS Fault Status Register Definitions */ #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ICB Implementation Control Block register (ICB) \brief Type definitions for the Implementation Control Block Register @{ */ /** \brief Structure type to access the Implementation Control Block (ICB). */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } ICB_Type; /* Auxiliary Control Register Definitions */ #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ #define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ #define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ #define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ #define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ #define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ #define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ #define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ #define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ #define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ /* Interrupt Controller Type Register Definitions */ #define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_ICB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[27U]; __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) ITM Integration Read Register */ uint32_t RESERVED4[1U]; __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ uint32_t RESERVED5[1U]; __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED6[46U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED7[3U]; __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Read Register Definitions */ #define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ #define ITM_ITREAD_AFVALID_Msk (0x1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ #define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ #define ITM_ITREAD_ATREADY_Msk (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ /* ITM Integration Write Register Definitions */ #define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ #define ITM_ITWRITE_AFVALID_Msk (0x1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ #define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ #define ITM_ITWRITE_ATREADY_Msk (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ #define ITM_ITCTRL_IME_Msk (0x1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED4[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED6[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED14[968U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ uint32_t RESERVED15[3U]; __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) @{ */ /** \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). */ typedef struct { __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ uint32_t RESERVED1[2U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ uint32_t RESERVED2[313U]; __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ uint32_t RESERVED3[2U]; __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ uint32_t RESERVED4[44U]; __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ uint32_t RESERVED5[2U]; __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ } MemSysCtl_Type; /* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ #define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ #define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ #define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ #define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ #define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ #define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ #define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ #define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ #define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ #define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ #define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ #define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ #define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ #define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ /* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ #define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ #define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ #define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ #define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ /* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ #define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ #define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ #define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ #define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ /* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ #define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ #define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ #define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ #define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ /* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ #define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ #define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ #define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ #define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ /* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ #define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ #define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ #define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ #define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ /* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ #define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ #define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ #define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ #define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ #define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ /* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ #define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ #define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ #define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ #define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ /* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ #define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ #define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ #define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ #define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ #define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ /*@}*/ /* end of group MemSysCtl_Type */ /** \ingroup CMSIS_core_register \defgroup PwrModCtl_Type Power Mode Control Registers \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) @{ */ /** \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). */ typedef struct { __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ } PwrModCtl_Type; /* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ #define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ /* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ #define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ /*@}*/ /* end of group PwrModCtl_Type */ /** \ingroup CMSIS_core_register \defgroup EWIC_Type External Wakeup Interrupt Controller Registers \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) @{ */ /** \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). */ typedef struct { __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ uint32_t RESERVED0[124U]; __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ uint32_t RESERVED1[112U]; __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ uint32_t RESERVED2[112U]; __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ } EWIC_Type; /* EWIC Control (EWIC_CR) Register Definitions */ #define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ #define EWIC_EWIC_CR_EN_Msk (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ /* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */ #define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ #define EWIC_EWIC_ASCR_ASPU_Msk (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ #define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ #define EWIC_EWIC_ASCR_ASPD_Msk (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ /* EWIC Event Number ID (EWIC_NUMID) Register Definitions */ #define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ #define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ /* EWIC MaskA (EWIC_MASKA) Register Definitions */ #define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ #define EWIC_EWIC_MASKA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ #define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ #define EWIC_EWIC_MASKA_NMI_Msk (0x1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ #define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ #define EWIC_EWIC_MASKA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ /* EWIC Mask n (EWIC_MASKn) Register Definitions */ #define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ #define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ /* EWIC PendA (EWIC_PENDA) Register Definitions */ #define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ #define EWIC_EWIC_PENDA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ #define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ #define EWIC_EWIC_PENDA_NMI_Msk (0x1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ #define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ #define EWIC_EWIC_PENDA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ /* EWIC Pend n (EWIC_PENDn) Register Definitions */ #define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ #define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ /* EWIC Pend Summary (EWIC_PSR) Register Definitions */ #define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ #define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ #define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ #define EWIC_EWIC_PSR_NZA_Msk (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ /*@}*/ /* end of group EWIC_Type */ /** \ingroup CMSIS_core_register \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) @{ */ /** \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). */ typedef struct { __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ uint32_t RESERVED0[31U]; __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ } EWIC_ISA_Type; /* EWIC_ISA Event Set Pending (EVENTSPR) Register Definitions */ #define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ #define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ #define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ #define EWIC_ISA_EVENTSPR_NMI_Msk (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ #define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ #define EWIC_ISA_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ /* EWIC_ISA Event Mask A (EVENTMASKA) Register Definitions */ #define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ #define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ #define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ #define EWIC_ISA_EVENTMASKA_NMI_Msk (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ #define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ #define EWIC_ISA_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ /* EWIC_ISA Event Mask n (EVENTMASKn) Register Definitions */ #define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ #define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ /*@}*/ /* end of group EWIC_ISA_Type */ /** \ingroup CMSIS_core_register \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Error Banking Registers (ERRBNK) @{ */ /** \brief Structure type to access the Error Banking Registers (ERRBNK). */ typedef struct { __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ uint32_t RESERVED0[2U]; __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ uint32_t RESERVED1[2U]; __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ } ErrBnk_Type; /* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ #define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ #define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ #define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ #define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ #define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ /* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ #define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ #define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ #define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ #define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ #define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ /* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ #define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ #define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ #define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ #define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ #define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ #define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ /* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ #define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ #define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ #define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ #define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ #define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ #define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ /* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ #define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ #define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ #define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ #define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ #define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ #define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ #define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ #define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ /* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ #define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ #define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ #define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ #define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ #define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ #define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ #define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ #define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ /*@}*/ /* end of group ErrBnk_Type */ /** \ingroup CMSIS_core_register \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) @{ */ /** \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). */ typedef struct { __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ } PrcCfgInf_Type; /* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ /* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ /*@}*/ /* end of group PrcCfgInf_Type */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) \brief Type definitions for the Performance Monitoring Unit (PMU) @{ */ /** \brief Structure type to access the Performance Monitoring Unit (PMU). */ typedef struct { __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ uint32_t RESERVED1[224]; __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ #if __PMU_NUM_EVENTCNT<31 uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; #endif __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ uint32_t RESERVED3[480]; __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ uint32_t RESERVED4[7]; __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ uint32_t RESERVED5[7]; __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ uint32_t RESERVED6[7]; __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ uint32_t RESERVED7[7]; __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ uint32_t RESERVED8[7]; __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ uint32_t RESERVED9[7]; __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ uint32_t RESERVED10[79]; __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ uint32_t RESERVED11[108]; __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ uint32_t RESERVED12[3]; __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ uint32_t RESERVED13[3]; __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ } PMU_Type; /** \brief PMU Event Counter Registers (0-30) Definitions */ #define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ /** \brief PMU Event Type and Filter Registers (0-30) Definitions */ #define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ /** \brief PMU Count Enable Set Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ /** \brief PMU Count Enable Clear Register Definitions */ #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ /** \brief PMU Interrupt Enable Set Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ #define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ /** \brief PMU Interrupt Enable Clear Register Definitions */ #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ /** \brief PMU Overflow Flag Status Set Register Definitions */ #define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ #define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ #define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ #define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ #define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ #define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ #define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ #define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ #define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ #define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ #define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ #define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ #define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ #define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ #define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ #define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ #define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ #define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ #define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ #define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ #define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ #define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ #define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ #define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ #define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ #define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ #define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ #define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ #define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ #define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ #define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ /** \brief PMU Overflow Flag Status Clear Register Definitions */ #define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ #define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ #define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ #define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ #define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ #define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ #define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ #define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ #define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ #define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ #define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ #define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ #define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ #define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ #define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ #define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ #define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ #define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ #define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ #define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ #define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ #define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ #define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ #define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ #define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ #define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ #define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ #define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ #define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ #define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ #define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ /** \brief PMU Software Increment Counter */ #define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ #define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ #define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ #define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ #define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ #define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ #define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ #define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ #define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ #define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ #define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ #define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ #define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ #define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ #define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ #define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ #define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ #define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ #define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ #define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ #define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ #define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ #define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ #define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ #define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ #define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ #define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ #define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ #define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ #define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ #define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ /** \brief PMU Control Register Definitions */ #define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ #define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ #define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ #define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ #define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ /** \brief PMU Type Register Definitions */ #define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ #define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ /** \brief PMU Authentication Status Register Definitions */ #define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ #define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ #define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ #define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ /*@} end of group CMSIS_PMU */ #endif #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ #define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ #define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Set Clear Exception and Monitor Control Register Definitions */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ #define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ #define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { uint32_t RESERVED0[2U]; __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ uint32_t RESERVED1[3U]; __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ } DIB_Type; /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ #define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## PMU functions and events #################################### */ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) #include "pmu_armv8.h" /** \brief Cortex-M85 PMU events \note Architectural PMU events can be found in pmu_armv8.h */ #define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ #define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ #define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ #define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ #define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ #define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ #define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ #define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ #define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ #define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ #define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ #define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ #define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ #define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ #define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ #define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ #define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ #define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ #define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ #define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ #define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ #define ARMCM85_PMU_FUSED_INST_RETIRED 0xC500 /*!< Fused instructions architecturally executed */ #define ARMCM85_PMU_BR_INDIRECT 0xC501 /*!< Indirect branch instruction architecturally executed */ #define ARMCM85_PMU_BTAC_HIT 0xC502 /*!< BTAC branch predictor hit */ #define ARMCM85_PMU_BTAC_HIT_RETURNS 0xC503 /*!< Return branch hits BTAC */ #define ARMCM85_PMU_BTAC_HIT_CALLS 0xC504 /*!< Call branch hits BTAC */ #define ARMCM85_PMU_BTAC_HIT_INDIRECT 0xC505 /*!< Indirect branch hits BTACT */ #define ARMCM85_PMU_BTAC_NEW_ALLOC 0xC506 /*!< New allocation to BTAC */ #define ARMCM85_PMU_BR_IND_MIS_PRED 0xC507 /*!< Indirect branch mis-predicted */ #define ARMCM85_PMU_BR_RETURN_MIS_PRED 0xC508 /*!< Return branch mis-predicted */ #define ARMCM85_PMU_BR_BTAC_OFFSET_OVERFLOW 0xC509 /*!< Branch does not allocate in BTAC due to offset overflow */ #define ARMCM85_PMU_STB_FULL_STALL_AXI 0xC50A /*!< STore Buffer (STB) full with AXI requests causing CPU to stall */ #define ARMCM85_PMU_STB_FULL_STALL_TCM 0xC50B /*!< STB full with TCM requests causing CPU to stall */ #define ARMCM85_PMU_CPU_STALLED_AHBS 0xC50C /*!< CPU is stalled because TCM access through AHBS */ #define ARMCM85_PMU_AHBS_STALLED_CPU 0xC50D /*!< AHBS is stalled due to TCM access by CPU */ #define ARMCM85_PMU_BR_INTERSTATING_MIS_PRED 0xC50E /*!< Inter-stating branch is mis-predicted. */ #define ARMCM85_PMU_DWT_STALL 0xC50F /*!< Data Watchpoint and Trace (DWT) stall */ #define ARMCM85_PMU_DWT_FLUSH 0xC510 /*!< DWT flush */ #define ARMCM85_PMU_ETM_STALL 0xC511 /*!< Embedded Trace Macrocell (ETM) stall */ #define ARMCM85_PMU_ETM_FLUSH 0xC512 /*!< ETM flush */ #define ARMCM85_PMU_ADDRESS_BANK_CONFLICT 0xC513 /*!< Bank conflict prevents memory instruction dual issue */ #define ARMCM85_PMU_BLOCKED_DUAL_ISSUE 0xC514 /*!< Dual instruction issuing is prevented */ #define ARMCM85_PMU_FP_CONTEXT_TRIGGER 0xC515 /*!< Floating Point Context is created */ #define ARMCM85_PMU_TAIL_CHAIN 0xC516 /*!< New exception is handled without first unstacking */ #define ARMCM85_PMU_LATE_ARRIVAL 0xC517 /*!< Late-arriving exception taken during exception entry */ #define ARMCM85_PMU_INT_STALL_FAULT 0xC518 /*!< Delayed exception entry due to ongoing fault processing */ #define ARMCM85_PMU_INT_STALL_DEV 0xC519 /*!< Delayed exception entry due to outstanding device access */ #define ARMCM85_PMU_PAC_STALL 0xC51A /*!< Stall caused by authentication code computation */ #define ARMCM85_PMU_PAC_RETIRED 0xC51B /*!< PAC instruction architecturally executed */ #define ARMCM85_PMU_AUT_RETIRED 0xC51C /*!< AUT instruction architecturally executed */ #define ARMCM85_PMU_BTI_RETIRED 0xC51D /*!< BTI instruction architecturally executed */ #define ARMCM85_PMU_PF_NL_MODE 0xC51E /*!< Prefetch in next line mode */ #define ARMCM85_PMU_PF_STREAM_MODE 0xC51F /*!< Prefetch in stream mode */ #define ARMCM85_PMU_PF_BUFF_CACHE_HIT 0xC520 /*!< Prefetch request that hit in the cache */ #define ARMCM85_PMU_PF_REQ_LFB_HIT 0xC521 /*!< Prefetch request that hit in line fill buffers */ #define ARMCM85_PMU_PF_BUFF_FULL 0xC522 /*!< Number of times prefetch buffer is full */ #define ARMCM85_PMU_PF_REQ_DCACHE_HIT 0xC523 /*!< Generated prefetch request address that hit in D-Cache */ #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## MVE functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_MveFunctions MVE Functions \brief Function that provides MVE type. @{ */ /** \brief get MVE type \details returns the MVE type \returns - \b 0: No Vector Extension (MVE) - \b 1: Integer Vector Extension (MVE-I) - \b 2: Floating-point Vector Extension (MVE-F) */ __STATIC_INLINE uint32_t SCB_GetMVEType(void) { const uint32_t mvfr1 = FPU->MVFR1; if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) { return 2U; } else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) { return 1U; } else { return 0U; } } /*@} end of CMSIS_Core_MveFunctions */ /* ########################## Cache functions #################################### */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) #include "cachel1_armv7.h" #endif /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################### PAC Key functions ########################### */ #if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) #include "pac_armv81.h" #endif /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM85_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined (__ARM_FP) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ti__) #if defined (__ARM_FP) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 1U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /** \ingroup CMSIS_core_register \defgroup CMSIS_register_aliases Backwards Compatibility Aliases \brief Register alias definitions for backwards compatibility. @{ */ /* Capitalize ITM_TCR Register Definitions */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_TraceBusID_Pos (ITM_TCR_TRACEBUSID_Pos) /*!< \deprecated ITM_TCR_TraceBusID_Pos */ #define ITM_TCR_TraceBusID_Msk (ITM_TCR_TRACEBUSID_Msk) /*!< \deprecated ITM_TCR_TraceBusID_Msk */ #define ITM_TCR_TSPrescale_Pos (ITM_TCR_TSPRESCALE_Pos) /*!< \deprecated ITM_TCR_TSPrescale_Pos */ #define ITM_TCR_TSPrescale_Msk (ITM_TCR_TSPRESCALE_Msk) /*!< \deprecated ITM_TCR_TSPrescale_Msk */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos (ITM_LSR_BYTEACC_Pos) /*!< \deprecated ITM_LSR_ByteAcc_Pos */ #define ITM_LSR_ByteAcc_Msk (ITM_LSR_BYTEACC_Msk) /*!< \deprecated ITM_LSR_ByteAcc_Msk */ #define ITM_LSR_Access_Pos (ITM_LSR_ACCESS_Pos) /*!< \deprecated ITM_LSR_Access_Pos */ #define ITM_LSR_Access_Msk (ITM_LSR_ACCESS_Msk) /*!< \deprecated ITM_LSR_Access_Msk */ #define ITM_LSR_Present_Pos (ITM_LSR_PRESENT_Pos) /*!< \deprecated ITM_LSR_Present_Pos */ #define ITM_LSR_Present_Msk (ITM_LSR_PRESENT_Msk) /*!< \deprecated ITM_LSR_Present_Msk */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/core_starmc1.h ================================================ /**************************************************************************//** * @file core_starmc1.h * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File * @version V1.1.0 * @date 04. April 2023 ******************************************************************************/ /* * Copyright (c) 2009-2013 Arm Limited. * Copyright (c) 2018-2022 Arm China. * All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #elif defined ( __GNUC__ ) #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_STAR_H_GENERIC #define __CORE_STAR_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup STAR-MC1 @{ */ #include "cmsis_version.h" /* Macro Define for STAR-MC1 */ #define __STAR_MC (1U) /*!< STAR-MC Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ti__) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_STAR_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_STAR_H_DEPENDANT #define __CORE_STAR_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __STAR_REV #define __STAR_REV 0x0000U #warning "__STAR_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group STAR-MC1 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for STAR-MC1 processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED_ADD1[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; typedef struct { __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ }EMSS_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ #define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ #define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache line Invalidate by Set-way Register Definitions */ #define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean line by Set-way Register Definitions */ #define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* ArmChina: Implementation Defined */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ #define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ #define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and VFP Feature Register 2 Definitions */ #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DCB Debug Control Block \brief Type definitions for the Debug Control Block Registers @{ */ /** \brief Structure type to access the Debug Control Block Registers (DCB). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } DCB_Type; /* DHCSR, Debug Halting Control and Status Register Definitions */ #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ /* DCRSR, Debug Core Register Select Register Definitions */ #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ /* DCRDR, Debug Core Register Data Register Definitions */ #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ /* DEMCR, Debug Exception and Monitor Control Register Definitions */ #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ /* DAUTHCTRL, Debug Authentication Control Register Definitions */ #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ /* DSCSR, Debug Security Control and Status Register Definitions */ #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ /*@} end of group CMSIS_DCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DIB Debug Identification Block \brief Type definitions for the Debug Identification Block Registers @{ */ /** \brief Structure type to access the Debug Identification Block Registers (DIB). */ typedef struct { __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ } DIB_Type; /* DLAR, SCS Software Lock Access Register Definitions */ #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ /* DLSR, SCS Software Lock Status Register Definitions */ #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ /* DDEVARCH, SCS Device Architecture Register Definitions */ #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ /* DDEVTYPE, SCS Device Type Register Definitions */ #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ /*@} end of group CMSIS_DIB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses including buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /** \brief Software Reset \details Initiates a system reset request to reset the CPU. */ __NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses including buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ SCB_AIRCR_SYSRESETREQ_Msk ); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## Debug Control function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DCBFunctions Debug Control Functions \brief Functions that access the Debug Control Block. @{ */ /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. \param [in] value value to be writen. */ __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) { __DSB(); __ISB(); DCB->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register \details Reads Debug Authentication Control register. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) { return (DCB->DAUTHCTRL); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Debug Authentication Control Register (non-secure) \details writes to non-secure Debug Authentication Control register when in secure state. \param [in] value value to be writen */ __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) { __DSB(); __ISB(); DCB_NS->DAUTHCTRL = value; __DSB(); __ISB(); } /** \brief Get Debug Authentication Control Register (non-secure) \details Reads non-secure Debug Authentication Control register when in secure state. \return Debug Authentication Control Register. */ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) { return (DCB_NS->DAUTHCTRL); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ /* ################################## Debug Identification function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions \brief Functions that access the Debug Identification Block. @{ */ /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) { return (DIB->DAUTHSTATUS); } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Debug Authentication Status Register (non-secure) \details Reads non-secure Debug Authentication Status register when in secure state. \return Debug Authentication Status Register. */ __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) { return (DIB_NS->DAUTHSTATUS); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_DCBFunctions */ #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_FORCEINLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief I-Cache Invalidate by address \details Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] isize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if ( isize > 0 ) { int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_ICACHE_LINE_SIZE; op_size -= __SCB_ICACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_FORCEINLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /*@} end of CMSIS_Core_CacheFunctions */ #endif /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_STAR_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h ================================================ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU * @version V5.1.2 * @date 25. May 2020 ******************************************************************************/ /* * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * * \param Region The region to be configured, number 0 to 15. * \param BaseAddress The base address for the region. */ #define ARM_MPU_RBAR(Region, BaseAddress) \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) /** * MPU Memory Access Attributes * * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. */ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (((MPU_RASR_ENABLE_Msk)))) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) /** * MPU Memory Access Attribute for strongly ordered memory. * - TEX: 000b * - Shareable * - Non-cacheable * - Non-bufferable */ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** * MPU Memory Access Attribute for device memory. * - TEX: 000b (if shareable) or 010b (if non-shareable) * - Shareable or non-shareable * - Non-cacheable * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** * MPU Memory Access Attribute for normal memory. * - TEX: 1BBb (reflecting outer cacheability rules) * - Shareable or non-shareable * - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules) * * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) /** * MPU Memory Access Attribute non-cacheable policy. */ #define ARM_MPU_CACHEP_NOCACHE 0U /** * MPU Memory Access Attribute write-back, write and read allocate policy. */ #define ARM_MPU_CACHEP_WB_WRA 1U /** * MPU Memory Access Attribute write-through, no write allocate policy. */ #define ARM_MPU_CACHEP_WT_NWA 2U /** * MPU Memory Access Attribute write-back, no write allocate policy. */ #define ARM_MPU_CACHEP_WB_NWA 3U /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DMB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; __DSB(); __ISB(); } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { MPU->RNR = rnr; MPU->RASR = 0U; } /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; MPU->RASR = rasr; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; MPU->RBAR = rbar; MPU->RASR = rasr; } /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h ================================================ /****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU * @version V5.9.0 * @date 11. April 2023 ******************************************************************************/ /* * Copyright (c) 2017-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H /** \brief Attribute for device memory (outer only) */ #define ARM_MPU_ATTR_DEVICE ( 0U ) /** \brief Attribute for non-cacheable, normal memory */ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) /** \brief Attribute for Normal memory, Outer and Inner cacheability. * \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. * \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. * \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. * \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGRE (2U) /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_GRE (3U) /** \brief Normal memory outer-cacheable and inner-cacheable attributes * WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate */ #define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) #define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) #define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) #define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) #define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) #define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) #define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) #define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) #define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) #define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) #define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) #define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) #define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) #define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) #define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) #define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) #define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) #define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) #define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) #define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) #define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) #define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) #define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) #define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) /** \brief Memory Attribute * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) /* \brief Specifies MAIR_ATTR number */ #define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) /** * Shareability */ /** \brief Normal memory, non-shareable */ #define ARM_MPU_SH_NON (0U) /** \brief Normal memory, outer shareable */ #define ARM_MPU_SH_OUTER (2U) /** \brief Normal memory, inner shareable */ #define ARM_MPU_SH_INNER (3U) /** * Access permissions * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only */ /** \brief Normal memory, read/write */ #define ARM_MPU_AP_RW (0U) /** \brief Normal memory, read-only */ #define ARM_MPU_AP_RO (1U) /** \brief Normal memory, any privilege level */ #define ARM_MPU_AP_NP (1U) /** \brief Normal memory, privileged access only */ #define ARM_MPU_AP_PO (0U) /* * Execute-never * XN = Execute-never, EX = Executable */ /** \brief Normal memory, Execution only permitted if read permitted */ #define ARM_MPU_XN (1U) /** \brief Normal memory, Execution only permitted if read permitted */ #define ARM_MPU_EX (0U) /** \brief Memory access permissions * \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. */ #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param SH Defines the Shareability domain for this memory region. * \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. * \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ (((BASE) & MPU_RBAR_BASE_Msk) | \ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #endif /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; /** \brief Read MPU Type Register \return Number of MPU regions */ __STATIC_INLINE uint32_t ARM_MPU_TYPE() { return ((MPU->TYPE) >> 8); } /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DMB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; __DSB(); __ISB(); } #ifdef MPU_NS /** Enable the Non-secure MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { __DMB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; __DSB(); __ISB(); } #endif /** Set the memory attribute encoding to the given MPU. * \param mpu Pointer to the MPU to be configured. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) { const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU, idx, attr); } #ifdef MPU_NS /** Set the memory attribute encoding to the Non-secure MPU. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); } #endif /** Clear and disable the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { mpu->RNR = rnr; mpu->RLAR = 0U; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU, rnr); } #ifdef MPU_NS /** Clear and disable the given Non-secure MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif /** Configure the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; mpu->RBAR = rbar; mpu->RLAR = rlar; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); } #ifdef MPU_NS /** Configure the given Non-secure MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table to the given MPU. * \param mpu Pointer to the MPU registers to be used. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } /** Load the given number of MPU regions from a table. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } #ifdef MPU_NS /** Load the given number of MPU regions from a table to the Non-secure MPU. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/pac_armv81.h ================================================ /****************************************************************************** * @file pac_armv81.h * @brief CMSIS PAC key functions for Armv8.1-M PAC extension * @version V1.0.0 * @date 23. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef PAC_ARMV81_H #define PAC_ARMV81_H /* ################### PAC Key functions ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions \brief Functions that access the PAC keys. @{ */ #if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) /** \brief read the PAC key used for privileged mode \details Reads the PAC key stored in the PAC_KEY_P registers. \param [out] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { __ASM volatile ( "mrs r1, pac_key_p_0\n" "str r1,[%0,#0]\n" "mrs r1, pac_key_p_1\n" "str r1,[%0,#4]\n" "mrs r1, pac_key_p_2\n" "str r1,[%0,#8]\n" "mrs r1, pac_key_p_3\n" "str r1,[%0,#12]\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief write the PAC key used for privileged mode \details writes the given PAC key to the PAC_KEY_P registers. \param [in] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { __ASM volatile ( "ldr r1,[%0,#0]\n" "msr pac_key_p_0, r1\n" "ldr r1,[%0,#4]\n" "msr pac_key_p_1, r1\n" "ldr r1,[%0,#8]\n" "msr pac_key_p_2, r1\n" "ldr r1,[%0,#12]\n" "msr pac_key_p_3, r1\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief read the PAC key used for unprivileged mode \details Reads the PAC key stored in the PAC_KEY_U registers. \param [out] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { __ASM volatile ( "mrs r1, pac_key_u_0\n" "str r1,[%0,#0]\n" "mrs r1, pac_key_u_1\n" "str r1,[%0,#4]\n" "mrs r1, pac_key_u_2\n" "str r1,[%0,#8]\n" "mrs r1, pac_key_u_3\n" "str r1,[%0,#12]\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief write the PAC key used for unprivileged mode \details writes the given PAC key to the PAC_KEY_U registers. \param [in] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { __ASM volatile ( "ldr r1,[%0,#0]\n" "msr pac_key_u_0, r1\n" "ldr r1,[%0,#4]\n" "msr pac_key_u_1, r1\n" "ldr r1,[%0,#8]\n" "msr pac_key_u_2, r1\n" "ldr r1,[%0,#12]\n" "msr pac_key_u_3, r1\n" : : "r" (pPacKey) : "memory", "r1" ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief read the PAC key used for privileged mode (non-secure) \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. \param [out] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { __ASM volatile ( "mrs r1, pac_key_p_0_ns\n" "str r1,[%0,#0]\n" "mrs r1, pac_key_p_1_ns\n" "str r1,[%0,#4]\n" "mrs r1, pac_key_p_2_ns\n" "str r1,[%0,#8]\n" "mrs r1, pac_key_p_3_ns\n" "str r1,[%0,#12]\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief write the PAC key used for privileged mode (non-secure) \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. \param [in] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { __ASM volatile ( "ldr r1,[%0,#0]\n" "msr pac_key_p_0_ns, r1\n" "ldr r1,[%0,#4]\n" "msr pac_key_p_1_ns, r1\n" "ldr r1,[%0,#8]\n" "msr pac_key_p_2_ns, r1\n" "ldr r1,[%0,#12]\n" "msr pac_key_p_3_ns, r1\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief read the PAC key used for unprivileged mode (non-secure) \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. \param [out] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { __ASM volatile ( "mrs r1, pac_key_u_0_ns\n" "str r1,[%0,#0]\n" "mrs r1, pac_key_u_1_ns\n" "str r1,[%0,#4]\n" "mrs r1, pac_key_u_2_ns\n" "str r1,[%0,#8]\n" "mrs r1, pac_key_u_3_ns\n" "str r1,[%0,#12]\n" : : "r" (pPacKey) : "memory", "r1" ); } /** \brief write the PAC key used for unprivileged mode (non-secure) \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. \param [in] pPacKey 128bit PAC key */ __STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { __ASM volatile ( "ldr r1,[%0,#0]\n" "msr pac_key_u_0_ns, r1\n" "ldr r1,[%0,#4]\n" "msr pac_key_u_1_ns, r1\n" "ldr r1,[%0,#8]\n" "msr pac_key_u_2_ns, r1\n" "ldr r1,[%0,#12]\n" "msr pac_key_u_3_ns, r1\n" : : "r" (pPacKey) : "memory", "r1" ); } #endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ #endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ /*@} end of CMSIS_Core_PacKeyFunctions */ #endif /* PAC_ARMV81_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h ================================================ /****************************************************************************** * @file pmu_armv8.h * @brief CMSIS PMU API for Armv8.1-M PMU * @version V1.0.1 * @date 15. April 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_PMU_ARMV8_H #define ARM_PMU_ARMV8_H /** * \brief PMU Events * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. * */ #define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ #define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ #define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ #define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ #define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ #define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ #define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ #define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ #define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ #define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ #define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ #define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ #define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ #define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ #define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ #define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ #define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ #define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ #define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ #define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ #define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ #define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ #define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ #define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ #define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ #define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ #define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ #define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ #define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ #define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ #define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ #define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ #define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ #define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ #define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ #define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ #define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ #define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ #define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ #define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ #define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ #define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ #define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ #define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ #define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ #define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ #define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ #define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ #define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ #define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ #define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ #define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ #define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ #define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ #define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ #define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ #define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ #define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ #define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ #define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ #define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ #define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ #define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ #define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ #define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ #define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ #define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ #define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ #define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ #define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ #define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ #define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ #define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ #define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ #define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ #define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ #define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ #define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ #define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ #define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ #define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ #define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ #define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ #define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ #define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ #define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ #define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ #define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ #define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ #define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ #define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ #define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ #define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ #define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ #define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ #define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ #define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ #define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ #define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ #define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ #define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ #define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ #define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ #define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ #define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ #define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ #define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ #define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ #define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ #define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ #define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ #define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ #define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ #define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ #define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ #define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ #define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ #define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ #define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ #define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ #define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ #define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ #define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ #define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ #define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ #define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ #define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ #define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ #define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ /** \brief PMU Functions */ __STATIC_INLINE void ARM_PMU_Enable(void); __STATIC_INLINE void ARM_PMU_Disable(void); __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); /** \brief Enable the PMU */ __STATIC_INLINE void ARM_PMU_Enable(void) { PMU->CTRL |= PMU_CTRL_ENABLE_Msk; } /** \brief Disable the PMU */ __STATIC_INLINE void ARM_PMU_Disable(void) { PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; } /** \brief Set event to count for PMU eventer counter \param [in] num Event counter (0-30) to configure \param [in] type Event to count */ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) { PMU->EVTYPER[num] = type; } /** \brief Reset cycle counter */ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) { PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; } /** \brief Reset all event counters */ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) { PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; } /** \brief Enable counters \param [in] mask Counters to enable \note Enables one or more of the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) { PMU->CNTENSET = mask; } /** \brief Disable counters \param [in] mask Counters to enable \note Disables one or more of the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) { PMU->CNTENCLR = mask; } /** \brief Read cycle counter \return Cycle count */ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) { return PMU->CCNTR; } /** \brief Read event counter \param [in] num Event counter (0-30) to read \return Event count */ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) { return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; } /** \brief Read counter overflow status \return Counter overflow status bits for the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) { return PMU->OVSSET; } /** \brief Clear counter overflow status \param [in] mask Counter overflow status bits to clear \note Clears overflow status bits for one or more of the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) { PMU->OVSCLR = mask; } /** \brief Enable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to set \note Sets overflow interrupt request bits for one or more of the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) { PMU->INTENSET = mask; } /** \brief Disable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to clear \note Clears overflow interrupt request bits for one or more of the following: - event counters (0-30) - cycle counter */ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) { PMU->INTENCLR = mask; } /** \brief Software increment event counter \param [in] mask Counters to increment \note Software increment bits for one or more event counters (0-30) */ __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) { PMU->SWINC = mask; } #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core/Include/tz_context.h ================================================ /****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c ================================================ /****************************************************************************** * @file main_s.c * @brief Code template for secure main function * @version V1.1.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2013-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* Use CMSE intrinsics */ #include #include "RTE_Components.h" #include CMSIS_device_header /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x200000U) #endif /* typedef for non-secure callback functions */ typedef void (*funcptr_void)(void) __attribute__((cmse_nonsecure_call)); /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; /* Add user setup code for secure part here*/ /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t * )(TZ_START_NS))); /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void) (*((uint32_t * )((TZ_START_NS) + 4U))); /* Start non-secure state software application */ NonSecure_ResetHandler(); /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); } } ================================================ FILE: external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c ================================================ /****************************************************************************** * @file tz_context.c * @brief Context Management for Armv8-M TrustZone - Sample implementation * @version V1.1.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2016-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "tz_context.h" /// Number of process slots (threads may call secure library code) #ifndef TZ_PROCESS_STACK_SLOTS #define TZ_PROCESS_STACK_SLOTS 8U #endif /// Stack size of the secure library code #ifndef TZ_PROCESS_STACK_SIZE #define TZ_PROCESS_STACK_SIZE 256U #endif typedef struct { uint32_t sp_top; // stack space top uint32_t sp_limit; // stack space limit uint32_t sp; // current stack pointer } stack_info_t; static stack_info_t ProcessStackInfo[TZ_PROCESS_STACK_SLOTS]; static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE / 8U]; static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) __attribute__((cmse_nonsecure_entry)) uint32_t TZ_InitContextSystem_S(void) { uint32_t n; if (__get_IPSR() == 0U) { return 0U; // Thread Mode } for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { ProcessStackInfo[n].sp = 0U; ProcessStackInfo[n].sp_limit = (uint32_t) &ProcessStackMemory[n]; ProcessStackInfo[n].sp_top = (uint32_t) &ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; *((uint32_t *) ProcessStackMemory[n]) = n + 1U; } *((uint32_t *) ProcessStackMemory[--n]) = 0xFFFFFFFFU; ProcessStackFreeSlot = 0U; // Default process stack pointer and stack limit __set_PSPLIM((uint32_t) ProcessStackMemory); __set_PSP((uint32_t) ProcessStackMemory); // Privileged Thread Mode using PSP __set_CONTROL(0x02U); return 1U; // Success } /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error __attribute__((cmse_nonsecure_entry)) TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module) { uint32_t slot; (void) module; // Ignore (fixed Stack size) if (__get_IPSR() == 0U) { return 0U; // Thread Mode } if (ProcessStackFreeSlot == 0xFFFFFFFFU) { return 0U; // No slot available } slot = ProcessStackFreeSlot; ProcessStackFreeSlot = *((uint32_t *) ProcessStackMemory[slot]); ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; return (slot + 1U); } /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) __attribute__((cmse_nonsecure_entry)) uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id) { uint32_t slot; if (__get_IPSR() == 0U) { return 0U; // Thread Mode } if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { return 0U; // Invalid ID } slot = id - 1U; if (ProcessStackInfo[slot].sp == 0U) { return 0U; // Inactive slot } ProcessStackInfo[slot].sp = 0U; *((uint32_t *) ProcessStackMemory[slot]) = ProcessStackFreeSlot; ProcessStackFreeSlot = slot; return 1U; // Success } /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) __attribute__((cmse_nonsecure_entry)) uint32_t TZ_LoadContext_S(TZ_MemoryId_t id) { uint32_t slot; if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { return 0U; // Thread Mode or using Main Stack for threads } if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { return 0U; // Invalid ID } slot = id - 1U; if (ProcessStackInfo[slot].sp == 0U) { return 0U; // Inactive slot } // Setup process stack pointer and stack limit __set_PSPLIM(ProcessStackInfo[slot].sp_limit); __set_PSP(ProcessStackInfo[slot].sp); return 1U; // Success } /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) __attribute__((cmse_nonsecure_entry)) uint32_t TZ_StoreContext_S(TZ_MemoryId_t id) { uint32_t slot; uint32_t sp; if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { return 0U; // Thread Mode or using Main Stack for threads } if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { return 0U; // Invalid ID } slot = id - 1U; if (ProcessStackInfo[slot].sp == 0U) { return 0U; // Inactive slot } sp = __get_PSP(); if ((sp < ProcessStackInfo[slot].sp_limit) || (sp > ProcessStackInfo[slot].sp_top)) { return 0U; // SP out of range } ProcessStackInfo[slot].sp = sp; // Default process stack pointer and stack limit __set_PSPLIM((uint32_t) ProcessStackMemory); __set_PSP((uint32_t) ProcessStackMemory); return 1U; // Success } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Framework.h * Purpose: Framework header *---------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __FRAMEWORK_H__ #define __FRAMEWORK_H__ #include "CV_Typedefs.h" #include "CV_Report.h" /*----------------------------------------------------------------------------- * Test framework global definitions *----------------------------------------------------------------------------*/ /* Test case definition macro */ #define TCD(x, y) {x, #x, y} /* Test case description structure */ typedef struct __TestCase { void (*TestFunc)(void); /* Test function */ const char *TFName; /* Test function name string */ BOOL en; /* Test function enabled */ } TEST_CASE; /* Test suite description structure */ typedef struct __TestSuite { const char *FileName; /* Test module file name */ const char *Date; /* Compilation date */ const char *Time; /* Compilation time */ const char *ReportTitle; /* Title or name of module under test */ void (*Init)(void); /* Init function callback */ uint32_t TCBaseNum; /* Base number for test case numbering */ TEST_CASE *TC; /* Array of test cases */ uint32_t NumOfTC; /* Number of test cases (sz of TC array)*/ } TEST_SUITE; /* Defined in user test module */ extern TEST_SUITE ts; #endif /* __FRAMEWORK_H__ */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Report.h * Purpose: Report statistics and layout header *---------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __REPORT_H__ #define __REPORT_H__ #include "CV_Config.h" #include "CV_Typedefs.h" /*----------------------------------------------------------------------------- * Test report global definitions *----------------------------------------------------------------------------*/ #define REP_TC_FAIL 0 #define REP_TC_WARN 1 #define REP_TC_PASS 2 #define REP_TC_NOEX 3 /* Test case result definition */ typedef enum { PASSED = 0, WARNING, FAILED, NOT_EXECUTED } TC_RES; /* Assertion result info */ typedef struct { const char *module; /* Module name */ uint32_t line; /* Assertion line */ } AS_INFO; /* Test case callback interface definition */ typedef struct { BOOL (* Result) (TC_RES res); BOOL (* Dbgi) (TC_RES res, const char *fn, uint32_t ln, char *desc); } TC_ITF; /* Assert interface to the report */ extern TC_ITF tcitf; /* Assertion result buffer */ typedef struct { AS_INFO passed[BUFFER_ASSERTIONS]; AS_INFO failed[BUFFER_ASSERTIONS]; AS_INFO warnings[BUFFER_ASSERTIONS]; } AS_T_INFO; /* Assertion statistics */ typedef struct { uint32_t passed; /* Total assertions passed */ uint32_t failed; /* Total assertions failed */ uint32_t warnings; /* Total assertions warnings */ AS_T_INFO info; /* Detailed assertion info */ } AS_STAT; /* Test global statistics */ typedef struct { uint32_t tests; /* Total test cases count */ uint32_t executed; /* Total test cases executed */ uint32_t passed; /* Total test cases passed */ uint32_t failed; /* Total test cases failed */ uint32_t warnings; /* Total test cases warnings */ AS_STAT assertions; /* Total assertions statistics */ } TEST_REPORT; /* Test report interface */ typedef struct { BOOL (* Init) (void); BOOL (* Open) (const char *title, const char *date, const char *time, const char *fn); BOOL (* Close) (void); BOOL (* Open_TC) (uint32_t num, const char *fn); BOOL (* Close_TC) (void); } REPORT_ITF; /* Test report statistics */ extern TEST_REPORT test_report; /* Test report interface */ extern REPORT_ITF ritf; /* Assertions and test results */ extern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc); extern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond); #endif /* __REPORT_H__ */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Typedefs.h * Purpose: Test framework filetypes and structures description *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __TYPEDEFS_H__ #define __TYPEDEFS_H__ #include #include #include #include typedef unsigned int BOOL; #ifndef __TRUE #define __TRUE 1 #endif #ifndef __FALSE #define __FALSE 0 #endif #ifndef ENABLED #define ENABLED 1 #endif #ifndef DISABLED #define DISABLED 0 #endif #ifndef NULL #ifdef __cplusplus // EC++ #define NULL 0 #else #define NULL ((void *) 0) #endif #endif #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0])) #if defined( __GNUC__ ) || defined ( __clang__ ) static const int PATH_DELIMITER = '/'; #else static const int PATH_DELIMITER = '\\'; #endif //lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename //lint -emacro(613,__FILENAME__) null pointer is checked #define __FILENAME__ ((strrchr(__FILE__, PATH_DELIMITER) != NULL) ? (strrchr(__FILE__, PATH_DELIMITER) + 1) : __FILE__) /* Assertions and test results */ #define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc)); //lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter //lint -emacro(613,ASSERT_TRUE) null pointer is checked #define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U) #endif /* __TYPEDEFS_H__ */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h ================================================ /*----------------------------------------------------------------------------- * Name: cmsis_cv.h * Purpose: cmsis_cv header *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __CMSIS_CV_H #define __CMSIS_CV_H #include #include "CV_Config.h" /* Expansion macro used to create CMSIS Driver references */ #define EXPAND_SYMBOL(name, port) name##port #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port) // Simulator counter #ifndef HW_PRESENT extern uint32_t SIM_CYCCNT; #endif // SVC interrupt callback extern void (*TST_IRQHandler)(void); // Test main function extern void cmsis_cv (void); extern void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc); // Test cases extern void TC_CoreInstr_NOP (void); extern void TC_CoreInstr_SEV (void); extern void TC_CoreInstr_BKPT (void); extern void TC_CoreInstr_ISB (void); extern void TC_CoreInstr_DSB (void); extern void TC_CoreInstr_DMB (void); extern void TC_CoreInstr_WFI (void); extern void TC_CoreInstr_WFE (void); extern void TC_CoreInstr_REV (void); extern void TC_CoreInstr_REV16 (void); extern void TC_CoreInstr_REVSH (void); extern void TC_CoreInstr_ROR (void); extern void TC_CoreInstr_RBIT (void); extern void TC_CoreInstr_CLZ (void); extern void TC_CoreInstr_SSAT (void); extern void TC_CoreInstr_USAT (void); extern void TC_CoreInstr_RRX (void); extern void TC_CoreInstr_LoadStoreExclusive (void); extern void TC_CoreInstr_LoadStoreUnpriv (void); extern void TC_CoreInstr_LoadStoreAcquire (void); extern void TC_CoreInstr_LoadStoreAcquireExclusive (void); extern void TC_CoreInstr_UnalignedUint16 (void); extern void TC_CoreInstr_UnalignedUint32 (void); extern void TC_CoreSimd_SatAddSub (void); extern void TC_CoreSimd_ParSat16 (void); extern void TC_CoreSimd_PackUnpack (void); extern void TC_CoreSimd_ParSel (void); extern void TC_CoreSimd_ParAddSub8 (void); extern void TC_CoreSimd_AbsDif8 (void); extern void TC_CoreSimd_ParAddSub16 (void); extern void TC_CoreSimd_ParMul16 (void); extern void TC_CoreSimd_Pack16 (void); extern void TC_CoreSimd_MulAcc32 (void); #if defined(__CORTEX_M) extern void TC_CoreFunc_EnDisIRQ (void); extern void TC_CoreFunc_IRQPrio (void); extern void TC_CoreFunc_EncDecIRQPrio (void); extern void TC_CoreFunc_IRQVect (void); extern void TC_CoreFunc_Control (void); extern void TC_CoreFunc_IPSR (void); extern void TC_CoreFunc_APSR (void); extern void TC_CoreFunc_PSP (void); extern void TC_CoreFunc_MSP (void); extern void TC_CoreFunc_PSPLIM (void); extern void TC_CoreFunc_PSPLIM_NS (void); extern void TC_CoreFunc_MSPLIM (void); extern void TC_CoreFunc_MSPLIM_NS (void); extern void TC_CoreFunc_PRIMASK (void); extern void TC_CoreFunc_FAULTMASK (void); extern void TC_CoreFunc_BASEPRI (void); extern void TC_CoreFunc_FPUType (void); extern void TC_CoreFunc_FPSCR (void); #elif defined(__CORTEX_A) extern void TC_CoreAFunc_IRQ (void); extern void TC_CoreAFunc_FaultIRQ (void); extern void TC_CoreAFunc_FPSCR (void); extern void TC_CoreAFunc_CPSR (void); extern void TC_CoreAFunc_Mode (void); extern void TC_CoreAFunc_SP (void); extern void TC_CoreAFunc_SP_usr (void); extern void TC_CoreAFunc_FPEXC (void); extern void TC_CoreAFunc_ACTLR (void); extern void TC_CoreAFunc_CPACR (void); extern void TC_CoreAFunc_DFSR (void); extern void TC_CoreAFunc_IFSR (void); extern void TC_CoreAFunc_ISR (void); extern void TC_CoreAFunc_CBAR (void); extern void TC_CoreAFunc_TTBR0 (void); extern void TC_CoreAFunc_DACR (void); extern void TC_CoreAFunc_SCTLR (void); extern void TC_CoreAFunc_ACTRL (void); extern void TC_CoreAFunc_MPIDR (void); extern void TC_CoreAFunc_VBAR (void); extern void TC_CoreAFunc_MVBAR (void); extern void TC_CoreAFunc_FPU_Enable (void); #endif #if defined(__CORTEX_M) extern void TC_MPU_SetClear (void); extern void TC_MPU_Load (void); #endif #if defined(__CORTEX_A) extern void TC_GenTimer_CNTFRQ (void); extern void TC_GenTimer_CNTP_TVAL (void); extern void TC_GenTimer_CNTP_CTL (void); extern void TC_GenTimer_CNTPCT(void); extern void TC_GenTimer_CNTP_CVAL(void); #endif #if defined(__CORTEX_M) extern void TC_CML1Cache_EnDisableICache(void); extern void TC_CML1Cache_EnDisableDCache(void); extern void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void); #elif defined(__CORTEX_A) extern void TC_CAL1Cache_EnDisable(void); extern void TC_CAL1Cache_EnDisableBTAC(void); extern void TC_CAL1Cache_log2_up(void); extern void TC_CAL1Cache_InvalidateDCacheAll(void); extern void TC_CAL1Cache_CleanDCacheAll(void); extern void TC_CAL1Cache_CleanInvalidateDCacheAll(void); #endif #endif /* __CMSIS_CV_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt ================================================ Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: App # name: CMSIS-Core_Validation (Bootloader) description: Validation of CMSIS-Core implementation (Bootloader part) # packs: # - pack: ARM::CMSIS groups: - group: Source Files files: - file: ./bootloader.c ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c ================================================ /* * Copyright (c) 2013-2016 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * ---------------------------------------------------------------------- * * $Date: 15. October 2016 * $Revision: 1.1.0 * * Project: TrustZone for ARMv8-M * Title: Code template for secure main function * *---------------------------------------------------------------------------*/ #include #include /* Use CMSE intrinsics */ #include #include "RTE_Components.h" #include CMSIS_device_header /* TZ_START_NS: Start address of non-secure application */ #ifndef TZ_START_NS #define TZ_START_NS (0x200000U) #endif #if 1 /* Dummy Non-secure callable (entry) function */ __attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { return x; } #endif /* typedef for non-secure callback functions */ typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); /* Secure main() */ int main(void) { funcptr_void NonSecure_ResetHandler; /* Add user setup code for secure part here*/ /* Set non-secure main stack (MSP_NS) */ __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); /* Get non-secure reset handler */ NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); /* Start non-secure state software application */ NonSecure_ResetHandler(); /* Non-secure software does not return, this code is not executed */ while (1) { __NOP(); } } #if defined(__CORTEX_M) __NO_RETURN extern void HardFault_Handler(void); void HardFault_Handler(void) { printf("Bootloader HardFault!\n"); #ifdef __MICROLIB for(;;) {} #else exit(1); #endif } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: App # name: CMSIS-Core_Validation description: Validation of CMSIS-Core implementation # packs: # - pack: ARM::CMSIS define: - PRINT_XML_REPORT: 1 add-path: - ../../../Include - ../../../Source/ConfigA misc: - for-compiler: AC6 C-CPP: - -Wno-declaration-after-statement - -Wno-covered-switch-default - for-compiler: GCC C-CPP: - -Wno-declaration-after-statement - -Wno-covered-switch-default groups: - group: Documentation files: - file: ../../../README.md - group: Source Files files: - file: ./main.c - group: CMSIS-Core_Validation files: - file: ../../../Source/cmsis_cv.c - file: ../../../Source/CV_CoreAFunc.c - file: ../../../Source/CV_CoreInstr.c - file: ../../../Source/CV_CAL1Cache.c # - file: ../../../Source/ConfigA/mmu.c - group: Validation Framework files: - file: ../../../Source/CV_Framework.c - file: ../../../Source/CV_Report.c ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c ================================================ /* * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include #include "RTE_Components.h" #include CMSIS_device_header #ifdef RTE_Compiler_EventRecorder #include "EventRecorder.h" #endif #include "cmsis_cv.h" #include "CV_Report.h" //lint -e970 allow using int for main int main (void) { // System Initialization SystemCoreClockUpdate(); #ifdef RTE_Compiler_EventRecorder // Initialize and start Event Recorder (void)EventRecorderInitialize(EventRecordError, 1U); (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU); #endif cmsis_cv(); #ifdef __MICROLIB for(;;) {} #else exit(0); #endif } #if defined(__CORTEX_A) #include "irq_ctrl.h" #if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ (defined ( __GNUC__ )) #define __IRQ __attribute__((interrupt("IRQ"))) #elif defined ( __CC_ARM ) #define __IRQ __irq #elif defined ( __ICCARM__ ) #define __IRQ __irq __arm #else #error "Unsupported compiler!" #endif __IRQ void IRQ_Handler(void); __IRQ void IRQ_Handler(void) { const IRQn_ID_t irqn = IRQ_GetActiveIRQ(); IRQHandler_t const handler = IRQ_GetHandler(irqn); if (handler != NULL) { __enable_irq(); handler(); __disable_irq(); } IRQ_EndOfInterrupt(irqn); } __IRQ __NO_RETURN void Undef_Handler (void); __IRQ __NO_RETURN void Undef_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!"); exit(0); } __IRQ void SVC_Handler (void); __IRQ void SVC_Handler (void) { } __IRQ __NO_RETURN void PAbt_Handler (void); __IRQ __NO_RETURN void PAbt_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!"); exit(0); } __IRQ __NO_RETURN void DAbt_Handler (void); __IRQ __NO_RETURN void DAbt_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!"); exit(0); } __IRQ void FIQ_Handler (void); __IRQ void FIQ_Handler (void) { } #endif #if defined(__CORTEX_M) __NO_RETURN void HardFault_Handler(void); __NO_RETURN void HardFault_Handler(void) { cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!"); #ifdef __MICROLIB for(;;) {} #else exit(0); #endif } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: App # name: CMSIS-Core_Validation description: Validation of CMSIS-Core implementation # packs: # - pack: ARM::CMSIS define: - PRINT_XML_REPORT: 1 add-path: - ../../../Include - ../../../Source/Config misc: - for-compiler: AC6 C-CPP: - -Wno-declaration-after-statement - -Wno-covered-switch-default - for-compiler: GCC C-CPP: - -Wno-declaration-after-statement - -Wno-covered-switch-default groups: - group: Documentation files: - file: ../../../README.md - group: Source Files files: - file: ./main.c - group: CMSIS-Core_Validation files: - file: ../../../Source/cmsis_cv.c - file: ../../../Source/CV_CoreFunc.c - file: ../../../Source/CV_CoreInstr.c - file: ../../../Source/CV_CoreSimd.c - file: ../../../Source/CV_CML1Cache.c - file: ../../../Source/CV_MPU_ARMv7.c for-context: - +CM0 - +CM0plus - +CM3 - +CM4 - +CM4FP - +CM7 - +CM7SP - +CM7DP - file: ../../../Source/CV_MPU_ARMv8.c for-context: - +CM23 - +CM23S - +CM23NS - +CM33 - +CM33S - +CM33NS - +CM35P - +CM35PS - +CM35PNS - +CM55S - +CM55NS - +CM85S - +CM85NS - group: Validation Framework files: - file: ../../../Source/CV_Framework.c - file: ../../../Source/CV_Report.c ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c ================================================ /* * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include #include "RTE_Components.h" #include CMSIS_device_header #ifdef RTE_Compiler_EventRecorder #include "EventRecorder.h" #endif #include "cmsis_cv.h" #include "CV_Report.h" //lint -e970 allow using int for main #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include /* Dummy Non-secure callable (entry) function */ __attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { return x; } #endif int main (void) { // System Initialization SystemCoreClockUpdate(); #ifdef RTE_Compiler_EventRecorder // Initialize and start Event Recorder (void)EventRecorderInitialize(EventRecordError, 1U); (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU); #endif cmsis_cv(); #ifdef __MICROLIB for(;;) {} #else exit(0); #endif } #if defined(__CORTEX_A) #include "irq_ctrl.h" #if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ (defined ( __GNUC__ )) #define __IRQ __attribute__((interrupt("IRQ"))) #elif defined ( __CC_ARM ) #define __IRQ __irq #elif defined ( __ICCARM__ ) #define __IRQ __irq __arm #else #error "Unsupported compiler!" #endif __IRQ void IRQ_Handler(void); __IRQ void IRQ_Handler(void) { const IRQn_ID_t irqn = IRQ_GetActiveIRQ(); IRQHandler_t const handler = IRQ_GetHandler(irqn); if (handler != NULL) { __enable_irq(); handler(); __disable_irq(); } IRQ_EndOfInterrupt(irqn); } __IRQ __NO_RETURN void Undef_Handler (void); __IRQ __NO_RETURN void Undef_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!"); exit(0); } __IRQ void SVC_Handler (void); __IRQ void SVC_Handler (void) { } __IRQ __NO_RETURN void PAbt_Handler (void); __IRQ __NO_RETURN void PAbt_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!"); exit(0); } __IRQ __NO_RETURN void DAbt_Handler (void); __IRQ __NO_RETURN void DAbt_Handler (void) { cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!"); exit(0); } __IRQ void FIQ_Handler (void); __IRQ void FIQ_Handler (void) { } #endif #if defined(__CORTEX_M) __NO_RETURN void HardFault_Handler(void); __NO_RETURN void HardFault_Handler(void) { cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!"); #ifdef __MICROLIB for(;;) {} #else exit(0); #endif } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld ================================================ #include "mem_ARMCA5.h" MEMORY { ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } ENTRY(Reset_Handler) SECTIONS { .text : { Image$$VECTORS$$Base = .; * (RESET) KEEP(*(.isr_vector)) Image$$VECTORS$$Limit = .; *(SVC_TABLE) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) Image$$RO_DATA$$Base = .; *(.rodata*) Image$$RO_DATA$$Limit = .; KEEP(*(.eh_frame*)) } > ROM .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ROM __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > ROM __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG (__data_end__ - __data_start__) __copy_table_end__ = .; } > ROM .zero.table : { . = ALIGN(4); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) __zero_table_end__ = .; } > ROM __etext = .; .ttb : { Image$$TTB$$ZI$$Base = .; . += __TTB_SIZE; Image$$TTB$$ZI$$Limit = .; } > L_TTB .data : { Image$$RW_DATA$$Base = .; __data_start__ = .; *(vtable) *(.data*) Image$$RW_DATA$$Limit = .; . = ALIGN(4); /* preinit data */ PROVIDE (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE (__fini_array_end = .); . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM .bss ALIGN(0x400): { Image$$ZI_DATA$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; Image$$ZI_DATA$$Limit = .; __end__ = .; end = __end__; } > RAM AT > RAM #if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) .heap (NOLOAD): { . = ALIGN(8); Image$$HEAP$$ZI$$Base = .; . += __HEAP_SIZE; Image$$HEAP$$ZI$$Limit = .; __HeapLimit = .; } > RAM #endif .stack (NOLOAD): { . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; . = ALIGN(8); __StackTop = .; Image$$SYS_STACK$$ZI$$Base = .; . += __STACK_SIZE; Image$$SYS_STACK$$ZI$$Limit = .; __stack = .; Image$$FIQ_STACK$$ZI$$Base = .; . += __FIQ_STACK_SIZE; Image$$FIQ_STACK$$ZI$$Limit = .; Image$$IRQ_STACK$$ZI$$Base = .; . += __IRQ_STACK_SIZE; Image$$IRQ_STACK$$ZI$$Limit = .; Image$$SVC_STACK$$ZI$$Base = .; . += __SVC_STACK_SIZE; Image$$SVC_STACK$$ZI$$Limit = .; Image$$ABT_STACK$$ZI$$Base = .; . += __ABT_STACK_SIZE; Image$$ABT_STACK$$ZI$$Limit = .; Image$$UND_STACK$$ZI$$Base = .; . += __UND_STACK_SIZE; Image$$UND_STACK$$ZI$$Limit = .; } > RAM } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc ;************************************************** ; Copyright (c) 2017 ARM Ltd. All rights reserved. ;************************************************** ; Scatter-file for RTX Example on Versatile Express ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. ; This platform has 2GB SDRAM starting at 0x80000000. #include "mem_ARMCA5.h" SDRAM __ROM_BASE __ROM_SIZE ; load region size_region { VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address { * (RESET, +FIRST) ; Vector table and other startup code * (InRoot$$Sections) ; All (library) code that must be in a root region * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } RW_DATA __RAM_BASE __RW_DATA_SIZE { * (+RW) } ; Application RW data (.data) ZI_DATA (__RAM_BASE+ __RW_DATA_SIZE) __ZI_DATA_SIZE { * (+ZI) } ; Application ZI data (.bss) ARM_LIB_HEAP (__RAM_BASE +__RW_DATA_SIZE +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up { } ARM_LIB_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down { } UND_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack { } ABT_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack { } SVC_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack { } IRQ_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack { } FIQ_STACK (__RAM_BASE +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack { } TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU { } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h ================================================ /**************************************************************************//** * @file mem_ARMCA5.h * @brief Memory base and size definitions (used in scatter file) * @version V1.1.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __MEM_ARMCA5_H #define __MEM_ARMCA5_H /*---------------------------------------------------------------------------- User Stack & Heap size definition *----------------------------------------------------------------------------*/ /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- ROM Configuration ------------------------------------ // // ROM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // ROM Base Address <0x0-0xFFFFFFFF:0x100000> // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x80000000 #define __ROM_SIZE 0x00200000 /*--------------------- RAM Configuration ----------------------------------- // RAM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // RAM Base Address <0x0-0xFFFFFFFF:0x100000> // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // Data Sections // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // // Stack / Heap Configuration // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> // Exceptional Modes // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // // // *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x80200000 #define __RAM_SIZE 0x00200000 #define __RW_DATA_SIZE 0x00100000 #define __ZI_DATA_SIZE 0x000F0000 #define __STACK_SIZE 0x00001000 #define __HEAP_SIZE 0x00008000 #define __UND_STACK_SIZE 0x00000100 #define __ABT_STACK_SIZE 0x00000100 #define __SVC_STACK_SIZE 0x00000100 #define __IRQ_STACK_SIZE 0x00000100 #define __FIQ_STACK_SIZE 0x00000100 /*----------------------------------------------------------------------------*/ /*--------------------- TTB Configuration ------------------------------------ // // TTB Configuration // The TLB L1 contains 4096 32-bit entries and must be 16kB aligned // The TLB L2 entries are placed after the L1 in the MMU config // TTB Base Address <0x0-0xFFFFFFFF:0x4000> // TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> // *----------------------------------------------------------------------------*/ #define __TTB_BASE 0x80500000 #define __TTB_SIZE 0x00005000 #endif /* __MEM_ARMCA5_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c ================================================ /**************************************************************************//** * @file mmu_ARMCA5.c * @brief MMU Configuration for ARM Cortex-A5 Device Series * @version V1.2.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map Memory Type 0xffffffff |--------------------------| ------------ | FLAG SYNC | Device Memory 0xfffff000 |--------------------------| ------------ | Fault | Fault 0xfff00000 |--------------------------| ------------ | | Normal | | | Daughterboard | | memory | | | 0x80505000 |--------------------------| ------------ |TTB (L2 Sync Flags ) 4k | Normal 0x80504C00 |--------------------------| ------------ |TTB (L2 Peripherals-B) 16k| Normal 0x80504800 |--------------------------| ------------ |TTB (L2 Peripherals-A) 16k| Normal 0x80504400 |--------------------------| ------------ |TTB (L2 Priv Periphs) 4k | Normal 0x80504000 |--------------------------| ------------ | TTB (L1 Descriptors) | Normal 0x80500000 |--------------------------| ------------ | Stack | Normal |--------------------------| ------------ | Heap | Normal 0x80400000 |--------------------------| ------------ | ZI Data | Normal 0x80300000 |--------------------------| ------------ | RW Data | Normal 0x80200000 |--------------------------| ------------ | RO Data | Normal |--------------------------| ------------ | RO Code | USH Normal 0x80000000 |--------------------------| ------------ | Daughterboard | Fault | HSB AXI buses | 0x40000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x2c002000 |--------------------------| ------------ | Private Address | Device Memory 0x2c000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x20000000 |--------------------------| ------------ | Peripherals | Device Memory RW/RO | | & Fault 0x00000000 |--------------------------| */ // L1 Cache info and restrictions about architecture of the caches (CCSIR register): // Write-Through support *not* available // Write-Back support available. // Read allocation support available. // Write allocation support available. //Note: You should use the Shareable attribute carefully. //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. //Following MMU configuration is expected //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) //Domain 0 is always the Client domain //Descriptors should place all memory in domain 0 #include "ARMCA5.h" #include "mem_ARMCA5.h" // TTB base address #define TTB_BASE ((uint32_t*)__TTB_BASE) // L2 table pointers //---------------------------------------- #define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization //--------------------- PERIPHERALS ------------------- #define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) #define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) //--------------------- SYNC FLAGS -------------------- #define FLAG_SYNC 0xFFFFF000 #define F_SYNC_BASE 0xFFF00000 //1M aligned static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable /* Define global descriptors */ static uint32_t Page_L1_4k = 0x0; //generic static uint32_t Page_L1_64k = 0x0; //generic static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 void MMU_CreateTranslationTable(void) { mmu_region_attributes_Type region; //Create 4GB of faulting entries MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); /* * Generate descriptors. Refer to core_ca.h to get information about attributes * */ //Create descriptors for Vectors, RO, RW, ZI sections section_normal(Sect_Normal, region); section_normal_cod(Sect_Normal_Cod, region); section_normal_ro(Sect_Normal_RO, region); section_normal_rw(Sect_Normal_RW, region); //Create descriptors for peripherals section_device_ro(Sect_Device_RO, region); section_device_rw(Sect_Device_RW, region); //Create descriptors for 64k pages page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); //Create descriptors for 4k pages page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); /* * Define MMU flat-map regions and attributes * */ //Define Image MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections //--------------------- PERIPHERALS ------------------- MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW); MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE , 16, Sect_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define private address space entry. MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Define L2CC entry. Uncomment if PL310 is present // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define synchronization space entry. MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); /* Set location of level 1 page table ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) ; 13:7 - 0x0 ; 6 - IRGN[0] 0x1 (Inner WB WA) ; 5 - NOS 0x0 (Non-shared) ; 4:3 - RGN 0x01 (Outer WB WA) ; 2 - IMP 0x0 (Implementation Defined) ; 1 - S 0x0 (Non-shared) ; 0 - IRGN[1] 0x0 (Inner WB WA) */ __set_TTBR0(__TTB_BASE | 0x48); __ISB(); /* Set up domain access control register ; We set domain 0 to Client and all other domains to No Access. ; All translation table entries specify domain 0 */ __set_DACR(1); __ISB(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c ================================================ /****************************************************************************** * @file startup_ARMCA5.c * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series * @version V1.0.1 * @date 10. January 2021 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include /*---------------------------------------------------------------------------- Definitions *----------------------------------------------------------------------------*/ #define USR_MODE 0x10 // User mode #define FIQ_MODE 0x11 // Fast Interrupt Request mode #define IRQ_MODE 0x12 // Interrupt Request mode #define SVC_MODE 0x13 // Supervisor mode #define ABT_MODE 0x17 // Abort mode #define UND_MODE 0x1B // Undefined Instruction mode #define SYS_MODE 0x1F // System mode /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void Vectors (void) __attribute__ ((naked, section("RESET"))); void Reset_Handler (void) __attribute__ ((naked)); void Default_Handler(void) __attribute__ ((noreturn)); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ void Vectors(void) { __ASM volatile( "LDR PC, =Reset_Handler \n" "LDR PC, =Undef_Handler \n" "LDR PC, =SVC_Handler \n" "LDR PC, =PAbt_Handler \n" "LDR PC, =DAbt_Handler \n" "NOP \n" "LDR PC, =IRQ_Handler \n" "LDR PC, =FIQ_Handler \n" ); } /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { __ASM volatile( // Mask interrupts "CPSID if \n" // Put any cores other than 0 to sleep "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR "ANDS R0, R0, #3 \n" "goToSleep: \n" "WFINE \n" "BNE goToSleep \n" // Reset SCTLR Settings "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register "ISB \n" // Configure ACTLR "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table "LDR R0, =Vectors \n" "MCR p15, 0, R0, c12, c0, 0 \n" // Setup Stack for each exceptional mode "CPS #0x11 \n" "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" "CPS #0x12 \n" "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" "CPS #0x13 \n" "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" "CPS #0x17 \n" "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" "CPS #0x1B \n" "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" "CPS #0x1F \n" #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" #elif defined ( __GNUC__ ) "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" #else #error Unknown compiler. #endif // Call SystemInit "BL SystemInit \n" // Unmask interrupts "CPSIE if \n" // Call __main #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "BL __main \n" #elif defined ( __GNUC__ ) "BL _start \n" #else #error Unknown compiler. #endif ); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 ================================================ /****************************************************************************** * @file startup_ARMCA5.c * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series * @version V1.0.1 * @date 10. January 2021 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include /*---------------------------------------------------------------------------- Definitions *----------------------------------------------------------------------------*/ #define USR_MODE 0x10 // User mode #define FIQ_MODE 0x11 // Fast Interrupt Request mode #define IRQ_MODE 0x12 // Interrupt Request mode #define SVC_MODE 0x13 // Supervisor mode #define ABT_MODE 0x17 // Abort mode #define UND_MODE 0x1B // Undefined Instruction mode #define SYS_MODE 0x1F // System mode /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void Vectors (void) __attribute__ ((naked, section("RESET"))); void Reset_Handler (void) __attribute__ ((naked)); void Default_Handler(void) __attribute__ ((noreturn)); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ void Vectors(void) { __ASM volatile( "LDR PC, =Reset_Handler \n" "LDR PC, =Undef_Handler \n" "LDR PC, =SVC_Handler \n" "LDR PC, =PAbt_Handler \n" "LDR PC, =DAbt_Handler \n" "NOP \n" "LDR PC, =IRQ_Handler \n" "LDR PC, =FIQ_Handler \n" ); } /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { __ASM volatile( // Mask interrupts "CPSID if \n" // Put any cores other than 0 to sleep "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR "ANDS R0, R0, #3 \n" "goToSleep: \n" "WFINE \n" "BNE goToSleep \n" // Reset SCTLR Settings "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register "ISB \n" // Configure ACTLR "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table "LDR R0, =Vectors \n" "MCR p15, 0, R0, c12, c0, 0 \n" // Setup Stack for each exceptional mode "CPS #0x11 \n" "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" "CPS #0x12 \n" "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" "CPS #0x13 \n" "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" "CPS #0x17 \n" "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" "CPS #0x1B \n" "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" "CPS #0x1F \n" "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" // Call SystemInit "BL SystemInit \n" // Unmask interrupts "CPSIE if \n" // Call __main "BL __main \n" ); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s ================================================ /****************************************************************************** * @file startup_ARMCA9.s * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA5 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(4) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCA9.s * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA5 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(4) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c ================================================ /****************************************************************************** * @file system_ARMCA5.c * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series * @version V1.0.1 * @date 13. February 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #define SYSTEM_CLOCK 12000000U /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System Initialization *----------------------------------------------------------------------------*/ void SystemInit (void) { /* do not use global variables because this function is called before reaching pre-main. RW section may be overwritten afterwards. */ // Invalidate entire Unified TLB __set_TLBIALL(0); // Invalidate entire branch predictor array __set_BPIALL(0); __DSB(); __ISB(); // Invalidate instruction cache and flush branch target cache __set_ICIALLU(0); __DSB(); __ISB(); // Invalidate data cache L1C_InvalidateDCacheAll(); #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) // Enable FPU __FPU_Enable(); #endif // Create Translation Table MMU_CreateTranslationTable(); // Enable MMU MMU_Enable(); // Enable Caches L1C_EnableCaches(); L1C_EnableBTAC(); #if (__L2C_PRESENT == 1) // Enable GIC L2C_Enable(); #endif // IRQ Initialize IRQ_Initialize(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 ================================================ /****************************************************************************** * @file system_ARMCA5.c * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series * @version V1.0.1 * @date 13. February 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #define SYSTEM_CLOCK 12000000U /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System Initialization *----------------------------------------------------------------------------*/ void SystemInit (void) { /* do not use global variables because this function is called before reaching pre-main. RW section may be overwritten afterwards. */ // Invalidate entire Unified TLB __set_TLBIALL(0); // Invalidate entire branch predictor array __set_BPIALL(0); __DSB(); __ISB(); // Invalidate instruction cache and flush branch target cache __set_ICIALLU(0); __DSB(); __ISB(); // Invalidate data cache L1C_InvalidateDCacheAll(); #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) // Enable FPU __FPU_Enable(); #endif // Create Translation Table MMU_CreateTranslationTable(); // Enable MMU MMU_Enable(); // Enable Caches L1C_EnableCaches(); L1C_EnableBTAC(); #if (__L2C_PRESENT == 1) // Enable GIC L2C_Enable(); #endif // IRQ Initialize IRQ_Initialize(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h ================================================ /****************************************************************************** * @file system_ARMCA5.h * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA5_H #define __SYSTEM_ARMCA5_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA5_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0 ================================================ /****************************************************************************** * @file system_ARMCA5.h * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA5_H #define __SYSTEM_ARMCA5_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA5_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup - component: Device:IRQ Controller:GIC misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether model has NEON support cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0 ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld ================================================ #include "mem_ARMCA7.h" MEMORY { ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } ENTRY(Reset_Handler) SECTIONS { .text : { Image$$VECTORS$$Base = .; * (RESET) KEEP(*(.isr_vector)) Image$$VECTORS$$Limit = .; *(SVC_TABLE) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) Image$$RO_DATA$$Base = .; *(.rodata*) Image$$RO_DATA$$Limit = .; KEEP(*(.eh_frame*)) } > ROM .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ROM __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > ROM __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG (__data_end__ - __data_start__) __copy_table_end__ = .; } > ROM .zero.table : { . = ALIGN(4); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) __zero_table_end__ = .; } > ROM __etext = .; .ttb : { Image$$TTB$$ZI$$Base = .; . += __TTB_SIZE; Image$$TTB$$ZI$$Limit = .; } > L_TTB .data : { Image$$RW_DATA$$Base = .; __data_start__ = .; *(vtable) *(.data*) Image$$RW_DATA$$Limit = .; . = ALIGN(4); /* preinit data */ PROVIDE (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE (__fini_array_end = .); . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM .bss ALIGN(0x400): { Image$$ZI_DATA$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; Image$$ZI_DATA$$Limit = .; __end__ = .; end = __end__; } > RAM AT > RAM #if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) .heap (NOLOAD): { . = ALIGN(8); Image$$HEAP$$ZI$$Base = .; . += __HEAP_SIZE; Image$$HEAP$$ZI$$Limit = .; __HeapLimit = .; } > RAM #endif .stack (NOLOAD): { . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; . = ALIGN(8); __StackTop = .; Image$$SYS_STACK$$ZI$$Base = .; . += __STACK_SIZE; Image$$SYS_STACK$$ZI$$Limit = .; __stack = .; Image$$FIQ_STACK$$ZI$$Base = .; . += __FIQ_STACK_SIZE; Image$$FIQ_STACK$$ZI$$Limit = .; Image$$IRQ_STACK$$ZI$$Base = .; . += __IRQ_STACK_SIZE; Image$$IRQ_STACK$$ZI$$Limit = .; Image$$SVC_STACK$$ZI$$Base = .; . += __SVC_STACK_SIZE; Image$$SVC_STACK$$ZI$$Limit = .; Image$$ABT_STACK$$ZI$$Base = .; . += __ABT_STACK_SIZE; Image$$ABT_STACK$$ZI$$Limit = .; Image$$UND_STACK$$ZI$$Base = .; . += __UND_STACK_SIZE; Image$$UND_STACK$$ZI$$Limit = .; } > RAM } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc ;************************************************** ; Copyright (c) 2017 ARM Ltd. All rights reserved. ;************************************************** ; Scatter-file for RTX Example on Versatile Express ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. ; This platform has 2GB SDRAM starting at 0x80000000. #include "mem_ARMCA7.h" SDRAM __ROM_BASE __ROM_SIZE ; load region size_region { VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address { * (RESET, +FIRST) ; Vector table and other startup code * (InRoot$$Sections) ; All (library) code that must be in a root region * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } RW_DATA __RAM_BASE __RW_DATA_SIZE { * (+RW) } ; Application RW data (.data) ZI_DATA (__RAM_BASE+ __RW_DATA_SIZE) __ZI_DATA_SIZE { * (+ZI) } ; Application ZI data (.bss) ARM_LIB_HEAP (__RAM_BASE +__RW_DATA_SIZE +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up { } ARM_LIB_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down { } UND_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack { } ABT_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack { } SVC_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack { } IRQ_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack { } FIQ_STACK (__RAM_BASE +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack { } TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU { } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h ================================================ /**************************************************************************//** * @file mem_ARMCA7.h * @brief Memory base and size definitions (used in scatter file) * @version V1.1.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __MEM_ARMCA7_H #define __MEM_ARMCA7_H /*---------------------------------------------------------------------------- User Stack & Heap size definition *----------------------------------------------------------------------------*/ /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- ROM Configuration ------------------------------------ // // ROM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // ROM Base Address <0x0-0xFFFFFFFF:0x100000> // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x80000000 #define __ROM_SIZE 0x00200000 /*--------------------- RAM Configuration ----------------------------------- // RAM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // RAM Base Address <0x0-0xFFFFFFFF:0x100000> // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // Data Sections // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // // Stack / Heap Configuration // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> // Exceptional Modes // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // // // *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x80200000 #define __RAM_SIZE 0x00200000 #define __RW_DATA_SIZE 0x00100000 #define __ZI_DATA_SIZE 0x000F0000 #define __STACK_SIZE 0x00001000 #define __HEAP_SIZE 0x00008000 #define __UND_STACK_SIZE 0x00000100 #define __ABT_STACK_SIZE 0x00000100 #define __SVC_STACK_SIZE 0x00000100 #define __IRQ_STACK_SIZE 0x00000100 #define __FIQ_STACK_SIZE 0x00000100 /*----------------------------------------------------------------------------*/ /*--------------------- TTB Configuration ------------------------------------ // // TTB Configuration // The TLB L1 contains 4096 32-bit entries and must be 16kB aligned // The TLB L2 entries are placed after the L1 in the MMU config // TTB Base Address <0x0-0xFFFFFFFF:0x4000> // TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> // *----------------------------------------------------------------------------*/ #define __TTB_BASE 0x80500000 #define __TTB_SIZE 0x00005000 #endif /* __MEM_ARMCA7_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c ================================================ /**************************************************************************//** * @file mmu_ARMCA7.c * @brief MMU Configuration for Arm Cortex-A7 Device Series * @version V1.2.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map Memory Type 0xffffffff |--------------------------| ------------ | FLAG SYNC | Device Memory 0xfffff000 |--------------------------| ------------ | Fault | Fault 0xfff00000 |--------------------------| ------------ | | Normal | | | Daughterboard | | memory | | | 0x80505000 |--------------------------| ------------ |TTB (L2 Sync Flags ) 4k | Normal 0x80504C00 |--------------------------| ------------ |TTB (L2 Peripherals-B) 16k| Normal 0x80504800 |--------------------------| ------------ |TTB (L2 Peripherals-A) 16k| Normal 0x80504400 |--------------------------| ------------ |TTB (L2 Priv Periphs) 4k | Normal 0x80504000 |--------------------------| ------------ | TTB (L1 Descriptors) | Normal 0x80500000 |--------------------------| ------------ | Stack | Normal |--------------------------| ------------ | Heap | Normal 0x80400000 |--------------------------| ------------ | ZI Data | Normal 0x80300000 |--------------------------| ------------ | RW Data | Normal 0x80200000 |--------------------------| ------------ | RO Data | Normal |--------------------------| ------------ | RO Code | USH Normal 0x80000000 |--------------------------| ------------ | Daughterboard | Fault | HSB AXI buses | 0x40000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x2c002000 |--------------------------| ------------ | Private Address | Device Memory 0x2c000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x20000000 |--------------------------| ------------ | Peripherals | Device Memory RW/RO | | & Fault 0x00000000 |--------------------------| */ // L1 Cache info and restrictions about architecture of the caches (CCSIR register): // Write-Through support *not* available // Write-Back support available. // Read allocation support available. // Write allocation support available. //Note: You should use the Shareable attribute carefully. //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. //Following MMU configuration is expected //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) //Domain 0 is always the Client domain //Descriptors should place all memory in domain 0 #include "ARMCA7.h" #include "mem_ARMCA7.h" // TTB base address #define TTB_BASE ((uint32_t*)__TTB_BASE) // L2 table pointers //---------------------------------------- #define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization //--------------------- PERIPHERALS ------------------- #define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) #define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) //--------------------- SYNC FLAGS -------------------- #define FLAG_SYNC 0xFFFFF000 #define F_SYNC_BASE 0xFFF00000 //1M aligned static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable /* Define global descriptors */ static uint32_t Page_L1_4k = 0x0; //generic static uint32_t Page_L1_64k = 0x0; //generic static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 void MMU_CreateTranslationTable(void) { mmu_region_attributes_Type region; //Create 4GB of faulting entries MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); /* * Generate descriptors. Refer to core_ca.h to get information about attributes * */ //Create descriptors for Vectors, RO, RW, ZI sections section_normal(Sect_Normal, region); section_normal_cod(Sect_Normal_Cod, region); section_normal_ro(Sect_Normal_RO, region); section_normal_rw(Sect_Normal_RW, region); //Create descriptors for peripherals section_device_ro(Sect_Device_RO, region); section_device_rw(Sect_Device_RW, region); //Create descriptors for 64k pages page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); //Create descriptors for 4k pages page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); /* * Define MMU flat-map regions and attributes * */ //Define Image MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections //--------------------- PERIPHERALS ------------------- MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW); MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define private address space entry. MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Define L2CC entry. Uncomment if PL310 is present // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define synchronization space entry. MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); /* Set location of level 1 page table ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) ; 13:7 - 0x0 ; 6 - IRGN[0] 0x1 (Inner WB WA) ; 5 - NOS 0x0 (Non-shared) ; 4:3 - RGN 0x01 (Outer WB WA) ; 2 - IMP 0x0 (Implementation Defined) ; 1 - S 0x0 (Non-shared) ; 0 - IRGN[1] 0x0 (Inner WB WA) */ __set_TTBR0(__TTB_BASE | 0x48); __ISB(); /* Set up domain access control register ; We set domain 0 to Client and all other domains to No Access. ; All translation table entries specify domain 0 */ __set_DACR(1); __ISB(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c ================================================ /****************************************************************************** * @file startup_ARMCA7.c * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series * @version V1.0.1 * @date 10. January 2021 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include /*---------------------------------------------------------------------------- Definitions *----------------------------------------------------------------------------*/ #define USR_MODE 0x10 // User mode #define FIQ_MODE 0x11 // Fast Interrupt Request mode #define IRQ_MODE 0x12 // Interrupt Request mode #define SVC_MODE 0x13 // Supervisor mode #define ABT_MODE 0x17 // Abort mode #define UND_MODE 0x1B // Undefined Instruction mode #define SYS_MODE 0x1F // System mode /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void Vectors (void) __attribute__ ((naked, section("RESET"))); void Reset_Handler (void) __attribute__ ((naked)); void Default_Handler(void) __attribute__ ((noreturn)); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ void Vectors(void) { __ASM volatile( "LDR PC, =Reset_Handler \n" "LDR PC, =Undef_Handler \n" "LDR PC, =SVC_Handler \n" "LDR PC, =PAbt_Handler \n" "LDR PC, =DAbt_Handler \n" "NOP \n" "LDR PC, =IRQ_Handler \n" "LDR PC, =FIQ_Handler \n" ); } /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { __ASM volatile( // Mask interrupts "CPSID if \n" // Put any cores other than 0 to sleep "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR "ANDS R0, R0, #3 \n" "goToSleep: \n" "WFINE \n" "BNE goToSleep \n" // Reset SCTLR Settings "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register "ISB \n" // Configure ACTLR "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table "LDR R0, =Vectors \n" "MCR p15, 0, R0, c12, c0, 0 \n" // Setup Stack for each exceptional mode "CPS #0x11 \n" "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" "CPS #0x12 \n" "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" "CPS #0x13 \n" "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" "CPS #0x17 \n" "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" "CPS #0x1B \n" "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" "CPS #0x1F \n" #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" #elif defined ( __GNUC__ ) "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" #else #error Unknown compiler. #endif // Call SystemInit "BL SystemInit \n" // Unmask interrupts "CPSIE if \n" // Call __main #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "BL __main \n" #elif defined ( __GNUC__ ) "BL _start \n" #else #error Unknown compiler. #endif ); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 ================================================ /****************************************************************************** * @file startup_ARMCA7.c * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series * @version V1.0.1 * @date 10. January 2021 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include /*---------------------------------------------------------------------------- Definitions *----------------------------------------------------------------------------*/ #define USR_MODE 0x10 // User mode #define FIQ_MODE 0x11 // Fast Interrupt Request mode #define IRQ_MODE 0x12 // Interrupt Request mode #define SVC_MODE 0x13 // Supervisor mode #define ABT_MODE 0x17 // Abort mode #define UND_MODE 0x1B // Undefined Instruction mode #define SYS_MODE 0x1F // System mode /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void Vectors (void) __attribute__ ((naked, section("RESET"))); void Reset_Handler (void) __attribute__ ((naked)); void Default_Handler(void) __attribute__ ((noreturn)); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ void Vectors(void) { __ASM volatile( "LDR PC, =Reset_Handler \n" "LDR PC, =Undef_Handler \n" "LDR PC, =SVC_Handler \n" "LDR PC, =PAbt_Handler \n" "LDR PC, =DAbt_Handler \n" "NOP \n" "LDR PC, =IRQ_Handler \n" "LDR PC, =FIQ_Handler \n" ); } /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { __ASM volatile( // Mask interrupts "CPSID if \n" // Put any cores other than 0 to sleep "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR "ANDS R0, R0, #3 \n" "goToSleep: \n" "WFINE \n" "BNE goToSleep \n" // Reset SCTLR Settings "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register "ISB \n" // Configure ACTLR "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table "LDR R0, =Vectors \n" "MCR p15, 0, R0, c12, c0, 0 \n" // Setup Stack for each exceptional mode "CPS #0x11 \n" "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" "CPS #0x12 \n" "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" "CPS #0x13 \n" "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" "CPS #0x17 \n" "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" "CPS #0x1B \n" "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" "CPS #0x1F \n" "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" // Call SystemInit "BL SystemInit \n" // Unmask interrupts "CPSIE if \n" // Call __main "BL __main \n" ); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s ================================================ /****************************************************************************** * @file startup_ARMCA7.s * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA7 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(4) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCA7.s * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA7 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(4) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c ================================================ /****************************************************************************** * @file system_ARMCA7.c * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series * @version V1.0.1 * @date 13. February 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #define SYSTEM_CLOCK 12000000U /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System Initialization *----------------------------------------------------------------------------*/ void SystemInit (void) { /* do not use global variables because this function is called before reaching pre-main. RW section may be overwritten afterwards. */ // Invalidate entire Unified TLB __set_TLBIALL(0); // Invalidate entire branch predictor array __set_BPIALL(0); __DSB(); __ISB(); // Invalidate instruction cache and flush branch target cache __set_ICIALLU(0); __DSB(); __ISB(); // Invalidate data cache L1C_InvalidateDCacheAll(); #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) // Enable FPU __FPU_Enable(); #endif // Create Translation Table MMU_CreateTranslationTable(); // Enable MMU MMU_Enable(); // Enable Caches L1C_EnableCaches(); L1C_EnableBTAC(); #if (__L2C_PRESENT == 1) // Enable GIC L2C_Enable(); #endif // IRQ Initialize IRQ_Initialize(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 ================================================ /****************************************************************************** * @file system_ARMCA7.c * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series * @version V1.0.1 * @date 13. February 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #define SYSTEM_CLOCK 12000000U /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System Initialization *----------------------------------------------------------------------------*/ void SystemInit (void) { /* do not use global variables because this function is called before reaching pre-main. RW section may be overwritten afterwards. */ // Invalidate entire Unified TLB __set_TLBIALL(0); // Invalidate entire branch predictor array __set_BPIALL(0); __DSB(); __ISB(); // Invalidate instruction cache and flush branch target cache __set_ICIALLU(0); __DSB(); __ISB(); // Invalidate data cache L1C_InvalidateDCacheAll(); #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) // Enable FPU __FPU_Enable(); #endif // Create Translation Table MMU_CreateTranslationTable(); // Enable MMU MMU_Enable(); // Enable Caches L1C_EnableCaches(); L1C_EnableBTAC(); #if (__L2C_PRESENT == 1) // Enable GIC L2C_Enable(); #endif // IRQ Initialize IRQ_Initialize(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h ================================================ /****************************************************************************** * @file system_ARMCA7.h * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA7_H #define __SYSTEM_ARMCA7_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA7_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0 ================================================ /****************************************************************************** * @file system_ARMCA7.h * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA7_H #define __SYSTEM_ARMCA7_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA7_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup - component: Device:IRQ Controller:GIC misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with VFP support cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether CT model has been built with NEON support cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cluster.l1_icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful implementation cluster.l1_dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful implementation cluster.l2_cache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether L2 cache has stateful implementation #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0 ================================================ /*-Memory Regions-*/ define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; define symbol __ICFEDIT_region_IROM2_start__ = 0x0; define symbol __ICFEDIT_region_IROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM1_start__ = 0x0; define symbol __ICFEDIT_region_EROM1_end__ = 0x0; define symbol __ICFEDIT_region_EROM2_start__ = 0x0; define symbol __ICFEDIT_region_EROM2_end__ = 0x0; define symbol __ICFEDIT_region_EROM3_start__ = 0x0; define symbol __ICFEDIT_region_EROM3_end__ = 0x0; define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_irqstack__ = 0x100; define symbol __ICFEDIT_size_fiqstack__ = 0x100; define symbol __ICFEDIT_size_svcstack__ = 0x100; define symbol __ICFEDIT_size_abtstack__ = 0x100; define symbol __ICFEDIT_size_undstack__ = 0x100; define symbol __ICFEDIT_size_heap__ = 0x8000; define symbol __ICFEDIT_size_ttb__ = 0x4000; define memory mem with size = 4G; define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; do not initialize { section .noinit }; initialize by copy { readwrite }; if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) { // Required in a multi-threaded application initialize by copy with packing = none { section __DLIB_PERTHREAD }; } place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; place in IROM_region { readonly }; place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; place in TTB_region { block TTB }; ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld ================================================ #include "mem_ARMCA9.h" MEMORY { ROM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } ENTRY(Reset_Handler) SECTIONS { .text : { Image$$VECTORS$$Base = .; * (RESET) KEEP(*(.isr_vector)) Image$$VECTORS$$Limit = .; *(SVC_TABLE) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) Image$$RO_DATA$$Base = .; *(.rodata*) Image$$RO_DATA$$Limit = .; KEEP(*(.eh_frame*)) } > ROM .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > ROM __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > ROM __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG (__data_end__ - __data_start__) __copy_table_end__ = .; } > ROM .zero.table : { . = ALIGN(4); __zero_table_start__ = .; LONG (__bss_start__) LONG (__bss_end__ - __bss_start__) __zero_table_end__ = .; } > ROM __etext = .; .ttb : { Image$$TTB$$ZI$$Base = .; . += __TTB_SIZE; Image$$TTB$$ZI$$Limit = .; } > L_TTB .data : { Image$$RW_DATA$$Base = .; __data_start__ = .; *(vtable) *(.data*) Image$$RW_DATA$$Limit = .; . = ALIGN(4); /* preinit data */ PROVIDE (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE (__fini_array_end = .); . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM .bss ALIGN(0x400): { Image$$ZI_DATA$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; Image$$ZI_DATA$$Limit = .; __end__ = .; end = __end__; } > RAM AT > RAM #if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0) .heap (NOLOAD): { . = ALIGN(8); Image$$HEAP$$ZI$$Base = .; . += __HEAP_SIZE; Image$$HEAP$$ZI$$Limit = .; __HeapLimit = .; } > RAM #endif .stack (NOLOAD): { . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE; . = ALIGN(8); __StackTop = .; Image$$SYS_STACK$$ZI$$Base = .; . += __STACK_SIZE; Image$$SYS_STACK$$ZI$$Limit = .; __stack = .; Image$$FIQ_STACK$$ZI$$Base = .; . += __FIQ_STACK_SIZE; Image$$FIQ_STACK$$ZI$$Limit = .; Image$$IRQ_STACK$$ZI$$Base = .; . += __IRQ_STACK_SIZE; Image$$IRQ_STACK$$ZI$$Limit = .; Image$$SVC_STACK$$ZI$$Base = .; . += __SVC_STACK_SIZE; Image$$SVC_STACK$$ZI$$Limit = .; Image$$ABT_STACK$$ZI$$Base = .; . += __ABT_STACK_SIZE; Image$$ABT_STACK$$ZI$$Limit = .; Image$$UND_STACK$$ZI$$Base = .; . += __UND_STACK_SIZE; Image$$UND_STACK$$ZI$$Limit = .; } > RAM } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc ;************************************************** ; Copyright (c) 2017 ARM Ltd. All rights reserved. ;************************************************** ; Scatter-file for RTX Example on Versatile Express ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. ; This platform has 2GB SDRAM starting at 0x80000000. #include "mem_ARMCA9.h" SDRAM __ROM_BASE __ROM_SIZE ; load region size_region { VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address { * (RESET, +FIRST) ; Vector table and other startup code * (InRoot$$Sections) ; All (library) code that must be in a root region * (+RO-CODE) ; Application RO code (.text) * (+RO-DATA) ; Application RO data (.constdata) } RW_DATA __RAM_BASE __RW_DATA_SIZE { * (+RW) } ; Application RW data (.data) ZI_DATA (__RAM_BASE+ __RW_DATA_SIZE) __ZI_DATA_SIZE { * (+ZI) } ; Application ZI data (.bss) ARM_LIB_HEAP (__RAM_BASE +__RW_DATA_SIZE +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up { } ARM_LIB_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down { } UND_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack { } ABT_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack { } SVC_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack { } IRQ_STACK (__RAM_BASE +__RAM_SIZE -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack { } FIQ_STACK (__RAM_BASE +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack { } TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU { } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h ================================================ /**************************************************************************//** * @file mem_ARMCA9.h * @brief Memory base and size definitions (used in scatter file) * @version V1.1.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __MEM_ARMCA9_H #define __MEM_ARMCA9_H /*---------------------------------------------------------------------------- User Stack & Heap size definition *----------------------------------------------------------------------------*/ /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- ROM Configuration ------------------------------------ // // ROM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // ROM Base Address <0x0-0xFFFFFFFF:0x100000> // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x80000000 #define __ROM_SIZE 0x00200000 /*--------------------- RAM Configuration ----------------------------------- // RAM Configuration // For compatibility with MMU config the sections must be multiple of 1MB // RAM Base Address <0x0-0xFFFFFFFF:0x100000> // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> // Data Sections // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> // // Stack / Heap Configuration // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> // Exceptional Modes // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // // // *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x80200000 #define __RAM_SIZE 0x00200000 #define __RW_DATA_SIZE 0x00100000 #define __ZI_DATA_SIZE 0x000F0000 #define __STACK_SIZE 0x00001000 #define __HEAP_SIZE 0x00008000 #define __UND_STACK_SIZE 0x00000100 #define __ABT_STACK_SIZE 0x00000100 #define __SVC_STACK_SIZE 0x00000100 #define __IRQ_STACK_SIZE 0x00000100 #define __FIQ_STACK_SIZE 0x00000100 /*----------------------------------------------------------------------------*/ /*--------------------- TTB Configuration ------------------------------------ // // TTB Configuration // The TLB L1 contains 4096 32-bit entries and must be 16kB aligned // The TLB L2 entries are placed after the L1 in the MMU config // TTB Base Address <0x0-0xFFFFFFFF:0x4000> // TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> // *----------------------------------------------------------------------------*/ #define __TTB_BASE 0x80500000 #define __TTB_SIZE 0x00005000 #endif /* __MEM_ARMCA9_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c ================================================ /**************************************************************************//** * @file mmu_ARMCA9.c * @brief MMU Configuration for Arm Cortex-A9 Device Series * @version V1.2.0 * @date 15. May 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map Memory Type 0xffffffff |--------------------------| ------------ | FLAG SYNC | Device Memory 0xfffff000 |--------------------------| ------------ | Fault | Fault 0xfff00000 |--------------------------| ------------ | | Normal | | | Daughterboard | | memory | | | 0x80505000 |--------------------------| ------------ |TTB (L2 Sync Flags ) 4k | Normal 0x80504C00 |--------------------------| ------------ |TTB (L2 Peripherals-B) 16k| Normal 0x80504800 |--------------------------| ------------ |TTB (L2 Peripherals-A) 16k| Normal 0x80504400 |--------------------------| ------------ |TTB (L2 Priv Periphs) 4k | Normal 0x80504000 |--------------------------| ------------ | TTB (L1 Descriptors) | Normal 0x80500000 |--------------------------| ------------ | Stack | Normal |--------------------------| ------------ | Heap | Normal 0x80400000 |--------------------------| ------------ | ZI Data | Normal 0x80300000 |--------------------------| ------------ | RW Data | Normal 0x80200000 |--------------------------| ------------ | RO Data | Normal |--------------------------| ------------ | RO Code | USH Normal 0x80000000 |--------------------------| ------------ | Daughterboard | Fault | HSB AXI buses | 0x40000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x2c002000 |--------------------------| ------------ | Private Address | Device Memory 0x2c000000 |--------------------------| ------------ | Daughterboard | Fault | test chips peripherals | 0x20000000 |--------------------------| ------------ | Peripherals | Device Memory RW/RO | | & Fault 0x00000000 |--------------------------| */ // L1 Cache info and restrictions about architecture of the caches (CCSIR register): // Write-Through support *not* available // Write-Back support available. // Read allocation support available. // Write allocation support available. //Note: You should use the Shareable attribute carefully. //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. //Following MMU configuration is expected //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) //Domain 0 is always the Client domain //Descriptors should place all memory in domain 0 #include "ARMCA9.h" #include "mem_ARMCA9.h" // TTB base address #define TTB_BASE ((uint32_t*)__TTB_BASE) // L2 table pointers //---------------------------------------- #define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core // into 4096 equally sized sections, each of which describes 1MB of virtual memory space. // The L1 translation table therefore contains 4096 32-bit (word-sized) entries. #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization //--------------------- PERIPHERALS ------------------- #define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M) #define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M) //--------------------- SYNC FLAGS -------------------- #define FLAG_SYNC 0xFFFFF000 #define F_SYNC_BASE 0xFFF00000 //1M aligned static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable /* Define global descriptors */ static uint32_t Page_L1_4k = 0x0; //generic static uint32_t Page_L1_64k = 0x0; //generic static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 void MMU_CreateTranslationTable(void) { mmu_region_attributes_Type region; //Create 4GB of faulting entries MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT); /* * Generate descriptors. Refer to core_ca.h to get information about attributes * */ //Create descriptors for Vectors, RO, RW, ZI sections section_normal(Sect_Normal, region); section_normal_cod(Sect_Normal_Cod, region); section_normal_ro(Sect_Normal_RO, region); section_normal_rw(Sect_Normal_RW, region); //Create descriptors for peripherals section_device_ro(Sect_Device_RO, region); section_device_rw(Sect_Device_RW, region); //Create descriptors for 64k pages page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); //Create descriptors for 4k pages page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); /* * Define MMU flat-map regions and attributes * */ //Define Image MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections //--------------------- PERIPHERALS ------------------- MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW); MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C000000-0x1C00FFFF MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT); // Define peripheral range 0x1C100000-0x1C10FFFF MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW); // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define private address space entry. MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Define L2CC entry. Uncomment if PL310 is present // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW); // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC) MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT); // Define synchronization space entry. MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW); /* Set location of level 1 page table ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) ; 13:7 - 0x0 ; 6 - IRGN[0] 0x1 (Inner WB WA) ; 5 - NOS 0x0 (Non-shared) ; 4:3 - RGN 0x01 (Outer WB WA) ; 2 - IMP 0x0 (Implementation Defined) ; 1 - S 0x0 (Non-shared) ; 0 - IRGN[1] 0x0 (Inner WB WA) */ __set_TTBR0(__TTB_BASE | 0x48); __ISB(); /* Set up domain access control register ; We set domain 0 to Client and all other domains to No Access. ; All translation table entries specify domain 0 */ __set_DACR(1); __ISB(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c ================================================ /****************************************************************************** * @file startup_ARMCA9.c * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series * @version V1.0.1 * @date 10. January 2021 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include /*---------------------------------------------------------------------------- Definitions *----------------------------------------------------------------------------*/ #define USR_MODE 0x10 // User mode #define FIQ_MODE 0x11 // Fast Interrupt Request mode #define IRQ_MODE 0x12 // Interrupt Request mode #define SVC_MODE 0x13 // Supervisor mode #define ABT_MODE 0x17 // Abort mode #define UND_MODE 0x1B // Undefined Instruction mode #define SYS_MODE 0x1F // System mode /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void Vectors (void) __attribute__ ((naked, section("RESET"))); void Reset_Handler (void) __attribute__ ((naked)); void Default_Handler(void) __attribute__ ((noreturn)); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ void Vectors(void) { __ASM volatile( "LDR PC, =Reset_Handler \n" "LDR PC, =Undef_Handler \n" "LDR PC, =SVC_Handler \n" "LDR PC, =PAbt_Handler \n" "LDR PC, =DAbt_Handler \n" "NOP \n" "LDR PC, =IRQ_Handler \n" "LDR PC, =FIQ_Handler \n" ); } /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ void Reset_Handler(void) { __ASM volatile( // Mask interrupts "CPSID if \n" // Put any cores other than 0 to sleep "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR "ANDS R0, R0, #3 \n" "goToSleep: \n" "WFINE \n" "BNE goToSleep \n" // Reset SCTLR Settings "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register "ISB \n" // Configure ACTLR "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1) "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table "LDR R0, =Vectors \n" "MCR p15, 0, R0, c12, c0, 0 \n" // Setup Stack for each exceptional mode "CPS #0x11 \n" "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n" "CPS #0x12 \n" "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n" "CPS #0x13 \n" "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n" "CPS #0x17 \n" "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n" "CPS #0x1B \n" "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n" "CPS #0x1F \n" #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n" #elif defined ( __GNUC__ ) "LDR SP, =Image$$SYS_STACK$$ZI$$Limit \n" #else #error Unknown compiler. #endif // Call SystemInit "BL SystemInit \n" // Unmask interrupts "CPSIE if \n" // Call __main #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) "BL __main \n" #elif defined ( __GNUC__ ) "BL _start \n" #else #error Unknown compiler. #endif ); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s ================================================ /****************************************************************************** * @file startup_ARMCA9.s * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA9 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(2) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCA9.s * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series * @version V1.00 * @date 01 Nov 2017 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ MODULE ?startup_ARMCA9 /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ PUBLIC Reset_Handler PUBWEAK Undef_Handler PUBWEAK SVC_Handler PUBWEAK PAbt_Handler PUBWEAK DAbt_Handler PUBWEAK IRQ_Handler PUBWEAK FIQ_Handler SECTION SVC_STACK:DATA:NOROOT(3) SECTION IRQ_STACK:DATA:NOROOT(3) SECTION FIQ_STACK:DATA:NOROOT(3) SECTION ABT_STACK:DATA:NOROOT(3) SECTION UND_STACK:DATA:NOROOT(3) SECTION USR_STACK:DATA:NOROOT(3) /*---------------------------------------------------------------------------- Exception / Interrupt Vector Table *----------------------------------------------------------------------------*/ section RESET:CODE:NOROOT(2) PUBLIC Vectors Vectors: LDR PC, =Reset_Handler LDR PC, =Undef_Handler LDR PC, =SVC_Handler LDR PC, =PAbt_Handler LDR PC, =DAbt_Handler NOP LDR PC, =IRQ_Handler LDR PC, =FIQ_Handler section .text:CODE:NOROOT(2) /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ EXTERN SystemInit EXTERN __iar_program_start Reset_Handler: // Mask interrupts CPSID if // Put any cores other than 0 to sleep MRC p15, 0, R0, c0, c0, 5 ANDS R0, R0, #3 goToSleep: WFINE BNE goToSleep // Reset SCTLR Settings MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register ISB // Configure ACTLR MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register // Set Vector Base Address Register (VBAR) to point to this application's vector table LDR R0, =Vectors MCR p15, 0, R0, c12, c0, 0 // Setup Stack for each exception mode CPS #0x11 LDR SP, =SFE(FIQ_STACK) CPS #0x12 LDR SP, =SFE(IRQ_STACK) CPS #0x13 LDR SP, =SFE(SVC_STACK) CPS #0x17 LDR SP, =SFE(ABT_STACK) CPS #0x1B LDR SP, =SFE(UND_STACK) CPS #0x1F LDR SP, =SFE(USR_STACK) // Call SystemInit BL SystemInit // Unmask interrupts CPSIE if // Call __iar_program_start BL __iar_program_start /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ Undef_Handler: SVC_Handler: PAbt_Handler: DAbt_Handler: IRQ_Handler: FIQ_Handler: Default_Handler: B . END ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c ================================================ /****************************************************************************** * @file system_ARMCA9.c * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series * @version V1.0.1 * @date 13. February 2019 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #define SYSTEM_CLOCK 12000000U /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System Initialization *----------------------------------------------------------------------------*/ void SystemInit (void) { /* do not use global variables because this function is called before reaching pre-main. RW section may be overwritten afterwards. */ // Invalidate entire Unified TLB __set_TLBIALL(0); // Invalidate entire branch predictor array __set_BPIALL(0); __DSB(); __ISB(); // Invalidate instruction cache and flush branch target cache __set_ICIALLU(0); __DSB(); __ISB(); // Invalidate data cache L1C_InvalidateDCacheAll(); #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) // Enable FPU __FPU_Enable(); #endif // Create Translation Table MMU_CreateTranslationTable(); // Enable MMU MMU_Enable(); // Enable Caches L1C_EnableCaches(); L1C_EnableBTAC(); #if (__L2C_PRESENT == 1) // Enable GIC L2C_Enable(); #endif // IRQ Initialize IRQ_Initialize(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h ================================================ /****************************************************************************** * @file system_ARMCA9.h * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA9_H #define __SYSTEM_ARMCA9_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA9_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0 ================================================ /****************************************************************************** * @file system_ARMCA9.h * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series * @version V1.00 * @date 10. January 2018 * * @note * ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __SYSTEM_ARMCA9_H #define __SYSTEM_ARMCA9_H #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); /** \brief Create Translation Table. Creates Memory Management Unit Translation Table. */ extern void MMU_CreateTranslationTable(void); #ifdef __cplusplus } #endif #endif /* __SYSTEM_ARMCA9_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup - component: Device:IRQ Controller:GIC misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- motherboard.vis.disable_visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cluster.cpu0.ase-present=0 # (bool , init-time) default = '1' : Set whether model has NEON support cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF] cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF] cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF] cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F] cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cluster.dcache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation cluster.icache-state_modelled=1 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c ================================================ /****************************************************************************** * @file startup_ARMCM0.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM0) #include "ARMCM0.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10..31 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM0.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM0) #include "ARMCM0.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10..31 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c ================================================ /**************************************************************************//** * @file system_ARMCM0.c * @brief CMSIS Device System Source File for * ARMCM0 Device * @version V1.0.0 * @date 09. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM0.h" /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation #------------------------------------------------------------------------------ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c ================================================ /****************************************************************************** * @file startup_ARMCM0plus.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM0P) #include "ARMCM0plus.h" #elif defined (ARMCM0P_MPU) #include "ARMCM0plus_MPU.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10..31 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM0plus.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM0P) #include "ARMCM0plus.h" #elif defined (ARMCM0P_MPU) #include "ARMCM0plus_MPU.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10..31 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c ================================================ /**************************************************************************//** * @file system_ARMCM0plus.c * @brief CMSIS Device System Source File for * ARMCM0plus Device * @version V1.0.1 * @date 05. September 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM0plus.h" /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #------------------------------------------------------------------------------ fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation #------------------------------------------------------------------------------ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c ================================================ /**************************************************************************//** * @file system_ARMCM23.c * @brief CMSIS Device System Source File for * ARMCM23 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM23.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00200000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20200000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00200000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20200000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/system_ARMCM23.c ================================================ /**************************************************************************//** * @file system_ARMCM23.c * @brief CMSIS Device System Source File for * ARMCM23 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM23.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h ================================================ /**************************************************************************//** * @file partition_ARMCM23.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 * @version V5.3.1 * @date 09. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM23_H #define PARTITION_ARMCM23_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of single SysTick */ #define SCB_ICSR_INIT 0 /* // in a single SysTick implementation, SysTick is // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS // only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM23_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/system_ARMCM23.c ================================================ /**************************************************************************//** * @file system_ARMCM23.c * @brief CMSIS Device System Source File for * ARMCM23 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM23.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h ================================================ /**************************************************************************//** * @file partition_ARMCM23.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 * @version V5.3.1 * @date 09. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM23_H #define PARTITION_ARMCM23_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of single SysTick */ #define SCB_ICSR_INIT 0 /* // in a single SysTick implementation, SysTick is // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS // only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x0000122B /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM23_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM23.c * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ 0, /* Reserved */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/system_ARMCM23.c ================================================ /**************************************************************************//** * @file system_ARMCM23.c * @brief CMSIS Device System Source File for * ARMCM23 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM23) #include "ARMCM23.h" #elif defined (ARMCM23_TZ) #include "ARMCM23_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM23.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c ================================================ /****************************************************************************** * @file startup_ARMCM3.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM3) #include "ARMCM3.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM3.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM3) #include "ARMCM3.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c ================================================ /**************************************************************************//** * @file system_ARMCM3.c * @brief CMSIS Device System Source File for * ARMCM3 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM3.h" /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 ================================================ /**************************************************************************//** * @file system_ARMCM3.c * @brief CMSIS Device System Source File for * ARMCM3 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "ARMCM3.h" /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm3ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm3ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm3ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm3ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm3ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm3ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm3ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm3ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/system_ARMCM33.c ================================================ /**************************************************************************//** * @file system_ARMCM33.c * @brief CMSIS Device System Source File for * ARMCM33 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00200000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20200000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00200000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20200000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c ================================================ /**************************************************************************//** * @file system_ARMCM33.c * @brief CMSIS Device System Source File for * ARMCM33 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h ================================================ /**************************************************************************//** * @file partition_ARMCM33.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 * @version V1.1.1 * @date 12. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM33_H #define PARTITION_ARMCM33_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM33_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c ================================================ /**************************************************************************//** * @file system_ARMCM33.c * @brief CMSIS Device System Source File for * ARMCM33 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h ================================================ /**************************************************************************//** * @file partition_ARMCM33.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 * @version V1.1.1 * @date 12. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM33_H #define PARTITION_ARMCM33_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x0000122B /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM33_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM33.c * @brief CMSIS-Core Device Startup File for Cortex-M33 Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVCall Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c ================================================ /**************************************************************************//** * @file system_ARMCM33.c * @brief CMSIS Device System Source File for * ARMCM33 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM33) #include "ARMCM33.h" #elif defined (ARMCM33_TZ) #include "ARMCM33_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #elif defined (ARMCM33_DSP_FP) #include "ARMCM33_DSP_FP.h" #elif defined (ARMCM33_DSP_FP_TZ) #include "ARMCM33_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM33.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/system_ARMCM35P.c ================================================ /**************************************************************************//** * @file system_ARMCM35P.c * @brief CMSIS Device System Source File for * ARMCM35P Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00200000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20200000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00200000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20200000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c ================================================ /**************************************************************************//** * @file system_ARMCM35P.c * @brief CMSIS Device System Source File for * ARMCM35P Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h ================================================ /**************************************************************************//** * @file partition_ARMCM35P.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P * @version V1.0.0 * @date 03. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM35P_H #define PARTITION_ARMCM35P_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM35P_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c ================================================ /**************************************************************************//** * @file system_ARMCM35P.c * @brief CMSIS Device System Source File for * ARMCM35P Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h ================================================ /**************************************************************************//** * @file partition_ARMCM35P.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P * @version V1.0.0 * @date 03. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM35P_H #define PARTITION_ARMCM35P_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x0000122B /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM35P_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM35P.c * @brief CMSIS-Core Device Startup File for Cortex-M35P Device * @version V2.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c ================================================ /**************************************************************************//** * @file system_ARMCM35P.c * @brief CMSIS Device System Source File for * ARMCM35P Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM35P) #include "ARMCM35P.h" #elif defined (ARMCM35P_TZ) #include "ARMCM35P_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #elif defined (ARMCM35P_DSP_FP) #include "ARMCM35P_DSP_FP.h" #elif defined (ARMCM35P_DSP_FP_TZ) #include "ARMCM35P_DSP_FP_TZ.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM35P.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c ================================================ /****************************************************************************** * @file startup_ARMCM4.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM4.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c ================================================ /**************************************************************************//** * @file system_ARMCM4.c * @brief CMSIS Device System Source File for * ARMCM4 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support armcortexm4ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm4ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm4ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm4ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c ================================================ /****************************************************************************** * @file startup_ARMCM4.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM4.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/system_ARMCM4.c ================================================ /**************************************************************************//** * @file system_ARMCM4.c * @brief CMSIS Device System Source File for * ARMCM4 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM4) #include "ARMCM4.h" #elif defined (ARMCM4_FP) #include "ARMCM4_FP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/tiac_arm.cmd ================================================ /****************************************************************************/ /* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS */ /* */ /* Description: This file is a sample command file that can be used */ /* for linking programs built with the TI Arm Clang */ /* Compiler. Use it as a guideline; you may want to change */ /* the allocation scheme according to the size of your */ /* program and the memory layout of your target system. */ /* */ /****************************************************************************/ -c /* LINK USING C CONVENTIONS */ -stack 0x4000 /* SOFTWARE STACK SIZE */ -heap 0x4000 /* HEAP AREA SIZE */ --args 0x1000 /* SPECIFY THE SYSTEM MEMORY MAP */ MEMORY { V_MEM : org = 0x00000000 len = 0x00001000 /* INT VECTOR */ P_MEM : org = 0x00001000 len = 0x20000000 /* PROGRAM MEMORY (ROM) */ D_MEM : org = 0x20001000 len = 0x20000000 /* DATA MEMORY (RAM) */ } /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ SECTIONS { .intvecs : {} > 0x0 /* INTERRUPT VECTORS */ .bss : {} > D_MEM /* GLOBAL & STATIC VARS */ .data : {} > D_MEM .sysmem : {} > D_MEM /* DYNAMIC MEMORY ALLOCATION AREA */ .stack : {} > D_MEM /* SOFTWARE SYSTEM STACK */ .text : {} > P_MEM /* CODE */ .cinit : {} > P_MEM /* INITIALIZATION TABLES */ .const : {} > P_MEM /* CONSTANT DATA */ .rodata : {} > P_MEM, palign(4) .init_array : {} > P_MEM /* C++ CONSTRUCTOR TABLES */ .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT) } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support armcortexm4ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm4ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm4ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm4ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm4ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00200000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20200000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00200000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20200000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h ================================================ /**************************************************************************//** * @file partition_ARMCM55.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 20. March 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM55_H #define PARTITION_ARMCM55_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM55_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.2.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h ================================================ /**************************************************************************//** * @file partition_ARMCM55.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 20. March 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM55_H #define PARTITION_ARMCM55_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x0000122B /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM55_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 ================================================ /****************************************************************************** * @file startup_ARMCM55.c * @brief CMSIS-Core Device Startup File for Cortex-M55 Device * @version V1.1.0 * @date 16. December 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 ================================================ /**************************************************************************//** * @file system_ARMCM55.c * @brief CMSIS Device System Source File for * ARMCM55 Device * @version V1.1.0 * @date 28. March 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM55) #include "ARMCM55.h" #else #error device not specified! #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM55.h" #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL ( 5000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (5U * XTAL) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Set low-power state for PDEPU */ /* 0b00 | ON, PDEPU is not in low-power state */ /* 0b01 | ON, but the clock is off */ /* 0b10 | RET(ention) */ /* 0b11 | OFF */ /* Clear ELPSTATE, value is 0b11 on Cold reset */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c ================================================ /**************************************************************************//** * @file system_ARMCM7.c * @brief CMSIS Device System Source File for * ARMCM7 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c ================================================ /**************************************************************************//** * @file system_ARMCM7.c * @brief CMSIS Device System Source File for * ARMCM7 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. armcortexm7ct.DP_FLOAT=1 # (bool , init-time) default = '1' : Support 8-byte floats #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc ; command above MUST be in first line (no comment above!) /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /*---------------------------------------------------------------------------- Scatter File Definitions definition *----------------------------------------------------------------------------*/ #define __RO_BASE __ROM_BASE #define __RO_SIZE __ROM_SIZE #define __RW_BASE __RAM_BASE #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device * @version V2.1.0 * @date 04. August 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3 ================================================ /****************************************************************************** * @file startup_ARMCM7.c * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device * @version V2.0.3 * @date 31. March 2020 ******************************************************************************/ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 223 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/system_ARMCM7.c ================================================ /**************************************************************************//** * @file system_ARMCM7.c * @brief CMSIS Device System Source File for * ARMCM7 Device * @version V1.0.1 * @date 15. November 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM7) #include "ARMCM7.h" #elif defined (ARMCM7_SP) #include "ARMCM7_SP.h" #elif defined (ARMCM7_DP) #include "ARMCM7_DP.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); #endif #if defined (__FPU_USED) && (__FPU_USED == 1U) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. armcortexm7ct.DP_FLOAT=0 # (bool , init-time) default = '1' : Support 8-byte floats #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00200000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20200000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00200000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20200000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h ================================================ /**************************************************************************//** * @file partition_ARMCM85.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 07. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM85_H #define PARTITION_ARMCM85_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Description */ #define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Description */ #define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Description */ #define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Description */ #define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Description */ #define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Description */ #define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Description */ #define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Description */ #define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM85_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 ================================================ /**************************************************************************//** * @file partition_ARMCM85.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 07. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM85_H #define PARTITION_ARMCM85_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Description */ #define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Description */ #define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Description */ #define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Description */ #define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Description */ #define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Description */ #define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Description */ #define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Description */ #define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM85_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00200000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00200000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_NOINIT __RW_BASE UNINIT __RW_SIZE { *(.bss.noinit) } RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 ================================================ #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". ; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse /* ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*--------------------- Flash Configuration ---------------------------------- ; Flash Configuration ; Flash Base Address <0x0-0xFFFFFFFF:8> ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __ROM_BASE 0x00000000 #define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration ; RAM Base Address <0x0-0xFFFFFFFF:8> ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __RAM_BASE 0x20000000 #define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ #define __STACK_SIZE 0x00000400 #define __HEAP_SIZE 0x00000C00 /*--------------------- CMSE Veneer Configuration --------------------------- ; CMSE Veneer Configuration ; CMSE VeneerBase Address <0x0-0xFFFFFFFF:8> ; 0xFFFFFFFF: Place Veneers at the end of Flash (default) ; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_BASE 0xFFFFFFFF #define __CMSEVENEER_SIZE 0x00000400 /* ;------------- <<< end of configuration section >>> --------------------------- */ /*---------------------------------------------------------------------------- User Stack & Heap boundary definition *----------------------------------------------------------------------------*/ #define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define __STACKSEAL_SIZE ( 8 ) #else #define __STACKSEAL_SIZE ( 0 ) #endif /*---------------------------------------------------------------------------- Region base & size definition *----------------------------------------------------------------------------*/ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF) #define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) #else #define __CV_BASE ( __CMSEVENEER_BASE ) #endif #define __CV_SIZE ( __CMSEVENEER_SIZE ) #else #define __CV_SIZE ( 0 ) #endif #define __RO_BASE ( __ROM_BASE ) #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) #define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) /*---------------------------------------------------------------------------- Scatter Region definition *----------------------------------------------------------------------------*/ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_RAM __RW_BASE __RW_SIZE { ; RW data .ANY (+RW +ZI) } #if __HEAP_SIZE > 0 ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap } #endif ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } } #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00200000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00200000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 8; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ .gnu.sgstubs : { . = ALIGN(32); } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 ================================================ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-M based device ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- */ /*---------------------- Flash Configuration ---------------------------------- Flash Configuration Flash Base Address <0x0-0xFFFFFFFF:8> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __ROM_BASE = 0x00000000; __ROM_SIZE = 0x00040000; /*--------------------- Embedded RAM Configuration ---------------------------- RAM Configuration RAM Base Address <0x0-0xFFFFFFFF:8> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00020000; /*--------------------- Stack / Heap Configuration ---------------------------- Stack / Heap Configuration Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00000400; __HEAP_SIZE = 0x00000C00; /* *-------------------- <<< end of configuration section >>> ------------------- */ /* ARMv8-M stack sealing: to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 */ __STACKSEAL_SIZE = 0; MEMORY { FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end * __copy_table_start__ * __copy_table_end__ * __zero_table_start__ * __zero_table_end__ * __etext * __data_start__ * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * __data_end__ * __bss_start__ * __bss_end__ * __end__ * end * __HeapLimit * __StackLimit * __StackTop * __stack * __StackSeal (only if ARMv8-M stack sealing is used) */ ENTRY(Reset_Handler) SECTIONS { .text : { KEEP(*(.vectors)) *(.text*) KEEP(*(.init)) KEEP(*(.fini)) /* .ctors */ *crtbegin.o(.ctors) *crtbegin?.o(.ctors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) *(SORT(.ctors.*)) *(.ctors) /* .dtors */ *crtbegin.o(.dtors) *crtbegin?.o(.dtors) *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) *(.rodata*) KEEP(*(.eh_frame*)) } > FLASH /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address * must be set, either with the command line option --section-start or in a linker script, * to indicate where to place these veneers in memory. */ /* .gnu.sgstubs : { . = ALIGN(32); } > FLASH */ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > FLASH __exidx_end = .; .copy.table : { . = ALIGN(4); __copy_table_start__ = .; LONG (__etext) LONG (__data_start__) LONG ((__data_end__ - __data_start__) / 4) /* Add each additional data section here */ /* LONG (__etext2) LONG (__data2_start__) LONG ((__data2_end__ - __data2_start__) / 4) */ __copy_table_end__ = .; } > FLASH .zero.table : { . = ALIGN(4); __zero_table_start__ = .; /* Add each additional bss section here */ /* LONG (__bss2_start__) LONG ((__bss2_end__ - __bss2_start__) / 4) */ __zero_table_end__ = .; } > FLASH /** * Location counter can end up 2byte aligned with narrow Thumb code but * __etext is assumed by startup code to be the LMA of a section in RAM * which must be 4byte aligned */ __etext = ALIGN (4); .data : AT (__etext) { __data_start__ = .; *(vtable) *(.data) *(.data.*) . = ALIGN(4); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) KEEP(*(.fini_array)) PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) . = ALIGN(4); /* All data end */ __data_end__ = .; } > RAM /* * Secondary data section, optional * * Remember to add each additional data section * to the .copy.table above to asure proper * initialization during startup. */ /* __etext2 = ALIGN (4); .data2 : AT (__etext2) { . = ALIGN(4); __data2_start__ = .; *(.data2) *(.data2.*) . = ALIGN(4); __data2_end__ = .; } > RAM2 */ .bss : { . = ALIGN(4); __bss_start__ = .; *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); __bss_end__ = .; } > RAM AT > RAM /* * Secondary bss section, optional * * Remember to add each additional bss section * to the .zero.table above to asure proper * initialization during startup. */ /* .bss2 : { . = ALIGN(4); __bss2_start__ = .; *(.bss2) *(.bss2.*) . = ALIGN(4); __bss2_end__ = .; } > RAM2 AT > RAM2 */ .heap (COPY) : { . = ALIGN(8); __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); __HeapLimit = .; } > RAM .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackLimit = .; . = . + __STACK_SIZE; . = ALIGN(8); __StackTop = .; } > RAM PROVIDE(__stack = __StackTop); /* ARMv8-M stack sealing: to use ARMv8-M stack sealing uncomment '.stackseal' section */ /* .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : { . = ALIGN(8); __StackSeal = .; . = . + 8; . = ALIGN(8); } > RAM */ /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h ================================================ /**************************************************************************//** * @file partition_ARMCM85.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 07. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM85_H #define PARTITION_ARMCM85_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Description */ #define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Description */ #define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Description */ #define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Description */ #define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Description */ #define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Description */ #define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Description */ #define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Description */ #define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x0000122B /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM85_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 ================================================ /**************************************************************************//** * @file partition_ARMCM85.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 07. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM85_H #define PARTITION_ARMCM85_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Description */ #define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Description */ #define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Description */ #define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Description */ #define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Description */ #define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Description */ #define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Description */ #define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Description */ #define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */ /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM85_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 ================================================ /****************************************************************************** * @file startup_ARMCM85.c * @brief CMSIS Device Startup File for ARMCM85 Device * @version V1.0.0 * @date 07. February 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #else #error device not specified! #endif /*---------------------------------------------------------------------------- External References *----------------------------------------------------------------------------*/ extern uint32_t __INITIAL_SP; extern uint32_t __STACK_LIMIT; #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) extern uint32_t __STACK_SEAL; #endif extern __NO_RETURN void __PROGRAM_START(void); /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler (void); void Default_Handler(void); /*---------------------------------------------------------------------------- Exception / Interrupt Handler *----------------------------------------------------------------------------*/ /* Exceptions */ void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void HardFault_Handler (void) __attribute__ ((weak)); void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ #if defined ( __GNUC__ ) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpedantic" #endif extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ Reset_Handler, /* Reset Handler */ NMI_Handler, /* -14 NMI Handler */ HardFault_Handler, /* -13 Hard Fault Handler */ MemManage_Handler, /* -12 MPU Fault Handler */ BusFault_Handler, /* -11 Bus Fault Handler */ UsageFault_Handler, /* -10 Usage Fault Handler */ SecureFault_Handler, /* -9 Secure Fault Handler */ 0, /* Reserved */ 0, /* Reserved */ 0, /* Reserved */ SVC_Handler, /* -5 SVC Handler */ DebugMon_Handler, /* -4 Debug Monitor Handler */ 0, /* Reserved */ PendSV_Handler, /* -2 PendSV Handler */ SysTick_Handler, /* -1 SysTick Handler */ /* Interrupts */ Interrupt0_Handler, /* 0 Interrupt 0 */ Interrupt1_Handler, /* 1 Interrupt 1 */ Interrupt2_Handler, /* 2 Interrupt 2 */ Interrupt3_Handler, /* 3 Interrupt 3 */ Interrupt4_Handler, /* 4 Interrupt 4 */ Interrupt5_Handler, /* 5 Interrupt 5 */ Interrupt6_Handler, /* 6 Interrupt 6 */ Interrupt7_Handler, /* 7 Interrupt 7 */ Interrupt8_Handler, /* 8 Interrupt 8 */ Interrupt9_Handler /* 9 Interrupt 9 */ /* Interrupts 10 .. 480 are left out */ }; #if defined ( __GNUC__ ) #pragma GCC diagnostic pop #endif /*---------------------------------------------------------------------------- Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __NO_RETURN void Reset_Handler(void) { __set_PSP((uint32_t)(&__INITIAL_SP)); __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); #endif SystemInit(); /* CMSIS System Initialization */ __PROGRAM_START(); /* Enter PreMain (C library entry point) */ } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wmissing-noreturn" #endif /*---------------------------------------------------------------------------- Hard Fault Handler *----------------------------------------------------------------------------*/ void HardFault_Handler(void) { while(1); } /*---------------------------------------------------------------------------- Default Handler for Exceptions / Interrupts *----------------------------------------------------------------------------*/ void Default_Handler(void) { while(1); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 ================================================ /**************************************************************************//** * @file system_ARMCM85.c * @brief CMSIS Device System Source File for ARMCM85 Device * @version V1.0.0 * @date 30. March 2022 ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined (ARMCM85) #include "ARMCM85.h" #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #include "partition_ARMCM85.h" #endif #else #error device not specified! #endif /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ #define XTAL (50000000UL) /* Oscillator frequency */ #define SYSTEM_CLOCK (XTAL / 2U) /*---------------------------------------------------------------------------- Exception / Interrupt Vector table *----------------------------------------------------------------------------*/ extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ /*---------------------------------------------------------------------------- System Core Clock update function *----------------------------------------------------------------------------*/ void SystemCoreClockUpdate (void) { SystemCoreClock = SYSTEM_CLOCK; } /*---------------------------------------------------------------------------- System initialization function *----------------------------------------------------------------------------*/ void SystemInit (void) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); #endif /* Set CPDLPSTATE.RLPSTATE to 0 Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ (3U << 11U*2U) ); /* enable CP11 Full Access */ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ /* PDEPU ON, Clock OFF */ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; #endif #ifdef UNALIGNED_SUPPORT_DISABLE SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Enable Loop and branch info cache */ SCB->CCR |= SCB_CCR_LOB_Msk; /* Enable Branch Prediction */ SCB->CCR |= SCB_CCR_BP_Msk; __DSB(); __ISB(); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) TZ_SAU_Setup(); #endif SystemCoreClock = SYSTEM_CLOCK; } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/Target.clayer.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json layer: # type: Target description: Target setup # packs: # - pack: ARM::CMSIS components: # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - component: ARM::CMSIS:CORE - component: Device:Startup&C Startup misc: - for-compiler: IAR Link: [--config generic_cortex.icf] groups: - group: VHT/FVP files: - file: ./model_config.txt ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/model_config.txt ================================================ # Parameters: # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] #---------------------------------------------------------------------------------------------- fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support cpu0.MVE=1 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included cpu0.ID_ISAR5.PACBTI=1 # (int , init-time) default = '0x0' : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access. cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic #---------------------------------------------------------------------------------------------- ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/Bootloader.cproject.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json project: layers: # App: CMSIS-Core Validation for Cortex-M (Bootloader part) - layer: ../Layer/App/Bootloader_Cortex-M/App.clayer.yml for-context: - .AC6_low - .AC6_mid - .AC6_high - .AC6_size - .AC6_tiny - .GCC_low - .GCC_mid - .GCC_high - .GCC_size - .GCC_tiny - .IAR_low - .IAR_mid - .IAR_high - .IAR_size - .IAR_tiny #Target: CM23S - layer: ../Layer/Target/CM23S_BL/Target.clayer.yml for-context: - .AC6_low+CM23S - .AC6_mid+CM23S - .AC6_high+CM23S - .AC6_size+CM23S - .AC6_tiny+CM23S - .GCC_low+CM23S - .GCC_mid+CM23S - .GCC_high+CM23S - .GCC_size+CM23S - .GCC_tiny+CM23S - .IAR_low+CM23S - .IAR_mid+CM23S - .IAR_high+CM23S - .IAR_size+CM23S - .IAR_tiny+CM23S #Target: CM33S - layer: ../Layer/Target/CM33S_BL/Target.clayer.yml for-context: - .AC6_low+CM33S - .AC6_mid+CM33S - .AC6_high+CM33S - .AC6_size+CM33S - .AC6_tiny+CM33S - .GCC_low+CM33S - .GCC_mid+CM33S - .GCC_high+CM33S - .GCC_size+CM33S - .GCC_tiny+CM33S - .IAR_low+CM33S - .IAR_mid+CM33S - .IAR_high+CM33S - .IAR_size+CM33S - .IAR_tiny+CM33S #Target: CM35PS - layer: ../Layer/Target/CM35PS_BL/Target.clayer.yml for-context: - .AC6_low+CM35PS - .AC6_mid+CM35PS - .AC6_high+CM35PS - .AC6_size+CM35PS - .AC6_tiny+CM35PS - .GCC_low+CM35PS - .GCC_mid+CM35PS - .GCC_high+CM35PS - .GCC_size+CM35PS - .GCC_tiny+CM35PS - .IAR_low+CM35PS - .IAR_mid+CM35PS - .IAR_high+CM35PS - .IAR_size+CM35PS - .IAR_tiny+CM35PS #Target: CM55S - layer: ../Layer/Target/CM55S_BL/Target.clayer.yml for-context: - .AC6_low+CM55S - .AC6_mid+CM55S - .AC6_high+CM55S - .AC6_size+CM55S - .AC6_tiny+CM55S - .GCC_low+CM55S - .GCC_mid+CM55S - .GCC_high+CM55S - .GCC_size+CM55S - .GCC_tiny+CM55S - .IAR_low+CM55S - .IAR_mid+CM55S - .IAR_high+CM55S - .IAR_size+CM55S - .IAR_tiny+CM55S #Target: CM85S - layer: ../Layer/Target/CM85S_BL/Target.clayer.yml for-context: - .AC6_low+CM85S - .AC6_mid+CM85S - .AC6_high+CM85S - .AC6_size+CM85S - .AC6_tiny+CM85S - .GCC_low+CM85S - .GCC_mid+CM85S - .GCC_high+CM85S - .GCC_size+CM85S - .GCC_tiny+CM85S - .IAR_low+CM85S - .IAR_mid+CM85S - .IAR_high+CM85S - .IAR_size+CM85S - .IAR_tiny+CM85S ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.cproject.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json project: layers: # App: CMSIS-Core Validation for Cortex-M - layer: ../Layer/App/Validation_Cortex-M/App.clayer.yml for-context: - +CM0 - +CM0plus - +CM3 - +CM4 - +CM4FP - +CM7 - +CM7SP - +CM7DP - +CM23 - +CM23S - +CM23NS - +CM33 - +CM33S - +CM33NS - +CM35P - +CM35PS - +CM35PNS - +CM55S - +CM55NS - +CM85S - +CM85NS # App: CMSIS-Core Validation for Cortex-A - layer: ../Layer/App/Validation_Cortex-A/App.clayer.yml for-context: - +CA5 - +CA7 - +CA9 #Target: CM0 - layer: ../Layer/Target/CM0/Target.clayer.yml for-context: - .AC6_low+CM0 - .AC6_mid+CM0 - .AC6_high+CM0 - .AC6_size+CM0 - .AC6_tiny+CM0 - .GCC_low+CM0 - .GCC_mid+CM0 - .GCC_high+CM0 - .GCC_size+CM0 - .GCC_tiny+CM0 - .IAR_low+CM0 - .IAR_mid+CM0 - .IAR_high+CM0 - .IAR_size+CM0 - .IAR_tiny+CM0 #Target: CM0plus - layer: ../Layer/Target/CM0plus/Target.clayer.yml for-context: - .AC6_low+CM0plus - .AC6_mid+CM0plus - .AC6_high+CM0plus - .AC6_size+CM0plus - .AC6_tiny+CM0plus - .GCC_low+CM0plus - .GCC_mid+CM0plus - .GCC_high+CM0plus - .GCC_size+CM0plus - .GCC_tiny+CM0plus - .IAR_low+CM0plus - .IAR_mid+CM0plus - .IAR_high+CM0plus - .IAR_size+CM0plus - .IAR_tiny+CM0plus #Target: CM3 - layer: ../Layer/Target/CM3/Target.clayer.yml for-context: - .AC6_low+CM3 - .AC6_mid+CM3 - .AC6_high+CM3 - .AC6_size+CM3 - .AC6_tiny+CM3 - .GCC_low+CM3 - .GCC_mid+CM3 - .GCC_high+CM3 - .GCC_size+CM3 - .GCC_tiny+CM3 - .IAR_low+CM3 - .IAR_mid+CM3 - .IAR_high+CM3 - .IAR_size+CM3 - .IAR_tiny+CM3 #Target: CM4 - layer: ../Layer/Target/CM4/Target.clayer.yml for-context: - .AC6_low+CM4 - .AC6_mid+CM4 - .AC6_high+CM4 - .AC6_size+CM4 - .AC6_tiny+CM4 - .GCC_low+CM4 - .GCC_mid+CM4 - .GCC_high+CM4 - .GCC_size+CM4 - .GCC_tiny+CM4 - .IAR_low+CM4 - .IAR_mid+CM4 - .IAR_high+CM4 - .IAR_size+CM4 - .IAR_tiny+CM4 #Target: CM4FP - layer: ../Layer/Target/CM4FP/Target.clayer.yml for-context: - .AC6_low+CM4FP - .AC6_mid+CM4FP - .AC6_high+CM4FP - .AC6_size+CM4FP - .AC6_tiny+CM4FP - .GCC_low+CM4FP - .GCC_mid+CM4FP - .GCC_high+CM4FP - .GCC_size+CM4FP - .GCC_tiny+CM4FP - .IAR_low+CM4FP - .IAR_mid+CM4FP - .IAR_high+CM4FP - .IAR_size+CM4FP - .IAR_tiny+CM4FP #Target: CM7 - layer: ../Layer/Target/CM7/Target.clayer.yml for-context: - .AC6_low+CM7 - .AC6_mid+CM7 - .AC6_high+CM7 - .AC6_size+CM7 - .AC6_tiny+CM7 - .GCC_low+CM7 - .GCC_mid+CM7 - .GCC_high+CM7 - .GCC_size+CM7 - .GCC_tiny+CM7 - .IAR_low+CM7 - .IAR_mid+CM7 - .IAR_high+CM7 - .IAR_size+CM7 - .IAR_tiny+CM7 #Target: CM7SP - layer: ../Layer/Target/CM7SP/Target.clayer.yml for-context: - .AC6_low+CM7SP - .AC6_mid+CM7SP - .AC6_high+CM7SP - .AC6_size+CM7SP - .AC6_tiny+CM7SP - .GCC_low+CM7SP - .GCC_mid+CM7SP - .GCC_high+CM7SP - .GCC_size+CM7SP - .GCC_tiny+CM7SP - .IAR_low+CM7SP - .IAR_mid+CM7SP - .IAR_high+CM7SP - .IAR_size+CM7SP - .IAR_tiny+CM7SP #Target: CM7DP - layer: ../Layer/Target/CM7DP/Target.clayer.yml for-context: - .AC6_low+CM7DP - .AC6_mid+CM7DP - .AC6_high+CM7DP - .AC6_size+CM7DP - .AC6_tiny+CM7DP - .GCC_low+CM7DP - .GCC_mid+CM7DP - .GCC_high+CM7DP - .GCC_size+CM7DP - .GCC_tiny+CM7DP - .IAR_low+CM7DP - .IAR_mid+CM7DP - .IAR_high+CM7DP - .IAR_size+CM7DP - .IAR_tiny+CM7DP #Target: CM23 - layer: ../Layer/Target/CM23/Target.clayer.yml for-context: - .AC6_low+CM23 - .AC6_mid+CM23 - .AC6_high+CM23 - .AC6_size+CM23 - .AC6_tiny+CM23 - .GCC_low+CM23 - .GCC_mid+CM23 - .GCC_high+CM23 - .GCC_size+CM23 - .GCC_tiny+CM23 - .IAR_low+CM23 - .IAR_mid+CM23 - .IAR_high+CM23 - .IAR_size+CM23 - .IAR_tiny+CM23 #Target: CM23S - layer: ../Layer/Target/CM23S/Target.clayer.yml for-context: - .AC6_low+CM23S - .AC6_mid+CM23S - .AC6_high+CM23S - .AC6_size+CM23S - .AC6_tiny+CM23S - .GCC_low+CM23S - .GCC_mid+CM23S - .GCC_high+CM23S - .GCC_size+CM23S - .GCC_tiny+CM23S - .IAR_low+CM23S - .IAR_mid+CM23S - .IAR_high+CM23S - .IAR_size+CM23S - .IAR_tiny+CM23S #Target: CM23NS - layer: ../Layer/Target/CM23NS/Target.clayer.yml for-context: - .AC6_low+CM23NS - .AC6_mid+CM23NS - .AC6_high+CM23NS - .AC6_size+CM23NS - .AC6_tiny+CM23NS - .GCC_low+CM23NS - .GCC_mid+CM23NS - .GCC_high+CM23NS - .GCC_size+CM23NS - .GCC_tiny+CM23NS - .IAR_low+CM23NS - .IAR_mid+CM23NS - .IAR_high+CM23NS - .IAR_size+CM23NS - .IAR_tiny+CM23NS #Target: CM33 - layer: ../Layer/Target/CM33/Target.clayer.yml for-context: - .AC6_low+CM33 - .AC6_mid+CM33 - .AC6_high+CM33 - .AC6_size+CM33 - .AC6_tiny+CM33 - .GCC_low+CM33 - .GCC_mid+CM33 - .GCC_high+CM33 - .GCC_size+CM33 - .GCC_tiny+CM33 - .IAR_low+CM33 - .IAR_mid+CM33 - .IAR_high+CM33 - .IAR_size+CM33 - .IAR_tiny+CM33 #Target: CM33S - layer: ../Layer/Target/CM33S/Target.clayer.yml for-context: - .AC6_low+CM33S - .AC6_mid+CM33S - .AC6_high+CM33S - .AC6_size+CM33S - .AC6_tiny+CM33S - .GCC_low+CM33S - .GCC_mid+CM33S - .GCC_high+CM33S - .GCC_size+CM33S - .GCC_tiny+CM33S - .IAR_low+CM33S - .IAR_mid+CM33S - .IAR_high+CM33S - .IAR_size+CM33S - .IAR_tiny+CM33S #Target: CM33NS - layer: ../Layer/Target/CM33NS/Target.clayer.yml for-context: - .AC6_low+CM33NS - .AC6_mid+CM33NS - .AC6_high+CM33NS - .AC6_size+CM33NS - .AC6_tiny+CM33NS - .GCC_low+CM33NS - .GCC_mid+CM33NS - .GCC_high+CM33NS - .GCC_size+CM33NS - .GCC_tiny+CM33NS - .IAR_low+CM33NS - .IAR_mid+CM33NS - .IAR_high+CM33NS - .IAR_size+CM33NS - .IAR_tiny+CM33NS #Target: CM35P - layer: ../Layer/Target/CM35P/Target.clayer.yml for-context: - .AC6_low+CM35P - .AC6_mid+CM35P - .AC6_high+CM35P - .AC6_size+CM35P - .AC6_tiny+CM35P - .GCC_low+CM35P - .GCC_mid+CM35P - .GCC_high+CM35P - .GCC_size+CM35P - .GCC_tiny+CM35P - .IAR_low+CM35P - .IAR_mid+CM35P - .IAR_high+CM35P - .IAR_size+CM35P - .IAR_tiny+CM35P #Target: CM35PS - layer: ../Layer/Target/CM35PS/Target.clayer.yml for-context: - .AC6_low+CM35PS - .AC6_mid+CM35PS - .AC6_high+CM35PS - .AC6_size+CM35PS - .AC6_tiny+CM35PS - .GCC_low+CM35PS - .GCC_mid+CM35PS - .GCC_high+CM35PS - .GCC_size+CM35PS - .GCC_tiny+CM35PS - .IAR_low+CM35PS - .IAR_mid+CM35PS - .IAR_high+CM35PS - .IAR_size+CM35PS - .IAR_tiny+CM35PS #Target: CM35PNS - layer: ../Layer/Target/CM35PNS/Target.clayer.yml for-context: - .AC6_low+CM35PNS - .AC6_mid+CM35PNS - .AC6_high+CM35PNS - .AC6_size+CM35PNS - .AC6_tiny+CM35PNS - .GCC_low+CM35PNS - .GCC_mid+CM35PNS - .GCC_high+CM35PNS - .GCC_size+CM35PNS - .GCC_tiny+CM35PNS - .IAR_low+CM35PNS - .IAR_mid+CM35PNS - .IAR_high+CM35PNS - .IAR_size+CM35PNS - .IAR_tiny+CM35PNS #Target: CM55S - layer: ../Layer/Target/CM55S/Target.clayer.yml for-context: - .AC6_low+CM55S - .AC6_mid+CM55S - .AC6_high+CM55S - .AC6_size+CM55S - .AC6_tiny+CM55S - .GCC_low+CM55S - .GCC_mid+CM55S - .GCC_high+CM55S - .GCC_size+CM55S - .GCC_tiny+CM55S - .IAR_low+CM55S - .IAR_mid+CM55S - .IAR_high+CM55S - .IAR_size+CM55S - .IAR_tiny+CM55S #Target: CM55NS - layer: ../Layer/Target/CM55NS/Target.clayer.yml for-context: - .AC6_low+CM55NS - .AC6_mid+CM55NS - .AC6_high+CM55NS - .AC6_size+CM55NS - .AC6_tiny+CM55NS - .GCC_low+CM55NS - .GCC_mid+CM55NS - .GCC_high+CM55NS - .GCC_size+CM55NS - .GCC_tiny+CM55NS - .IAR_low+CM55NS - .IAR_mid+CM55NS - .IAR_high+CM55NS - .IAR_size+CM55NS - .IAR_tiny+CM55NS #Target: CM85S - layer: ../Layer/Target/CM85S/Target.clayer.yml for-context: - .AC6_low+CM85S - .AC6_mid+CM85S - .AC6_high+CM85S - .AC6_size+CM85S - .AC6_tiny+CM85S - .GCC_low+CM85S - .GCC_mid+CM85S - .GCC_high+CM85S - .GCC_size+CM85S - .GCC_tiny+CM85S - .IAR_low+CM85S - .IAR_mid+CM85S - .IAR_high+CM85S - .IAR_size+CM85S - .IAR_tiny+CM85S #Target: CM85NS - layer: ../Layer/Target/CM85NS/Target.clayer.yml for-context: - .AC6_low+CM85NS - .AC6_mid+CM85NS - .AC6_high+CM85NS - .AC6_size+CM85NS - .AC6_tiny+CM85NS - .GCC_low+CM85NS - .GCC_mid+CM85NS - .GCC_high+CM85NS - .GCC_size+CM85NS - .GCC_tiny+CM85NS - .IAR_low+CM85NS - .IAR_mid+CM85NS - .IAR_high+CM85NS - .IAR_size+CM85NS - .IAR_tiny+CM85NS #Target: CA5 - layer: ../Layer/Target/CA5/Target.clayer.yml for-context: - .AC6_low+CA5 - .AC6_mid+CA5 - .AC6_high+CA5 - .AC6_size+CA5 - .AC6_tiny+CA5 - .GCC_low+CA5 - .GCC_mid+CA5 - .GCC_high+CA5 - .GCC_size+CA5 - .GCC_tiny+CA5 - .IAR_low+CA5 - .IAR_mid+CA5 - .IAR_high+CA5 - .IAR_size+CA5 - .IAR_tiny+CA5 #Target: CA7 - layer: ../Layer/Target/CA7/Target.clayer.yml for-context: - .AC6_low+CA7 - .AC6_mid+CA7 - .AC6_high+CA7 - .AC6_size+CA7 - .AC6_tiny+CA7 - .GCC_low+CA7 - .GCC_mid+CA7 - .GCC_high+CA7 - .GCC_size+CA7 - .GCC_tiny+CA7 - .IAR_low+CA7 - .IAR_mid+CA7 - .IAR_high+CA7 - .IAR_size+CA7 - .IAR_tiny+CA7 #Target: CA9 - layer: ../Layer/Target/CA9/Target.clayer.yml for-context: - .AC6_low+CA9 - .AC6_mid+CA9 - .AC6_high+CA9 - .AC6_size+CA9 - .AC6_tiny+CA9 - .GCC_low+CA9 - .GCC_mid+CA9 - .GCC_high+CA9 - .GCC_size+CA9 - .GCC_tiny+CA9 - .IAR_low+CA9 - .IAR_mid+CA9 - .IAR_high+CA9 - .IAR_size+CA9 - .IAR_tiny+CA9 ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.csolution.yml ================================================ # yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/csolution.schema.json solution: packs: - pack: ARM::CMSIS path: ../../../ misc: - for-compiler: AC6 C: [-std=c99, -gdwarf-4, -ffunction-sections] Link: [--entry=Reset_Handler, --symbols, --map] - for-compiler: GCC C: [-std=gnu99, -gdwarf-2, -ffunction-sections, -fdata-sections] Link: [--specs=nano.specs, --specs=rdimon.specs] - for-compiler: IAR Link: [--semihosting] target-types: #CM0 - type: CM0 device: ARMCM0 #CM0plus - type: CM0plus device: ARMCM0P #CM3 - type: CM3 device: ARMCM3 #CM4 - type: CM4 device: ARMCM4 #CM4FP - type: CM4FP device: ARMCM4_FP #CM7 - type: CM7 device: ARMCM7 #CM7SP - type: CM7SP device: ARMCM7_SP #CM7DP - type: CM7DP device: ARMCM7_DP #CM23 - type: CM23 device: ARMCM23 processor: trustzone: off #CM23S - type: CM23S device: ARMCM23_TZ processor: trustzone: secure #CM23NS - type: CM23NS device: ARMCM23_TZ processor: trustzone: non-secure #CM33 - type: CM33 device: ARMCM33_DSP_FP processor: trustzone: off #CM33S - type: CM33S device: ARMCM33_DSP_FP_TZ processor: trustzone: secure #CM33NS - type: CM33NS device: ARMCM33_DSP_FP_TZ processor: trustzone: non-secure #CM35P - type: CM35P device: ARMCM35P_DSP_FP processor: trustzone: off #CM35PS - type: CM35PS device: ARMCM35P_DSP_FP_TZ processor: trustzone: secure #CM35PNS - type: CM35PNS device: ARMCM35P_DSP_FP_TZ processor: trustzone: non-secure #CM55S - type: CM55S device: ARMCM55 processor: trustzone: secure #CM55NS - type: CM55NS device: ARMCM55 processor: trustzone: non-secure #CM85S - type: CM85S device: ARMCM85 processor: trustzone: secure #CM85NS - type: CM85NS device: ARMCM85 processor: trustzone: non-secure #CA5 - type: CA5 device: ARMCA5 #CA7 - type: CA7 device: ARMCA7 #CA9 - type: CA9 device: ARMCA9 build-types: #AC6_low, AC6_mid, AC6_high, AC6_size, AC6_OZ, - type: AC6_low compiler: AC6 misc: - for-compiler: AC6 C: [-O1] - type: AC6_mid compiler: AC6 misc: - for-compiler: AC6 C: [-O2] - type: AC6_high compiler: AC6 misc: - for-compiler: AC6 C: [-O3] - type: AC6_size compiler: AC6 misc: - for-compiler: AC6 C: [-Os] - type: AC6_tiny compiler: AC6 misc: - for-compiler: AC6 C: [-Oz] #GCC_low, GCC_mid, GCC_high, GCC_size, GCC_OZ, - type: GCC_low compiler: GCC misc: - for-compiler: GCC C: [-O1] - type: GCC_mid compiler: GCC misc: - for-compiler: GCC C: [-O2] - type: GCC_high compiler: GCC misc: - for-compiler: GCC C: [-O3] - type: GCC_size compiler: GCC misc: - for-compiler: GCC C: [-Os] - type: GCC_tiny compiler: GCC misc: - for-compiler: GCC C: [-Ofast] #IAR_low - type: IAR_low compiler: IAR misc: - for-compiler: IAR C: [-Ol, --dlib_config DLib_Config_Full.h] - type: IAR_mid compiler: IAR misc: - for-compiler: IAR C: [-Om, --dlib_config DLib_Config_Full.h] - type: IAR_high compiler: IAR misc: - for-compiler: IAR C: [-Oh, --dlib_config DLib_Config_Full.h] - type: IAR_size compiler: IAR misc: - for-compiler: IAR C: [-Ohz, --dlib_config DLib_Config_Full.h] - type: IAR_tiny compiler: IAR misc: - for-compiler: IAR C: [-Ohs, --dlib_config DLib_Config_Full.h] projects: - project: ./Validation.cproject.yml - project: ./Bootloader.cproject.yml for-context: - +CM23S - +CM33S - +CM35PS - +CM55S - +CM85S output-dirs: cprjdir: ./$Project$.$BuildType$+$TargetType$ intdir: ./$Project$.$BuildType$+$TargetType$/intdir outdir: ./$Project$.$BuildType$+$TargetType$/outdir ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/avh.yml ================================================ name: "RTOS2 Validation" workdir: ../../../ backend: aws: ami-version: ~=1.3 instance-type: t2.micro upload: - ARM.CMSIS.pdsc - CMSIS/Core/**/* - CMSIS/Core_A/**/* - CMSIS/CoreValidation/**/* - -:CMSIS/CoreValidation/Project/Core_Validation-*.zip - -:CMSIS/CoreValidation/Project/Core_Validation-*.junit - -:CMSIS/CoreValidation/Project/Validation.*/**/* - -:CMSIS/CoreValidation/Project/Bootloader.*/**/* - Device/ARM/**/* steps: - run: | wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh chmod +x cmsis-toolbox.sh sudo ./cmsis-toolbox.sh </dev/null)) $(dirname $(which armcc 2>/dev/null)) $(dirname $(which arm-none-eabi-gcc 2>/dev/null)) EOI echo "cpackget : $(which cpackget)" echo "csolution: $(which csolution)" echo "cbuild : $(which cbuild)" - run: | pip install -r requirements.txt 2>&1 - run: | cd CMSIS/CoreValidation/Project python build.py --verbose -c AC6 -c GCC -d "CM[047]*" -d "CM[23]3*" build run 2>&1 || echo "Something failed!" download: - CMSIS/CoreValidation/Project/Core_Validation-*.zip - CMSIS/CoreValidation/Project/Core_Validation-*.junit ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/build.py ================================================ #!/usr/bin/python # -*- coding: utf-8 -*- import logging from datetime import datetime from enum import Enum from glob import glob, iglob from pathlib import Path from lxml.etree import XMLSyntaxError from zipfile import ZipFile from matrix_runner import main, matrix_axis, matrix_action, matrix_command, matrix_filter, \ ConsoleReport, CropReport, TransformReport, JUnitReport @matrix_axis("device", "d", "Device(s) to be considered.") class DeviceAxis(Enum): CM0 = ('Cortex-M0', 'CM0') CM0plus = ('Cortex-M0plus', 'CM0plus') CM3 = ('Cortex-M3', 'CM3') CM4 = ('Cortex-M4', 'CM4') CM4FP = ('Cortex-M4FP', 'CM4FP') CM7 = ('Cortex-M7', 'CM7') CM7SP = ('Cortex-M7SP', 'CM7SP') CM7DP = ('Cortex-M7DP', 'CM7DP') CM23 = ('Cortex-M23', 'CM23') CM23S = ('Cortex-M23S', 'CM23S') CM23NS = ('Cortex-M23NS', 'CM23NS') CM33 = ('Cortex-M33', 'CM33') CM33S = ('Cortex-M33S', 'CM33S') CM33NS = ('Cortex-M33NS', 'CM33NS') CM35P = ('Cortex-M35P', 'CM35P') CM35PS = ('Cortex-M35PS', 'CM35PS') CM35PNS = ('Cortex-M35PNS', 'CM35PNS') CM55S = ('Cortex-M55S', 'CM55S') CM55NS = ('Cortex-M55NS', 'CM55NS') CM85S = ('Cortex-M85S', 'CM85S') CM85NS = ('Cortex-M85NS', 'CM85NS') CA5 = ('Cortex-A5', 'CA5') CA7 = ('Cortex-A7', 'CA7') CA9 = ('Cortex-A9', 'CA9') # CA5NEON = ('Cortex-A5neon', 'CA5neon') # CA7NEON = ('Cortex-A7neon', 'CA7neon') # CA9NEON = ('Cortex-A9neon', 'CA9neon') def has_bl(self): return self in [ DeviceAxis.CM23NS, DeviceAxis.CM33NS, DeviceAxis.CM35PNS, DeviceAxis.CM55NS, DeviceAxis.CM85NS ] @property def bl_device(self): bld = { DeviceAxis.CM23NS: 'CM23S', DeviceAxis.CM33NS: 'CM33S', DeviceAxis.CM35PNS: 'CM35PS', DeviceAxis.CM55NS: 'CM55S', DeviceAxis.CM85NS: 'CM85S' } return bld[self] @matrix_axis("compiler", "c", "Compiler(s) to be considered.") class CompilerAxis(Enum): AC6 = ('AC6') AC6LTM = ('AC6LTM') GCC = ('GCC') IAR = ('IAR') @property def image_ext(self): ext = { CompilerAxis.AC6: 'axf', CompilerAxis.AC6LTM: 'axf', CompilerAxis.GCC: 'elf', CompilerAxis.IAR: 'elf' } return ext[self] @matrix_axis("optimize", "o", "Optimization level(s) to be considered.") class OptimizationAxis(Enum): LOW = ('low', 'O1') MID = ('mid', 'O2') HIGH = ('high', 'Ofast') SIZE = ('size', 'Os') TINY = ('tiny', 'Oz') MODEL_EXECUTABLE = { DeviceAxis.CM0: ("VHT_MPS2_Cortex-M0", []), DeviceAxis.CM0plus: ("VHT_MPS2_Cortex-M0plus", []), DeviceAxis.CM3: ("VHT_MPS2_Cortex-M3", []), DeviceAxis.CM4: ("VHT_MPS2_Cortex-M4", []), DeviceAxis.CM4FP: ("VHT_MPS2_Cortex-M4", []), DeviceAxis.CM7: ("VHT_MPS2_Cortex-M7", []), DeviceAxis.CM7DP: ("VHT_MPS2_Cortex-M7", []), DeviceAxis.CM7SP: ("VHT_MPS2_Cortex-M7", []), DeviceAxis.CM23: ("VHT_MPS2_Cortex-M23", []), DeviceAxis.CM23S: ("VHT_MPS2_Cortex-M23", []), DeviceAxis.CM23NS: ("VHT_MPS2_Cortex-M23", []), DeviceAxis.CM33: ("VHT_MPS2_Cortex-M33", []), DeviceAxis.CM33S: ("VHT_MPS2_Cortex-M33", []), DeviceAxis.CM33NS: ("VHT_MPS2_Cortex-M33", []), DeviceAxis.CM35P: ("VHT_MPS2_Cortex-M35P", []), DeviceAxis.CM35PS: ("VHT_MPS2_Cortex-M35P", []), DeviceAxis.CM35PNS: ("VHT_MPS2_Cortex-M35P", []), DeviceAxis.CM55S: ("VHT_MPS2_Cortex-M55", []), DeviceAxis.CM55NS: ("VHT_MPS2_Cortex-M55", []), DeviceAxis.CM85S: ("VHT_MPS2_Cortex-M85", []), DeviceAxis.CM85NS: ("VHT_MPS2_Cortex-M85", []), DeviceAxis.CA5: ("FVP_VE_Cortex-A5x1", []), DeviceAxis.CA7: ("FVP_VE_Cortex-A7x1", []), DeviceAxis.CA9: ("FVP_VE_Cortex-A9x1", []), # DeviceAxis.CA5NEON: ("FVP_VE_Cortex-A5x1", []), # DeviceAxis.CA7NEON: ("FVP_VE_Cortex-A7x1", []), # DeviceAxis.CA9NEON: ("FVP_VE_Cortex-A9x1", []) } def config_suffix(config, timestamp=True): suffix = f"{config.compiler[0]}-{config.optimize[0]}-{config.device[1]}" if timestamp: suffix += f"-{datetime.now().strftime('%Y%m%d%H%M%S')}" return suffix def image_name(config): return f"Validation" def project_name(config): return f"Validation.{config.compiler}_{config.optimize}+{config.device[1]}" def bl_image_name(config): return f"Bootloader" def bl_project_name(config): return f"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}" def output_dir(config): return "outdir" def bl_output_dir(config): return "outdir" def model_config(config): return f"../Layer/Target/{config.device[1]}/model_config.txt" @matrix_action def clean(config): """Build the selected configurations using CMSIS-Build.""" yield cbuild_clean(f"{project_name(config)}/{project_name(config)}.cprj") @matrix_action def build(config, results): """Build the selected configurations using CMSIS-Build.""" if config.device.has_bl(): logging.info("Compiling Bootloader...") yield csolution(f"{bl_project_name(config)}") yield cbuild(f"{bl_project_name(config)}/{bl_project_name(config)}.cprj") logging.info("Compiling Tests...") if config.compiler == CompilerAxis.GCC and config.device.match("CA*"): ldfile = Path(f"{project_name(config)}/RTE/Device/ARM{config.device[1]}/ARM{config.device[1]}.ld") infile = ldfile.replace(ldfile.with_suffix('.ld.in')) yield preprocess(infile, ldfile) yield csolution(f"{project_name(config)}") yield cbuild(f"{project_name(config)}/{project_name(config)}.cprj") if not all(r.success for r in results): return file = f"Core_Validation-{config_suffix(config)}.zip" logging.info(f"Archiving build output to {file}...") with ZipFile(file, "w") as archive: for content in iglob(f"{project_name(config)}/**/*", recursive=True): if Path(content).is_file(): archive.write(content) @matrix_action def extract(config): """Extract the latest build archive.""" archives = sorted(glob(f"RTOS2_Validation-{config_suffix(config, timestamp=False)}-*.zip"), reverse=True) yield unzip(archives[0]) @matrix_action def run(config, results): """Run the selected configurations.""" logging.info("Running Core Validation on Arm model ...") yield model_exec(config) try: results[0].test_report.write(f"Core_Validation-{config_suffix(config)}.junit") except RuntimeError as e: if isinstance(e.__cause__, XMLSyntaxError): logging.error("No valid test report found in model output!") else: logging.exception(e) @matrix_command() def cbuild_clean(project): return ["cbuild", "-c", project] @matrix_command() def unzip(archive): return ["bash", "-c", f"unzip {archive}"] @matrix_command() def preprocess(infile, outfile): return ["arm-none-eabi-gcc", "-xc", "-E", infile, "-P", "-o", outfile] @matrix_command() def csolution(project): return ["csolution", "convert", "-s", "Validation.csolution.yml", "-c", project] @matrix_command() def cbuild(project): return ["cbuild", project] @matrix_command(test_report=ConsoleReport() | CropReport('<\?xml version="1.0"\?>', '') | TransformReport('validation.xsl') | JUnitReport(title=lambda title, result: f"{result.command.config.compiler}." f"{result.command.config.optimize}." f"{result.command.config.device}." f"{title}")) def model_exec(config): cmdline = [MODEL_EXECUTABLE[config.device][0], "-q", "--simlimit", 100, "-f", model_config(config)] cmdline += MODEL_EXECUTABLE[config.device][1] cmdline += ["-a", f"{project_name(config)}/{output_dir(config)}/{image_name(config)}.{config.compiler.image_ext}"] if config.device.has_bl(): cmdline += ["-a", f"{bl_project_name(config)}/{bl_output_dir(config)}/{bl_image_name(config)}.{config.compiler.image_ext}"] return cmdline if __name__ == "__main__": main() ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/cpacklist.txt ================================================ ARM.CMSIS.5.9.0 ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/requirements.txt ================================================ # -*- coding: utf-8 -*- # # Python requirements for build.py script # python-matrix-runner~=1.0 lxml~=4.8 ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Project/validation.xsl ================================================ : ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/README.md ================================================ # CMSIS-Core Validation This folder contains a test suite that validates CMSIS-Core implementations. It uses [**Fixed Virtual Platforms**](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms) to run tests to verify correct operation of the CMSIS-Core functionality on various Arm Cortex based processors. ## Folder structure ```txt 📂 CoreValidation ┣ 📂 Include Include files for test cases etc. ┣ 📂 Layer Layers for creating the projects. ┣ 📂 Project Solution and project files to build tests for various configurations. ┗ 📂 Source Test case source code. ``` ## Test matrix Currently, the following build configurations are provided: 1. Compiler - Arm Compiler 6 (AC6) - GNU Compiler (GCC) - IAR Compiler (IAR) 2. Devices - Cortex-M0 - Cortex-M0+ - Cortex-M3 - Cortex-M4 - w/o FPU - with FPU - Cortex-M7 - w/o FPU - with SP FPU - with DP FPU - Cortex-M23 - w/o security extensions (TrustZone) - in secure mode - in non-secure mode - Cortex-M33 (with FPU and DSP extensions) - w/o security extensions (TrustZone) - in secure mode - in non-secure mode - Cortex-M35P (with FPU and DSP extensions) - w/o security extensions (TrustZone) - in secure mode - in non-secure mode - Cortex-M55 (with FPU and DSP extensions) - in secure mode - in non-secure mode - Cortex-M85 (with FPU and DSP extensions) - in secure mode - in non-secure mode - Cortex-A5 - w/o NEON extensions - Cortex-A7 - w/o NEON extensions - Cortex-A9 - w/o NEON extensions 3. Optimization Levels - Low - AC6: `-O1` - GCC: `-O1` - IAR: `-Ol` - Mid - AC6: `-O2` - GCC: `-O2` - IAR: `-Om` - High - AC6: `-O3` - GCC: `-O3` - IAR: `-Oh` - Size - AC6: `-Os` - GCC: `-Os` - IAR: `-Ohz` - Tiny - AC6: `-Oz` - GCC: `-Ofast` - IAR: `-Ohs` ## Prerequisites The following tools are required to build and run the CoreValidation tests: - [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) 1.3.0 or higher - CMake - Ninja build - Arm Compiler 6 - GNU Compiler - IAR Compiler - Python 3.8 or higher - Arm Virtual Hardware Models The executables need to be present on the `PATH`. Install the Python packages required by `build.py`: ```bash CMSIS_5/CMSIS/CoreValidation/Project $ pip install -r requirements.txt ``` ## Build and run To build and run the CoreValidation tests for one or more configurations use the following command line. Select the ``, ``, and `optimize` level to `build` and `run` for. ```bash CMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c -d -o [build] [run] ``` For example, build and run the tests using GCC for Cortex-M3 with low optimization, execute: ```bash CMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c GCC -d CM3 -o low build run [GCC][Cortex-M3][low](build:csolution) csolution convert -s Validation.csolution.yml -c Validation.GCC_low+CM3 [GCC][Cortex-M3][low](build:csolution) csolution succeeded with exit code 0 [GCC][Cortex-M3][low](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj [GCC][Cortex-M3][low](build:cbuild) cbuild succeeded with exit code 0 [GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf [GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0 Matrix Summary ============== compiler device optimize build clean extract run ---------- --------- ---------- ------- ------- --------- ----- GCC Cortex-M3 low success (skip) (skip) 35/35 ``` The full test report is written to `Core_Validation-GCC-low-CM3-.junit` file. ## License [![License](https://img.shields.io/badge/License-Apache_2.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CAL1Cache.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CAL1Cache.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_EnDisable(void) { uint32_t orig = __get_SCTLR(); L1C_EnableCaches(); uint32_t sctlr = __get_SCTLR(); ASSERT_TRUE((sctlr & SCTLR_I_Msk) == SCTLR_I_Msk); ASSERT_TRUE((sctlr & SCTLR_C_Msk) == SCTLR_C_Msk); L1C_CleanDCacheAll(); L1C_DisableCaches(); sctlr = __get_SCTLR(); ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U); ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U); __set_SCTLR(orig); __ISB(); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_EnDisableBTAC(void) { uint32_t orig = __get_SCTLR(); L1C_EnableBTAC(); uint32_t sctlr = __get_SCTLR(); ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk); L1C_DisableBTAC(); sctlr = __get_SCTLR(); #if __CORTEX_A == 7 // On Cortex-A7 SCTLR_Z is RAO/WI. ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk); #else ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U); #endif __set_SCTLR(orig); __ISB(); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_log2_up(void) { uint8_t log2 = __log2_up(0U); ASSERT_TRUE(log2 == 0U); log2 = __log2_up(1U); ASSERT_TRUE(log2 == 0U); log2 = __log2_up(2U); ASSERT_TRUE(log2 == 1U); log2 = __log2_up(3U); ASSERT_TRUE(log2 == 2U); log2 = __log2_up(4U); ASSERT_TRUE(log2 == 2U); log2 = __log2_up(0x80000000U); ASSERT_TRUE(log2 == 31U); log2 = __log2_up(0x80000001U); ASSERT_TRUE(log2 == 32U); log2 = __log2_up(0xFFFFFFFFU); ASSERT_TRUE(log2 == 32U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_InvalidateDCacheAll(void) { /* setup */ uint32_t orig = __get_SCTLR(); volatile uint32_t value = 0x0815U; L1C_EnableCaches(); L1C_CleanDCacheAll(); /* test cached value gets lost */ // WHEN a value is written value = 0x4711U; // ... and the cache is invalidated L1C_InvalidateDCacheAll(); // ... and the cache is disabled L1C_DisableCaches(); // THEN the new value has been lost ASSERT_TRUE(value == 0x0815U); /* tear down */ L1C_InvalidateDCacheAll(); __set_SCTLR(orig); __ISB(); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_CleanDCacheAll(void) { /* setup */ uint32_t orig = __get_SCTLR(); uint32_t value = 0x0815U; L1C_EnableCaches(); L1C_CleanDCacheAll(); /* test cached value is preserved */ // WHEN a value is written value = 0x4711U; // ... and the cache is cleaned L1C_CleanDCacheAll(); // ... and the cache is disabled L1C_DisableCaches(); // THEN the new value is preserved ASSERT_TRUE(value == 0x4711U); /* tear down */ L1C_InvalidateDCacheAll(); __set_SCTLR(orig); __ISB(); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CAL1Cache_CleanInvalidateDCacheAll(void) { /* setup */ uint32_t orig = __get_SCTLR(); uint32_t value = 0x0815U; L1C_EnableCaches(); L1C_CleanDCacheAll(); /* test cached value is preserved */ // WHEN a value is written value = 0x4711U; // ... and the cache is cleaned/invalidated L1C_CleanInvalidateDCacheAll(); // ... and the cache is disabled L1C_DisableCaches(); // THEN the new value is preserved ASSERT_TRUE(value == 0x4711U); /* tear down */ L1C_InvalidateDCacheAll(); __set_SCTLR(orig); __ISB(); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CML1Cache.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CML1Cache.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2020 - 2021 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CML1Cache_EnDisableICache(void) { #ifdef __ICACHE_PRESENT SCB_EnableICache(); ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk); SCB_DisableICache(); ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CML1Cache_EnDisableDCache(void) { #ifdef __DCACHE_PRESENT SCB_EnableDCache(); ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk); SCB_DisableDCache(); ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #ifdef __DCACHE_PRESENT static uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U }; #endif void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) { #ifdef __DCACHE_PRESENT SCB_DisableDCache(); SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0])); ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U); #endif } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreAFunc.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CoreFunc.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_IRQ(void) { uint32_t orig = __get_CPSR(); __enable_irq(); uint32_t cpsr = __get_CPSR(); ASSERT_TRUE((cpsr & CPSR_I_Msk) == 0U); __disable_irq(); cpsr = __get_CPSR(); ASSERT_TRUE((cpsr & CPSR_I_Msk) == CPSR_I_Msk); __set_CPSR(orig); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_FaultIRQ(void) { uint32_t orig = __get_CPSR(); __enable_fault_irq(); uint32_t cpsr = __get_CPSR(); ASSERT_TRUE((cpsr & CPSR_F_Msk) == 0U); __disable_fault_irq(); cpsr = __get_CPSR(); ASSERT_TRUE((cpsr & CPSR_F_Msk) == CPSR_F_Msk); __set_CPSR(orig); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_FPSCR(void) { volatile float f1 = 47.11f; volatile float f2 = 8.15f; volatile float f3 = f1 / f2; uint32_t fpscr = __get_FPSCR(); __set_FPSCR(fpscr); ASSERT_TRUE(fpscr == __get_FPSCR()); ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f)); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if defined(__CC_ARM) #define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn) #define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn) #elif defined( __GNUC__ ) && defined(__thumb__) #define __SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) #define __ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) #else #define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) #define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn)) #endif void TC_CoreAFunc_CPSR(void) { uint32_t result; uint32_t cpsr = __get_CPSR(); __set_CPSR(cpsr & CPSR_M_Msk); // Check negative flag int32_t Rm = 5; int32_t Rn = 7; __SUBS(Rm, Rm, Rn); result = __get_CPSR(); ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk); // Check zero and compare flag Rm = 5; __SUBS(Rm, Rm, Rm); result = __get_CPSR(); ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk); ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk); // Check overflow flag Rm = 5; Rn = INT32_MAX; __ADDS(Rm, Rm, Rn); result = __get_CPSR(); ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_Mode(void) { uint32_t mode = __get_mode(); __set_mode(mode); ASSERT_TRUE(mode == __get_mode()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ static uint32_t TC_CoreAFunc_SP_orig; static uint32_t TC_CoreAFunc_SP_sp; static uint32_t TC_CoreAFunc_SP_result; void TC_CoreAFunc_SP(void) { TC_CoreAFunc_SP_orig = __get_SP(); TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U; __set_SP(TC_CoreAFunc_SP_sp); TC_CoreAFunc_SP_result = __get_SP(); __set_SP(TC_CoreAFunc_SP_orig); ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ static uint32_t TC_CoreAFunc_SP_usr_orig; static uint32_t TC_CoreAFunc_SP_usr_sp; static uint32_t TC_CoreAFunc_SP_usr_result; void TC_CoreAFunc_SP_usr(void) { TC_CoreAFunc_SP_usr_orig = __get_SP_usr(); TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U; __set_SP(TC_CoreAFunc_SP_usr_sp); TC_CoreAFunc_SP_usr_result = __get_SP_usr(); __set_SP(TC_CoreAFunc_SP_usr_orig); ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_FPEXC(void) { uint32_t fpexc = __get_FPEXC(); __set_FPEXC(fpexc); ASSERT_TRUE(fpexc == __get_FPEXC()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_ACTLR(void) { uint32_t actlr = __get_ACTLR(); __set_ACTLR(actlr); ASSERT_TRUE(actlr == __get_ACTLR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_CPACR(void) { uint32_t cpacr = __get_CPACR(); __set_CPACR(cpacr); ASSERT_TRUE(cpacr == __get_CPACR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_DFSR(void) { uint32_t dfsr = __get_DFSR(); __set_DFSR(dfsr); ASSERT_TRUE(dfsr == __get_DFSR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_IFSR(void) { uint32_t ifsr = __get_IFSR(); __set_IFSR(ifsr); ASSERT_TRUE(ifsr == __get_IFSR()); } /*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_ISR(void) { uint32_t isr = __get_ISR(); ASSERT_TRUE(isr == __get_ISR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_CBAR(void) { uint32_t cbar = __get_CBAR(); ASSERT_TRUE(cbar == __get_CBAR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_TTBR0(void) { uint32_t ttbr0 = __get_TTBR0(); __set_TTBR0(ttbr0); ASSERT_TRUE(ttbr0 == __get_TTBR0()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_DACR(void) { uint32_t dacr = __get_DACR(); __set_DACR(dacr); ASSERT_TRUE(dacr == __get_DACR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_SCTLR(void) { uint32_t sctlr = __get_SCTLR(); __set_SCTLR(sctlr); ASSERT_TRUE(sctlr == __get_SCTLR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_ACTRL(void) { uint32_t actrl = __get_ACTRL(); __set_ACTRL(actrl); ASSERT_TRUE(actrl == __get_ACTRL()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_MPIDR(void) { uint32_t mpidr = __get_MPIDR(); ASSERT_TRUE(mpidr == __get_MPIDR()); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ static uint8_t vectorRAM[32U] __attribute__((aligned(32U))); void TC_CoreAFunc_VBAR(void) { uint32_t vbar = __get_VBAR(); memcpy(vectorRAM, (void*)vbar, sizeof(vectorRAM)); __set_VBAR((uint32_t)vectorRAM); ASSERT_TRUE(((uint32_t)vectorRAM) == __get_VBAR()); __set_VBAR(vbar); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_MVBAR(void) { uint32_t mvbar = __get_MVBAR(); memcpy(vectorRAM, (void*)mvbar, sizeof(vectorRAM)); __set_MVBAR((uint32_t)vectorRAM); ASSERT_TRUE(((uint32_t)vectorRAM) == __get_MVBAR()); __set_MVBAR(mvbar); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_CoreAFunc_FPU_Enable(void) { uint32_t fpexc = __get_FPEXC(); __set_FPEXC(fpexc & ~0x40000000u); // disable FPU uint32_t cp15; __get_CP(15, 0, cp15, 1, 0, 2); cp15 &= ~0x00F00000u; __set_CP(15, 0, cp15, 1, 0, 2); // disable FPU access __FPU_Enable(); __get_CP(15, 0, cp15, 1, 0, 2); ASSERT_TRUE((cp15 & 0x00F00000u) == 0x00F00000u); fpexc = __get_FPEXC(); ASSERT_TRUE((fpexc & 0x40000000u) == 0x40000000u); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreFunc.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CoreFunc.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 - 2023 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ static volatile uint32_t irqTaken = 0U; #if defined(__CORTEX_M) && (__CORTEX_M > 0) static volatile uint32_t irqActive = 0U; #endif static void TC_CoreFunc_EnDisIRQIRQHandler(void) { ++irqTaken; #if defined(__CORTEX_M) && (__CORTEX_M > 0) irqActive = NVIC_GetActive(Interrupt0_IRQn); #endif } static volatile uint32_t irqIPSR = 0U; static volatile uint32_t irqXPSR = 0U; static void TC_CoreFunc_IPSR_IRQHandler(void) { irqIPSR = __get_IPSR(); irqXPSR = __get_xPSR(); } /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_EnDisIRQ \details Check expected behavior of interrupt related control functions: - __disable_irq() and __enable_irq() - NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ - NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ - NVIC_GetActive (not on Cortex-M0/M0+) */ void TC_CoreFunc_EnDisIRQ (void) { // Globally disable all interrupt servicing __disable_irq(); // Enable the interrupt NVIC_EnableIRQ(Interrupt0_IRQn); ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U); // Clear its pending state NVIC_ClearPendingIRQ(Interrupt0_IRQn); ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); // Register test interrupt handler. TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler; irqTaken = 0U; #if defined(__CORTEX_M) && (__CORTEX_M > 0) irqActive = UINT32_MAX; #endif // Set the interrupt pending state NVIC_SetPendingIRQ(Interrupt0_IRQn); for(uint32_t i = 10U; i > 0U; --i) {__NOP();} // Interrupt is not taken ASSERT_TRUE(irqTaken == 0U); ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U); #if defined(__CORTEX_M) && (__CORTEX_M > 0) ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U); #endif // Globally enable interrupt servicing __enable_irq(); for(uint32_t i = 10U; i > 0U; --i) {__NOP();} // Interrupt was taken ASSERT_TRUE(irqTaken == 1U); #if defined(__CORTEX_M) && (__CORTEX_M > 0) ASSERT_TRUE(irqActive != 0U); ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U); #endif // Interrupt it not pending anymore. ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); // Disable interrupt NVIC_DisableIRQ(Interrupt0_IRQn); ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U); // Set interrupt pending NVIC_SetPendingIRQ(Interrupt0_IRQn); for(uint32_t i = 10U; i > 0U; --i) {__NOP();} // Interrupt is not taken again ASSERT_TRUE(irqTaken == 1U); ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U); // Clear interrupt pending NVIC_ClearPendingIRQ(Interrupt0_IRQn); for(uint32_t i = 10U; i > 0U; --i) {__NOP();} // Interrupt it not pending anymore. ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U); // Globally disable interrupt servicing __disable_irq(); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_IRQPrio \details Check expected behavior of interrupt priority control functions: - NVIC_SetPriority, NVIC_GetPriority */ void TC_CoreFunc_IRQPrio (void) { /* Test Exception Priority */ uint32_t orig = NVIC_GetPriority(SVCall_IRQn); NVIC_SetPriority(SVCall_IRQn, orig+1U); uint32_t prio = NVIC_GetPriority(SVCall_IRQn); ASSERT_TRUE(prio == orig+1U); NVIC_SetPriority(SVCall_IRQn, orig); /* Test Interrupt Priority */ orig = NVIC_GetPriority(Interrupt0_IRQn); NVIC_SetPriority(Interrupt0_IRQn, orig+1U); prio = NVIC_GetPriority(Interrupt0_IRQn); ASSERT_TRUE(prio == orig+1U); NVIC_SetPriority(Interrupt0_IRQn, orig); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** Helper function for TC_CoreFunc_EncDecIRQPrio \details The helper encodes and decodes the given priority configuration. \param[in] prigroup The PRIGROUP setting to be considered for encoding/decoding. \param[in] pre The preempt priority value. \param[in] sub The subpriority value. */ static void TC_CoreFunc_EncDecIRQPrio_Step(uint32_t prigroup, uint32_t pre, uint32_t sub) { uint32_t prio = NVIC_EncodePriority(prigroup, pre, sub); uint32_t ret_pre = UINT32_MAX; uint32_t ret_sub = UINT32_MAX; NVIC_DecodePriority(prio, prigroup, &ret_pre, &ret_sub); ASSERT_TRUE(ret_pre == pre); ASSERT_TRUE(ret_sub == sub); } /** \brief Test case: TC_CoreFunc_EncDecIRQPrio \details Check expected behavior of interrupt priority encoding/decoding functions: - NVIC_EncodePriority, NVIC_DecodePriority */ void TC_CoreFunc_EncDecIRQPrio (void) { /* Check only the valid range of PRIGROUP and preempt-/sub-priority values. */ static const uint32_t priobits = (__NVIC_PRIO_BITS > 7U) ? 7U : __NVIC_PRIO_BITS; for(uint32_t prigroup = 7U-priobits; prigroup<7U; prigroup++) { for(uint32_t pre = 0U; pre<(128U>>prigroup); pre++) { for(uint32_t sub = 0U; sub<(256U>>(8U-__NVIC_PRIO_BITS+7U-prigroup)); sub++) { TC_CoreFunc_EncDecIRQPrio_Step(prigroup, pre, sub); } } } } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_IRQVect \details Check expected behavior of interrupt vector relocation functions: - NVIC_SetVector, NVIC_GetVector */ void TC_CoreFunc_IRQVect(void) { #if defined(__VTOR_PRESENT) && __VTOR_PRESENT /* relocate vector table */ extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; static VECTOR_TABLE_Type vectors[sizeof(__VECTOR_TABLE)/sizeof(__VECTOR_TABLE[0])] __ALIGNED(1024) __NO_INIT; memcpy(vectors, __VECTOR_TABLE, sizeof(__VECTOR_TABLE)); const uint32_t orig_vtor = SCB->VTOR; const uint32_t vtor = ((uint32_t)vectors) & SCB_VTOR_TBLOFF_Msk; SCB->VTOR = vtor; ASSERT_TRUE(vtor == SCB->VTOR); /* check exception vectors */ extern void HardFault_Handler(void); extern void SVC_Handler(void); extern void PendSV_Handler(void); extern void SysTick_Handler(void); ASSERT_TRUE(NVIC_GetVector(HardFault_IRQn) == (uint32_t)HardFault_Handler); ASSERT_TRUE(NVIC_GetVector(SVCall_IRQn) == (uint32_t)SVC_Handler); ASSERT_TRUE(NVIC_GetVector(PendSV_IRQn) == (uint32_t)PendSV_Handler); ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler); /* reconfigure WDT IRQ vector */ extern void Interrupt0_Handler(void); const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn); ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler); NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U); ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U)); /* restore vector table */ SCB->VTOR = orig_vtor; #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_GetCtrl \details - Check if __set_CONTROL and __get_CONTROL() sets/gets control register */ void TC_CoreFunc_Control (void) { // don't use stack for this variables static uint32_t orig; static uint32_t ctrl; static uint32_t result; orig = __get_CONTROL(); ctrl = orig; result = UINT32_MAX; #ifdef CONTROL_SPSEL_Msk // SPSEL set to 0 (MSP) ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U); // SPSEL set to 1 (PSP) ctrl |= CONTROL_SPSEL_Msk; // Move MSP to PSP __set_PSP(__get_MSP()); #endif __set_CONTROL(ctrl); __ISB(); result = __get_CONTROL(); __set_CONTROL(orig); __ISB(); ASSERT_TRUE(result == ctrl); ASSERT_TRUE(__get_CONTROL() == orig); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_IPSR \details - Check if __get_IPSR intrinsic is available - Check if __get_xPSR intrinsic is available - Result differentiates between thread and exception modes */ void TC_CoreFunc_IPSR (void) { uint32_t result = __get_IPSR(); ASSERT_TRUE(result == 0U); // Thread Mode result = __get_xPSR(); ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler; irqIPSR = 0U; irqXPSR = 0U; NVIC_ClearPendingIRQ(Interrupt0_IRQn); NVIC_EnableIRQ(Interrupt0_IRQn); __enable_irq(); NVIC_SetPendingIRQ(Interrupt0_IRQn); for(uint32_t i = 10U; i > 0U; --i) {__NOP();} __disable_irq(); NVIC_DisableIRQ(Interrupt0_IRQn); ASSERT_TRUE(irqIPSR != 0U); // Exception Mode ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if defined(__CC_ARM) #define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn) #define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn) #elif defined( __GNUC__ ) && (!defined(__ti__)) && (!defined(__ARMCC_VERSION)) && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) #define SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") #define ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") #elif defined(_lint) //lint -save -e(9026) allow function-like macro #define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn)) #define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn)) //lint -restore #else #define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") #define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc") #endif /** \brief Test case: TC_CoreFunc_APSR \details - Check if __get_APSR intrinsic is available - Check if __get_xPSR intrinsic is available - Check negative, zero and overflow flags */ void TC_CoreFunc_APSR (void) { volatile uint32_t result; //lint -esym(838, Rm) unused values //lint -esym(438, Rm) unused values // Check negative flag volatile int32_t Rm = 5; volatile int32_t Rn = 7; SUBS(Rm, Rm, Rn); result = __get_APSR(); ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk); Rm = 5; Rn = 7; SUBS(Rm, Rm, Rn); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk); // Check zero and compare flag Rm = 5; SUBS(Rm, Rm, Rm); result = __get_APSR(); ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk); ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); Rm = 5; SUBS(Rm, Rm, Rm); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk); ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); // Check overflow flag Rm = 5; Rn = INT32_MAX; ADDS(Rm, Rm, Rn); result = __get_APSR(); ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk); Rm = 5; Rn = INT32_MAX; ADDS(Rm, Rm, Rn); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_PSP \details - Check if __get_PSP and __set_PSP intrinsic can be used to manipulate process stack pointer. */ void TC_CoreFunc_PSP (void) { // don't use stack for this variables static uint32_t orig; static uint32_t psp; static uint32_t result; orig = __get_PSP(); psp = orig + 0x12345678U; __set_PSP(psp); result = __get_PSP(); __set_PSP(orig); ASSERT_TRUE(result == psp); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_MSP \details - Check if __get_MSP and __set_MSP intrinsic can be used to manipulate main stack pointer. */ void TC_CoreFunc_MSP (void) { // don't use stack for this variables static uint32_t orig; static uint32_t msp; static uint32_t result; static uint32_t ctrl; ctrl = __get_CONTROL(); orig = __get_MSP(); __set_PSP(orig); __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP msp = orig + 0x12345678U; __set_MSP(msp); result = __get_MSP(); __set_MSP(orig); __set_CONTROL(ctrl); ASSERT_TRUE(result == msp); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_PSPLIM \details - Check if __get_PSPLIM and __set_PSPLIM intrinsic can be used to manipulate process stack pointer limit. */ void TC_CoreFunc_PSPLIM (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) // don't use stack for this variables static uint32_t orig; static uint32_t psplim; static uint32_t result; orig = __get_PSPLIM(); psplim = orig + 0x12345678U; __set_PSPLIM(psplim); result = __get_PSPLIM(); __set_PSPLIM(orig); #if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) ) // without main extensions, the non-secure PSPLIM is RAZ/WI ASSERT_TRUE(result == 0U); #else ASSERT_TRUE(result == psplim); #endif #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_PSPLIM_NS \details - Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS intrinsic can be used to manipulate process stack pointer limit. */ void TC_CoreFunc_PSPLIM_NS (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) uint32_t orig; uint32_t psplim; uint32_t result; orig = __TZ_get_PSPLIM_NS(); psplim = orig + 0x12345678U; __TZ_set_PSPLIM_NS(psplim); result = __TZ_get_PSPLIM_NS(); __TZ_set_PSPLIM_NS(orig); #if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) // without main extensions, the non-secure PSPLIM is RAZ/WI ASSERT_TRUE(result == 0U); #else ASSERT_TRUE(result == psplim); #endif #endif #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_MSPLIM \details - Check if __get_MSPLIM and __set_MSPLIM intrinsic can be used to manipulate main stack pointer limit. */ void TC_CoreFunc_MSPLIM (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) // don't use stack for this variables static uint32_t orig; static uint32_t msplim; static uint32_t result; static uint32_t ctrl; ctrl = __get_CONTROL(); __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP orig = __get_MSPLIM(); msplim = orig + 0x12345678U; __set_MSPLIM(msplim); result = __get_MSPLIM(); __set_MSPLIM(orig); __set_CONTROL(ctrl); #if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) ) // without main extensions, the non-secure MSPLIM is RAZ/WI ASSERT_TRUE(result == 0U); #else ASSERT_TRUE(result == msplim); #endif #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_MSPLIM_NS \details - Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS intrinsic can be used to manipulate process stack pointer limit. */ void TC_CoreFunc_MSPLIM_NS (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) uint32_t orig; uint32_t msplim; uint32_t result; orig = __TZ_get_MSPLIM_NS(); msplim = orig + 0x12345678U; __TZ_set_MSPLIM_NS(msplim); result = __TZ_get_MSPLIM_NS(); __TZ_set_MSPLIM_NS(orig); #if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ !(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) // without main extensions, the non-secure MSPLIM is RAZ/WI ASSERT_TRUE(result == 0U); #else ASSERT_TRUE(result == msplim); #endif #endif #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_PRIMASK \details - Check if __get_PRIMASK and __set_PRIMASK intrinsic can be used to manipulate PRIMASK. - Check if __enable_irq and __disable_irq are reflected in PRIMASK. */ void TC_CoreFunc_PRIMASK (void) { uint32_t orig = __get_PRIMASK(); // toggle primask uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U); __set_PRIMASK(primask); uint32_t result = __get_PRIMASK(); ASSERT_TRUE(result == primask); __disable_irq(); result = __get_PRIMASK(); ASSERT_TRUE((result & 0x01U) == 1U); __enable_irq(); result = __get_PRIMASK(); ASSERT_TRUE((result & 0x01U) == 0U); __disable_irq(); result = __get_PRIMASK(); ASSERT_TRUE((result & 0x01U) == 1U); __set_PRIMASK(orig); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_FAULTMASK \details - Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK. - Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK. */ void TC_CoreFunc_FAULTMASK (void) { #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) uint32_t orig = __get_FAULTMASK(); // toggle faultmask uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U); __set_FAULTMASK(faultmask); uint32_t result = __get_FAULTMASK(); ASSERT_TRUE(result == faultmask); __disable_fault_irq(); result = __get_FAULTMASK(); ASSERT_TRUE((result & 0x01U) == 1U); __enable_fault_irq(); result = __get_FAULTMASK(); ASSERT_TRUE((result & 0x01U) == 0U); __disable_fault_irq(); result = __get_FAULTMASK(); ASSERT_TRUE((result & 0x01U) == 1U); __set_FAULTMASK(orig); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_BASEPRI \details - Check if __get_BASEPRI and __set_BASEPRI intrinsic can be used to manipulate BASEPRI. - Check if __set_BASEPRI_MAX intrinsic can be used to manipulate BASEPRI. */ void TC_CoreFunc_BASEPRI(void) { #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) uint32_t orig = __get_BASEPRI(); uint32_t basepri = ~orig & 0x80U; __set_BASEPRI(basepri); uint32_t result = __get_BASEPRI(); ASSERT_TRUE(result == basepri); __set_BASEPRI(orig); __set_BASEPRI_MAX(basepri); result = __get_BASEPRI(); ASSERT_TRUE(result == basepri); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_FPUType \details Check SCB_GetFPUType returns information. */ void TC_CoreFunc_FPUType(void) { uint32_t fpuType = SCB_GetFPUType(); #if defined(__FPU_PRESENT) && (__FPU_PRESENT != 0) ASSERT_TRUE(fpuType > 0U); #else ASSERT_TRUE(fpuType == 0U); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreFunc_FPSCR \details - Check if __get_FPSCR and __set_FPSCR intrinsics can be used */ void TC_CoreFunc_FPSCR(void) { uint32_t fpscr = __get_FPSCR(); __ISB(); __DSB(); __set_FPSCR(~fpscr); __ISB(); __DSB(); uint32_t result = __get_FPSCR(); __set_FPSCR(fpscr); #if (defined (__FPU_USED ) && (__FPU_USED == 1U)) ASSERT_TRUE(result != fpscr); #else ASSERT_TRUE(result == 0U); #endif } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreInstr.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CoreInstr.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" #if defined(__CORTEX_M) #elif defined(__CORTEX_A) #include "irq_ctrl.h" #else #error __CORTEX_M or __CORTEX_A must be defined! #endif /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_NOP \details - Check if __NOP instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_NOP (void) { __NOP(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_SEV \details - Check if __SEV instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_SEV (void) { __SEV(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_BKPT \details - Check if __BKPT instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_BKPT (void) { __BKPT(0xABU); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_ISB \details - Check if __ISB instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_ISB (void) { __ISB(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_DSB \details - Check if __DSB instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_DSB (void) { __DSB(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_DMB \details - Check if __DNB instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_DMB (void) { __DMB(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_WFI \details - Check if __WFI instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_WFI (void) { __WFI(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_WFE \details - Check if __WFE instrinsic is available - No real assertion is deployed, just a compile time check. */ void TC_CoreInstr_WFE (void) { __WFE(); ASSERT_TRUE(1U == 1U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_REV \details - Check if __REV instrinsic swaps all bytes in a word. */ void TC_CoreInstr_REV (void) { volatile uint32_t op1_u32; volatile uint32_t res_u32; op1_u32 = 0x47110815U; res_u32 = __REV(op1_u32); ASSERT_TRUE(res_u32 == 0x15081147U); op1_u32 = 0x80000000U; res_u32 = __REV(op1_u32); ASSERT_TRUE(res_u32 == 0x00000080U); op1_u32 = 0x00000080U; res_u32 = __REV(op1_u32); ASSERT_TRUE(res_u32 == 0x80000000U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_REV16 \details - Check if __REV16 instrinsic swaps the bytes in both halfwords independendly. */ void TC_CoreInstr_REV16(void) { volatile uint32_t op1_u32; volatile uint32_t res_u32; op1_u32 = 0x47110815U; res_u32 = __REV16(op1_u32); ASSERT_TRUE(res_u32 == 0x11471508U); op1_u32 = 0x00001234U; res_u32 = __REV16(op1_u32); ASSERT_TRUE(res_u32 == 0x00003412U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_REVSH \details - Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign. */ void TC_CoreInstr_REVSH(void) { volatile int16_t value = 0U; int16_t result = 0U; value = 0x4711; result = __REVSH(value); ASSERT_TRUE(result == 0x1147); value = (int16_t)0x8000; result = __REVSH(value); ASSERT_TRUE(result == 0x0080); value = 0x0080; result = __REVSH(value); ASSERT_TRUE(result == (int16_t)0x8000); value = -0x1234; result = __REVSH(value); ASSERT_TRUE(result == (int16_t)0xcced); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_RBIT \details - Check if __RBIT instrinsic revserses the bit order of arbitrary words. */ void TC_CoreInstr_RBIT (void) { volatile uint32_t value = 0U; uint32_t result = 0U; value = 0xAAAAAAAAU; result = __RBIT(value); ASSERT_TRUE(result == 0x55555555U); value = 0x55555555U; result = __RBIT(value); ASSERT_TRUE(result == 0xAAAAAAAAU); value = 0x00000001U; result = __RBIT(value); ASSERT_TRUE(result == 0x80000000U); value = 0x80000000U; result = __RBIT(value); ASSERT_TRUE(result == 0x00000001U); value = 0xDEADBEEFU; result = __RBIT(value); ASSERT_TRUE(result == 0xF77DB57BU); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_ROR \details - Check if __ROR instrinsic moves all bits as expected. */ void TC_CoreInstr_ROR(void) { volatile uint32_t value = 0U; uint32_t result = 0U; value = 0x00000001U; result = __ROR(value, 1U); ASSERT_TRUE(result == 0x80000000U); value = 0x80000000U; result = __ROR(value, 1U); ASSERT_TRUE(result == 0x40000000U); value = 0x40000000U; result = __ROR(value, 30U); ASSERT_TRUE(result == 0x00000001U); value = 0x00000001U; result = __ROR(value, 32U); ASSERT_TRUE(result == 0x00000001U); value = 0x08154711U; result = __ROR(value, 8U); ASSERT_TRUE(result == 0x11081547U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_CLZ \details - Check if __CLZ instrinsic counts leading zeros. */ void TC_CoreInstr_CLZ (void) { volatile uint32_t value = 0U; uint32_t result = 0U; value = 0x00000000U; result = __CLZ(value); ASSERT_TRUE(result == 32); value = 0x00000001U; result = __CLZ(value); ASSERT_TRUE(result == 31); value = 0x40000000U; result = __CLZ(value); ASSERT_TRUE(result == 1); value = 0x80000000U; result = __CLZ(value); ASSERT_TRUE(result == 0); value = 0xFFFFFFFFU; result = __CLZ(value); ASSERT_TRUE(result == 0); value = 0x80000001U; result = __CLZ(value); ASSERT_TRUE(result == 0); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_SSAT \details - Check if __SSAT instrinsic saturates signed integer values. */ void TC_CoreInstr_SSAT (void) { volatile int32_t value = 0; int32_t result = 0; value = INT32_MAX; result = __SSAT(value, 32U); ASSERT_TRUE(result == INT32_MAX); value = INT32_MAX; result = __SSAT(value, 16U); ASSERT_TRUE(result == INT16_MAX); value = INT32_MAX; result = __SSAT(value, 8U); ASSERT_TRUE(result == INT8_MAX); value = INT32_MAX; result = __SSAT(value, 1U); ASSERT_TRUE(result == 0); value = INT32_MIN; result = __SSAT(value, 32U); ASSERT_TRUE(result == INT32_MIN); value = INT32_MIN; result = __SSAT(value, 16U); ASSERT_TRUE(result == INT16_MIN); value = INT32_MIN; result = __SSAT(value, 8U); ASSERT_TRUE(result == INT8_MIN); value = INT32_MIN; result = __SSAT(value, 1U); ASSERT_TRUE(result == -1); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_USAT \details - Check if __USAT instrinsic saturates unsigned integer values. */ void TC_CoreInstr_USAT (void) { volatile int32_t value = 0U; uint32_t result = 0U; value = INT32_MAX; result = __USAT(value, 31U); ASSERT_TRUE(result == (UINT32_MAX >> 1U)); value = INT32_MAX; result = __USAT(value, 16U); ASSERT_TRUE(result == UINT16_MAX); value = INT32_MAX; result = __USAT(value, 8U); ASSERT_TRUE(result == UINT8_MAX); value = INT32_MAX; result = __USAT(value, 0U); ASSERT_TRUE(result == 0U); value = INT32_MIN; result = __USAT(value, 31U); ASSERT_TRUE(result == 0U); value = INT32_MIN; result = __USAT(value, 16U); ASSERT_TRUE(result == 0U); value = INT32_MIN; result = __USAT(value, 8U); ASSERT_TRUE(result == 0U); value = INT32_MIN; result = __USAT(value, 0U); ASSERT_TRUE(result == 0U); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_CoreInstr_RRX \details - Check if __USAT instrinsic saturates unsigned integer values. */ void TC_CoreInstr_RRX (void) { #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) volatile uint32_t value = 0U; volatile uint32_t result = 0U; volatile xPSR_Type xPSR; value = 0x80000002; xPSR.w = __get_xPSR(); result = __RRX(value); ASSERT_TRUE(result == (0x40000001 | (uint32_t)(xPSR.b.C << 31))); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined(__CORTEX_A) ) ) /// Exclusive byte value static volatile uint8_t TC_CoreInstr_LoadStoreExclusive_byte = 0x47U; /// Exclusive halfword value static volatile uint16_t TC_CoreInstr_LoadStoreExclusive_hword = 0x0815U; /// Exclusive word value static volatile uint32_t TC_CoreInstr_LoadStoreExclusive_word = 0x08154711U; /** \brief Interrupt function for TC_CoreInstr_LoadStoreExclusive \details The interrupt manipulates all the global data which disrupts the exclusive sequences in the test */ static void TC_CoreInstr_LoadStoreExclusive_IRQHandler(void) { const uint8_t b = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); __STREXB((uint8_t)~b, &TC_CoreInstr_LoadStoreExclusive_byte); const uint16_t hw = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); __STREXH((uint16_t)~hw, &TC_CoreInstr_LoadStoreExclusive_hword); const uint32_t w = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); __STREXW((uint32_t)~w, &TC_CoreInstr_LoadStoreExclusive_word); } /** \brief Helper function for TC_CoreInstr_LoadStoreExclusive to enable test interrupt. \details This helper function implements interrupt enabling according to target architecture, i.e. Cortex-A or Cortex-M. */ static void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) { #if defined(__CORTEX_M) TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler; NVIC_EnableIRQ(Interrupt0_IRQn); #elif defined(__CORTEX_A) IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler); IRQ_Enable(SGI0_IRQn); #else #error __CORTEX_M or __CORTEX_A must be defined! #endif __enable_irq(); } /** \brief Helper function for TC_CoreInstr_LoadStoreExclusive to set test interrupt pending. \details This helper function implements set pending the test interrupt according to target architecture, i.e. Cortex-A or Cortex-M. */ static void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) { #if defined(__CORTEX_M) NVIC_SetPendingIRQ(Interrupt0_IRQn); #elif defined(__CORTEX_A) IRQ_SetPending(SGI0_IRQn); #else #error __CORTEX_M or __CORTEX_A must be defined! #endif for(uint32_t i = 10U; i > 0U; --i) {} } /** \brief Helper function for TC_CoreInstr_LoadStoreExclusive to disable test interrupt. \details This helper function implements interrupt disabling according to target architecture, i.e. Cortex-A or Cortex-M. */ static void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) { __disable_irq(); #if defined(__CORTEX_M) NVIC_DisableIRQ(Interrupt0_IRQn); TST_IRQHandler = NULL; #elif defined(__CORTEX_A) IRQ_Disable(SGI0_IRQn); IRQ_SetHandler(SGI0_IRQn, NULL); #else #error __CORTEX_M or __CORTEX_A must be defined! #endif } #endif /** \brief Test case: TC_CoreInstr_LoadStoreExclusive \details Checks exclusive load and store instructions: - LDREXB, LDREXH, LDREXW - STREXB, STREXH, STREXW - CLREX */ void TC_CoreInstr_LoadStoreExclusive (void) { #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined(__CORTEX_A) ) ) uint8_t u8, u8Inv; uint16_t u16, u16Inv; uint32_t u32, u32Inv; uint32_t result; /* 1. Test exclusives without interruption */ u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8+1U); u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16+1U); u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32+1U); /* 2. Test exclusives with clear */ u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); __CLREX(); result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(result == 1U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8); u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); __CLREX(); result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(result == 1U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16); u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); __CLREX(); result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(result == 1U); ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32); /* 3. Test exclusives with interruption */ TC_CoreInstr_LoadStoreExclusive_IRQEnable(); u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte); TC_CoreInstr_LoadStoreExclusive_IRQPend(); result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte); ASSERT_TRUE(result == 1U); u8Inv = (uint8_t)~u8; ASSERT_TRUE(u8Inv == TC_CoreInstr_LoadStoreExclusive_byte); u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword); TC_CoreInstr_LoadStoreExclusive_IRQPend(); result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword); ASSERT_TRUE(result == 1U); u16Inv = (uint16_t)~u16; ASSERT_TRUE(u16Inv == TC_CoreInstr_LoadStoreExclusive_hword); u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word); TC_CoreInstr_LoadStoreExclusive_IRQPend(); result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word); ASSERT_TRUE(result == 1U); u32Inv = (uint32_t)~u32; ASSERT_TRUE(u32Inv == TC_CoreInstr_LoadStoreExclusive_word); TC_CoreInstr_LoadStoreExclusive_IRQDisable(); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) /// byte value unprivileged access static volatile uint8_t TC_CoreInstr_LoadStoreUnpriv_byte = 0x47U; /// halfword value unprivileged access static volatile uint16_t TC_CoreInstr_LoadStoreUnpriv_hword = 0x0815U; /// word value unprivileged access static volatile uint32_t TC_CoreInstr_LoadStoreUnpriv_word = 0x08154711U; #endif /** \brief Test case: TC_CoreInstr_LoadStoreUnpriv \details Checks load/store unprivileged instructions: - LDRBT, LDRHT, LDRT - STRBT, STRHT, STRT */ void TC_CoreInstr_LoadStoreUnpriv (void) { #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) uint8_t u8 = 0U; uint16_t u16 = 0U; uint32_t u32 = 0U; /* 1. Test without interruption */ u8 = __LDRBT(&TC_CoreInstr_LoadStoreUnpriv_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreUnpriv_byte); __STRBT(u8+1U, &TC_CoreInstr_LoadStoreUnpriv_byte); ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_byte == u8+1U); u16 = __LDRHT(&TC_CoreInstr_LoadStoreUnpriv_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreUnpriv_hword); __STRHT(u16+1U, &TC_CoreInstr_LoadStoreUnpriv_hword); ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_hword == u16+1U); u32 = __LDRT(&TC_CoreInstr_LoadStoreUnpriv_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreUnpriv_word); __STRT(u32+1U, &TC_CoreInstr_LoadStoreUnpriv_word); ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_word == u32+1U); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /// byte value unprivileged access static volatile uint8_t TC_CoreInstr_LoadStoreAcquire_byte = 0x47U; /// halfword value unprivileged access static volatile uint16_t TC_CoreInstr_LoadStoreAcquire_hword = 0x0815U; /// word value unprivileged access static volatile uint32_t TC_CoreInstr_LoadStoreAcquire_word = 0x08154711U; #endif /** \brief Test case: TC_CoreInstr_LoadStoreAquire \details Checks Load-Acquire and Store-Release instructions: - LDAB, LDAH, LDA - STLB, STLH, STL */ void TC_CoreInstr_LoadStoreAcquire (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) uint8_t u8 = 0U; uint16_t u16 = 0U; uint32_t u32 = 0U; /* 1. Test without interruption */ u8 = __LDAB(&TC_CoreInstr_LoadStoreAcquire_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquire_byte); __STLB(u8+1U, &TC_CoreInstr_LoadStoreAcquire_byte); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_byte == u8+1U); u16 = __LDAH(&TC_CoreInstr_LoadStoreAcquire_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquire_hword); __STLH(u16+1U, &TC_CoreInstr_LoadStoreAcquire_hword); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_hword == u16+1U); u32 = __LDA(&TC_CoreInstr_LoadStoreAcquire_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquire_word); __STL(u32+1U, &TC_CoreInstr_LoadStoreAcquire_word); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_word == u32+1U); #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /// byte value unprivileged access static volatile uint8_t TC_CoreInstr_LoadStoreAcquireExclusive_byte = 0x47U; /// halfword value unprivileged access static volatile uint16_t TC_CoreInstr_LoadStoreAcquireExclusive_hword = 0x0815U; /// word value unprivileged access static volatile uint32_t TC_CoreInstr_LoadStoreAcquireExclusive_word = 0x08154711U; #endif /** \brief Test case: TC_CoreInstr_LoadStoreAquire \details Checks Load-Acquire and Store-Release exclusive instructions: - LDAEXB, LDAEXH, LDAEX - STLEXB, STLEXH, STLEX */ void TC_CoreInstr_LoadStoreAcquireExclusive (void) { #if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) uint8_t u8 = 0U; uint16_t u16 = 0U; uint32_t u32 = 0U; uint32_t result = 0U; /* 1. Test without interruption */ u8 = __LDAEXB(&TC_CoreInstr_LoadStoreAcquireExclusive_byte); ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquireExclusive_byte); result = __STLEXB(u8+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_byte); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_byte == u8+1U); u16 = __LDAEXH(&TC_CoreInstr_LoadStoreAcquireExclusive_hword); ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquireExclusive_hword); result = __STLEXH(u16+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_hword); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_hword == u16+1U); u32 = __LDAEX(&TC_CoreInstr_LoadStoreAcquireExclusive_word); ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquireExclusive_word); result = __STLEX(u32+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_word); ASSERT_TRUE(result == 0U); ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_word == u32+1U); #endif } /** \brief Test case: TC_CoreInstr_UnalignedUint16 \details Checks macro functions to access unaligned uint16_t values: - __UNALIGNED_UINT16_READ - __UNALIGNED_UINT16_WRITE */ void TC_CoreInstr_UnalignedUint16(void) { uint8_t buffer[3] = { 0U, 0U, 0U }; uint16_t val; for(int i=0; i<2; i++) { __UNALIGNED_UINT16_WRITE(&(buffer[i]), 0x4711U); ASSERT_TRUE(buffer[i] == 0x11U); ASSERT_TRUE(buffer[i+1] == 0x47U); ASSERT_TRUE(buffer[(i+2)%3] == 0x00U); buffer[i] = 0x12U; buffer[i+1] = 0x46U; val = __UNALIGNED_UINT16_READ(&(buffer[i])); ASSERT_TRUE(val == 0x4612U); buffer[i] = 0x00U; buffer[i+1] = 0x00U; } } /** \brief Test case: TC_CoreInstr_UnalignedUint32 \details Checks macro functions to access unaligned uint32_t values: - __UNALIGNED_UINT32_READ - __UNALIGNED_UINT32_WRITE */ void TC_CoreInstr_UnalignedUint32(void) { uint8_t buffer[7] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U }; uint32_t val; for(int i=0; i<4; i++) { __UNALIGNED_UINT32_WRITE(&(buffer[i]), 0x08154711UL); ASSERT_TRUE(buffer[i+0] == 0x11U); ASSERT_TRUE(buffer[i+1] == 0x47U); ASSERT_TRUE(buffer[i+2] == 0x15U); ASSERT_TRUE(buffer[i+3] == 0x08U); ASSERT_TRUE(buffer[(i+4)%7] == 0x00U); ASSERT_TRUE(buffer[(i+5)%7] == 0x00U); ASSERT_TRUE(buffer[(i+6)%7] == 0x00U); buffer[i+0] = 0x12U; buffer[i+1] = 0x46U; buffer[i+2] = 0x14U; buffer[i+3] = 0x09U; val = __UNALIGNED_UINT32_READ(&(buffer[i])); ASSERT_TRUE(val == 0x09144612UL); buffer[i+0] = 0x00U; buffer[i+1] = 0x00U; buffer[i+2] = 0x00U; buffer[i+3] = 0x00U; } } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreSimd.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_CoreSimd.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2018 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /** \brief Test case: TC_CoreSimd_SatAddSub \details - Check Saturating addition and subtraction: __QADD __QSUB */ void TC_CoreSimd_SatAddSub (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; /* --- __QADD Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80000003; op2_s32 = (int32_t)0x00000004; res_s32 = __QADD(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80000007); op1_s32 = (int32_t)0x80000000; op2_s32 = (int32_t)0x80000002; res_s32 = __QADD(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80000000); /* --- __QSUB Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80000003; op2_s32 = (int32_t)0x00000004; res_s32 = __QSUB(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80000000); op1_s32 = (int32_t)0x80000003; op2_s32 = (int32_t)0x00000002; res_s32 = __QSUB(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80000001); #endif } /** \brief Test case: TC_CoreSimd_ParSat16 \details - Check Parallel 16-bit saturation: __SSAT16 __USAT16 */ void TC_CoreSimd_ParSat16 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile int32_t op1_s32; volatile int32_t res_s32; /* --- __SSAT16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80030168; res_s32 = __SSAT16(op1_s32, 8); ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F); /* --- __USAT16 Test ---------------------------------------------- */ op1_s32 = 0x0030168; res_s32 = __USAT16(op1_s32, 8); ASSERT_TRUE(res_s32 == 0x000300FF); #endif } /** \brief Test case: TC_CoreSimd_PackUnpack \details - Check Packing and unpacking: __SXTB16 __SXTB16_RORn __SXTAB16 __SXTAB16__RORn __UXTB16 __UXTAB16 */ void TC_CoreSimd_PackUnpack (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; /* --- __SXTB16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80830168; res_s32 = __SXTB16(op1_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFF830068); /* --- __SXTB16_ROR8 Test ----------------------------------------- */ op1_s32 = (int32_t)0x80830168; res_s32 = __SXTB16_RORn(op1_s32, 8); ASSERT_TRUE(res_s32 == (int32_t)0xFF800001); /* --- __SXTB16_ROR16 Test ---------------------------------------- */ op1_s32 = (int32_t)0x80830168; res_s32 = __SXTB16_RORn(op1_s32, 16); ASSERT_TRUE(res_s32 == (int32_t)0x68FF83); /* --- __SXTB16_ROR24 Test ---------------------------------------- */ op1_s32 = (int32_t)0x80830168; res_s32 = __SXTB16_RORn(op1_s32, 24); ASSERT_TRUE(res_s32 == (int32_t)0x1FF80); /* --- __SXTAB16 Test --------------------------------------------- */ op1_s32 = (int32_t)0x000D0008; op2_s32 = (int32_t)0x80830168; res_s32 = __SXTAB16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFF900070); /* --- __SXTAB16__ROR8 Test --------------------------------------- */ op1_s32 = (int32_t)0x000A000A; op2_s32 = (int32_t)0x80830168; res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8); ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B); /* --- __SXTAB16__ROR8 Test --------------------------------------- */ op1_s32 = (int32_t)0xFFF6FFF6; op2_s32 = (int32_t)0x80830168; res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8); ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7); /* --- __SXTAB16__ROR16 Test -------------------------------------- */ op1_s32 = (int32_t)0xFFF60015; op2_s32 = (int32_t)0x70880168; res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16); ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D); /* --- __SXTAB16__ROR24 Test -------------------------------------- */ op1_s32 = (int32_t)0xFFF60015; op2_s32 = (int32_t)0x70880168; res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24); ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085); /* --- __UXTB16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80830168; res_s32 = __UXTB16(op1_s32); ASSERT_TRUE(res_s32 == 0x00830068); /* --- __UXTAB16 Test --------------------------------------------- */ op1_s32 = 0x000D0008; op2_s32 = (int32_t)0x80830168; res_s32 = __UXTAB16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == 0x00900070); #endif } /** \brief Test case: TC_CoreSimd_ParSel \details - Check Parallel selection: __SEL */ void TC_CoreSimd_ParSel (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t res_u32; volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; APSR_Type apsr; xPSR_Type xpsr; /* --- __SEL Test ---------------------------------------------- */ op1_s32 = 0x33221100; op2_s32 = 0x77665544; res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */ ASSERT_TRUE( res_s32 == 0x77665544); res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */ ASSERT_TRUE(res_s32 == 0x77665500); res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */ ASSERT_TRUE(res_s32 == 0x77661144); #endif } /** \brief Test case: TC_CoreSimd_ParAddSub8 \details - Check Parallel 8-bit addition and subtraction: __SADD8 S Signed __SSUB8 Q Signed Saturating __SHADD8 SH Signed Halving __SHSUB8 U Unsigned __QADD8 UQ Unsigned Saturating __QSUB8 UH Unsigned Halving __UADD8 __USUB8 __UHADD8 __UHSUB8 __UQADD8 __UQSUB8 */ void TC_CoreSimd_ParAddSub8 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t op1_u32, op2_u32; volatile uint32_t res_u32; volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; /* --- __SADD8 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x87858381; op2_s32 = (int32_t)0x08060402; res_s32 = __SADD8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783); /* --- __SSUB8 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x8F8B8783; op2_s32 = (int32_t)0x08060402; res_s32 = __SSUB8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x87858381); /* --- __SHADD8 Test ---------------------------------------------- */ op1_s32 = 0x07050302; op2_s32 = 0x08060402; res_s32 = __SHADD8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == 0x07050302); /* --- __SHSUB8 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x8F8B8783; op2_s32 = 0x08060402; res_s32 = __SHSUB8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0); /* --- __QADD8 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x8085837F; op2_s32 = (int32_t)0xFF060402; res_s32 = __QADD8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x808B877F); /* --- __QSUB8 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x808B8783; op2_s32 = (int32_t)0x08060402; res_s32 = __QSUB8(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80858381); /* --- __UADD8 Test ---------------------------------------------- */ op1_u32 = 0x07050301; op2_u32 = 0x08060402; res_u32 = __UADD8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x0F0B0703); /* --- __USUB8 Test ---------------------------------------------- */ op1_u32 = 0x0F0B0703; op2_u32 = 0x08060402; res_u32 = __USUB8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x07050301); /* --- __UHADD8 Test ---------------------------------------------- */ op1_u32 = 0x07050302; op2_u32 = 0x08060402; res_u32 = __UHADD8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x07050302); /* --- __UHSUB8 Test ---------------------------------------------- */ op1_u32 = 0x0F0B0703; op2_u32 = 0x08060402; res_u32 = __UHSUB8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x03020100); /* --- __UQADD8 Test ---------------------------------------------- */ op1_u32 = 0xFF050301; op2_u32 = 0x08060402; res_u32 = __UQADD8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0xFF0B0703); /* --- __UQSUB8 Test ---------------------------------------------- */ op1_u32 = 0x080B0702; op2_u32 = 0x0F060408; res_u32 = __UQSUB8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00050300); #endif } /** \brief Test case: TC_CoreSimd_AbsDif8 \details - Check Sum of 8-bit absolute differences: __USAD8 __USADA8 */ void TC_CoreSimd_AbsDif8 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t op1_u32, op2_u32, op3_u32; volatile uint32_t res_u32; /* --- __USAD8 Test ---------------------------------------------- */ op1_u32 = 0x87858381; op2_u32 = 0x08060402; res_u32 = __USAD8(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x000001FC); /* --- __USADA8 Test ---------------------------------------------- */ op1_u32 = 0x87858381; op2_u32 = 0x08060402; op3_u32 = 0x00008000; res_u32 = __USADA8(op1_u32, op2_u32, op3_u32); ASSERT_TRUE(res_u32 == 0x000081FC); #endif } /** \brief Test case: TC_CoreSimd_ParAddSub16 \details - Check Parallel 16-bit addition and subtraction: __SADD16 __SSUB16 __SASX __SSAX __SHADD16 __SHSUB16 __SHASX __SHSAX __QADD16 __QSUB16 __QASX __QSAX __UADD16 __USUB16 __UASX __USAX __UHADD16 __UHSUB16 __UHASX __UHSAX __UQSUB16 __UQADD16 __UQASX __UQSAX */ void TC_CoreSimd_ParAddSub16 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t op1_u32, op2_u32; volatile uint32_t res_u32; volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; /* --- __SADD16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038001; op2_s32 = (int32_t)0x00040002; res_s32 = __SADD16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80078003); /* --- __SSUB16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80078003; op2_s32 = (int32_t)0x00040002; res_s32 = __SSUB16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80038001); /* --- __SASX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80078003; op2_s32 = (int32_t)0x00040002; res_s32 = __SASX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF); /* --- __SSAX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038007; op2_s32 = (int32_t)0x00020004; res_s32 = __SSAX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009); /* --- __SHADD16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038001; op2_s32 = (int32_t)0x00040002; res_s32 = __SHADD16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xC003C001); /* --- __SHSUB16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80078003; op2_s32 = (int32_t)0x00040002; res_s32 = __SHSUB16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xC001C000); /* --- __SHASX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80078003; op2_s32 = (int32_t)0x00040002; res_s32 = __SHASX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF); /* --- __SHSAX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038007; op2_s32 = (int32_t)0x00020004; res_s32 = __SHSAX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004); /* --- __QADD16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038000; op2_s32 = (int32_t)0x00048002; res_s32 = __QADD16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80078000); /* --- __QSUB16 Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038003; op2_s32 = (int32_t)0x00040002; res_s32 = __QSUB16(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80008001); /* --- __QASX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80078003; op2_s32 = (int32_t)0x00040002; res_s32 = __QASX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80098000); /* --- __QSAX Test ---------------------------------------------- */ op1_s32 = (int32_t)0x80038007; op2_s32 = (int32_t)0x00020004; res_s32 = __QSAX(op1_s32, op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x80008009); /* --- __UADD16 Test ---------------------------------------------- */ op1_u32 = 0x00010002; op2_u32 = 0x00020004; res_u32 = __UADD16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00030006); /* --- __USUB16 Test ---------------------------------------------- */ op1_u32 = 0x00030006; op2_u32 = 0x00020004; res_u32 = __USUB16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00010002); /* --- __UASX Test ---------------------------------------------- */ op1_u32 = 0x80078003; op2_u32 = 0x00040002; res_u32 = __UASX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x80097FFF); /* --- __USAX Test ---------------------------------------------- */ op1_u32 = 0x80038007; op2_u32 = 0x00020004; res_u32 = __USAX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x7FFF8009); /* --- __UHADD16 Test ---------------------------------------------- */ op1_u32 = 0x00010002; op2_u32 = 0x00020004; res_u32 = __UHADD16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00010003); /* --- __UHSUB16 Test ---------------------------------------------- */ op1_u32 = 0x00030006; op2_u32 = 0x00020004; res_u32 = __UHSUB16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00000001); /* --- __UHASX Test ---------------------------------------------- */ op1_u32 = 0x80078003; op2_u32 = 0x00040002; res_u32 = __UHASX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x40043FFF); /* --- __UHSAX Test ---------------------------------------------- */ op1_u32 = 0x80038007; op2_u32 = 0x00020004; res_u32 = __UHSAX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x3FFF4004); /* --- __UQADD16 Test ---------------------------------------------- */ op1_u32 = 0xFFFE0002; op2_u32 = 0x00020004; res_u32 = __UQADD16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0xFFFF0006); /* --- __UQSUB16 Test ---------------------------------------------- */ op1_u32 = 0x00020006; op2_u32 = 0x00030004; res_u32 = __UQSUB16(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x00000002); /* --- __UQASX Test ---------------------------------------------- */ op1_u32 = 0xFFF80003; op2_u32 = 0x00040009; res_u32 = __UQASX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0xFFFF0000); /* --- __UQSAX Test ---------------------------------------------- */ op1_u32 = 0x0003FFF8; op2_u32 = 0x00090004; res_u32 = __UQSAX(op1_u32, op2_u32); ASSERT_TRUE(res_u32 == 0x0000FFFF); #endif } /** \brief Test case: TC_CoreSimd_ParMul16 \details - Check Parallel 16-bit multiplication: __SMLAD __SMLADX __SMLALD __SMLALDX __SMLSD __SMLSDX __SMLSLD __SMLSLDX __SMUAD __SMUADX __SMUSD __SMUSDX */ void TC_CoreSimd_ParMul16 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile int32_t op1_s32, op2_s32, op3_s32; volatile int32_t res_s32; volatile int64_t op1_s64; volatile int64_t res_s64; /* --- __SMLAD Test ---------------------------------------------- */ op1_s32 = 0x00030002; op2_s32 = 0x00050004; op3_s32 = 0x20000000; res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x20000017); /* --- __SMLADX Test ---------------------------------------------- */ op1_s32 = 0x00030002; op2_s32 = 0x00050004; op3_s32 = 0x00000800; res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x00000816); /* --- __SMLALD Test ---------------------------------------------- */ op1_s32 = 0x00030002; op2_s32 = 0x00050004; op1_s64 = 0x00000000200000000LL; res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64); ASSERT_TRUE(res_s64 == 0x0000000200000017LL); /* --- __SMLALDX Test ---------------------------------------------- */ op1_s32 = 0x00030002; op2_s32 = 0x00050004; op1_s64 = 0x00000000200000000LL; res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64); ASSERT_TRUE(res_s64 == 0x0000000200000016LL); /* --- __SMLSD Test ---------------------------------------------- */ op1_s32 = 0x00030006; op2_s32 = 0x00050004; op3_s32 = 0x00000800; res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x00000809); /* --- __SMLSDX Test ---------------------------------------------- */ op1_s32 = 0x00030002; op2_s32 = 0x00050004; op3_s32 = 0x00000800; res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x000007FE); /* --- __SMLSLD Test ---------------------------------------------- */ op1_s32 = 0x00030006; op2_s32 = 0x00050004; op1_s64 = 0x00000000200000000LL; res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64); ASSERT_TRUE(res_s64 == 0x0000000200000009LL); /* --- __SMLSLDX Test ---------------------------------------------- */ op1_s32 = 0x00030006; op2_s32 = 0x00050004; op1_s64 = 0x00000000200000000LL; res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64); ASSERT_TRUE(res_s64 == 0x0000000200000012LL); /* --- __SMUAD Test ---------------------------------------------- */ op1_s32 = 0x00030001; op2_s32 = 0x00040002; res_s32 = __SMUAD(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == 0x0000000E); op1_s32 = (int32_t)0xFFFDFFFF; op2_s32 = (int32_t)0x00040002; res_s32 = __SMUAD(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2); /* --- __SMUADX Test ---------------------------------------------- */ op1_s32 = 0x00030001; op2_s32 = 0x00040002; res_s32 = __SMUADX(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == 0x0000000A); op1_s32 = (int32_t)0xFFFDFFFF; op2_s32 = (int32_t)0x00040002; res_s32 = __SMUADX(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6); /* --- __SMUSD Test ---------------------------------------------- */ op1_s32 = (int32_t)0x00030001; op2_s32 = (int32_t)0x00040002; res_s32 = __SMUSD(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6); op1_s32 = (int32_t)0xFFFDFFFF; op2_s32 = (int32_t)0x00040002; res_s32 = __SMUSD(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == 0x0000000A); /* --- __SMUSDX Test ---------------------------------------------- */ op1_s32 = 0x00030001; op2_s32 = 0x00040002; res_s32 = __SMUSDX(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE); op1_s32 = (int32_t)0xFFFDFFFF; op2_s32 = (int32_t)0x00040002; res_s32 = __SMUSDX(op1_s32,op2_s32); ASSERT_TRUE(res_s32 == (int32_t)0x00000002); #endif } /** \brief Test case: TC_CoreSimd_Part9 \details - Check Packing Halfword: __PKHBT __PKHTB */ void TC_CoreSimd_Pack16 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t op1_u32, op2_u32; volatile uint32_t res_u32; /* --- __PKHBT Test ---------------------------------------------- */ op1_u32 = 0x00000111; op2_u32 = 0x22200000; res_u32 = __PKHBT(op1_u32, op2_u32, 0); ASSERT_TRUE(res_u32 == 0x22200111); op1_u32 = 0x00000111; op2_u32 = 0x22200000; res_u32 = __PKHBT(op1_u32, op2_u32, 4); ASSERT_TRUE(res_u32 == 0x22000111); /* --- __PKHTB Test ---------------------------------------------- */ op1_u32 = 0x11100000; op2_u32 = 0x00000222; res_u32 = __PKHTB(op1_u32, op2_u32, 0); ASSERT_TRUE(res_u32 == 0x11100222); op1_u32 = 0x11100000; op2_u32 = 0x00000222; res_u32 = __PKHTB(op1_u32, op2_u32, 4); ASSERT_TRUE(res_u32 == 0x11100022); #endif } /** \brief Test case: TC_CoreSimd_MulAcc32 \details - Check Signed Most Significant Word Multiply Accumulate: __SMMLA */ void TC_CoreSimd_MulAcc32 (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile int32_t op1_s32, op2_s32, op3_s32; volatile int32_t res_s32; /* --- __SMMLA Test ---------------------------------------------- */ op1_s32 = 0x00000200; op2_s32 = 0x00000004; op3_s32 = 0x00000100; res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x00000100); op1_s32 = 0x40000000; op2_s32 = 0x00000010; op3_s32 = 0x00000300; res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32); ASSERT_TRUE(res_s32 == 0x00000304); #endif } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Framework.c ================================================ /*----------------------------------------------------------------------------- * Name: cv_framework.c * Purpose: Test framework entry point *---------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /* Prototypes */ void ts_cmsis_cv(void); void closeDebug(void); /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \defgroup framework_funcs Framework Functions \brief Functions in the Framework software component \details @{ */ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Close the debug session. \details Debug session dead end - debug script should close session here. */ void closeDebug(void) { __NOP(); // Test completed } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief This is CORE Validation test suite. \details Program flow: -# Test report statistics is initialized -# Test report headers are written to the standard output -# All defined test cases are executed: - Test case statistics is initialized - Test case report header is written to the standard output - Test case is executed - Test case results are written to the standard output - Test case report footer is written to the standard output - Test case is closed -# Test report footer is written to the standard output -# Debug session ends in dead loop */ void ts_cmsis_cv () { const char *fn; uint32_t tc, no; (void)ritf.Init (); /* Init test report */ (void)ritf.Open (ts.ReportTitle, /* Write test report title */ ts.Date, /* Write compilation date */ ts.Time, /* Write compilation time */ ts.FileName); /* Write module file name */ /* Execute all test cases */ for (tc = 0; tc < ts.NumOfTC; tc++) { no = ts.TCBaseNum+tc; /* Test case number */ fn = ts.TC[tc].TFName; /* Test function name string */ (void)ritf.Open_TC (no, fn); /* Open test case #(Base + TC) */ if (ts.TC[tc].en != 0U) { ts.TC[tc].TestFunc(); /* Execute test case if enabled */ } (void)ritf.Close_TC (); /* Close test case */ } (void)ritf.Close (); /* Close test report */ closeDebug(); /* Close debug session */ } /** \brief This is the entry point of the test framework. \details Program flow: -# Hardware is first initialized if Init callback function is provided -# Main thread is initialized */ void cmsis_cv (void) { /* Init test suite */ if (ts.Init != NULL) { ts.Init(); /* Init hardware */ } ts_cmsis_cv(); } void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc) { (void)__set_result(fn, ln, FAILED, desc); (void)ritf.Close_TC(); (void)ritf.Close(); closeDebug(); } /** @} */ // end of group framework_funcs ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_GenTimer.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_GenTimer.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_GenTimer_CNTFRQ(void) { const uint32_t cntfrq1 = __get_CNTFRQ(); __set_CNTFRQ(cntfrq1 + 1U); const uint32_t cntfrq2 = __get_CNTFRQ(); ASSERT_TRUE((cntfrq1 + 1U) == cntfrq2); __set_CNTFRQ(cntfrq1); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_GenTimer_CNTP_TVAL(void) { const uint32_t cntp_tval1 = __get_CNTP_TVAL(); __set_CNTP_TVAL(cntp_tval1 + 1U); const uint32_t cntp_tval2 = __get_CNTP_TVAL(); ASSERT_TRUE((cntp_tval2 - cntp_tval1) >= 1ULL); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_GenTimer_CNTP_CTL(void) { static const uint32_t CNTP_CTL_ENABLE = 0x01U; const uint32_t cntp_ctl = __get_CNTP_CTL(); const uint32_t cntp_ctl_toggled = (cntp_ctl & (~CNTP_CTL_ENABLE)) | ((~cntp_ctl) & CNTP_CTL_ENABLE); __set_CNTP_CTL(cntp_ctl_toggled); const uint32_t cntp_ctl_new = __get_CNTP_CTL(); ASSERT_TRUE((cntp_ctl_toggled & CNTP_CTL_ENABLE) == (cntp_ctl_new & CNTP_CTL_ENABLE)); __set_CNTP_CTL(cntp_ctl); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_GenTimer_CNTPCT(void) { const uint64_t cntpct1 = __get_CNTPCT(); for(int i=0; i<10; i++); const uint64_t cntpct2 = __get_CNTPCT(); ASSERT_TRUE((cntpct2 - cntpct1) <= 120ULL); } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ void TC_GenTimer_CNTP_CVAL(void) { const uint64_t cntp_cval1 = __get_CNTP_CVAL(); __set_CNTP_CVAL(cntp_cval1 + 1ULL); const uint64_t cntp_cval2 = __get_CNTP_CVAL(); ASSERT_TRUE((cntp_cval2 - cntp_cval1) >= 1ULL); } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_MPU_ARMv7.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ #if defined(__MPU_PRESENT) && __MPU_PRESENT static void ClearMpu(void) { for(uint32_t i = 0U; i < 8U; ++i) { MPU->RNR = i; MPU->RBAR = 0U; MPU->RASR = 0U; } } #endif /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_MPU_SetClear \details - Check if ARM_MPU_Load correctly loads MPU table to registers. */ void TC_MPU_SetClear(void) { #if defined(__MPU_PRESENT) && __MPU_PRESENT static const ARM_MPU_Region_t table[] = { { .RBAR = 0U, .RASR = 0U }, { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) }, { .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) } }; #define ASSERT_MPU_REGION(rnr, region) \ MPU->RNR = rnr; \ ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \ ASSERT_TRUE(MPU->RASR == region.RASR) ClearMpu(); ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR); ASSERT_MPU_REGION(1U, table[0]); ASSERT_MPU_REGION(2U, table[1]); ASSERT_MPU_REGION(3U, table[0]); ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR); ASSERT_MPU_REGION(4U, table[0]); ASSERT_MPU_REGION(5U, table[2]); ASSERT_MPU_REGION(6U, table[0]); ARM_MPU_ClrRegion(5U); MPU->RNR = 5U; ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U); #undef ASSERT_MPU_REGION #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_MPU_Load \details - Check if ARM_MPU_Load correctly loads MPU table to registers. */ void TC_MPU_Load(void) { #if defined(__MPU_PRESENT) && __MPU_PRESENT static const ARM_MPU_Region_t table[] = { { .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) }, { .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }, { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) }, { .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) }, { .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) }, { .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB) }, { .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB) }, { .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB) } }; #define ASSERT_MPU_REGION(rnr, table) \ MPU->RNR = rnr; \ ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \ ASSERT_TRUE(MPU->RASR == table[rnr].RASR) ClearMpu(); ARM_MPU_Load(&(table[0]), 1U); ASSERT_MPU_REGION(0U, table); ARM_MPU_Load(&(table[1]), 5U); ASSERT_MPU_REGION(0U, table); ASSERT_MPU_REGION(1U, table); ASSERT_MPU_REGION(2U, table); ASSERT_MPU_REGION(3U, table); ASSERT_MPU_REGION(4U, table); ASSERT_MPU_REGION(5U, table); ARM_MPU_Load(&(table[6]), 2U); ASSERT_MPU_REGION(5U, table); ASSERT_MPU_REGION(6U, table); ASSERT_MPU_REGION(7U, table); #undef ASSERT_MPU_REGION #endif } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c ================================================ /*----------------------------------------------------------------------------- * Name: CV_MPU_ARMv7.c * Purpose: CMSIS CORE validation tests implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Framework.h" #include "cmsis_cv.h" /*----------------------------------------------------------------------------- * Test implementation *----------------------------------------------------------------------------*/ #if defined(__MPU_PRESENT) && __MPU_PRESENT static void ClearMpu(void) { for(uint32_t i = 0U; i < 8U; ++i) { MPU->RNR = i; MPU->RBAR = 0U; MPU->RLAR = 0U; } } #endif /*----------------------------------------------------------------------------- * Test cases *----------------------------------------------------------------------------*/ /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_MPU_SetClear \details - Check if ARM_MPU_Load correctly loads MPU table to registers. */ void TC_MPU_SetClear(void) { #if defined(__MPU_PRESENT) && __MPU_PRESENT static const ARM_MPU_Region_t table[] = { { .RBAR = 0U, .RLAR = 0U }, { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) } }; #define ASSERT_MPU_REGION(rnr, region) \ MPU->RNR = rnr; \ ASSERT_TRUE(MPU->RBAR == region.RBAR); \ ASSERT_TRUE(MPU->RLAR == region.RLAR) ClearMpu(); ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR); ASSERT_MPU_REGION(1U, table[0]); ASSERT_MPU_REGION(2U, table[1]); ASSERT_MPU_REGION(3U, table[0]); ARM_MPU_ClrRegion(2U); MPU->RNR = 2U; ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U); #undef ASSERT_MPU_REGION #endif } /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/ /** \brief Test case: TC_MPU_Load \details - Check if ARM_MPU_Load correctly loads MPU table to registers. */ void TC_MPU_Load(void) { #if defined(__MPU_PRESENT) && __MPU_PRESENT static const ARM_MPU_Region_t table[] = { { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) }, { .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) } }; #define ASSERT_MPU_REGION(rnr, table) \ MPU->RNR = rnr; \ ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \ ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR) ClearMpu(); ARM_MPU_Load(0U, &(table[0]), 1U); ASSERT_MPU_REGION(0U, table); ARM_MPU_Load(1U, &(table[1]), 5U); ASSERT_MPU_REGION(0U, table); ASSERT_MPU_REGION(1U, table); ASSERT_MPU_REGION(2U, table); ASSERT_MPU_REGION(3U, table); ASSERT_MPU_REGION(4U, table); ASSERT_MPU_REGION(5U, table); ARM_MPU_Load(6U, &(table[6]), 2U); ASSERT_MPU_REGION(5U, table); ASSERT_MPU_REGION(6U, table); ASSERT_MPU_REGION(7U, table); #undef ASSERT_MPU_REGION #endif } ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Report.c ================================================ /*----------------------------------------------------------------------------- * Name: cv_report.c * Purpose: Report statistics and layout implementation *----------------------------------------------------------------------------- * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "CV_Report.h" #include #include TEST_REPORT test_report; static AS_STAT current_assertions; /* Current test case assertions statistics */ #define TAS (&test_report.assertions) /* Total assertions */ #define CAS (¤t_assertions) /* Current assertions */ #ifdef DISABLE_SEMIHOSTING #if defined (__CC_ARM) #pragma import __use_no_semihosting #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) __ASM(".global __use_no_semihosting"); #endif #define PRINT(x) #define FLUSH() void _sys_exit(int return_code) {} #else #define PRINT(x) MsgPrint x #define FLUSH() MsgFlush() #endif // DISABLE_SEMIHOSTING static uint8_t Passed[] = "PASSED"; static uint8_t Warning[] = "WARNING"; static uint8_t Failed[] = "FAILED"; static uint8_t NotExe[] = "NOT EXECUTED"; /*----------------------------------------------------------------------------- * Test report function prototypes *----------------------------------------------------------------------------*/ static BOOL tr_Init (void); static BOOL tc_Init (void); static uint8_t *tr_Eval (void); static uint8_t *tc_Eval (void); static BOOL StatCount (TC_RES res); /*----------------------------------------------------------------------------- * Printer function prototypes *----------------------------------------------------------------------------*/ static void MsgPrint (const char *msg, ...); static void MsgFlush (void); /*----------------------------------------------------------------------------- * Assert interface function prototypes *----------------------------------------------------------------------------*/ static BOOL As_File_Result (TC_RES res); static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc); TC_ITF tcitf = { As_File_Result, As_File_Dbgi, }; /*----------------------------------------------------------------------------- * Test report interface function prototypes *----------------------------------------------------------------------------*/ BOOL tr_File_Init (void); BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn); BOOL tr_File_Close (void); BOOL tc_File_Open (uint32_t num, const char *fn); BOOL tc_File_Close (void); REPORT_ITF ritf = { tr_File_Init, tr_File_Open, tr_File_Close, tc_File_Open, tc_File_Close }; /*----------------------------------------------------------------------------- * Init test report *----------------------------------------------------------------------------*/ BOOL tr_File_Init (void) { return (tr_Init()); } /*----------------------------------------------------------------------------- * Open test report *----------------------------------------------------------------------------*/ #if (PRINT_XML_REPORT==1) BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) { PRINT(("\n")); PRINT(("\n")); PRINT(("\n")); PRINT(("\n")); PRINT(("%s\n", title)); PRINT(("%s\n", date)); PRINT(("\n", time)); PRINT(("%s\n", fn)); PRINT(("\n")); #else BOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) { PRINT(("%s %s %s \n\n", title, date, time)); #endif return (__TRUE); } /*----------------------------------------------------------------------------- * Open test case *----------------------------------------------------------------------------*/ BOOL tc_File_Open (uint32_t num, const char *fn) { (void)tc_Init (); #if (PRINT_XML_REPORT==1) PRINT(("\n")); PRINT(("%d\n", num)); PRINT(("%s\n", fn)); PRINT(("")); PRINT(("")); PRINT(("\n")); #else PRINT(("TEST %02d: %-42s ", num, fn)); #endif return (__TRUE); } /*----------------------------------------------------------------------------- * Close test case *----------------------------------------------------------------------------*/ BOOL tc_File_Close (void) { uint8_t *res = tc_Eval(); #if (PRINT_XML_REPORT==1) PRINT(("\n")); PRINT(("%s\n", res)); PRINT(("\n")); #else if ((res==Passed)||(res==NotExe)) { PRINT(("%s\n", res)); } else { PRINT(("\n")); } #endif FLUSH(); return (__TRUE); } /*----------------------------------------------------------------------------- * Close test report *----------------------------------------------------------------------------*/ BOOL tr_File_Close (void) { #if (PRINT_XML_REPORT==1) PRINT(("\n")); PRINT(("\n")); PRINT(("%d\n", test_report.tests)); PRINT(("%d\n", test_report.executed)); PRINT(("%d\n", test_report.passed)); PRINT(("%d\n", test_report.failed)); PRINT(("%d\n", test_report.warnings)); PRINT(("%s\n", tr_Eval())); PRINT(("\n")); PRINT(("\n")); PRINT(("\n")); #else PRINT(("\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\n", test_report.tests, test_report.executed, test_report.passed, test_report.failed, test_report.warnings)); PRINT(("Test Result: %s\n", tr_Eval())); #endif FLUSH(); return (__TRUE); } /*----------------------------------------------------------------------------- * Assertion result counter *----------------------------------------------------------------------------*/ static BOOL As_File_Result (TC_RES res) { return (StatCount (res)); } /*----------------------------------------------------------------------------- * Set debug information state *----------------------------------------------------------------------------*/ #if (PRINT_XML_REPORT==1) static BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) { PRINT(("\n")); if (desc!=NULL) PRINT(("%s\n", desc)); PRINT(("%s\n", fn)); PRINT(("%d\n", ln)); PRINT(("\n")); #else static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) { PRINT(("\n %s (%d)", fn, ln)); if (res==WARNING){ PRINT((" [WARNING]")); } if (res==FAILED) { PRINT((" [FAILED]")); } if (desc!=NULL) { PRINT((" %s", desc)); } #endif return (__TRUE); } /*----------------------------------------------------------------------------- * Init test report *----------------------------------------------------------------------------*/ static BOOL tr_Init (void) { TAS->passed = 0; TAS->failed = 0; TAS->warnings = 0; return (__TRUE); } /*----------------------------------------------------------------------------- * Init test case *----------------------------------------------------------------------------*/ static BOOL tc_Init (void) { CAS->passed = 0; CAS->failed = 0; CAS->warnings = 0; return (__TRUE); } /*----------------------------------------------------------------------------- * Evaluate test report results *----------------------------------------------------------------------------*/ static uint8_t *tr_Eval (void) { if (test_report.failed > 0U) { /* Test fails if any test case failed */ return (Failed); } else if (test_report.warnings > 0U) { /* Test warns if any test case warnings */ return (Warning); } else if (test_report.passed > 0U) { /* Test passes if at least one test case passed */ return (Passed); } else { /* No test cases were executed */ return (NotExe); } } /*----------------------------------------------------------------------------- * Evaluate test case results *----------------------------------------------------------------------------*/ static uint8_t *tc_Eval (void) { test_report.tests++; test_report.executed++; if (CAS->failed > 0U) { /* Test case fails if any failed assertion recorded */ test_report.failed++; return Failed; } else if (CAS->warnings > 0U) { /* Test case warns if any warnings assertion recorded */ test_report.warnings++; return Warning; } else if (CAS->passed > 0U) { /* Test case passes if at least one assertion passed */ test_report.passed++; return Passed; } else { /* Assert was not invoked - nothing to evaluate */ test_report.executed--; return NotExe; } } /*----------------------------------------------------------------------------- * Statistics result counter *----------------------------------------------------------------------------*/ static BOOL StatCount (TC_RES res) { switch (res) { case PASSED: CAS->passed++; TAS->passed++; break; case WARNING: CAS->warnings++; TAS->warnings++; break; case FAILED: CAS->failed++; TAS->failed++; break; case NOT_EXECUTED: return (__FALSE); default: break; } return (__TRUE); } /*----------------------------------------------------------------------------- * Set result *----------------------------------------------------------------------------*/ TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) { // save assertion result switch (res) { case PASSED: if (TAS->passed < BUFFER_ASSERTIONS) { test_report.assertions.info.passed[TAS->passed].module = fn; test_report.assertions.info.passed[TAS->passed].line = ln; } break; case FAILED: if (TAS->failed < BUFFER_ASSERTIONS) { test_report.assertions.info.failed[TAS->failed].module = fn; test_report.assertions.info.failed[TAS->failed].line = ln; } break; case WARNING: if (TAS->warnings < BUFFER_ASSERTIONS) { test_report.assertions.info.warnings[TAS->warnings].module = fn; test_report.assertions.info.warnings[TAS->warnings].line = ln; } break; case NOT_EXECUTED: break; default: break; } // set debug info (if the test case didn't pass) if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); } // set result (void)tcitf.Result (res); return (res); } /*----------------------------------------------------------------------------- * Assert true *----------------------------------------------------------------------------*/ TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) { TC_RES res = FAILED; if (cond != 0U) { res = PASSED; } (void)__set_result(fn, ln, res, NULL); return (res); } #ifndef DISABLE_SEMIHOSTING /*----------------------------------------------------------------------------- * MsgFlush: Flush the standard output *----------------------------------------------------------------------------*/ static void MsgFlush(void) { (void)fflush(stdout); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wformat-nonliteral" #endif /*----------------------------------------------------------------------------- * MsgPrint: Print a message to the standard output *----------------------------------------------------------------------------*/ static void MsgPrint (const char *msg, ...) { va_list args; va_start(args, msg); vprintf(msg, args); va_end(args); } #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif #endif // DISABLE_SEMIHOSTING /*----------------------------------------------------------------------------- * End of file *----------------------------------------------------------------------------*/ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Config.h * Purpose: CV Config header *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __CV_CONFIG_H #define __CV_CONFIG_H #include "RTE_Components.h" #include CMSIS_device_header #define RTE_CV_COREINSTR 1 #define RTE_CV_COREFUNC 1 #define RTE_CV_CORESIMD 1 #define RTE_CV_MPUFUNC (__MPU_PRESENT) #if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT #define RTE_CV_L1CACHE (__ICACHE_PRESENT || __DCACHE_PRESENT) #endif //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // Common Test Settings // Print Output Format <0=> Plain Text <1=> XML // Set the test results output format to plain text or XML #ifndef PRINT_XML_REPORT #define PRINT_XML_REPORT 1 #endif // Buffer size for assertions results // Set the buffer size for assertions results buffer #define BUFFER_ASSERTIONS 128U // // Disable Test Cases // Uncheck to disable an individual test case // TC_CoreInstr_NOP #define TC_COREINSTR_NOP_EN 1 // TC_CoreInstr_SEV #define TC_COREINSTR_SEV_EN 1 // TC_CoreInstr_BKPT #define TC_COREINSTR_BKPT_EN 1 // TC_CoreInstr_ISB #define TC_COREINSTR_ISB_EN 1 // TC_CoreInstr_DSB #define TC_COREINSTR_DSB_EN 1 // TC_CoreInstr_DMB #define TC_COREINSTR_DMB_EN 1 // TC_CoreInstr_WFI #define TC_COREINSTR_WFI_EN 0 // TC_CoreInstr_WFE #define TC_COREINSTR_WFE_EN 0 // TC_CoreInstr_REV #define TC_COREINSTR_REV_EN 1 // TC_CoreInstr_REV16 #define TC_COREINSTR_REV16_EN 1 // TC_CoreInstr_REVSH #define TC_COREINSTR_REVSH_EN 1 // TC_CoreInstr_ROR #define TC_COREINSTR_ROR_EN 1 // TC_CoreInstr_RBIT #define TC_COREINSTR_RBIT_EN 1 // TC_CoreInstr_CLZ #define TC_COREINSTR_CLZ_EN 1 // TC_CoreInstr_SSAT #define TC_COREINSTR_SSAT_EN 1 // TC_CoreInstr_USAT #define TC_COREINSTR_USAT_EN 1 // TC_CoreInstr_RRX #define TC_COREINSTR_RRX_EN 1 // TC_CoreInstr_LoadStoreExlusive #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1 // TC_CoreInstr_LoadStoreUnpriv #define TC_COREINSTR_LOADSTOREUNPRIV_EN 1 // TC_CoreInstr_LoadStoreAcquire #define TC_COREINSTR_LOADSTOREACQUIRE_EN 1 // TC_CoreInstr_LoadStoreAcquireExclusive #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1 // TC_CoreInstr_UnalignedUint16 #define TC_COREINSTR_UNALIGNEDUINT16_EN 1 // TC_CoreInstr_UnalignedUint32 #define TC_COREINSTR_UNALIGNEDUINT32_EN 1 // TC_CoreSimd_SatAddSub #define TC_CORESIMD_SATADDSUB_EN 1 // TC_CoreSimd_ParSat16 #define TC_CORESIMD_PARSAT16_EN 1 // TC_CoreSimd_PackUnpack #define TC_CORESIMD_PACKUNPACK_EN 1 // TC_CoreSimd_ParSel #define TC_CORESIMD_PARSEL_EN 1 // TC_CoreSimd_ParAddSub8 #define TC_CORESIMD_PARADDSUB8_EN 1 // TC_CoreSimd_AbsDif8 #define TC_CORESIMD_ABSDIF8_EN 1 // TC_CoreSimd_ParAddSub16 #define TC_CORESIMD_PARADDSUB16_EN 1 // TC_CoreSimd_ParMul16 #define TC_CORESIMD_PARMUL16_EN 1 // TC_CoreSimd_Pack16 #define TC_CORESIMD_PACK16_EN 1 // TC_CoreSimd_MulAcc32 #define TC_CORESIMD_MULACC32_EN 1 // TC_CoreFunc_EnDisIRQ #define TC_COREFUNC_ENDISIRQ_EN 1 // TC_CoreFunc_IRQPrio #define TC_COREFUNC_IRQPRIO_EN 1 // TC_CoreFunc_EncDecIRQPrio #define TC_COREFUNC_ENCDECIRQPRIO_EN 1 // TC_CoreFunc_IRQVect #define TC_COREFUNC_IRQVECT_EN 1 // TC_CoreFunc_Control #define TC_COREFUNC_CONTROL_EN 1 // TC_CoreFunc_IPSR #define TC_COREFUNC_IPSR_EN 1 // TC_CoreFunc_APSR #define TC_COREFUNC_APSR_EN 1 // TC_CoreFunc_PSP #define TC_COREFUNC_PSP_EN 1 // TC_CoreFunc_MSP #define TC_COREFUNC_MSP_EN 1 // TC_CoreFunc_PSPLIM #define TC_COREFUNC_PSPLIM_EN 1 // TC_CoreFunc_PSPLIM_NS #define TC_COREFUNC_PSPLIM_NS_EN 1 // TC_CoreFunc_MSPLIM #define TC_COREFUNC_MSPLIM_EN 1 // TC_CoreFunc_MSPLIM_NS #define TC_COREFUNC_MSPLIM_NS_EN 1 // TC_CoreFunc_PRIMASK #define TC_COREFUNC_PRIMASK_EN 1 // TC_CoreFunc_FAULTMASK #define TC_COREFUNC_FAULTMASK_EN 1 // TC_CoreFunc_BASEPRI #define TC_COREFUNC_BASEPRI_EN 1 // TC_CoreFunc_FPUType #define TC_COREFUNC_FPUTYPE_EN 1 // TC_CoreFunc_FPSCR #define TC_COREFUNC_FPSCR_EN 1 // TC_MPU_SetClear #define TC_MPU_SETCLEAR_EN 1 // TC_MPU_Load #define TC_MPU_LOAD_EN 1 // TC_CML1Cache_EnDisableICache #define TC_CML1CACHE_ENDISABLE_ICACHE 1 // TC_CML1Cache_EnDisableDCache #define TC_CML1CACHE_ENDISABLE_DCACHE 1 // TC_CML1Cache_CleanDCacheByAddrWhileDisabled #define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1 // #endif /* __CV_CONFIG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config_template.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Config.h * Purpose: CV Config header *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __CV_CONFIG_H #define __CV_CONFIG_H #include "RTE_Components.h" #include CMSIS_device_header //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // Common Test Settings // Print Output Format <0=> Plain Text <1=> XML // Set the test results output format to plain text or XML #ifndef PRINT_XML_REPORT #define PRINT_XML_REPORT 1 #endif // Buffer size for assertions results // Set the buffer size for assertions results buffer #define BUFFER_ASSERTIONS 128U // // Disable Test Cases // Uncheck to disable an individual test case // TC_CoreInstr_NOP #define TC_COREINSTR_NOP_EN 1 // TC_CoreInstr_SEV #define TC_COREINSTR_SEV_EN 1 // TC_CoreInstr_BKPT #define TC_COREINSTR_BKPT_EN 1 // TC_CoreInstr_ISB #define TC_COREINSTR_ISB_EN 1 // TC_CoreInstr_DSB #define TC_COREINSTR_DSB_EN 1 // TC_CoreInstr_DMB #define TC_COREINSTR_DMB_EN 1 // TC_CoreInstr_WFI #define TC_COREINSTR_WFI_EN 0 // TC_CoreInstr_WFE #define TC_COREINSTR_WFE_EN 0 // TC_CoreInstr_REV #define TC_COREINSTR_REV_EN 1 // TC_CoreInstr_REV16 #define TC_COREINSTR_REV16_EN 1 // TC_CoreInstr_REVSH #define TC_COREINSTR_REVSH_EN 1 // TC_CoreInstr_ROR #define TC_COREINSTR_ROR_EN 1 // TC_CoreInstr_RBIT #define TC_COREINSTR_RBIT_EN 1 // TC_CoreInstr_CLZ #define TC_COREINSTR_CLZ_EN 1 // TC_CoreInstr_SSAT #define TC_COREINSTR_SSAT_EN 1 // TC_CoreInstr_USAT #define TC_COREINSTR_USAT_EN 1 // TC_CoreInstr_RRX #define TC_COREINSTR_RRX_EN 1 // TC_CoreInstr_LoadStoreExlusive #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1 // TC_CoreInstr_LoadStoreUnpriv #define TC_COREINSTR_LOADSTOREUNPRIV_EN 1 // TC_CoreInstr_LoadStoreAcquire #define TC_COREINSTR_LOADSTOREACQUIRE_EN 1 // TC_CoreInstr_LoadStoreAcquireExclusive #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1 // TC_CoreSimd_SatAddSub #define TC_CORESIMD_SATADDSUB_EN 1 // TC_CoreSimd_ParSat16 #define TC_CORESIMD_PARSAT16_EN 1 // TC_CoreSimd_PackUnpack #define TC_CORESIMD_PACKUNPACK_EN 1 // TC_CoreSimd_ParSel #define TC_CORESIMD_PARSEL_EN 1 // TC_CoreSimd_ParAddSub8 #define TC_CORESIMD_PARADDSUB8_EN 1 // TC_CoreSimd_AbsDif8 #define TC_CORESIMD_ABSDIF8_EN 1 // TC_CoreSimd_ParAddSub16 #define TC_CORESIMD_PARADDSUB16_EN 1 // TC_CoreSimd_ParMul16 #define TC_CORESIMD_PARMUL16_EN 1 // TC_CoreSimd_Pack16 #define TC_CORESIMD_PACK16_EN 1 // TC_CoreSimd_MulAcc32 #define TC_CORESIMD_MULACC32_EN 1 // TC_CoreFunc_EnDisIRQ #define TC_COREFUNC_ENDISIRQ_EN 1 // TC_CoreFunc_IRQPrio #define TC_COREFUNC_IRQPRIO_EN 1 // TC_CoreFunc_EncDecIRQPrio #define TC_COREFUNC_ENCDECIRQPRIO_EN 1 // TC_CoreFunc_IRQVect #define TC_COREFUNC_IRQVECT_EN 1 // TC_CoreFunc_Control #define TC_COREFUNC_CONTROL_EN 1 // TC_CoreFunc_IPSR #define TC_COREFUNC_IPSR_EN 1 // TC_CoreFunc_APSR #define TC_COREFUNC_APSR_EN 1 // TC_CoreFunc_PSP #define TC_COREFUNC_PSP_EN 1 // TC_CoreFunc_MSP #define TC_COREFUNC_MSP_EN 1 // TC_CoreFunc_PSPLIM #define TC_COREFUNC_PSPLIM_EN 1 // TC_CoreFunc_PSPLIM_NS #define TC_COREFUNC_PSPLIM_NS_EN 1 // TC_CoreFunc_MSPLIM #define TC_COREFUNC_MSPLIM_EN 1 // TC_CoreFunc_MSPLIM_NS #define TC_COREFUNC_MSPLIM_NS_EN 1 // TC_CoreFunc_PRIMASK #define TC_COREFUNC_PRIMASK_EN 1 // TC_CoreFunc_FAULTMASK #define TC_COREFUNC_FAULTMASK_EN 1 // TC_CoreFunc_BASEPRI #define TC_COREFUNC_BASEPRI_EN 1 // TC_CoreFunc_FPUType #define TC_COREFUNC_FPUTYPE_EN 1 // TC_CoreFunc_FPSCR #define TC_COREFUNC_FPSCR_EN 1 // TC_MPU_SetClear #define TC_MPU_SETCLEAR_EN 1 // TC_MPU_Load #define TC_MPU_LOAD_EN 1 // TC_CML1Cache_EnDisableICache #define TC_CML1CACHE_ENDISABLE_ICACHE 1 // TC_CML1Cache_EnDisableDCache #define TC_CML1CACHE_ENDISABLE_DCACHE 1 // TC_CML1Cache_CleanDCacheByAddrWhileDisabled #define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1 // #endif /* __CV_CONFIG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM23.h ================================================ /**************************************************************************//** * @file partition_ARMCM23.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 * @version V5.3.1 * @date 09. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM23_H #define PARTITION_ARMCM23_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of single SysTick */ #define SCB_ICSR_INIT 0 /* // in a single SysTick implementation, SysTick is // <0=>Secure // <1=>Non-Secure // Value for SCB->ICSR register bit STTNS // only for single SysTick implementation */ #define SCB_ICSR_STTNS_VAL 0 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM23_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h ================================================ /**************************************************************************//** * @file partition_ARMCM33.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 * @version V5.3.1 * @date 09. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM33_H #define PARTITION_ARMCM33_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM33_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h ================================================ /**************************************************************************//** * @file partition_ARMCM35P.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P * @version V5.4.1 * @date 03. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM35P_H #define PARTITION_ARMCM35P_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point Unit */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM35P_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM55.h ================================================ /**************************************************************************//** * @file partition_ARMCM55.h * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline * @version V1.0.0 * @date 20. March 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef PARTITION_ARMCM55_H #define PARTITION_ARMCM55_H /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ /* // Initialize Security Attribution Unit (SAU) CTRL register */ #define SAU_INIT_CTRL 1 /* // Enable SAU // Value for SAU->CTRL register bit ENABLE */ #define SAU_INIT_CTRL_ENABLE 1 /* // When SAU is disabled // <0=> All Memory is Secure // <1=> All Memory is Non-Secure // Value for SAU->CTRL register bit ALLNS // When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. */ #define SAU_INIT_CTRL_ALLNS 0 /* // */ /* // Initialize Security Attribution Unit (SAU) Address Regions // SAU configuration specifies regions to be one of: // - Secure and Non-Secure Callable // - Non-Secure // Note: All memory regions not configured by SAU are Secure */ #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ /* // Initialize SAU Region 0 // Setup SAU Region 0 memory attributes */ #define SAU_INIT_REGION0 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC0 1 /* // */ /* // Initialize SAU Region 1 // Setup SAU Region 1 memory attributes */ #define SAU_INIT_REGION1 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START1 0x00200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END1 0x003FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC1 0 /* // */ /* // Initialize SAU Region 2 // Setup SAU Region 2 memory attributes */ #define SAU_INIT_REGION2 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START2 0x20200000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END2 0x203FFFFF /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC2 0 /* // */ /* // Initialize SAU Region 3 // Setup SAU Region 3 memory attributes */ #define SAU_INIT_REGION3 1 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START3 0x40000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END3 0x40040000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC3 0 /* // */ /* // Initialize SAU Region 4 // Setup SAU Region 4 memory attributes */ #define SAU_INIT_REGION4 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC4 0 /* // */ /* // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ #define SAU_INIT_REGION5 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START5 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END5 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC5 0 /* // */ /* // Initialize SAU Region 6 // Setup SAU Region 6 memory attributes */ #define SAU_INIT_REGION6 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START6 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END6 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC6 0 /* // */ /* // Initialize SAU Region 7 // Setup SAU Region 7 memory attributes */ #define SAU_INIT_REGION7 0 /* // Start Address <0-0xFFFFFFE0> */ #define SAU_INIT_START7 0x00000000 /* // End Address <0x1F-0xFFFFFFFF> */ #define SAU_INIT_END7 0x00000000 /* // Region is // <0=>Non-Secure // <1=>Secure, Non-Secure Callable */ #define SAU_INIT_NSC7 0 /* // */ /* // */ /* // Setup behaviour of Sleep and Exception Handling */ #define SCB_CSR_AIRCR_INIT 1 /* // Deep Sleep can be enabled by // <0=>Secure and Non-Secure state // <1=>Secure state only // Value for SCB->CSR register bit DEEPSLEEPS */ #define SCB_CSR_DEEPSLEEPS_VAL 1 /* // System reset request accessible from // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for SCB->AIRCR register bit SYSRESETREQS */ #define SCB_AIRCR_SYSRESETREQS_VAL 1 /* // Priority of Non-Secure exceptions is // <0=> Not altered // <1=> Lowered to 0x80-0xFF // Value for SCB->AIRCR register bit PRIS */ #define SCB_AIRCR_PRIS_VAL 1 /* // BusFault, HardFault, and NMI target // <0=> Secure state // <1=> Non-Secure state // Value for SCB->AIRCR register bit BFHFNMINS */ #define SCB_AIRCR_BFHFNMINS_VAL 0 /* // */ /* // Setup behaviour of Floating Point and Vector Unit (FPU/MVE) */ #define TZ_FPU_NS_USAGE 1 /* // Floating Point and Vector Unit usage // <0=> Secure state only // <3=> Secure and Non-Secure state // Value for SCB->NSACR register bits CP10, CP11 */ #define SCB_NSACR_CP10_11_VAL 3 /* // Treat floating-point registers as Secure // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit TS */ #define FPU_FPCCR_TS_VAL 0 /* // Clear on return (CLRONRET) accessibility // <0=> Secure and Non-Secure state // <1=> Secure state only // Value for FPU->FPCCR register bit CLRONRETS */ #define FPU_FPCCR_CLRONRETS_VAL 0 /* // Clear floating-point caller saved registers on exception return // <0=> Disabled // <1=> Enabled // Value for FPU->FPCCR register bit CLRONRET */ #define FPU_FPCCR_CLRONRET_VAL 1 /* // */ /* // Setup Interrupt Target */ /* // Initialize ITNS 0 (Interrupts 0..31) */ #define NVIC_INIT_ITNS0 1 /* // Interrupts 0..31 // Interrupt 0 <0=> Secure state <1=> Non-Secure state // Interrupt 1 <0=> Secure state <1=> Non-Secure state // Interrupt 2 <0=> Secure state <1=> Non-Secure state // Interrupt 3 <0=> Secure state <1=> Non-Secure state // Interrupt 4 <0=> Secure state <1=> Non-Secure state // Interrupt 5 <0=> Secure state <1=> Non-Secure state // Interrupt 6 <0=> Secure state <1=> Non-Secure state // Interrupt 7 <0=> Secure state <1=> Non-Secure state // Interrupt 8 <0=> Secure state <1=> Non-Secure state // Interrupt 9 <0=> Secure state <1=> Non-Secure state // Interrupt 10 <0=> Secure state <1=> Non-Secure state // Interrupt 11 <0=> Secure state <1=> Non-Secure state // Interrupt 12 <0=> Secure state <1=> Non-Secure state // Interrupt 13 <0=> Secure state <1=> Non-Secure state // Interrupt 14 <0=> Secure state <1=> Non-Secure state // Interrupt 15 <0=> Secure state <1=> Non-Secure state // Interrupt 16 <0=> Secure state <1=> Non-Secure state // Interrupt 17 <0=> Secure state <1=> Non-Secure state // Interrupt 18 <0=> Secure state <1=> Non-Secure state // Interrupt 19 <0=> Secure state <1=> Non-Secure state // Interrupt 20 <0=> Secure state <1=> Non-Secure state // Interrupt 21 <0=> Secure state <1=> Non-Secure state // Interrupt 22 <0=> Secure state <1=> Non-Secure state // Interrupt 23 <0=> Secure state <1=> Non-Secure state // Interrupt 24 <0=> Secure state <1=> Non-Secure state // Interrupt 25 <0=> Secure state <1=> Non-Secure state // Interrupt 26 <0=> Secure state <1=> Non-Secure state // Interrupt 27 <0=> Secure state <1=> Non-Secure state // Interrupt 28 <0=> Secure state <1=> Non-Secure state // Interrupt 29 <0=> Secure state <1=> Non-Secure state // Interrupt 30 <0=> Secure state <1=> Non-Secure state // Interrupt 31 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS0_VAL 0x00000000 /* // */ /* // Initialize ITNS 1 (Interrupts 32..63) */ #define NVIC_INIT_ITNS1 1 /* // Interrupts 32..63 // Interrupt 32 <0=> Secure state <1=> Non-Secure state // Interrupt 33 <0=> Secure state <1=> Non-Secure state // Interrupt 34 <0=> Secure state <1=> Non-Secure state // Interrupt 35 <0=> Secure state <1=> Non-Secure state // Interrupt 36 <0=> Secure state <1=> Non-Secure state // Interrupt 37 <0=> Secure state <1=> Non-Secure state // Interrupt 38 <0=> Secure state <1=> Non-Secure state // Interrupt 39 <0=> Secure state <1=> Non-Secure state // Interrupt 40 <0=> Secure state <1=> Non-Secure state // Interrupt 41 <0=> Secure state <1=> Non-Secure state // Interrupt 42 <0=> Secure state <1=> Non-Secure state // Interrupt 43 <0=> Secure state <1=> Non-Secure state // Interrupt 44 <0=> Secure state <1=> Non-Secure state // Interrupt 45 <0=> Secure state <1=> Non-Secure state // Interrupt 46 <0=> Secure state <1=> Non-Secure state // Interrupt 47 <0=> Secure state <1=> Non-Secure state // Interrupt 48 <0=> Secure state <1=> Non-Secure state // Interrupt 49 <0=> Secure state <1=> Non-Secure state // Interrupt 50 <0=> Secure state <1=> Non-Secure state // Interrupt 51 <0=> Secure state <1=> Non-Secure state // Interrupt 52 <0=> Secure state <1=> Non-Secure state // Interrupt 53 <0=> Secure state <1=> Non-Secure state // Interrupt 54 <0=> Secure state <1=> Non-Secure state // Interrupt 55 <0=> Secure state <1=> Non-Secure state // Interrupt 56 <0=> Secure state <1=> Non-Secure state // Interrupt 57 <0=> Secure state <1=> Non-Secure state // Interrupt 58 <0=> Secure state <1=> Non-Secure state // Interrupt 59 <0=> Secure state <1=> Non-Secure state // Interrupt 60 <0=> Secure state <1=> Non-Secure state // Interrupt 61 <0=> Secure state <1=> Non-Secure state // Interrupt 62 <0=> Secure state <1=> Non-Secure state // Interrupt 63 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS1_VAL 0x00000000 /* // */ /* // Initialize ITNS 2 (Interrupts 64..95) */ #define NVIC_INIT_ITNS2 0 /* // Interrupts 64..95 // Interrupt 64 <0=> Secure state <1=> Non-Secure state // Interrupt 65 <0=> Secure state <1=> Non-Secure state // Interrupt 66 <0=> Secure state <1=> Non-Secure state // Interrupt 67 <0=> Secure state <1=> Non-Secure state // Interrupt 68 <0=> Secure state <1=> Non-Secure state // Interrupt 69 <0=> Secure state <1=> Non-Secure state // Interrupt 70 <0=> Secure state <1=> Non-Secure state // Interrupt 71 <0=> Secure state <1=> Non-Secure state // Interrupt 72 <0=> Secure state <1=> Non-Secure state // Interrupt 73 <0=> Secure state <1=> Non-Secure state // Interrupt 74 <0=> Secure state <1=> Non-Secure state // Interrupt 75 <0=> Secure state <1=> Non-Secure state // Interrupt 76 <0=> Secure state <1=> Non-Secure state // Interrupt 77 <0=> Secure state <1=> Non-Secure state // Interrupt 78 <0=> Secure state <1=> Non-Secure state // Interrupt 79 <0=> Secure state <1=> Non-Secure state // Interrupt 80 <0=> Secure state <1=> Non-Secure state // Interrupt 81 <0=> Secure state <1=> Non-Secure state // Interrupt 82 <0=> Secure state <1=> Non-Secure state // Interrupt 83 <0=> Secure state <1=> Non-Secure state // Interrupt 84 <0=> Secure state <1=> Non-Secure state // Interrupt 85 <0=> Secure state <1=> Non-Secure state // Interrupt 86 <0=> Secure state <1=> Non-Secure state // Interrupt 87 <0=> Secure state <1=> Non-Secure state // Interrupt 88 <0=> Secure state <1=> Non-Secure state // Interrupt 89 <0=> Secure state <1=> Non-Secure state // Interrupt 90 <0=> Secure state <1=> Non-Secure state // Interrupt 91 <0=> Secure state <1=> Non-Secure state // Interrupt 92 <0=> Secure state <1=> Non-Secure state // Interrupt 93 <0=> Secure state <1=> Non-Secure state // Interrupt 94 <0=> Secure state <1=> Non-Secure state // Interrupt 95 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS2_VAL 0x00000000 /* // */ /* // Initialize ITNS 3 (Interrupts 96..127) */ #define NVIC_INIT_ITNS3 0 /* // Interrupts 96..127 // Interrupt 96 <0=> Secure state <1=> Non-Secure state // Interrupt 97 <0=> Secure state <1=> Non-Secure state // Interrupt 98 <0=> Secure state <1=> Non-Secure state // Interrupt 99 <0=> Secure state <1=> Non-Secure state // Interrupt 100 <0=> Secure state <1=> Non-Secure state // Interrupt 101 <0=> Secure state <1=> Non-Secure state // Interrupt 102 <0=> Secure state <1=> Non-Secure state // Interrupt 103 <0=> Secure state <1=> Non-Secure state // Interrupt 104 <0=> Secure state <1=> Non-Secure state // Interrupt 105 <0=> Secure state <1=> Non-Secure state // Interrupt 106 <0=> Secure state <1=> Non-Secure state // Interrupt 107 <0=> Secure state <1=> Non-Secure state // Interrupt 108 <0=> Secure state <1=> Non-Secure state // Interrupt 109 <0=> Secure state <1=> Non-Secure state // Interrupt 110 <0=> Secure state <1=> Non-Secure state // Interrupt 111 <0=> Secure state <1=> Non-Secure state // Interrupt 112 <0=> Secure state <1=> Non-Secure state // Interrupt 113 <0=> Secure state <1=> Non-Secure state // Interrupt 114 <0=> Secure state <1=> Non-Secure state // Interrupt 115 <0=> Secure state <1=> Non-Secure state // Interrupt 116 <0=> Secure state <1=> Non-Secure state // Interrupt 117 <0=> Secure state <1=> Non-Secure state // Interrupt 118 <0=> Secure state <1=> Non-Secure state // Interrupt 119 <0=> Secure state <1=> Non-Secure state // Interrupt 120 <0=> Secure state <1=> Non-Secure state // Interrupt 121 <0=> Secure state <1=> Non-Secure state // Interrupt 122 <0=> Secure state <1=> Non-Secure state // Interrupt 123 <0=> Secure state <1=> Non-Secure state // Interrupt 124 <0=> Secure state <1=> Non-Secure state // Interrupt 125 <0=> Secure state <1=> Non-Secure state // Interrupt 126 <0=> Secure state <1=> Non-Secure state // Interrupt 127 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS3_VAL 0x00000000 /* // */ /* // Initialize ITNS 4 (Interrupts 128..159) */ #define NVIC_INIT_ITNS4 0 /* // Interrupts 128..159 // Interrupt 128 <0=> Secure state <1=> Non-Secure state // Interrupt 129 <0=> Secure state <1=> Non-Secure state // Interrupt 130 <0=> Secure state <1=> Non-Secure state // Interrupt 131 <0=> Secure state <1=> Non-Secure state // Interrupt 132 <0=> Secure state <1=> Non-Secure state // Interrupt 133 <0=> Secure state <1=> Non-Secure state // Interrupt 134 <0=> Secure state <1=> Non-Secure state // Interrupt 135 <0=> Secure state <1=> Non-Secure state // Interrupt 136 <0=> Secure state <1=> Non-Secure state // Interrupt 137 <0=> Secure state <1=> Non-Secure state // Interrupt 138 <0=> Secure state <1=> Non-Secure state // Interrupt 139 <0=> Secure state <1=> Non-Secure state // Interrupt 140 <0=> Secure state <1=> Non-Secure state // Interrupt 141 <0=> Secure state <1=> Non-Secure state // Interrupt 142 <0=> Secure state <1=> Non-Secure state // Interrupt 143 <0=> Secure state <1=> Non-Secure state // Interrupt 144 <0=> Secure state <1=> Non-Secure state // Interrupt 145 <0=> Secure state <1=> Non-Secure state // Interrupt 146 <0=> Secure state <1=> Non-Secure state // Interrupt 147 <0=> Secure state <1=> Non-Secure state // Interrupt 148 <0=> Secure state <1=> Non-Secure state // Interrupt 149 <0=> Secure state <1=> Non-Secure state // Interrupt 150 <0=> Secure state <1=> Non-Secure state // Interrupt 151 <0=> Secure state <1=> Non-Secure state // Interrupt 152 <0=> Secure state <1=> Non-Secure state // Interrupt 153 <0=> Secure state <1=> Non-Secure state // Interrupt 154 <0=> Secure state <1=> Non-Secure state // Interrupt 155 <0=> Secure state <1=> Non-Secure state // Interrupt 156 <0=> Secure state <1=> Non-Secure state // Interrupt 157 <0=> Secure state <1=> Non-Secure state // Interrupt 158 <0=> Secure state <1=> Non-Secure state // Interrupt 159 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS4_VAL 0x00000000 /* // */ /* // Initialize ITNS 5 (Interrupts 160..191) */ #define NVIC_INIT_ITNS5 0 /* // Interrupts 160..191 // Interrupt 160 <0=> Secure state <1=> Non-Secure state // Interrupt 161 <0=> Secure state <1=> Non-Secure state // Interrupt 162 <0=> Secure state <1=> Non-Secure state // Interrupt 163 <0=> Secure state <1=> Non-Secure state // Interrupt 164 <0=> Secure state <1=> Non-Secure state // Interrupt 165 <0=> Secure state <1=> Non-Secure state // Interrupt 166 <0=> Secure state <1=> Non-Secure state // Interrupt 167 <0=> Secure state <1=> Non-Secure state // Interrupt 168 <0=> Secure state <1=> Non-Secure state // Interrupt 169 <0=> Secure state <1=> Non-Secure state // Interrupt 170 <0=> Secure state <1=> Non-Secure state // Interrupt 171 <0=> Secure state <1=> Non-Secure state // Interrupt 172 <0=> Secure state <1=> Non-Secure state // Interrupt 173 <0=> Secure state <1=> Non-Secure state // Interrupt 174 <0=> Secure state <1=> Non-Secure state // Interrupt 175 <0=> Secure state <1=> Non-Secure state // Interrupt 176 <0=> Secure state <1=> Non-Secure state // Interrupt 177 <0=> Secure state <1=> Non-Secure state // Interrupt 178 <0=> Secure state <1=> Non-Secure state // Interrupt 179 <0=> Secure state <1=> Non-Secure state // Interrupt 180 <0=> Secure state <1=> Non-Secure state // Interrupt 181 <0=> Secure state <1=> Non-Secure state // Interrupt 182 <0=> Secure state <1=> Non-Secure state // Interrupt 183 <0=> Secure state <1=> Non-Secure state // Interrupt 184 <0=> Secure state <1=> Non-Secure state // Interrupt 185 <0=> Secure state <1=> Non-Secure state // Interrupt 186 <0=> Secure state <1=> Non-Secure state // Interrupt 187 <0=> Secure state <1=> Non-Secure state // Interrupt 188 <0=> Secure state <1=> Non-Secure state // Interrupt 189 <0=> Secure state <1=> Non-Secure state // Interrupt 190 <0=> Secure state <1=> Non-Secure state // Interrupt 191 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS5_VAL 0x00000000 /* // */ /* // Initialize ITNS 6 (Interrupts 192..223) */ #define NVIC_INIT_ITNS6 0 /* // Interrupts 192..223 // Interrupt 192 <0=> Secure state <1=> Non-Secure state // Interrupt 193 <0=> Secure state <1=> Non-Secure state // Interrupt 194 <0=> Secure state <1=> Non-Secure state // Interrupt 195 <0=> Secure state <1=> Non-Secure state // Interrupt 196 <0=> Secure state <1=> Non-Secure state // Interrupt 197 <0=> Secure state <1=> Non-Secure state // Interrupt 198 <0=> Secure state <1=> Non-Secure state // Interrupt 199 <0=> Secure state <1=> Non-Secure state // Interrupt 200 <0=> Secure state <1=> Non-Secure state // Interrupt 201 <0=> Secure state <1=> Non-Secure state // Interrupt 202 <0=> Secure state <1=> Non-Secure state // Interrupt 203 <0=> Secure state <1=> Non-Secure state // Interrupt 204 <0=> Secure state <1=> Non-Secure state // Interrupt 205 <0=> Secure state <1=> Non-Secure state // Interrupt 206 <0=> Secure state <1=> Non-Secure state // Interrupt 207 <0=> Secure state <1=> Non-Secure state // Interrupt 208 <0=> Secure state <1=> Non-Secure state // Interrupt 209 <0=> Secure state <1=> Non-Secure state // Interrupt 210 <0=> Secure state <1=> Non-Secure state // Interrupt 211 <0=> Secure state <1=> Non-Secure state // Interrupt 212 <0=> Secure state <1=> Non-Secure state // Interrupt 213 <0=> Secure state <1=> Non-Secure state // Interrupt 214 <0=> Secure state <1=> Non-Secure state // Interrupt 215 <0=> Secure state <1=> Non-Secure state // Interrupt 216 <0=> Secure state <1=> Non-Secure state // Interrupt 217 <0=> Secure state <1=> Non-Secure state // Interrupt 218 <0=> Secure state <1=> Non-Secure state // Interrupt 219 <0=> Secure state <1=> Non-Secure state // Interrupt 220 <0=> Secure state <1=> Non-Secure state // Interrupt 221 <0=> Secure state <1=> Non-Secure state // Interrupt 222 <0=> Secure state <1=> Non-Secure state // Interrupt 223 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS6_VAL 0x00000000 /* // */ /* // Initialize ITNS 7 (Interrupts 224..255) */ #define NVIC_INIT_ITNS7 0 /* // Interrupts 224..255 // Interrupt 224 <0=> Secure state <1=> Non-Secure state // Interrupt 225 <0=> Secure state <1=> Non-Secure state // Interrupt 226 <0=> Secure state <1=> Non-Secure state // Interrupt 227 <0=> Secure state <1=> Non-Secure state // Interrupt 228 <0=> Secure state <1=> Non-Secure state // Interrupt 229 <0=> Secure state <1=> Non-Secure state // Interrupt 230 <0=> Secure state <1=> Non-Secure state // Interrupt 231 <0=> Secure state <1=> Non-Secure state // Interrupt 232 <0=> Secure state <1=> Non-Secure state // Interrupt 233 <0=> Secure state <1=> Non-Secure state // Interrupt 234 <0=> Secure state <1=> Non-Secure state // Interrupt 235 <0=> Secure state <1=> Non-Secure state // Interrupt 236 <0=> Secure state <1=> Non-Secure state // Interrupt 237 <0=> Secure state <1=> Non-Secure state // Interrupt 238 <0=> Secure state <1=> Non-Secure state // Interrupt 239 <0=> Secure state <1=> Non-Secure state // Interrupt 240 <0=> Secure state <1=> Non-Secure state // Interrupt 241 <0=> Secure state <1=> Non-Secure state // Interrupt 242 <0=> Secure state <1=> Non-Secure state // Interrupt 243 <0=> Secure state <1=> Non-Secure state // Interrupt 244 <0=> Secure state <1=> Non-Secure state // Interrupt 245 <0=> Secure state <1=> Non-Secure state // Interrupt 246 <0=> Secure state <1=> Non-Secure state // Interrupt 247 <0=> Secure state <1=> Non-Secure state // Interrupt 248 <0=> Secure state <1=> Non-Secure state // Interrupt 249 <0=> Secure state <1=> Non-Secure state // Interrupt 250 <0=> Secure state <1=> Non-Secure state // Interrupt 251 <0=> Secure state <1=> Non-Secure state // Interrupt 252 <0=> Secure state <1=> Non-Secure state // Interrupt 253 <0=> Secure state <1=> Non-Secure state // Interrupt 254 <0=> Secure state <1=> Non-Secure state // Interrupt 255 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS7_VAL 0x00000000 /* // */ /* // Initialize ITNS 8 (Interrupts 256..287) */ #define NVIC_INIT_ITNS8 0 /* // Interrupts 256..287 // Interrupt 256 <0=> Secure state <1=> Non-Secure state // Interrupt 257 <0=> Secure state <1=> Non-Secure state // Interrupt 258 <0=> Secure state <1=> Non-Secure state // Interrupt 259 <0=> Secure state <1=> Non-Secure state // Interrupt 260 <0=> Secure state <1=> Non-Secure state // Interrupt 261 <0=> Secure state <1=> Non-Secure state // Interrupt 262 <0=> Secure state <1=> Non-Secure state // Interrupt 263 <0=> Secure state <1=> Non-Secure state // Interrupt 264 <0=> Secure state <1=> Non-Secure state // Interrupt 265 <0=> Secure state <1=> Non-Secure state // Interrupt 266 <0=> Secure state <1=> Non-Secure state // Interrupt 267 <0=> Secure state <1=> Non-Secure state // Interrupt 268 <0=> Secure state <1=> Non-Secure state // Interrupt 269 <0=> Secure state <1=> Non-Secure state // Interrupt 270 <0=> Secure state <1=> Non-Secure state // Interrupt 271 <0=> Secure state <1=> Non-Secure state // Interrupt 272 <0=> Secure state <1=> Non-Secure state // Interrupt 273 <0=> Secure state <1=> Non-Secure state // Interrupt 274 <0=> Secure state <1=> Non-Secure state // Interrupt 275 <0=> Secure state <1=> Non-Secure state // Interrupt 276 <0=> Secure state <1=> Non-Secure state // Interrupt 277 <0=> Secure state <1=> Non-Secure state // Interrupt 278 <0=> Secure state <1=> Non-Secure state // Interrupt 279 <0=> Secure state <1=> Non-Secure state // Interrupt 280 <0=> Secure state <1=> Non-Secure state // Interrupt 281 <0=> Secure state <1=> Non-Secure state // Interrupt 282 <0=> Secure state <1=> Non-Secure state // Interrupt 283 <0=> Secure state <1=> Non-Secure state // Interrupt 284 <0=> Secure state <1=> Non-Secure state // Interrupt 285 <0=> Secure state <1=> Non-Secure state // Interrupt 286 <0=> Secure state <1=> Non-Secure state // Interrupt 287 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS8_VAL 0x00000000 /* // */ /* // Initialize ITNS 9 (Interrupts 288..319) */ #define NVIC_INIT_ITNS9 0 /* // Interrupts 288..319 // Interrupt 288 <0=> Secure state <1=> Non-Secure state // Interrupt 289 <0=> Secure state <1=> Non-Secure state // Interrupt 290 <0=> Secure state <1=> Non-Secure state // Interrupt 291 <0=> Secure state <1=> Non-Secure state // Interrupt 292 <0=> Secure state <1=> Non-Secure state // Interrupt 293 <0=> Secure state <1=> Non-Secure state // Interrupt 294 <0=> Secure state <1=> Non-Secure state // Interrupt 295 <0=> Secure state <1=> Non-Secure state // Interrupt 296 <0=> Secure state <1=> Non-Secure state // Interrupt 297 <0=> Secure state <1=> Non-Secure state // Interrupt 298 <0=> Secure state <1=> Non-Secure state // Interrupt 299 <0=> Secure state <1=> Non-Secure state // Interrupt 300 <0=> Secure state <1=> Non-Secure state // Interrupt 301 <0=> Secure state <1=> Non-Secure state // Interrupt 302 <0=> Secure state <1=> Non-Secure state // Interrupt 303 <0=> Secure state <1=> Non-Secure state // Interrupt 304 <0=> Secure state <1=> Non-Secure state // Interrupt 305 <0=> Secure state <1=> Non-Secure state // Interrupt 306 <0=> Secure state <1=> Non-Secure state // Interrupt 307 <0=> Secure state <1=> Non-Secure state // Interrupt 308 <0=> Secure state <1=> Non-Secure state // Interrupt 309 <0=> Secure state <1=> Non-Secure state // Interrupt 310 <0=> Secure state <1=> Non-Secure state // Interrupt 311 <0=> Secure state <1=> Non-Secure state // Interrupt 312 <0=> Secure state <1=> Non-Secure state // Interrupt 313 <0=> Secure state <1=> Non-Secure state // Interrupt 314 <0=> Secure state <1=> Non-Secure state // Interrupt 315 <0=> Secure state <1=> Non-Secure state // Interrupt 316 <0=> Secure state <1=> Non-Secure state // Interrupt 317 <0=> Secure state <1=> Non-Secure state // Interrupt 318 <0=> Secure state <1=> Non-Secure state // Interrupt 319 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS9_VAL 0x00000000 /* // */ /* // Initialize ITNS 10 (Interrupts 320..351) */ #define NVIC_INIT_ITNS10 0 /* // Interrupts 320..351 // Interrupt 320 <0=> Secure state <1=> Non-Secure state // Interrupt 321 <0=> Secure state <1=> Non-Secure state // Interrupt 322 <0=> Secure state <1=> Non-Secure state // Interrupt 323 <0=> Secure state <1=> Non-Secure state // Interrupt 324 <0=> Secure state <1=> Non-Secure state // Interrupt 325 <0=> Secure state <1=> Non-Secure state // Interrupt 326 <0=> Secure state <1=> Non-Secure state // Interrupt 327 <0=> Secure state <1=> Non-Secure state // Interrupt 328 <0=> Secure state <1=> Non-Secure state // Interrupt 329 <0=> Secure state <1=> Non-Secure state // Interrupt 330 <0=> Secure state <1=> Non-Secure state // Interrupt 331 <0=> Secure state <1=> Non-Secure state // Interrupt 332 <0=> Secure state <1=> Non-Secure state // Interrupt 333 <0=> Secure state <1=> Non-Secure state // Interrupt 334 <0=> Secure state <1=> Non-Secure state // Interrupt 335 <0=> Secure state <1=> Non-Secure state // Interrupt 336 <0=> Secure state <1=> Non-Secure state // Interrupt 337 <0=> Secure state <1=> Non-Secure state // Interrupt 338 <0=> Secure state <1=> Non-Secure state // Interrupt 339 <0=> Secure state <1=> Non-Secure state // Interrupt 340 <0=> Secure state <1=> Non-Secure state // Interrupt 341 <0=> Secure state <1=> Non-Secure state // Interrupt 342 <0=> Secure state <1=> Non-Secure state // Interrupt 343 <0=> Secure state <1=> Non-Secure state // Interrupt 344 <0=> Secure state <1=> Non-Secure state // Interrupt 345 <0=> Secure state <1=> Non-Secure state // Interrupt 346 <0=> Secure state <1=> Non-Secure state // Interrupt 347 <0=> Secure state <1=> Non-Secure state // Interrupt 348 <0=> Secure state <1=> Non-Secure state // Interrupt 349 <0=> Secure state <1=> Non-Secure state // Interrupt 350 <0=> Secure state <1=> Non-Secure state // Interrupt 351 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS10_VAL 0x00000000 /* // */ /* // Initialize ITNS 11 (Interrupts 352..383) */ #define NVIC_INIT_ITNS11 0 /* // Interrupts 352..383 // Interrupt 352 <0=> Secure state <1=> Non-Secure state // Interrupt 353 <0=> Secure state <1=> Non-Secure state // Interrupt 354 <0=> Secure state <1=> Non-Secure state // Interrupt 355 <0=> Secure state <1=> Non-Secure state // Interrupt 356 <0=> Secure state <1=> Non-Secure state // Interrupt 357 <0=> Secure state <1=> Non-Secure state // Interrupt 358 <0=> Secure state <1=> Non-Secure state // Interrupt 359 <0=> Secure state <1=> Non-Secure state // Interrupt 360 <0=> Secure state <1=> Non-Secure state // Interrupt 361 <0=> Secure state <1=> Non-Secure state // Interrupt 362 <0=> Secure state <1=> Non-Secure state // Interrupt 363 <0=> Secure state <1=> Non-Secure state // Interrupt 364 <0=> Secure state <1=> Non-Secure state // Interrupt 365 <0=> Secure state <1=> Non-Secure state // Interrupt 366 <0=> Secure state <1=> Non-Secure state // Interrupt 367 <0=> Secure state <1=> Non-Secure state // Interrupt 368 <0=> Secure state <1=> Non-Secure state // Interrupt 369 <0=> Secure state <1=> Non-Secure state // Interrupt 370 <0=> Secure state <1=> Non-Secure state // Interrupt 371 <0=> Secure state <1=> Non-Secure state // Interrupt 372 <0=> Secure state <1=> Non-Secure state // Interrupt 373 <0=> Secure state <1=> Non-Secure state // Interrupt 374 <0=> Secure state <1=> Non-Secure state // Interrupt 375 <0=> Secure state <1=> Non-Secure state // Interrupt 376 <0=> Secure state <1=> Non-Secure state // Interrupt 377 <0=> Secure state <1=> Non-Secure state // Interrupt 378 <0=> Secure state <1=> Non-Secure state // Interrupt 379 <0=> Secure state <1=> Non-Secure state // Interrupt 380 <0=> Secure state <1=> Non-Secure state // Interrupt 381 <0=> Secure state <1=> Non-Secure state // Interrupt 382 <0=> Secure state <1=> Non-Secure state // Interrupt 383 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS11_VAL 0x00000000 /* // */ /* // Initialize ITNS 12 (Interrupts 384..415) */ #define NVIC_INIT_ITNS12 0 /* // Interrupts 384..415 // Interrupt 384 <0=> Secure state <1=> Non-Secure state // Interrupt 385 <0=> Secure state <1=> Non-Secure state // Interrupt 386 <0=> Secure state <1=> Non-Secure state // Interrupt 387 <0=> Secure state <1=> Non-Secure state // Interrupt 388 <0=> Secure state <1=> Non-Secure state // Interrupt 389 <0=> Secure state <1=> Non-Secure state // Interrupt 390 <0=> Secure state <1=> Non-Secure state // Interrupt 391 <0=> Secure state <1=> Non-Secure state // Interrupt 392 <0=> Secure state <1=> Non-Secure state // Interrupt 393 <0=> Secure state <1=> Non-Secure state // Interrupt 394 <0=> Secure state <1=> Non-Secure state // Interrupt 395 <0=> Secure state <1=> Non-Secure state // Interrupt 396 <0=> Secure state <1=> Non-Secure state // Interrupt 397 <0=> Secure state <1=> Non-Secure state // Interrupt 398 <0=> Secure state <1=> Non-Secure state // Interrupt 399 <0=> Secure state <1=> Non-Secure state // Interrupt 400 <0=> Secure state <1=> Non-Secure state // Interrupt 401 <0=> Secure state <1=> Non-Secure state // Interrupt 402 <0=> Secure state <1=> Non-Secure state // Interrupt 403 <0=> Secure state <1=> Non-Secure state // Interrupt 404 <0=> Secure state <1=> Non-Secure state // Interrupt 405 <0=> Secure state <1=> Non-Secure state // Interrupt 406 <0=> Secure state <1=> Non-Secure state // Interrupt 407 <0=> Secure state <1=> Non-Secure state // Interrupt 408 <0=> Secure state <1=> Non-Secure state // Interrupt 409 <0=> Secure state <1=> Non-Secure state // Interrupt 410 <0=> Secure state <1=> Non-Secure state // Interrupt 411 <0=> Secure state <1=> Non-Secure state // Interrupt 412 <0=> Secure state <1=> Non-Secure state // Interrupt 413 <0=> Secure state <1=> Non-Secure state // Interrupt 414 <0=> Secure state <1=> Non-Secure state // Interrupt 415 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS12_VAL 0x00000000 /* // */ /* // Initialize ITNS 13 (Interrupts 416..447) */ #define NVIC_INIT_ITNS13 0 /* // Interrupts 416..447 // Interrupt 416 <0=> Secure state <1=> Non-Secure state // Interrupt 417 <0=> Secure state <1=> Non-Secure state // Interrupt 418 <0=> Secure state <1=> Non-Secure state // Interrupt 419 <0=> Secure state <1=> Non-Secure state // Interrupt 420 <0=> Secure state <1=> Non-Secure state // Interrupt 421 <0=> Secure state <1=> Non-Secure state // Interrupt 422 <0=> Secure state <1=> Non-Secure state // Interrupt 423 <0=> Secure state <1=> Non-Secure state // Interrupt 424 <0=> Secure state <1=> Non-Secure state // Interrupt 425 <0=> Secure state <1=> Non-Secure state // Interrupt 426 <0=> Secure state <1=> Non-Secure state // Interrupt 427 <0=> Secure state <1=> Non-Secure state // Interrupt 428 <0=> Secure state <1=> Non-Secure state // Interrupt 429 <0=> Secure state <1=> Non-Secure state // Interrupt 430 <0=> Secure state <1=> Non-Secure state // Interrupt 431 <0=> Secure state <1=> Non-Secure state // Interrupt 432 <0=> Secure state <1=> Non-Secure state // Interrupt 433 <0=> Secure state <1=> Non-Secure state // Interrupt 434 <0=> Secure state <1=> Non-Secure state // Interrupt 435 <0=> Secure state <1=> Non-Secure state // Interrupt 436 <0=> Secure state <1=> Non-Secure state // Interrupt 437 <0=> Secure state <1=> Non-Secure state // Interrupt 438 <0=> Secure state <1=> Non-Secure state // Interrupt 439 <0=> Secure state <1=> Non-Secure state // Interrupt 440 <0=> Secure state <1=> Non-Secure state // Interrupt 441 <0=> Secure state <1=> Non-Secure state // Interrupt 442 <0=> Secure state <1=> Non-Secure state // Interrupt 443 <0=> Secure state <1=> Non-Secure state // Interrupt 444 <0=> Secure state <1=> Non-Secure state // Interrupt 445 <0=> Secure state <1=> Non-Secure state // Interrupt 446 <0=> Secure state <1=> Non-Secure state // Interrupt 447 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS13_VAL 0x00000000 /* // */ /* // Initialize ITNS 14 (Interrupts 448..479) */ #define NVIC_INIT_ITNS14 0 /* // Interrupts 448..479 // Interrupt 448 <0=> Secure state <1=> Non-Secure state // Interrupt 449 <0=> Secure state <1=> Non-Secure state // Interrupt 450 <0=> Secure state <1=> Non-Secure state // Interrupt 451 <0=> Secure state <1=> Non-Secure state // Interrupt 452 <0=> Secure state <1=> Non-Secure state // Interrupt 453 <0=> Secure state <1=> Non-Secure state // Interrupt 454 <0=> Secure state <1=> Non-Secure state // Interrupt 455 <0=> Secure state <1=> Non-Secure state // Interrupt 456 <0=> Secure state <1=> Non-Secure state // Interrupt 457 <0=> Secure state <1=> Non-Secure state // Interrupt 458 <0=> Secure state <1=> Non-Secure state // Interrupt 459 <0=> Secure state <1=> Non-Secure state // Interrupt 460 <0=> Secure state <1=> Non-Secure state // Interrupt 461 <0=> Secure state <1=> Non-Secure state // Interrupt 462 <0=> Secure state <1=> Non-Secure state // Interrupt 463 <0=> Secure state <1=> Non-Secure state // Interrupt 464 <0=> Secure state <1=> Non-Secure state // Interrupt 465 <0=> Secure state <1=> Non-Secure state // Interrupt 466 <0=> Secure state <1=> Non-Secure state // Interrupt 467 <0=> Secure state <1=> Non-Secure state // Interrupt 468 <0=> Secure state <1=> Non-Secure state // Interrupt 469 <0=> Secure state <1=> Non-Secure state // Interrupt 470 <0=> Secure state <1=> Non-Secure state // Interrupt 471 <0=> Secure state <1=> Non-Secure state // Interrupt 472 <0=> Secure state <1=> Non-Secure state // Interrupt 473 <0=> Secure state <1=> Non-Secure state // Interrupt 474 <0=> Secure state <1=> Non-Secure state // Interrupt 475 <0=> Secure state <1=> Non-Secure state // Interrupt 476 <0=> Secure state <1=> Non-Secure state // Interrupt 477 <0=> Secure state <1=> Non-Secure state // Interrupt 478 <0=> Secure state <1=> Non-Secure state // Interrupt 479 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS14_VAL 0x00000000 /* // */ /* // Initialize ITNS 15 (Interrupts 480..511) */ #define NVIC_INIT_ITNS15 0 /* // Interrupts 480..511 // Interrupt 480 <0=> Secure state <1=> Non-Secure state // Interrupt 481 <0=> Secure state <1=> Non-Secure state // Interrupt 482 <0=> Secure state <1=> Non-Secure state // Interrupt 483 <0=> Secure state <1=> Non-Secure state // Interrupt 484 <0=> Secure state <1=> Non-Secure state // Interrupt 485 <0=> Secure state <1=> Non-Secure state // Interrupt 486 <0=> Secure state <1=> Non-Secure state // Interrupt 487 <0=> Secure state <1=> Non-Secure state // Interrupt 488 <0=> Secure state <1=> Non-Secure state // Interrupt 489 <0=> Secure state <1=> Non-Secure state // Interrupt 490 <0=> Secure state <1=> Non-Secure state // Interrupt 491 <0=> Secure state <1=> Non-Secure state // Interrupt 492 <0=> Secure state <1=> Non-Secure state // Interrupt 493 <0=> Secure state <1=> Non-Secure state // Interrupt 494 <0=> Secure state <1=> Non-Secure state // Interrupt 495 <0=> Secure state <1=> Non-Secure state // Interrupt 496 <0=> Secure state <1=> Non-Secure state // Interrupt 497 <0=> Secure state <1=> Non-Secure state // Interrupt 498 <0=> Secure state <1=> Non-Secure state // Interrupt 499 <0=> Secure state <1=> Non-Secure state // Interrupt 500 <0=> Secure state <1=> Non-Secure state // Interrupt 501 <0=> Secure state <1=> Non-Secure state // Interrupt 502 <0=> Secure state <1=> Non-Secure state // Interrupt 503 <0=> Secure state <1=> Non-Secure state // Interrupt 504 <0=> Secure state <1=> Non-Secure state // Interrupt 505 <0=> Secure state <1=> Non-Secure state // Interrupt 506 <0=> Secure state <1=> Non-Secure state // Interrupt 507 <0=> Secure state <1=> Non-Secure state // Interrupt 508 <0=> Secure state <1=> Non-Secure state // Interrupt 509 <0=> Secure state <1=> Non-Secure state // Interrupt 510 <0=> Secure state <1=> Non-Secure state // Interrupt 511 <0=> Secure state <1=> Non-Secure state */ #define NVIC_INIT_ITNS15_VAL 0x00000000 /* // */ /* // */ /* max 128 SAU regions. SAU regions are defined in partition.h */ #define SAU_INIT_REGION(n) \ SAU->RNR = (n & SAU_RNR_REGION_Msk); \ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U /** \brief Setup a SAU Region \details Writes the region information contained in SAU_Region to the registers SAU_RNR, SAU_RBAR, and SAU_RLAR */ __STATIC_INLINE void TZ_SAU_Setup (void) { #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) SAU_INIT_REGION(0); #endif #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) SAU_INIT_REGION(1); #endif #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) SAU_INIT_REGION(2); #endif #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) SAU_INIT_REGION(3); #endif #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) SAU_INIT_REGION(4); #endif #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) SAU_INIT_REGION(5); #endif #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) SAU_INIT_REGION(6); #endif #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) SAU_INIT_REGION(7); #endif /* repeat this for all possible SAU regions */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; #endif #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); #endif #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; #endif #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; #endif #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; #endif #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; #endif #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; #endif #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; #endif #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; #endif #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; #endif #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; #endif #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; #endif #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; #endif #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; #endif #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; #endif #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; #endif #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; #endif #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; #endif /* repeat this for all possible ITNS elements */ } #endif /* PARTITION_ARMCM55_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Config.h * Purpose: CV Config header *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2021 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __CV_CONFIG_H #define __CV_CONFIG_H #include "RTE_Components.h" #include CMSIS_device_header #define RTE_CV_COREINSTR 1 #define RTE_CV_COREFUNC 1 #define RTE_CV_L1CACHE 1 //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // Common Test Settings // Print Output Format <0=> Plain Text <1=> XML // Set the test results output format to plain text or XML #ifndef PRINT_XML_REPORT #define PRINT_XML_REPORT 1 #endif // Buffer size for assertions results // Set the buffer size for assertions results buffer #define BUFFER_ASSERTIONS 128U // // Disable Test Cases // Uncheck to disable an individual test case // TC_CoreInstr_NOP #define TC_COREINSTR_NOP_EN 1 // TC_CoreInstr_REV #define TC_COREINSTR_REV_EN 1 // TC_CoreInstr_REV16 #define TC_COREINSTR_REV16_EN 1 // TC_CoreInstr_REVSH #define TC_COREINSTR_REVSH_EN 1 // TC_CoreInstr_ROR #define TC_COREINSTR_ROR_EN 1 // TC_CoreInstr_RBIT #define TC_COREINSTR_RBIT_EN 1 // TC_CoreInstr_CLZ #define TC_COREINSTR_CLZ_EN 1 // TC_CoreInstr_Exclusives #define TC_COREINSTR_EXCLUSIVES_EN 1 // TC_CoreInstr_SSAT #define TC_COREINSTR_SSAT_EN 1 // TC_CoreInstr_USAT #define TC_COREINSTR_USAT_EN 1 // TC_CoreAFunc_IRQ #define TC_COREAFUNC_IRQ 1 // TC_CoreAFunc_FaultIRQ #define TC_COREAFUNC_FAULTIRQ 1 // TC_CoreAFunc_FPSCR #define TC_COREAFUNC_FPSCR 1 // TC_CoreAFunc_CPSR #define TC_COREAFUNC_CPSR 1 // TC_CoreAFunc_Mode #define TC_COREAFUNC_MODE 1 // TC_CoreAFunc_SP #define TC_COREAFUNC_SP 1 // TC_CoreAFunc_SP_usr #define TC_COREAFUNC_SP_USR 1 // TC_CoreAFunc_FPEXC #define TC_COREAFUNC_FPEXC 1 // TC_CoreAFunc_ACTLR #define TC_COREAFUNC_ACTLR 1 // TC_CoreAFunc_CPACR #define TC_COREAFUNC_CPACR 1 // TC_CoreAFunc_DFSR #define TC_COREAFUNC_DFSR 1 // TC_CoreAFunc_IFSR #define TC_COREAFUNC_IFSR 1 // TC_CoreAFunc_ISR #define TC_COREAFUNC_ISR 1 // TC_CoreAFunc_CBAR #define TC_COREAFUNC_CBAR 1 // TC_CoreAFunc_TTBR0 #define TC_COREAFUNC_TTBR0 1 // TC_CoreAFunc_DACR #define TC_COREAFUNC_DACR 1 // TC_CoreAFunc_SCTLR #define TC_COREAFUNC_SCTLR 1 // TC_CoreAFunc_ACTRL #define TC_COREAFUNC_ACTRL 1 // TC_CoreAFunc_MPIDR #define TC_COREAFUNC_MPIDR 1 // TC_CoreAFunc_VBAR #define TC_COREAFUNC_VBAR 1 // TC_CoreAFunc_MVBAR #define TC_COREAFUNC_MVBAR 1 // TC_CoreAFunc_FPU_Enable #define TC_COREAFUNC_FPU_ENABLE 1 // TC_GenTimer_CNTFRQ #define TC_GENTIMER_CNTFRQ 1 // TC_GenTimer_CNTP_TVAL #define TC_GENTIMER_CNTP_TVAL 1 // TC_GenTimer_CNTP_CTL #define TC_GENTIMER_CNTP_CTL 1 // TC_GenTimer_CNTPCT #define TC_GENTIMER_CNTPCT 1 // TC_GenTimer_CNTP_CVAL #define TC_GENTIMER_CNTP_CVAL 1 // TC_CAL1Cache_EnDisable #define TC_CAL1CACHE_ENDISABLE 1 // TC_CAL1Cache_EnDisableBTAC #define TC_CAL1CACHE_ENDISABLEBTAC 1 // TC_CAL1Cache_log2_up #define TC_CAL1CACHE_LOG2_UP 1 // TC_CAL1Cache_InvalidateDCacheAll #define TC_CAL1CACHE_INVALIDATEDCACHEALL 1 // TC_CAL1Cache_CleanDCacheAll #define TC_CAL1CACHE_CLEANDCACHEALL 1 // TC_CAL1Cache_CleanInvalidateDCacheAll #define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1 // #endif /* __CV_CONFIG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h ================================================ /*----------------------------------------------------------------------------- * Name: CV_Config.h * Purpose: CV Config header *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2021 ARM Limited. All rights reserved. *----------------------------------------------------------------------------*/ #ifndef __CV_CONFIG_H #define __CV_CONFIG_H #include "RTE_Components.h" #include CMSIS_device_header //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- // Common Test Settings // Print Output Format <0=> Plain Text <1=> XML // Set the test results output format to plain text or XML #ifndef PRINT_XML_REPORT #define PRINT_XML_REPORT 0 #endif // Buffer size for assertions results // Set the buffer size for assertions results buffer #define BUFFER_ASSERTIONS 128U // // Disable Test Cases // Uncheck to disable an individual test case // TC_CoreInstr_NOP #define TC_COREINSTR_NOP_EN 1 // TC_CoreInstr_REV #define TC_COREINSTR_REV_EN 1 // TC_CoreInstr_REV16 #define TC_COREINSTR_REV16_EN 1 // TC_CoreInstr_REVSH #define TC_COREINSTR_REVSH_EN 1 // TC_CoreInstr_ROR #define TC_COREINSTR_ROR_EN 1 // TC_CoreInstr_RBIT #define TC_COREINSTR_RBIT_EN 1 // TC_CoreInstr_CLZ #define TC_COREINSTR_CLZ_EN 1 // TC_CoreInstr_Exclusives #define TC_COREINSTR_EXCLUSIVES_EN 1 // TC_CoreInstr_SSAT #define TC_COREINSTR_SSAT_EN 1 // TC_CoreInstr_USAT #define TC_COREINSTR_USAT_EN 1 // TC_CoreAFunc_IRQ #define TC_COREAFUNC_IRQ 1 // TC_CoreAFunc_FaultIRQ #define TC_COREAFUNC_FAULTIRQ 1 // TC_CoreAFunc_FPSCR #define TC_COREAFUNC_FPSCR 1 // TC_CoreAFunc_CPSR #define TC_COREAFUNC_CPSR 1 // TC_CoreAFunc_Mode #define TC_COREAFUNC_MODE 1 // TC_CoreAFunc_SP #define TC_COREAFUNC_SP 1 // TC_CoreAFunc_SP_usr #define TC_COREAFUNC_SP_USR 1 // TC_CoreAFunc_FPEXC #define TC_COREAFUNC_FPEXC 1 // TC_CoreAFunc_ACTLR #define TC_COREAFUNC_ACTLR 1 // TC_CoreAFunc_CPACR #define TC_COREAFUNC_CPACR 1 // TC_CoreAFunc_DFSR #define TC_COREAFUNC_DFSR 1 // TC_CoreAFunc_IFSR #define TC_COREAFUNC_IFSR 1 // TC_CoreAFunc_ISR #define TC_COREAFUNC_ISR 1 // TC_CoreAFunc_CBAR #define TC_COREAFUNC_CBAR 1 // TC_CoreAFunc_TTBR0 #define TC_COREAFUNC_TTBR0 1 // TC_CoreAFunc_DACR #define TC_COREAFUNC_DACR 1 // TC_CoreAFunc_SCTLR #define TC_COREAFUNC_SCTLR 1 // TC_CoreAFunc_ACTRL #define TC_COREAFUNC_ACTRL 1 // TC_CoreAFunc_MPIDR #define TC_COREAFUNC_MPIDR 1 // TC_CoreAFunc_VBAR #define TC_COREAFUNC_VBAR 1 // TC_CoreAFunc_MVBAR #define TC_COREAFUNC_MVBAR 1 // TC_CoreAFunc_FPU_Enable #define TC_COREAFUNC_FPU_ENABLE 1 // TC_GenTimer_CNTFRQ #define TC_GENTIMER_CNTFRQ 1 // TC_GenTimer_CNTP_TVAL #define TC_GENTIMER_CNTP_TVAL 1 // TC_GenTimer_CNTP_CTL #define TC_GENTIMER_CNTP_CTL 1 // TC_GenTimer_CNTPCT #define TC_GENTIMER_CNTPCT 1 // TC_GenTimer_CNTP_CVAL #define TC_GENTIMER_CNTP_CVAL 1 // TC_CAL1Cache_EnDisable #define TC_CAL1CACHE_ENDISABLE 1 // TC_CAL1Cache_EnDisableBTAC #define TC_CAL1CACHE_ENDISABLEBTAC 1 // TC_CAL1Cache_log2_up #define TC_CAL1CACHE_LOG2_UP 1 // TC_CAL1Cache_InvalidateDCacheAll #define TC_CAL1CACHE_INVALIDATEDCACHEALL 1 // TC_CAL1Cache_CleanDCacheAll #define TC_CAL1CACHE_CLEANDCACHEALL 1 // TC_CAL1Cache_CleanInvalidateDCacheAll #define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1 // #endif /* __CV_CONFIG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/CoreValidation/Source/cmsis_cv.c ================================================ /*----------------------------------------------------------------------------- * Name: cmsis_cv.c * Purpose: Driver validation test cases entry point *---------------------------------------------------------------------------- * Copyright (c) 2017 - 2021 Arm Limited. All rights reserved. *----------------------------------------------------------------------------*/ #include "cmsis_cv.h" #include "RTE_Components.h" #include "CV_Framework.h" #include "CV_Config.h" /*----------------------------------------------------------------------------- * Prototypes *----------------------------------------------------------------------------*/ void Interrupt0_Handler(void); /*----------------------------------------------------------------------------- * Variables declarations *----------------------------------------------------------------------------*/ void (*TST_IRQHandler)(void); void Interrupt0_Handler(void) { if (TST_IRQHandler != NULL) TST_IRQHandler(); } /*----------------------------------------------------------------------------- * Init test suite *----------------------------------------------------------------------------*/ static void TS_Init (void) { TST_IRQHandler = NULL; #ifdef RTE_CV_MEASURETICKS StartCortexCycleCounter(); #endif } /*----------------------------------------------------------------------------- * Test cases list *----------------------------------------------------------------------------*/ static TEST_CASE TC_LIST[] = { #if defined(RTE_CV_COREINSTR) && RTE_CV_COREINSTR #if defined(__CORTEX_M) TCD ( TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ), TCD ( TC_CoreInstr_WFI, TC_COREINSTR_WFI_EN ), TCD ( TC_CoreInstr_WFE, TC_COREINSTR_WFE_EN ), TCD ( TC_CoreInstr_SEV, TC_COREINSTR_SEV_EN ), TCD ( TC_CoreInstr_BKPT, TC_COREINSTR_BKPT_EN ), TCD ( TC_CoreInstr_ISB, TC_COREINSTR_ISB_EN ), TCD ( TC_CoreInstr_DSB, TC_COREINSTR_DSB_EN ), TCD ( TC_CoreInstr_DMB, TC_COREINSTR_DMB_EN ), TCD ( TC_CoreInstr_REV, TC_COREINSTR_REV_EN ), TCD ( TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ), TCD ( TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ), TCD ( TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ), TCD ( TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ), TCD ( TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ), TCD ( TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ), TCD ( TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ), TCD ( TC_CoreInstr_RRX, TC_COREINSTR_RRX_EN ), TCD ( TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_LOADSTOREEXCLUSIVE_EN ), TCD ( TC_CoreInstr_LoadStoreUnpriv, TC_COREINSTR_LOADSTOREUNPRIV_EN ), TCD ( TC_CoreInstr_LoadStoreAcquire, TC_COREINSTR_LOADSTOREACQUIRE_EN ), TCD ( TC_CoreInstr_LoadStoreAcquireExclusive, TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN ), TCD ( TC_CoreInstr_UnalignedUint16, TC_COREINSTR_UNALIGNEDUINT16_EN ), TCD ( TC_CoreInstr_UnalignedUint32, TC_COREINSTR_UNALIGNEDUINT32_EN ), #elif defined(__CORTEX_A) TCD (TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ), TCD (TC_CoreInstr_REV, TC_COREINSTR_REV_EN ), TCD (TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ), TCD (TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ), TCD (TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ), TCD (TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ), TCD (TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ), TCD (TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ), TCD (TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ), TCD (TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_EXCLUSIVES_EN ), #endif #endif /* RTE_CV_COREINSTR */ #if defined (RTE_CV_CORESIMD) && RTE_CV_CORESIMD TCD ( TC_CoreSimd_SatAddSub, TC_CORESIMD_SATADDSUB_EN ), TCD ( TC_CoreSimd_ParSat16, TC_CORESIMD_PARSAT16_EN ), TCD ( TC_CoreSimd_PackUnpack, TC_CORESIMD_PACKUNPACK_EN ), TCD ( TC_CoreSimd_ParSel, TC_CORESIMD_PARSEL_EN ), TCD ( TC_CoreSimd_ParAddSub8, TC_CORESIMD_PARADDSUB8_EN ), TCD ( TC_CoreSimd_AbsDif8, TC_CORESIMD_ABSDIF8_EN ), TCD ( TC_CoreSimd_ParAddSub16, TC_CORESIMD_PARADDSUB16_EN ), TCD ( TC_CoreSimd_ParMul16, TC_CORESIMD_PARMUL16_EN ), TCD ( TC_CoreSimd_Pack16, TC_CORESIMD_PACK16_EN ), TCD ( TC_CoreSimd_MulAcc32, TC_CORESIMD_MULACC32_EN ), #endif /* RTE_CV_CORESIMD */ #if defined(RTE_CV_COREFUNC) && RTE_CV_COREFUNC #if defined(__CORTEX_M) TCD ( TC_CoreFunc_EnDisIRQ, TC_COREFUNC_ENDISIRQ_EN ), TCD ( TC_CoreFunc_IRQPrio, TC_COREFUNC_IRQPRIO_EN ), TCD ( TC_CoreFunc_EncDecIRQPrio, TC_COREFUNC_ENCDECIRQPRIO_EN ), TCD ( TC_CoreFunc_IRQVect, TC_COREFUNC_IRQVECT_EN ), TCD ( TC_CoreFunc_Control, TC_COREFUNC_CONTROL_EN ), TCD ( TC_CoreFunc_IPSR, TC_COREFUNC_IPSR_EN ), TCD ( TC_CoreFunc_APSR, TC_COREFUNC_APSR_EN ), TCD ( TC_CoreFunc_PSP, TC_COREFUNC_PSP_EN ), TCD ( TC_CoreFunc_MSP, TC_COREFUNC_MSP_EN ), TCD ( TC_CoreFunc_PSPLIM, TC_COREFUNC_PSPLIM_EN ), TCD ( TC_CoreFunc_PSPLIM_NS, TC_COREFUNC_PSPLIM_NS_EN ), TCD ( TC_CoreFunc_MSPLIM, TC_COREFUNC_MSPLIM_EN ), TCD ( TC_CoreFunc_MSPLIM_NS, TC_COREFUNC_MSPLIM_NS_EN ), TCD ( TC_CoreFunc_PRIMASK, TC_COREFUNC_PRIMASK_EN ), TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ), TCD ( TC_CoreFunc_BASEPRI, TC_COREFUNC_BASEPRI_EN ), TCD ( TC_CoreFunc_FPUType, TC_COREFUNC_FPUTYPE_EN ), TCD ( TC_CoreFunc_FPSCR, TC_COREFUNC_FPSCR_EN ), #elif defined(__CORTEX_A) TCD ( TC_CoreAFunc_IRQ, TC_COREAFUNC_IRQ ), TCD ( TC_CoreAFunc_FaultIRQ, TC_COREAFUNC_FAULTIRQ ), TCD ( TC_CoreAFunc_FPSCR, TC_COREAFUNC_FPSCR ), TCD ( TC_CoreAFunc_CPSR, TC_COREAFUNC_CPSR ), TCD ( TC_CoreAFunc_Mode, TC_COREAFUNC_MODE ), TCD ( TC_CoreAFunc_SP, TC_COREAFUNC_SP ), TCD ( TC_CoreAFunc_SP_usr, TC_COREAFUNC_SP_USR ), TCD ( TC_CoreAFunc_FPEXC, TC_COREAFUNC_FPEXC ), TCD ( TC_CoreAFunc_ACTLR, TC_COREAFUNC_ACTLR ), TCD ( TC_CoreAFunc_CPACR, TC_COREAFUNC_CPACR ), TCD ( TC_CoreAFunc_DFSR, TC_COREAFUNC_DFSR ), TCD ( TC_CoreAFunc_IFSR, TC_COREAFUNC_IFSR ), TCD ( TC_CoreAFunc_ISR, TC_COREAFUNC_ISR ), TCD ( TC_CoreAFunc_CBAR, TC_COREAFUNC_CBAR ), TCD ( TC_CoreAFunc_TTBR0, TC_COREAFUNC_TTBR0 ), TCD ( TC_CoreAFunc_DACR, TC_COREAFUNC_DACR ), TCD ( TC_CoreAFunc_SCTLR, TC_COREAFUNC_SCTLR ), TCD ( TC_CoreAFunc_ACTRL, TC_COREAFUNC_ACTRL ), TCD ( TC_CoreAFunc_MPIDR, TC_COREAFUNC_MPIDR ), TCD ( TC_CoreAFunc_VBAR, TC_COREAFUNC_VBAR ), TCD ( TC_CoreAFunc_MVBAR, TC_COREAFUNC_MVBAR ), TCD ( TC_CoreAFunc_FPU_Enable, TC_COREAFUNC_FPU_ENABLE ), #endif #endif /* RTE_CV_COREFUNC */ #if defined(RTE_CV_MPUFUNC) && RTE_CV_MPUFUNC TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ), TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ), #endif /* RTE_CV_MPUFUNC */ #if defined(RTE_CV_GENTIMER) && RTE_CV_GENTIMER TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ), TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ), TCD ( TC_GenTimer_CNTP_CTL, TC_GENTIMER_CNTP_CTL ), TCD ( TC_GenTimer_CNTPCT, TC_GENTIMER_CNTPCT ), TCD ( TC_GenTimer_CNTP_CVAL, TC_GENTIMER_CNTP_CVAL ), #endif /* RTE_CV_GENTIMER */ #if defined(RTE_CV_L1CACHE) && RTE_CV_L1CACHE #if defined(__CORTEX_M) TCD ( TC_CML1Cache_EnDisableICache, TC_CML1CACHE_ENDISABLE_ICACHE ), TCD ( TC_CML1Cache_EnDisableDCache, TC_CML1CACHE_ENDISABLE_DCACHE ), TCD ( TC_CML1Cache_CleanDCacheByAddrWhileDisabled, TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED), #elif defined(__CORTEX_A) TCD ( TC_CAL1Cache_EnDisable, TC_CAL1CACHE_ENDISABLE ), TCD ( TC_CAL1Cache_EnDisableBTAC, TC_CAL1CACHE_ENDISABLEBTAC ), TCD ( TC_CAL1Cache_log2_up, TC_CAL1CACHE_LOG2_UP ), TCD ( TC_CAL1Cache_InvalidateDCacheAll, TC_CAL1CACHE_INVALIDATEDCACHEALL ), TCD ( TC_CAL1Cache_CleanDCacheAll, TC_CAL1CACHE_CLEANDCACHEALL ), TCD ( TC_CAL1Cache_CleanInvalidateDCacheAll, TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL ), #endif #endif /* RTE_CV_L1CACHE */ }; #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wdate-time" #endif /*----------------------------------------------------------------------------- * Test suite description *----------------------------------------------------------------------------*/ TEST_SUITE ts = { __FILE__, __DATE__, __TIME__, "CMSIS-CORE Test Suite", TS_Init, 1, TC_LIST, ARRAY_SIZE (TC_LIST), }; #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armcc.h ================================================ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file * @version V1.0.6 * @date 13. November 2022 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) #define __ARM_ARCH_7A__ 1 #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE __forceinline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __memory_changed() #endif /* ########################## Core Instruction Access ######################### */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /* ########################### Core Function Access ########################### */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(void); */ /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get FPSCR (Floating Point Status/Control) \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0U); #endif } /** \brief Set FPSCR (Floating Point Status/Control) \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } /** \brief Get CPSR (Current Program Status Register) \return CPSR Register value */ __STATIC_INLINE uint32_t __get_CPSR(void) { register uint32_t __regCPSR __ASM("cpsr"); return(__regCPSR); } /** \brief Set CPSR (Current Program Status Register) \param [in] cpsr CPSR value to set */ __STATIC_INLINE void __set_CPSR(uint32_t cpsr) { register uint32_t __regCPSR __ASM("cpsr"); __regCPSR = cpsr; } /** \brief Get Mode \return Processor Mode */ __STATIC_INLINE uint32_t __get_mode(void) { return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ __STATIC_INLINE __ASM void __set_mode(uint32_t mode) { MOV r1, lr MSR CPSR_C, r0 BX r1 } /** \brief Get Stack Pointer \return Stack Pointer */ __STATIC_INLINE __ASM uint32_t __get_SP(void) { MOV r0, sp BX lr } /** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ __STATIC_INLINE __ASM void __set_SP(uint32_t stack) { MOV sp, r0 BX lr } /** \brief Get USR/SYS Stack Pointer \return USR/SYSStack Pointer */ __STATIC_INLINE __ASM uint32_t __get_SP_usr(void) { ARM PRESERVE8 MRS R1, CPSR CPS #0x1F ;no effect in USR mode MOV R0, SP MSR CPSR_c, R1 ;no effect in USR mode ISB BX LR } /** \brief Set USR/SYS Stack Pointer \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) { ARM PRESERVE8 MRS R1, CPSR CPS #0x1F ;no effect in USR mode MOV SP, R0 MSR CPSR_c, R1 ;no effect in USR mode ISB BX LR } /** \brief Get FPEXC (Floating Point Exception Control Register) \return Floating Point Exception Control Register value */ __STATIC_INLINE uint32_t __get_FPEXC(void) { #if (__FPU_PRESENT == 1) register uint32_t __regfpexc __ASM("fpexc"); return(__regfpexc); #else return(0); #endif } /** \brief Set FPEXC (Floating Point Exception Control Register) \param [in] fpexc Floating Point Exception Control value to set */ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) { #if (__FPU_PRESENT == 1) register uint32_t __regfpexc __ASM("fpexc"); __regfpexc = (fpexc); #endif } /* * Include common core functions to access Coprocessor 15 registers */ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) #define __get_CP64(cp, op1, Rt, CRm) \ do { \ uint32_t ltmp, htmp; \ __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ } while(0) #define __set_CP64(cp, op1, Rt, CRm) \ do { \ const uint64_t tmp = (Rt); \ const uint32_t ltmp = (uint32_t)(tmp); \ const uint32_t htmp = (uint32_t)(tmp >> 32U); \ __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ } while(0) #include "cmsis_cp15.h" /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ __STATIC_INLINE __ASM void __FPU_Enable(void) { ARM //Permit access to VFP/NEON, registers by modifying CPACR MRC p15,0,R1,c1,c0,2 ORR R1,R1,#0x00F00000 MCR p15,0,R1,c1,c0,2 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted ISB //Enable VFP/NEON VMRS R1,FPEXC ORR R1,R1,#0x40000000 VMSR FPEXC,R1 //Initialise VFP/NEON registers to 0 MOV R2,#0 //Initialise D16 registers to 0 VMOV D0, R2,R2 VMOV D1, R2,R2 VMOV D2, R2,R2 VMOV D3, R2,R2 VMOV D4, R2,R2 VMOV D5, R2,R2 VMOV D6, R2,R2 VMOV D7, R2,R2 VMOV D8, R2,R2 VMOV D9, R2,R2 VMOV D10,R2,R2 VMOV D11,R2,R2 VMOV D12,R2,R2 VMOV D13,R2,R2 VMOV D14,R2,R2 VMOV D15,R2,R2 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 //Initialise D32 registers to 0 VMOV D16,R2,R2 VMOV D17,R2,R2 VMOV D18,R2,R2 VMOV D19,R2,R2 VMOV D20,R2,R2 VMOV D21,R2,R2 VMOV D22,R2,R2 VMOV D23,R2,R2 VMOV D24,R2,R2 VMOV D25,R2,R2 VMOV D26,R2,R2 VMOV D27,R2,R2 VMOV D28,R2,R2 VMOV D29,R2,R2 VMOV D30,R2,R2 VMOV D31,R2,R2 ENDIF //Initialise FPSCR to a known state VMRS R1,FPSCR LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. AND R1,R1,R2 VMSR FPSCR,R1 BX LR } #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V1.2.2 * @date 13. November 2022 ******************************************************************************/ /* * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE __attribute__((always_inline)) #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ########################## Core Instruction Access ######################### */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) #define __SADD8 __builtin_arm_sadd8 #define __SADD16 __builtin_arm_sadd16 #define __QADD8 __builtin_arm_qadd8 #define __QSUB8 __builtin_arm_qsub8 #define __QADD16 __builtin_arm_qadd16 #define __SHADD16 __builtin_arm_shadd16 #define __QSUB16 __builtin_arm_qsub16 #define __SHSUB16 __builtin_arm_shsub16 #define __QASX __builtin_arm_qasx #define __SHASX __builtin_arm_shasx #define __QSAX __builtin_arm_qsax #define __SHSAX __builtin_arm_shsax #define __SXTB16 __builtin_arm_sxtb16 #define __SMUAD __builtin_arm_smuad #define __SMUADX __builtin_arm_smuadx #define __SMLAD __builtin_arm_smlad #define __SMLADX __builtin_arm_smladx #define __SMLALD __builtin_arm_smlald #define __SMLALDX __builtin_arm_smlaldx #define __SMUSD __builtin_arm_smusd #define __SMUSDX __builtin_arm_smusdx #define __SMLSDX __builtin_arm_smlsdx #define __USAT16 __builtin_arm_usat16 #define __SSUB8 __builtin_arm_ssub8 #define __SXTB16 __builtin_arm_sxtb16 #define __SXTAB16 __builtin_arm_sxtab16 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /* ########################### Core Function Access ########################### */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #define __get_FPSCR __builtin_arm_get_fpscr /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #define __set_FPSCR __builtin_arm_set_fpscr /** \brief Get CPSR Register \return CPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_CPSR(void) { uint32_t result; __ASM volatile("MRS %0, cpsr" : "=r" (result) ); return(result); } /** \brief Set CPSR Register \param [in] cpsr CPSR value to set */ __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) { __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); } /** \brief Get Mode \return Processor Mode */ __STATIC_FORCEINLINE uint32_t __get_mode(void) { return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ __STATIC_FORCEINLINE void __set_mode(uint32_t mode) { __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } /** \brief Get Stack Pointer \return Stack Pointer value */ __STATIC_FORCEINLINE uint32_t __get_SP(void) { uint32_t result; __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); return result; } /** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_SP(uint32_t stack) { __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); } /** \brief Get USR/SYS Stack Pointer \return USR/SYS Stack Pointer value */ __STATIC_FORCEINLINE uint32_t __get_SP_usr(void) { uint32_t cpsr; uint32_t result; __ASM volatile( "MRS %0, cpsr \n" "CPS #0x1F \n" // no effect in USR mode "MOV %1, sp \n" "MSR cpsr_c, %0 \n" // no effect in USR mode "ISB" : "=r"(cpsr), "=r"(result) : : "memory" ); return result; } /** \brief Set USR/SYS Stack Pointer \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) { uint32_t cpsr; __ASM volatile( "MRS %0, cpsr \n" "CPS #0x1F \n" // no effect in USR mode "MOV sp, %1 \n" "MSR cpsr_c, %0 \n" // no effect in USR mode "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" ); } /** \brief Get FPEXC \return Floating Point Exception Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPEXC(void) { #if (__FPU_PRESENT == 1) uint32_t result; __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); return(result); #else return(0); #endif } /** \brief Set FPEXC \param [in] fpexc Floating Point Exception Control value to set */ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) { #if (__FPU_PRESENT == 1) __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); #endif } /* * Include common core functions to access Coprocessor 15 registers */ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" " VMOV D3, R2,R2 \n" " VMOV D4, R2,R2 \n" " VMOV D5, R2,R2 \n" " VMOV D6, R2,R2 \n" " VMOV D7, R2,R2 \n" " VMOV D8, R2,R2 \n" " VMOV D9, R2,R2 \n" " VMOV D10,R2,R2 \n" " VMOV D11,R2,R2 \n" " VMOV D12,R2,R2 \n" " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" #if (defined(__ARM_NEON) && (__ARM_NEON == 1)) //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" " VMOV D19,R2,R2 \n" " VMOV D20,R2,R2 \n" " VMOV D21,R2,R2 \n" " VMOV D22,R2,R2 \n" " VMOV D23,R2,R2 \n" " VMOV D24,R2,R2 \n" " VMOV D25,R2,R2 \n" " VMOV D26,R2,R2 \n" " VMOV D27,R2,R2 \n" " VMOV D28,R2,R2 \n" " VMOV D29,R2,R2 \n" " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" #endif //Initialise FPSCR to a known state " VMRS R1,FPSCR \n" " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R1,R1,R2 \n" " VMSR FPSCR,R1 " : : : "cc", "r1", "r2" ); } #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler specific macros, functions, instructions * @version V1.0.3 * @date 13. November 2022 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6.6 LTM (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #include "cmsis_armclang_ltm.h" /* * Arm Compiler above 6.10.1 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef CMSIS_DEPRECATED #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. #define CMSIS_DEPRECATED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_cp15.h ================================================ /**************************************************************************//** * @file cmsis_cp15.h * @brief CMSIS compiler specific macros, functions, instructions * @version V1.0.2 * @date 19. December 2022 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_CP15_H #define __CMSIS_CP15_H /** \brief Get ACTLR \return Auxiliary Control register value */ __STATIC_FORCEINLINE uint32_t __get_ACTLR(void) { uint32_t result; __get_CP(15, 0, result, 1, 0, 1); return(result); } /** \brief Set ACTLR \param [in] actlr Auxiliary Control value to set */ __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) { __set_CP(15, 0, actlr, 1, 0, 1); } /** \brief Get CPACR \return Coprocessor Access Control register value */ __STATIC_FORCEINLINE uint32_t __get_CPACR(void) { uint32_t result; __get_CP(15, 0, result, 1, 0, 2); return result; } /** \brief Set CPACR \param [in] cpacr Coprocessor Access Control value to set */ __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) { __set_CP(15, 0, cpacr, 1, 0, 2); } /** \brief Get DFSR \return Data Fault Status Register value */ __STATIC_FORCEINLINE uint32_t __get_DFSR(void) { uint32_t result; __get_CP(15, 0, result, 5, 0, 0); return result; } /** \brief Set DFSR \param [in] dfsr Data Fault Status value to set */ __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) { __set_CP(15, 0, dfsr, 5, 0, 0); } /** \brief Get IFSR \return Instruction Fault Status Register value */ __STATIC_FORCEINLINE uint32_t __get_IFSR(void) { uint32_t result; __get_CP(15, 0, result, 5, 0, 1); return result; } /** \brief Set IFSR \param [in] ifsr Instruction Fault Status value to set */ __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) { __set_CP(15, 0, ifsr, 5, 0, 1); } /** \brief Get ISR \return Interrupt Status Register value */ __STATIC_FORCEINLINE uint32_t __get_ISR(void) { uint32_t result; __get_CP(15, 0, result, 12, 1, 0); return result; } /** \brief Get CBAR \return Configuration Base Address register value */ __STATIC_FORCEINLINE uint32_t __get_CBAR(void) { uint32_t result; __get_CP(15, 4, result, 15, 0, 0); return result; } /** \brief Get TTBR0 This function returns the value of the Translation Table Base Register 0. \return Translation Table Base Register 0 value */ __STATIC_FORCEINLINE uint32_t __get_TTBR0(void) { uint32_t result; __get_CP(15, 0, result, 2, 0, 0); return result; } /** \brief Set TTBR0 This function assigns the given value to the Translation Table Base Register 0. \param [in] ttbr0 Translation Table Base Register 0 value to set */ __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) { __set_CP(15, 0, ttbr0, 2, 0, 0); } /** \brief Get DACR This function returns the value of the Domain Access Control Register. \return Domain Access Control Register value */ __STATIC_FORCEINLINE uint32_t __get_DACR(void) { uint32_t result; __get_CP(15, 0, result, 3, 0, 0); return result; } /** \brief Set DACR This function assigns the given value to the Domain Access Control Register. \param [in] dacr Domain Access Control Register value to set */ __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) { __set_CP(15, 0, dacr, 3, 0, 0); } /** \brief Set SCTLR This function assigns the given value to the System Control Register. \param [in] sctlr System Control Register value to set */ __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) { __set_CP(15, 0, sctlr, 1, 0, 0); } /** \brief Get SCTLR \return System Control Register value */ __STATIC_FORCEINLINE uint32_t __get_SCTLR(void) { uint32_t result; __get_CP(15, 0, result, 1, 0, 0); return result; } /** \brief Set ACTRL \param [in] actrl Auxiliary Control Register value to set */ __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) { __set_CP(15, 0, actrl, 1, 0, 1); } /** \brief Get ACTRL \return Auxiliary Control Register value */ __STATIC_FORCEINLINE uint32_t __get_ACTRL(void) { uint32_t result; __get_CP(15, 0, result, 1, 0, 1); return result; } /** \brief Get MPIDR This function returns the value of the Multiprocessor Affinity Register. \return Multiprocessor Affinity Register value */ __STATIC_FORCEINLINE uint32_t __get_MPIDR(void) { uint32_t result; __get_CP(15, 0, result, 0, 0, 5); return result; } /** \brief Get VBAR This function returns the value of the Vector Base Address Register. \return Vector Base Address Register */ __STATIC_FORCEINLINE uint32_t __get_VBAR(void) { uint32_t result; __get_CP(15, 0, result, 12, 0, 0); return result; } /** \brief Set VBAR This function assigns the given value to the Vector Base Address Register. \param [in] vbar Vector Base Address Register value to set */ __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) { __set_CP(15, 0, vbar, 12, 0, 0); } /** \brief Get MVBAR This function returns the value of the Monitor Vector Base Address Register. \return Monitor Vector Base Address Register */ __STATIC_FORCEINLINE uint32_t __get_MVBAR(void) { uint32_t result; __get_CP(15, 0, result, 12, 0, 1); return result; } /** \brief Set MVBAR This function assigns the given value to the Monitor Vector Base Address Register. \param [in] mvbar Monitor Vector Base Address Register value to set */ __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) { __set_CP(15, 0, mvbar, 12, 0, 1); } #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ defined(DOXYGEN) /** \brief Set CNTFRQ This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). \param [in] value CNTFRQ Register value to set */ __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) { __set_CP(15, 0, value, 14, 0, 0); } /** \brief Get CNTFRQ This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). \return CNTFRQ Register value */ __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) { uint32_t result; __get_CP(15, 0, result, 14, 0 , 0); return result; } /** \brief Set CNTP_TVAL This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). \param [in] value CNTP_TVAL Register value to set */ __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) { __set_CP(15, 0, value, 14, 2, 0); } /** \brief Get CNTP_TVAL This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). \return CNTP_TVAL Register value */ __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) { uint32_t result; __get_CP(15, 0, result, 14, 2, 0); return result; } /** \brief Get CNTPCT This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). \return CNTPCT Register value */ __STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) { uint64_t result; __get_CP64(15, 0, result, 14); return result; } /** \brief Set CNTP_CVAL This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). \param [in] value CNTP_CVAL Register value to set */ __STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) { __set_CP64(15, 2, value, 14); } /** \brief Get CNTP_CVAL This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). \return CNTP_CVAL Register value */ __STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) { uint64_t result; __get_CP64(15, 2, result, 14); return result; } /** \brief Set CNTP_CTL This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). \param [in] value CNTP_CTL Register value to set */ __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) { __set_CP(15, 0, value, 14, 2, 1); } /** \brief Get CNTP_CTL register \return CNTP_CTL Register value */ __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) { uint32_t result; __get_CP(15, 0, result, 14, 2, 1); return result; } #endif /** \brief Set TLBIALL TLB Invalidate All */ __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) { __set_CP(15, 0, value, 8, 7, 0); } /** \brief Set BPIALL. Branch Predictor Invalidate All */ __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) { __set_CP(15, 0, value, 7, 5, 6); } /** \brief Set ICIALLU Instruction Cache Invalidate All */ __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) { __set_CP(15, 0, value, 7, 5, 0); } /** \brief Set ICIMVAC Instruction Cache Invalidate */ __STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value) { __set_CP(15, 0, value, 7, 5, 1); } /** \brief Set DCCMVAC Data cache clean */ __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) { __set_CP(15, 0, value, 7, 10, 1); } /** \brief Set DCIMVAC Data cache invalidate */ __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) { __set_CP(15, 0, value, 7, 6, 1); } /** \brief Set DCCIMVAC Data cache clean and invalidate */ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) { __set_CP(15, 0, value, 7, 14, 1); } /** \brief Set CSSELR */ __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) { // __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); __set_CP(15, 2, value, 0, 0, 0); } /** \brief Get CSSELR \return CSSELR Register value */ __STATIC_FORCEINLINE uint32_t __get_CSSELR(void) { uint32_t result; // __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 2, result, 0, 0, 0); return result; } /** \brief Set CCSIDR \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. */ CMSIS_DEPRECATED __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) { __set_CSSELR(value); } /** \brief Get CCSIDR \return CCSIDR Register value */ __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) { uint32_t result; // __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); __get_CP(15, 1, result, 0, 0, 0); return result; } /** \brief Get CLIDR \return CLIDR Register value */ __STATIC_FORCEINLINE uint32_t __get_CLIDR(void) { uint32_t result; // __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); __get_CP(15, 1, result, 0, 0, 1); return result; } /** \brief Set DCISW */ __STATIC_FORCEINLINE void __set_DCISW(uint32_t value) { // __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") __set_CP(15, 0, value, 7, 6, 2); } /** \brief Set DCCSW */ __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) { // __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") __set_CP(15, 0, value, 7, 10, 2); } /** \brief Set DCCISW */ __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) { // __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") __set_CP(15, 0, value, 7, 14, 2); } #endif ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V1.3.3 * @date 13. November 2022 ******************************************************************************/ /* * Copyright (c) 2009-2022 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE __attribute__((always_inline)) #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ########################## Core Instruction Access ######################### */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi":::"memory") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe":::"memory") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1, ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1, ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Enable FIQ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } /*@} end of group CMSIS_SIMD_intrinsics */ /** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics Access to dedicated SIMD instructions @{ */ /** \brief Get CPSR Register \return CPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_CPSR(void) { uint32_t result; __ASM volatile("MRS %0, cpsr" : "=r" (result) ); return(result); } /** \brief Set CPSR Register \param [in] cpsr CPSR value to set */ __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) { __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); } /** \brief Get Mode \return Processor Mode */ __STATIC_FORCEINLINE uint32_t __get_mode(void) { return (__get_CPSR() & 0x1FU); } /** \brief Set Mode \param [in] mode Mode value to set */ __STATIC_FORCEINLINE void __set_mode(uint32_t mode) { __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } /** \brief Get Stack Pointer \return Stack Pointer value */ __STATIC_FORCEINLINE uint32_t __get_SP(void) { uint32_t result; __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); return result; } /** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_SP(uint32_t stack) { __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); } /** \brief Get USR/SYS Stack Pointer \return USR/SYS Stack Pointer value */ __STATIC_FORCEINLINE uint32_t __get_SP_usr(void) { uint32_t cpsr = __get_CPSR(); uint32_t result; __ASM volatile( "CPS #0x1F \n" "MOV %0, sp " : "=r"(result) : : "memory" ); __set_CPSR(cpsr); __ISB(); return result; } /** \brief Set USR/SYS Stack Pointer \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) { uint32_t cpsr = __get_CPSR(); __ASM volatile( "CPS #0x1F \n" "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" ); __set_CPSR(cpsr); __ISB(); } /** \brief Get FPEXC \return Floating Point Exception Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPEXC(void) { #if (__FPU_PRESENT == 1) uint32_t result; __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); return(result); #else return(0); #endif } /** \brief Set FPEXC \param [in] fpexc Floating Point Exception Control value to set */ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) { #if (__FPU_PRESENT == 1) __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); #endif } /* * Include common core functions to access Coprocessor 15 registers */ #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" " VMOV D3, R2,R2 \n" " VMOV D4, R2,R2 \n" " VMOV D5, R2,R2 \n" " VMOV D6, R2,R2 \n" " VMOV D7, R2,R2 \n" " VMOV D8, R2,R2 \n" " VMOV D9, R2,R2 \n" " VMOV D10,R2,R2 \n" " VMOV D11,R2,R2 \n" " VMOV D12,R2,R2 \n" " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" #if (defined(__ARM_NEON) && (__ARM_NEON == 1)) //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" " VMOV D19,R2,R2 \n" " VMOV D20,R2,R2 \n" " VMOV D21,R2,R2 \n" " VMOV D22,R2,R2 \n" " VMOV D23,R2,R2 \n" " VMOV D24,R2,R2 \n" " VMOV D25,R2,R2 \n" " VMOV D26,R2,R2 \n" " VMOV D27,R2,R2 \n" " VMOV D28,R2,R2 \n" " VMOV D29,R2,R2 \n" " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" #endif //Initialise FPSCR to a known state " VMRS R1,FPSCR \n" " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R1,R1,R2 \n" " VMSR FPSCR,R1 " : : : "cc", "r1", "r2" ); } /*@} end of group CMSIS_Core_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/cmsis_iccarm.h ================================================ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.0.8 * @date 13. November 2022 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems // Copyright (c) 2018-2019 Arm Limited // // SPDX-License-Identifier: Apache-2.0 // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #pragma language=extended #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_7A__ /* Macro already defined */ #else #if defined(__ARM7A__) #define __ARM_ARCH_7A__ 1 #endif #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #if __ICCARM_V8 #define __RESTRICT __restrict #else /* Needs IAR language extensions */ #define __RESTRICT restrict #endif #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef CMSIS_DEPRECATED #define CMSIS_DEPRECATED __attribute__((deprecated)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #if 0 #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_CPSR() (__arm_rsr("CPSR")) #define __get_mode() (__get_CPSR() & 0x1FU) #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) #define __get_FPEXC() (__arm_rsr("FPEXC")) #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) #define __get_CP64(cp, op1, Rt, CRm) \ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) #define __set_CP64(cp, op1, Rt, CRm) \ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #define __SSAT __iar_builtin_SSAT #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #define __USAT __iar_builtin_USAT #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) #define __get_FPSCR() (0) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #define __NOP __no_operation #define __get_xPSR __get_PSR __IAR_FT void __set_mode(uint32_t mode) { __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } __IAR_FT uint32_t __get_FPEXC(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) uint32_t result; __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); return(result); #else return(0); #endif } __IAR_FT void __set_FPEXC(uint32_t fpexc) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))) __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); #endif } #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) #define __get_CP64(cp, op1, Rt, CRm) \ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) #define __set_CP64(cp, op1, Rt, CRm) \ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) #include "cmsis_cp15.h" #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) __IAR_FT uint32_t __get_SP_usr(void) { uint32_t cpsr; uint32_t result; __ASM volatile( "MRS %0, cpsr \n" "CPS #0x1F \n" // no effect in USR mode "MOV %1, sp \n" "MSR cpsr_c, %2 \n" // no effect in USR mode "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" ); return result; } __IAR_FT void __set_SP_usr(uint32_t topOfProcStack) { uint32_t cpsr; __ASM volatile( "MRS %0, cpsr \n" "CPS #0x1F \n" // no effect in USR mode "MOV sp, %1 \n" "MSR cpsr_c, %2 \n" // no effect in USR mode "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" ); } #define __get_mode() (__get_CPSR() & 0x1FU) __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" " VMOV D3, R2,R2 \n" " VMOV D4, R2,R2 \n" " VMOV D5, R2,R2 \n" " VMOV D6, R2,R2 \n" " VMOV D7, R2,R2 \n" " VMOV D8, R2,R2 \n" " VMOV D9, R2,R2 \n" " VMOV D10,R2,R2 \n" " VMOV D11,R2,R2 \n" " VMOV D12,R2,R2 \n" " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" #ifdef __ARM_ADVANCED_SIMD__ //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" " VMOV D19,R2,R2 \n" " VMOV D20,R2,R2 \n" " VMOV D21,R2,R2 \n" " VMOV D22,R2,R2 \n" " VMOV D23,R2,R2 \n" " VMOV D24,R2,R2 \n" " VMOV D25,R2,R2 \n" " VMOV D26,R2,R2 \n" " VMOV D27,R2,R2 \n" " VMOV D28,R2,R2 \n" " VMOV D29,R2,R2 \n" " VMOV D30,R2,R2 \n" " VMOV D31,R2,R2 \n" #endif //Initialise FPSCR to a known state " VMRS R1,FPSCR \n" " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R1,R1,R2 \n" " VMSR FPSCR,R1 \n" : : : "cc", "r1", "r2" ); } #undef __IAR_FT #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/core_ca.h ================================================ /**************************************************************************//** * @file core_ca.h * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File * @version V1.0.8 * @date 23. March 2023 ******************************************************************************/ /* * Copyright (c) 2009-2022 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CA_H_GENERIC #define __CORE_CA_H_GENERIC #ifdef __cplusplus extern "C" { #endif /******************************************************************************* * CMSIS definitions ******************************************************************************/ /* CMSIS CA definitions */ #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TMS470__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CA_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CA_H_DEPENDANT #define __CORE_CA_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CA_REV #define __CA_REV 0x0000U #warning "__CA_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __GIC_PRESENT #define __GIC_PRESENT 1U #warning "__GIC_PRESENT not defined in device header file; using default!" #endif #ifndef __TIM_PRESENT #define __TIM_PRESENT 1U #warning "__TIM_PRESENT not defined in device header file; using default!" #endif #ifndef __L2C_PRESENT #define __L2C_PRESENT 0U #warning "__L2C_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ #ifdef __cplusplus #define __I volatile /*!< \brief Defines 'read only' permissions */ #else #define __I volatile const /*!< \brief Defines 'read only' permissions */ #endif #define __O volatile /*!< \brief Defines 'write only' permissions */ #define __IO volatile /*!< \brief Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas /******************************************************************************* * Register Abstraction Core Register contain: - CPSR - CP15 Registers - L2C-310 Cache Controller - Generic Interrupt Controller Distributor - Generic Interrupt Controller Interface ******************************************************************************/ /* Core Register CPSR */ typedef union { struct { uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ RESERVED(0:4, uint32_t) uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } CPSR_Type; /* CPSR Register Definitions */ #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ /* CP15 Register SCTLR */ typedef union { struct { uint32_t M:1; /*!< \brief bit: 0 MMU enable */ uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ uint32_t C:1; /*!< \brief bit: 2 Cache enable */ RESERVED(0:2, uint32_t) uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ RESERVED(1:1, uint32_t) uint32_t B:1; /*!< \brief bit: 7 Endianness model */ RESERVED(2:2, uint32_t) uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ RESERVED(3:2, uint32_t) uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ RESERVED(4:1, uint32_t) uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ uint32_t U:1; /*!< \brief bit: 22 Alignment model */ RESERVED(5:1, uint32_t) uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ RESERVED(6:1, uint32_t) uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ RESERVED(7:1, uint32_t) } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } SCTLR_Type; #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ /* CP15 Register ACTLR */ typedef union { #if __CORTEX_A == 5 || defined(DOXYGEN) /** \brief Structure used for bit access on Cortex-A5 */ struct { uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ RESERVED(0:5, uint32_t) uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ RESERVED(1:2, uint32_t) uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ RESERVED(3:9, uint32_t) uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ RESERVED(7:3, uint32_t) } b; #endif #if __CORTEX_A == 7 || defined(DOXYGEN) /** \brief Structure used for bit access on Cortex-A7 */ struct { RESERVED(0:6, uint32_t) uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ RESERVED(1:3, uint32_t) uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ RESERVED(3:12, uint32_t) uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ RESERVED(7:3, uint32_t) } b; #endif #if __CORTEX_A == 9 || defined(DOXYGEN) /** \brief Structure used for bit access on Cortex-A9 */ struct { uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ RESERVED(0:1, uint32_t) uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ RESERVED(1:2, uint32_t) uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ RESERVED(7:22, uint32_t) } b; #endif uint32_t w; /*!< \brief Type used for word access */ } ACTLR_Type; #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ /* CP15 Register CPACR */ typedef union { struct { uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ RESERVED(0:1, uint32_t) uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } CPACR_Type; #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ /* CP15 Register DFSR */ typedef union { struct { uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ RESERVED(0:1, uint32_t) uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ RESERVED(1:18, uint32_t) } s; /*!< \brief Structure used for bit access in short format */ struct { uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ RESERVED(0:3, uint32_t) uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ RESERVED(1:1, uint32_t) uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ RESERVED(2:18, uint32_t) } l; /*!< \brief Structure used for bit access in long format */ uint32_t w; /*!< \brief Type used for word access */ } DFSR_Type; #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ /* CP15 Register IFSR */ typedef union { struct { uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ RESERVED(0:5, uint32_t) uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ RESERVED(1:1, uint32_t) uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ RESERVED(2:19, uint32_t) } s; /*!< \brief Structure used for bit access in short format */ struct { uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ RESERVED(0:3, uint32_t) uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ RESERVED(1:2, uint32_t) uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ RESERVED(2:19, uint32_t) } l; /*!< \brief Structure used for bit access in long format */ uint32_t w; /*!< \brief Type used for word access */ } IFSR_Type; #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ /* CP15 Register ISR */ typedef union { struct { RESERVED(0:6, uint32_t) uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ RESERVED(1:23, uint32_t) } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } ISR_Type; #define ISR_A_Pos 13U /*!< \brief ISR: A Position */ #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ #define ISR_I_Pos 12U /*!< \brief ISR: I Position */ #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ #define ISR_F_Pos 11U /*!< \brief ISR: F Position */ #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ /* DACR Register */ #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ /** \brief Mask and shift a bit field value for use in a register bit range. \param [in] field Name of the register bit field. \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param [in] field Name of the register bit field. \param [in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /** \brief Union type to access the L2C_310 Cache Controller. */ #if (__L2C_PRESENT == 1U) || defined(DOXYGEN) typedef struct { __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ RESERVED(0[0x3e], uint32_t) __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ RESERVED(1[0x3e], uint32_t) __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ RESERVED(2[0x2], uint32_t) __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ RESERVED(3[0x143], uint32_t) __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ RESERVED(4[0xf], uint32_t) __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ RESERVED(6[2], uint32_t) __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ RESERVED(5[0xc], uint32_t) __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ RESERVED(7[1], uint32_t) __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ RESERVED(8[0xc], uint32_t) __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ RESERVED(9[1], uint32_t) __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ RESERVED(10[0x40], uint32_t) __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ RESERVED(11[0x4], uint32_t) __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ RESERVED(12[0xaa], uint32_t) __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ RESERVED(13[0xce], uint32_t) __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ } L2C_310_TypeDef; #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ #endif #if (__GIC_PRESENT == 1U) || defined(DOXYGEN) /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) */ typedef struct { __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ RESERVED(0, uint32_t) __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ RESERVED(1[11], uint32_t) __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ RESERVED(2, uint32_t) __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ RESERVED(3, uint32_t) __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ RESERVED(4, uint32_t) __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ RESERVED(5[9], uint32_t) __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ RESERVED(6, uint32_t) __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ RESERVED(7, uint32_t) __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ RESERVED(8[32], uint32_t) __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ RESERVED(9[3], uint32_t) __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ RESERVED(10[5236], uint32_t) __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ } GICDistributor_Type; #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ /* GICDistributor CTLR Register */ #define GICDistributor_CTLR_EnableGrp0_Pos 0U /*!< GICDistributor CTLR: EnableGrp0 Position */ #define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/) /*!< GICDistributor CTLR: EnableGrp0 Mask */ #define GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk) #define GICDistributor_CTLR_EnableGrp1_Pos 1U /*!< GICDistributor CTLR: EnableGrp1 Position */ #define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos) /*!< GICDistributor CTLR: EnableGrp1 Mask */ #define GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk) #define GICDistributor_CTLR_ARE_Pos 4U /*!< GICDistributor CTLR: ARE Position */ #define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos) /*!< GICDistributor CTLR: ARE Mask */ #define GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk) #define GICDistributor_CTLR_DC_Pos 6U /*!< GICDistributor CTLR: DC Position */ #define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos) /*!< GICDistributor CTLR: DC Mask */ #define GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk) #define GICDistributor_CTLR_EINWF_Pos 7U /*!< GICDistributor CTLR: EINWF Position */ #define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos) /*!< GICDistributor CTLR: EINWF Mask */ #define GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk) #define GICDistributor_CTLR_RWP_Pos 31U /*!< GICDistributor CTLR: RWP Position */ #define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos) /*!< GICDistributor CTLR: RWP Mask */ #define GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk) /* GICDistributor TYPER Register */ #define GICDistributor_TYPER_ITLinesNumber_Pos 0U /*!< GICDistributor TYPER: ITLinesNumber Position */ #define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */ #define GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk) #define GICDistributor_TYPER_CPUNumber_Pos 5U /*!< GICDistributor TYPER: CPUNumber Position */ #define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos) /*!< GICDistributor TYPER: CPUNumber Mask */ #define GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk) #define GICDistributor_TYPER_SecurityExtn_Pos 10U /*!< GICDistributor TYPER: SecurityExtn Position */ #define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos) /*!< GICDistributor TYPER: SecurityExtn Mask */ #define GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk) #define GICDistributor_TYPER_LSPI_Pos 11U /*!< GICDistributor TYPER: LSPI Position */ #define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos) /*!< GICDistributor TYPER: LSPI Mask */ #define GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk) /* GICDistributor IIDR Register */ #define GICDistributor_IIDR_Implementer_Pos 0U /*!< GICDistributor IIDR: Implementer Position */ #define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/) /*!< GICDistributor IIDR: Implementer Mask */ #define GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk) #define GICDistributor_IIDR_Revision_Pos 12U /*!< GICDistributor IIDR: Revision Position */ #define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos) /*!< GICDistributor IIDR: Revision Mask */ #define GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk) #define GICDistributor_IIDR_Variant_Pos 16U /*!< GICDistributor IIDR: Variant Position */ #define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos) /*!< GICDistributor IIDR: Variant Mask */ #define GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk) #define GICDistributor_IIDR_ProductID_Pos 24U /*!< GICDistributor IIDR: ProductID Position */ #define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos) /*!< GICDistributor IIDR: ProductID Mask */ #define GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk) /* GICDistributor STATUSR Register */ #define GICDistributor_STATUSR_RRD_Pos 0U /*!< GICDistributor STATUSR: RRD Position */ #define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/) /*!< GICDistributor STATUSR: RRD Mask */ #define GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk) #define GICDistributor_STATUSR_WRD_Pos 1U /*!< GICDistributor STATUSR: WRD Position */ #define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos) /*!< GICDistributor STATUSR: WRD Mask */ #define GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk) #define GICDistributor_STATUSR_RWOD_Pos 2U /*!< GICDistributor STATUSR: RWOD Position */ #define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos) /*!< GICDistributor STATUSR: RWOD Mask */ #define GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk) #define GICDistributor_STATUSR_WROD_Pos 3U /*!< GICDistributor STATUSR: WROD Position */ #define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos) /*!< GICDistributor STATUSR: WROD Mask */ #define GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk) /* GICDistributor SETSPI_NSR Register */ #define GICDistributor_SETSPI_NSR_INTID_Pos 0U /*!< GICDistributor SETSPI_NSR: INTID Position */ #define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/) /*!< GICDistributor SETSPI_NSR: INTID Mask */ #define GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk) /* GICDistributor CLRSPI_NSR Register */ #define GICDistributor_CLRSPI_NSR_INTID_Pos 0U /*!< GICDistributor CLRSPI_NSR: INTID Position */ #define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/) /*!< GICDistributor CLRSPI_NSR: INTID Mask */ #define GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk) /* GICDistributor SETSPI_SR Register */ #define GICDistributor_SETSPI_SR_INTID_Pos 0U /*!< GICDistributor SETSPI_SR: INTID Position */ #define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/) /*!< GICDistributor SETSPI_SR: INTID Mask */ #define GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk) /* GICDistributor CLRSPI_SR Register */ #define GICDistributor_CLRSPI_SR_INTID_Pos 0U /*!< GICDistributor CLRSPI_SR: INTID Position */ #define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/) /*!< GICDistributor CLRSPI_SR: INTID Mask */ #define GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk) /* GICDistributor ITARGETSR Register */ #define GICDistributor_ITARGETSR_CPU0_Pos 0U /*!< GICDistributor ITARGETSR: CPU0 Position */ #define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/) /*!< GICDistributor ITARGETSR: CPU0 Mask */ #define GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk) #define GICDistributor_ITARGETSR_CPU1_Pos 1U /*!< GICDistributor ITARGETSR: CPU1 Position */ #define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos) /*!< GICDistributor ITARGETSR: CPU1 Mask */ #define GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk) #define GICDistributor_ITARGETSR_CPU2_Pos 2U /*!< GICDistributor ITARGETSR: CPU2 Position */ #define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos) /*!< GICDistributor ITARGETSR: CPU2 Mask */ #define GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk) #define GICDistributor_ITARGETSR_CPU3_Pos 3U /*!< GICDistributor ITARGETSR: CPU3 Position */ #define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos) /*!< GICDistributor ITARGETSR: CPU3 Mask */ #define GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk) #define GICDistributor_ITARGETSR_CPU4_Pos 4U /*!< GICDistributor ITARGETSR: CPU4 Position */ #define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos) /*!< GICDistributor ITARGETSR: CPU4 Mask */ #define GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk) #define GICDistributor_ITARGETSR_CPU5_Pos 5U /*!< GICDistributor ITARGETSR: CPU5 Position */ #define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos) /*!< GICDistributor ITARGETSR: CPU5 Mask */ #define GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk) #define GICDistributor_ITARGETSR_CPU6_Pos 6U /*!< GICDistributor ITARGETSR: CPU6 Position */ #define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos) /*!< GICDistributor ITARGETSR: CPU6 Mask */ #define GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk) #define GICDistributor_ITARGETSR_CPU7_Pos 7U /*!< GICDistributor ITARGETSR: CPU7 Position */ #define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos) /*!< GICDistributor ITARGETSR: CPU7 Mask */ #define GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk) /* GICDistributor SGIR Register */ #define GICDistributor_SGIR_INTID_Pos 0U /*!< GICDistributor SGIR: INTID Position */ #define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/) /*!< GICDistributor SGIR: INTID Mask */ #define GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk) #define GICDistributor_SGIR_NSATT_Pos 15U /*!< GICDistributor SGIR: NSATT Position */ #define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos) /*!< GICDistributor SGIR: NSATT Mask */ #define GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk) #define GICDistributor_SGIR_CPUTargetList_Pos 16U /*!< GICDistributor SGIR: CPUTargetList Position */ #define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos) /*!< GICDistributor SGIR: CPUTargetList Mask */ #define GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk) #define GICDistributor_SGIR_TargetFilterList_Pos 24U /*!< GICDistributor SGIR: TargetFilterList Position */ #define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */ #define GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk) /* GICDistributor IROUTER Register */ #define GICDistributor_IROUTER_Aff0_Pos 0UL /*!< GICDistributor IROUTER: Aff0 Position */ #define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/) /*!< GICDistributor IROUTER: Aff0 Mask */ #define GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk) #define GICDistributor_IROUTER_Aff1_Pos 8UL /*!< GICDistributor IROUTER: Aff1 Position */ #define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos) /*!< GICDistributor IROUTER: Aff1 Mask */ #define GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk) #define GICDistributor_IROUTER_Aff2_Pos 16UL /*!< GICDistributor IROUTER: Aff2 Position */ #define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos) /*!< GICDistributor IROUTER: Aff2 Mask */ #define GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk) #define GICDistributor_IROUTER_IRM_Pos 31UL /*!< GICDistributor IROUTER: IRM Position */ #define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos) /*!< GICDistributor IROUTER: IRM Mask */ #define GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk) #define GICDistributor_IROUTER_Aff3_Pos 32UL /*!< GICDistributor IROUTER: Aff3 Position */ #define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos) /*!< GICDistributor IROUTER: Aff3 Mask */ #define GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk) /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) */ typedef struct { __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ RESERVED(1[40], uint32_t) __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ RESERVED(2[3], uint32_t) __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ RESERVED(3[960], uint32_t) __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ } GICInterface_Type; #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ /* GICInterface CTLR Register */ #define GICInterface_CTLR_Enable_Pos 0U /*!< PTIM CTLR: Enable Position */ #define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/) /*!< PTIM CTLR: Enable Mask */ #define GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk) /* GICInterface PMR Register */ #define GICInterface_PMR_Priority_Pos 0U /*!< PTIM PMR: Priority Position */ #define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/) /*!< PTIM PMR: Priority Mask */ #define GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk) /* GICInterface BPR Register */ #define GICInterface_BPR_Binary_Point_Pos 0U /*!< PTIM BPR: Binary_Point Position */ #define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */ #define GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk) /* GICInterface IAR Register */ #define GICInterface_IAR_INTID_Pos 0U /*!< PTIM IAR: INTID Position */ #define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/) /*!< PTIM IAR: INTID Mask */ #define GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk) /* GICInterface EOIR Register */ #define GICInterface_EOIR_INTID_Pos 0U /*!< PTIM EOIR: INTID Position */ #define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/) /*!< PTIM EOIR: INTID Mask */ #define GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk) /* GICInterface RPR Register */ #define GICInterface_RPR_INTID_Pos 0U /*!< PTIM RPR: INTID Position */ #define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/) /*!< PTIM RPR: INTID Mask */ #define GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk) /* GICInterface HPPIR Register */ #define GICInterface_HPPIR_INTID_Pos 0U /*!< PTIM HPPIR: INTID Position */ #define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/) /*!< PTIM HPPIR: INTID Mask */ #define GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk) /* GICInterface ABPR Register */ #define GICInterface_ABPR_Binary_Point_Pos 0U /*!< PTIM ABPR: Binary_Point Position */ #define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */ #define GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk) /* GICInterface AIAR Register */ #define GICInterface_AIAR_INTID_Pos 0U /*!< PTIM AIAR: INTID Position */ #define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/) /*!< PTIM AIAR: INTID Mask */ #define GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk) /* GICInterface AEOIR Register */ #define GICInterface_AEOIR_INTID_Pos 0U /*!< PTIM AEOIR: INTID Position */ #define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */ #define GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk) /* GICInterface AHPPIR Register */ #define GICInterface_AHPPIR_INTID_Pos 0U /*!< PTIM AHPPIR: INTID Position */ #define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */ #define GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk) /* GICInterface STATUSR Register */ #define GICInterface_STATUSR_RRD_Pos 0U /*!< GICInterface STATUSR: RRD Position */ #define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/) /*!< GICInterface STATUSR: RRD Mask */ #define GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk) #define GICInterface_STATUSR_WRD_Pos 1U /*!< GICInterface STATUSR: WRD Position */ #define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos) /*!< GICInterface STATUSR: WRD Mask */ #define GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk) #define GICInterface_STATUSR_RWOD_Pos 2U /*!< GICInterface STATUSR: RWOD Position */ #define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos) /*!< GICInterface STATUSR: RWOD Mask */ #define GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk) #define GICInterface_STATUSR_WROD_Pos 3U /*!< GICInterface STATUSR: WROD Position */ #define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos) /*!< GICInterface STATUSR: WROD Mask */ #define GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk) #define GICInterface_STATUSR_ASV_Pos 4U /*!< GICInterface STATUSR: ASV Position */ #define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos) /*!< GICInterface STATUSR: ASV Mask */ #define GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk) /* GICInterface IIDR Register */ #define GICInterface_IIDR_Implementer_Pos 0U /*!< GICInterface IIDR: Implementer Position */ #define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/) /*!< GICInterface IIDR: Implementer Mask */ #define GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk) #define GICInterface_IIDR_Revision_Pos 12U /*!< GICInterface IIDR: Revision Position */ #define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos) /*!< GICInterface IIDR: Revision Mask */ #define GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk) #define GICInterface_IIDR_Arch_version_Pos 16U /*!< GICInterface IIDR: Arch_version Position */ #define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos) /*!< GICInterface IIDR: Arch_version Mask */ #define GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk) #define GICInterface_IIDR_ProductID_Pos 20U /*!< GICInterface IIDR: ProductID Position */ #define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos) /*!< GICInterface IIDR: ProductID Mask */ #define GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk) /* GICInterface DIR Register */ #define GICInterface_DIR_INTID_Pos 0U /*!< PTIM DIR: INTID Position */ #define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/) /*!< PTIM DIR: INTID Mask */ #define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk) #endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */ #if (__TIM_PRESENT == 1U) || defined(DOXYGEN) #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) /** \brief Structure type to access the Private Timer */ typedef struct { __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register RESERVED(0[4], uint32_t) __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register } Timer_Type; #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ /* PTIM Control Register */ #define PTIM_CONTROL_Enable_Pos 0U /*!< PTIM CONTROL: Enable Position */ #define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/) /*!< PTIM CONTROL: Enable Mask */ #define PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk) #define PTIM_CONTROL_AutoReload_Pos 1U /*!< PTIM CONTROL: Auto Reload Position */ #define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos) /*!< PTIM CONTROL: Auto Reload Mask */ #define PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk) #define PTIM_CONTROL_IRQenable_Pos 2U /*!< PTIM CONTROL: IRQ Enabel Position */ #define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos) /*!< PTIM CONTROL: IRQ Enabel Mask */ #define PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk) #define PTIM_CONTROL_Prescaler_Pos 8U /*!< PTIM CONTROL: Prescaler Position */ #define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos) /*!< PTIM CONTROL: Prescaler Mask */ #define PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk) /* WCONTROL Watchdog Control Register */ #define PTIM_WCONTROL_Enable_Pos 0U /*!< PTIM WCONTROL: Enable Position */ #define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/) /*!< PTIM WCONTROL: Enable Mask */ #define PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk) #define PTIM_WCONTROL_AutoReload_Pos 1U /*!< PTIM WCONTROL: Auto Reload Position */ #define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos) /*!< PTIM WCONTROL: Auto Reload Mask */ #define PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk) #define PTIM_WCONTROL_IRQenable_Pos 2U /*!< PTIM WCONTROL: IRQ Enable Position */ #define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos) /*!< PTIM WCONTROL: IRQ Enable Mask */ #define PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk) #define PTIM_WCONTROL_Mode_Pos 3U /*!< PTIM WCONTROL: Watchdog Mode Position */ #define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos) /*!< PTIM WCONTROL: Watchdog Mode Mask */ #define PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk) #define PTIM_WCONTROL_Presacler_Pos 8U /*!< PTIM WCONTROL: Prescaler Position */ #define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos) /*!< PTIM WCONTROL: Prescaler Mask */ #define PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk) /* WISR Watchdog Interrupt Status Register */ #define PTIM_WISR_EventFlag_Pos 0U /*!< PTIM WISR: Event Flag Position */ #define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/) /*!< PTIM WISR: Event Flag Mask */ #define PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk) /* WRESET Watchdog Reset Status */ #define PTIM_WRESET_ResetFlag_Pos 0U /*!< PTIM WRESET: Reset Flag Position */ #define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/) /*!< PTIM WRESET: Reset Flag Mask */ #define PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk) #endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */ #endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - L1 Cache Functions - L2C-310 Cache Controller Functions - PL1 Timer Functions - GIC Functions - MMU Functions ******************************************************************************/ /* ########################## L1 Cache functions ################################# */ /** \brief Enable Caches by setting I and C bits in SCTLR register. */ __STATIC_FORCEINLINE void L1C_EnableCaches(void) { __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); __ISB(); } /** \brief Disable Caches by clearing I and C bits in SCTLR register. */ __STATIC_FORCEINLINE void L1C_DisableCaches(void) { __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); __ISB(); } /** \brief Enable Branch Prediction by setting Z bit in SCTLR register. */ __STATIC_FORCEINLINE void L1C_EnableBTAC(void) { __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); __ISB(); } /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. */ __STATIC_FORCEINLINE void L1C_DisableBTAC(void) { __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); __ISB(); } /** \brief Invalidate entire branch predictor array */ __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { __set_BPIALL(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new state } /** \brief Clean instruction cache line by address. * \param [in] va Pointer to instructions to clear the cache for. */ __STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) { __set_ICIMVAC((uint32_t)va); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new I cache state } /** \brief Invalidate the whole instruction cache */ __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { __set_ICIALLU(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new I cache state } /** \brief Clean data cache line by address. * \param [in] va Pointer to data to clear the cache for. */ __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { __set_DCCMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } /** \brief Invalidate data cache line by address. * \param [in] va Pointer to data to invalidate the cache for. */ __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { __set_DCIMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } /** \brief Clean and Invalidate data cache by address. * \param [in] va Pointer to data to invalidate the cache for. */ __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { __set_DCCIMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } /** \brief Calculate log2 rounded up * - log(0) => 0 * - log(1) => 0 * - log(2) => 1 * - log(3) => 2 * - log(4) => 2 * - log(5) => 3 * : : * - log(16) => 4 * - log(32) => 5 * : : * \param [in] n input value parameter * \return log2(n) */ __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) { if (n < 2U) { return 0U; } uint8_t log = 0U; uint32_t t = n; while(t > 1U) { log++; t >>= 1U; } if (n & 1U) { log++; } return log; } /** \brief Apply cache maintenance to given cache level. * \param [in] level cache level to be maintained * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) { uint32_t Dummy; uint32_t ccsidr; uint32_t num_sets; uint32_t num_ways; uint32_t shift_way; uint32_t log2_linesize; int32_t log2_num_ways; Dummy = level << 1U; /* set csselr, select ccsidr register */ __set_CSSELR(Dummy); /* get current ccsidr register */ ccsidr = __get_CCSIDR(); num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; log2_num_ways = __log2_up(num_ways); if ((log2_num_ways < 0) || (log2_num_ways > 32)) { return; // FATAL ERROR } shift_way = 32U - (uint32_t)log2_num_ways; for(int32_t way = num_ways-1; way >= 0; way--) { for(int32_t set = num_sets-1; set >= 0; set--) { Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); switch (maint) { case 0U: __set_DCISW(Dummy); break; case 1U: __set_DCCSW(Dummy); break; default: __set_DCCISW(Dummy); break; } } } __DMB(); } /** \brief Clean and Invalidate the entire data or unified cache * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { uint32_t clidr; uint32_t cache_type; clidr = __get_CLIDR(); for(uint32_t i = 0U; i<7U; i++) { cache_type = (clidr >> i*3U) & 0x7UL; if ((cache_type >= 2U) && (cache_type <= 4U)) { __L1C_MaintainDCacheSetWay(i, op); } } } /** \brief Clean and Invalidate the entire data or unified cache * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean * \deprecated Use generic L1C_CleanInvalidateCache instead. */ CMSIS_DEPRECATED __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { L1C_CleanInvalidateCache(op); } /** \brief Invalidate the whole data cache. */ __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { L1C_CleanInvalidateCache(0); } /** \brief Clean the whole data cache. */ __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { L1C_CleanInvalidateCache(1); } /** \brief Clean and invalidate the whole data cache. */ __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { L1C_CleanInvalidateCache(2); } /* ########################## L2 Cache functions ################################# */ #if (__L2C_PRESENT == 1U) || defined(DOXYGEN) /** \brief Cache Sync operation by writing CACHE_SYNC register. */ __STATIC_INLINE void L2C_Sync(void) { L2C_310->CACHE_SYNC = 0x0; } /** \brief Read cache controller cache ID from CACHE_ID register. * \return L2C_310_TypeDef::CACHE_ID */ __STATIC_INLINE int L2C_GetID (void) { return L2C_310->CACHE_ID; } /** \brief Read cache controller cache type from CACHE_TYPE register. * \return L2C_310_TypeDef::CACHE_TYPE */ __STATIC_INLINE int L2C_GetType (void) { return L2C_310->CACHE_TYPE; } /** \brief Invalidate all cache by way */ __STATIC_INLINE void L2C_InvAllByWay (void) { unsigned int assoc; if (L2C_310->AUX_CNT & (1U << 16U)) { assoc = 16U; } else { assoc = 8U; } L2C_310->INV_WAY = (1U << assoc) - 1U; while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate L2C_Sync(); } /** \brief Clean and Invalidate all cache by way */ __STATIC_INLINE void L2C_CleanInvAllByWay (void) { unsigned int assoc; if (L2C_310->AUX_CNT & (1U << 16U)) { assoc = 16U; } else { assoc = 8U; } L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate L2C_Sync(); } /** \brief Enable Level 2 Cache */ __STATIC_INLINE void L2C_Enable(void) { L2C_310->CONTROL = 0; L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; L2C_310->DEBUG_CONTROL = 0; L2C_310->DATA_LOCK_0_WAY = 0; L2C_310->CACHE_SYNC = 0; L2C_310->CONTROL = 0x01; L2C_Sync(); } /** \brief Disable Level 2 Cache */ __STATIC_INLINE void L2C_Disable(void) { L2C_310->CONTROL = 0x00; L2C_Sync(); } /** \brief Invalidate cache by physical address * \param [in] pa Pointer to data to invalidate cache for. */ __STATIC_INLINE void L2C_InvPa (void *pa) { L2C_310->INV_LINE_PA = (unsigned int)pa; L2C_Sync(); } /** \brief Clean cache by physical address * \param [in] pa Pointer to data to invalidate cache for. */ __STATIC_INLINE void L2C_CleanPa (void *pa) { L2C_310->CLEAN_LINE_PA = (unsigned int)pa; L2C_Sync(); } /** \brief Clean and invalidate cache by physical address * \param [in] pa Pointer to data to invalidate cache for. */ __STATIC_INLINE void L2C_CleanInvPa (void *pa) { L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; L2C_Sync(); } #endif /* ########################## GIC functions ###################################### */ #if (__GIC_PRESENT == 1U) || defined(DOXYGEN) /** \brief Enable the interrupt distributor using the GIC's CTLR register. */ __STATIC_INLINE void GIC_EnableDistributor(void) { GICDistributor->CTLR |= 1U; } /** \brief Disable the interrupt distributor using the GIC's CTLR register. */ __STATIC_INLINE void GIC_DisableDistributor(void) { GICDistributor->CTLR &=~1U; } /** \brief Read the GIC's TYPER register. * \return GICDistributor_Type::TYPER */ __STATIC_INLINE uint32_t GIC_DistributorInfo(void) { return (GICDistributor->TYPER); } /** \brief Reads the GIC's IIDR register. * \return GICDistributor_Type::IIDR */ __STATIC_INLINE uint32_t GIC_DistributorImplementer(void) { return (GICDistributor->IIDR); } /** \brief Sets the GIC's ITARGETSR register for the given interrupt. * \param [in] IRQn Interrupt to be configured. * \param [in] cpu_target CPU interfaces to assign this interrupt to. */ __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) { uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); } /** \brief Read the GIC's ITARGETSR register. * \param [in] IRQn Interrupt to acquire the configuration for. * \return GICDistributor_Type::ITARGETSR */ __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) { return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; } /** \brief Enable the CPU's interrupt interface. */ __STATIC_INLINE void GIC_EnableInterface(void) { GICInterface->CTLR |= 1U; //enable interface } /** \brief Disable the CPU's interrupt interface. */ __STATIC_INLINE void GIC_DisableInterface(void) { GICInterface->CTLR &=~1U; //disable distributor } /** \brief Read the CPU's IAR register. * \return GICInterface_Type::IAR */ __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) { return (IRQn_Type)(GICInterface->IAR); } /** \brief Writes the given interrupt number to the CPU's EOIR register. * \param [in] IRQn The interrupt to be signaled as finished. */ __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) { GICInterface->EOIR = IRQn; } /** \brief Enables the given interrupt using GIC's ISENABLER register. * \param [in] IRQn The interrupt to be enabled. */ __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) { GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); } /** \brief Get interrupt enable status using GIC's ISENABLER register. * \param [in] IRQn The interrupt to be queried. * \return 0 - interrupt is not enabled, 1 - interrupt is enabled. */ __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) { return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; } /** \brief Disables the given interrupt using GIC's ICENABLER register. * \param [in] IRQn The interrupt to be disabled. */ __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) { GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); } /** \brief Get interrupt pending status from GIC's ISPENDR register. * \param [in] IRQn The interrupt to be queried. * \return 0 - interrupt is not pending, 1 - interrupt is pendig. */ __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) { uint32_t pend; if (IRQn >= 16U) { pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; } else { // INTID 0-15 Software Generated Interrupt pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; // No CPU identification offered if (pend != 0U) { pend = 1U; } else { pend = 0U; } } return (pend); } /** \brief Sets the given interrupt as pending using GIC's ISPENDR register. * \param [in] IRQn The interrupt to be enabled. */ __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) { if (IRQn >= 16U) { GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); } else { // INTID 0-15 Software Generated Interrupt // Forward the interrupt to the CPU interface that requested it GICDistributor->SGIR = (IRQn | 0x02000000U); } } /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. * \param [in] IRQn The interrupt to be enabled. */ __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) { if (IRQn >= 16U) { GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); } else { // INTID 0-15 Software Generated Interrupt GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); } } /** \brief Sets the interrupt configuration using GIC's ICFGR register. * \param [in] IRQn The interrupt to be configured. * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) * Bit 1: 0 - level sensitive, 1 - edge triggered */ __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) { uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; /* read current register content */ uint32_t shift = (IRQn % 16U) << 1U; /* calculate shift value */ int_config &= 3U; /* only 2 bits are valid */ icfgr &= (~(3U << shift)); /* clear bits to change */ icfgr |= ( int_config << shift); /* set new configuration */ GICDistributor->ICFGR[IRQn / 16U] = icfgr; /* write new register content */ } /** \brief Get the interrupt configuration from the GIC's ICFGR register. * \param [in] IRQn Interrupt to acquire the configuration for. * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) * Bit 1: 0 - level sensitive, 1 - edge triggered */ __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) { return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); } /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. * \param [in] IRQn The interrupt to be configured. * \param [in] priority The priority for the interrupt, lower values denote higher priorities. */ __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); } /** \brief Read the current interrupt priority from GIC's IPRIORITYR register. * \param [in] IRQn The interrupt to be queried. */ __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) { return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; } /** \brief Set the interrupt priority mask using CPU's PMR register. * \param [in] priority Priority mask to be set. */ __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) { GICInterface->PMR = priority & 0xFFUL; //set priority mask } /** \brief Read the current interrupt priority mask from CPU's PMR register. * \result GICInterface_Type::PMR */ __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) { return GICInterface->PMR; } /** \brief Configures the group priority and subpriority split point using CPU's BPR register. * \param [in] binary_point Amount of bits used as subpriority. */ __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) { GICInterface->BPR = binary_point & 7U; //set binary point } /** \brief Read the current group priority and subpriority split point from CPU's BPR register. * \return GICInterface_Type::BPR */ __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) { return GICInterface->BPR; } /** \brief Get the status for a given interrupt. * \param [in] IRQn The interrupt to get status for. * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active */ __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) { uint32_t pending, active; active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; return ((active<<1U) | pending); } /** \brief Generate a software interrupt using GIC's SGIR register. * \param [in] IRQn Software interrupt to be generated. * \param [in] target_list List of CPUs the software interrupt should be forwarded to. * \param [in] filter_list Filter to be applied to determine interrupt receivers. */ __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) { GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); } /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. * \return GICInterface_Type::HPPIR */ __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) { return GICInterface->HPPIR; } /** \brief Provides information about the implementer and revision of the CPU interface. * \return GICInterface_Type::IIDR */ __STATIC_INLINE uint32_t GIC_GetInterfaceId(void) { return GICInterface->IIDR; } /** \brief Set the interrupt group from the GIC's IGROUPR register. * \param [in] IRQn The interrupt to be queried. * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 */ __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) { uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; uint32_t shift = (IRQn % 32U); igroupr &= (~(1U << shift)); igroupr |= ( (group & 1U) << shift); GICDistributor->IGROUPR[IRQn / 32U] = igroupr; } #define GIC_SetSecurity GIC_SetGroup /** \brief Get the interrupt group from the GIC's IGROUPR register. * \param [in] IRQn The interrupt to be queried. * \return 0 - Group 0, 1 - Group 1 */ __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) { return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; } #define GIC_GetSecurity GIC_GetGroup /** \brief Initialize the interrupt distributor. */ __STATIC_INLINE void GIC_DistInit(void) { uint32_t i; uint32_t num_irq = 0U; uint32_t priority_field; //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, //configuring all of the interrupts as Secure. //Disable interrupt forwarding GIC_DisableDistributor(); //Get the maximum number of interrupts that the GIC supports num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); /* Priority level is implementation defined. To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ GIC_SetPriority((IRQn_Type)0U, 0xFFU); priority_field = GIC_GetPriority((IRQn_Type)0U); for (i = 32U; i < num_irq; i++) { //Disable the SPI interrupt GIC_DisableIRQ((IRQn_Type)i); //Set level-sensitive (and N-N model) GIC_SetConfiguration((IRQn_Type)i, 0U); //Set priority GIC_SetPriority((IRQn_Type)i, priority_field/2U); //Set target list to CPU0 GIC_SetTarget((IRQn_Type)i, 1U); } //Enable distributor GIC_EnableDistributor(); } /** \brief Initialize the CPU's interrupt interface */ __STATIC_INLINE void GIC_CPUInterfaceInit(void) { uint32_t i; uint32_t priority_field; //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, //configuring all of the interrupts as Secure. //Disable interrupt forwarding GIC_DisableInterface(); /* Priority level is implementation defined. To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ GIC_SetPriority((IRQn_Type)0U, 0xFFU); priority_field = GIC_GetPriority((IRQn_Type)0U); //SGI and PPI for (i = 0U; i < 32U; i++) { if(i > 15U) { //Set level-sensitive (and N-N model) for PPI GIC_SetConfiguration((IRQn_Type)i, 0U); } //Disable SGI and PPI interrupts GIC_DisableIRQ((IRQn_Type)i); //Set priority GIC_SetPriority((IRQn_Type)i, priority_field/2U); } //Enable interface GIC_EnableInterface(); //Set binary point to 0 GIC_SetBinaryPoint(0U); //Set priority mask GIC_SetInterfacePriorityMask(0xFFU); } /** \brief Initialize and enable the GIC */ __STATIC_INLINE void GIC_Enable(void) { GIC_DistInit(); GIC_CPUInterfaceInit(); //per CPU } #endif /* ########################## Generic Timer functions ############################ */ #if (__TIM_PRESENT == 1U) || defined(DOXYGEN) /* PL1 Physical Timer */ #if (__CORTEX_A == 7U) || defined(DOXYGEN) /** \brief Physical Timer Control register */ typedef union { struct { uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ RESERVED(0:29, uint32_t) } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } CNTP_CTL_Type; /** \brief Configures the frequency the timer shall run at. * \param [in] value The timer frequency in Hz. */ __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) { __set_CNTFRQ(value); __ISB(); } /** \brief Sets the reset value of the timer. * \param [in] value The value the timer is loaded with. */ __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) { __set_CNTP_TVAL(value); __ISB(); } /** \brief Get the current counter value. * \return Current counter value. */ __STATIC_INLINE uint32_t PL1_GetCurrentValue(void) { return(__get_CNTP_TVAL()); } /** \brief Get the current physical counter value. * \return Current physical counter value. */ __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) { return(__get_CNTPCT()); } /** \brief Set the physical compare value. * \param [in] value New physical timer compare value. */ __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) { __set_CNTP_CVAL(value); __ISB(); } /** \brief Get the physical compare value. * \return Physical compare value. */ __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) { return(__get_CNTP_CVAL()); } /** \brief Configure the timer by setting the control value. * \param [in] value New timer control value. */ __STATIC_INLINE void PL1_SetControl(uint32_t value) { __set_CNTP_CTL(value); __ISB(); } /** \brief Get the control value. * \return Control value. */ __STATIC_INLINE uint32_t PL1_GetControl(void) { return(__get_CNTP_CTL()); } #endif /* Private Timer */ #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) /** \brief Set the load value to timers LOAD register. * \param [in] value The load value to be set. */ __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) { PTIM->LOAD = value; } /** \brief Get the load value from timers LOAD register. * \return Timer_Type::LOAD */ __STATIC_INLINE uint32_t PTIM_GetLoadValue(void) { return(PTIM->LOAD); } /** \brief Set current counter value from its COUNTER register. */ __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) { PTIM->COUNTER = value; } /** \brief Get current counter value from timers COUNTER register. * \result Timer_Type::COUNTER */ __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) { return(PTIM->COUNTER); } /** \brief Configure the timer using its CONTROL register. * \param [in] value The new configuration value to be set. */ __STATIC_INLINE void PTIM_SetControl(uint32_t value) { PTIM->CONTROL = value; } /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. * \return Timer_Type::CONTROL */ __STATIC_INLINE uint32_t PTIM_GetControl(void) { return(PTIM->CONTROL); } /** ref Timer_Type::CONTROL Get the event flag in timers ISR register. * \return 0 - flag is not set, 1- flag is set */ __STATIC_INLINE uint32_t PTIM_GetEventFlag(void) { return (PTIM->ISR & 1UL); } /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. */ __STATIC_INLINE void PTIM_ClearEventFlag(void) { PTIM->ISR = 1; } #endif #endif /* ########################## MMU functions ###################################### */ #define SECTION_DESCRIPTOR (0x2) #define SECTION_MASK (0xFFFFFFFC) #define SECTION_TEXCB_MASK (0xFFFF8FF3) #define SECTION_B_SHIFT (2) #define SECTION_C_SHIFT (3) #define SECTION_TEX0_SHIFT (12) #define SECTION_TEX1_SHIFT (13) #define SECTION_TEX2_SHIFT (14) #define SECTION_XN_MASK (0xFFFFFFEF) #define SECTION_XN_SHIFT (4) #define SECTION_DOMAIN_MASK (0xFFFFFE1F) #define SECTION_DOMAIN_SHIFT (5) #define SECTION_P_MASK (0xFFFFFDFF) #define SECTION_P_SHIFT (9) #define SECTION_AP_MASK (0xFFFF73FF) #define SECTION_AP_SHIFT (10) #define SECTION_AP2_SHIFT (15) #define SECTION_S_MASK (0xFFFEFFFF) #define SECTION_S_SHIFT (16) #define SECTION_NG_MASK (0xFFFDFFFF) #define SECTION_NG_SHIFT (17) #define SECTION_NS_MASK (0xFFF7FFFF) #define SECTION_NS_SHIFT (19) #define PAGE_L1_DESCRIPTOR (0x1) #define PAGE_L1_MASK (0xFFFFFFFC) #define PAGE_L2_4K_DESC (0x2) #define PAGE_L2_4K_MASK (0xFFFFFFFD) #define PAGE_L2_64K_DESC (0x1) #define PAGE_L2_64K_MASK (0xFFFFFFFC) #define PAGE_4K_TEXCB_MASK (0xFFFFFE33) #define PAGE_4K_B_SHIFT (2) #define PAGE_4K_C_SHIFT (3) #define PAGE_4K_TEX0_SHIFT (6) #define PAGE_4K_TEX1_SHIFT (7) #define PAGE_4K_TEX2_SHIFT (8) #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) #define PAGE_64K_B_SHIFT (2) #define PAGE_64K_C_SHIFT (3) #define PAGE_64K_TEX0_SHIFT (12) #define PAGE_64K_TEX1_SHIFT (13) #define PAGE_64K_TEX2_SHIFT (14) #define PAGE_TEXCB_MASK (0xFFFF8FF3) #define PAGE_B_SHIFT (2) #define PAGE_C_SHIFT (3) #define PAGE_TEX_SHIFT (12) #define PAGE_XN_4K_MASK (0xFFFFFFFE) #define PAGE_XN_4K_SHIFT (0) #define PAGE_XN_64K_MASK (0xFFFF7FFF) #define PAGE_XN_64K_SHIFT (15) #define PAGE_DOMAIN_MASK (0xFFFFFE1F) #define PAGE_DOMAIN_SHIFT (5) #define PAGE_P_MASK (0xFFFFFDFF) #define PAGE_P_SHIFT (9) #define PAGE_AP_MASK (0xFFFFFDCF) #define PAGE_AP_SHIFT (4) #define PAGE_AP2_SHIFT (9) #define PAGE_S_MASK (0xFFFFFBFF) #define PAGE_S_SHIFT (10) #define PAGE_NG_MASK (0xFFFFF7FF) #define PAGE_NG_SHIFT (11) #define PAGE_NS_MASK (0xFFFFFFF7) #define PAGE_NS_SHIFT (3) #define OFFSET_1M (0x00100000) #define OFFSET_64K (0x00010000) #define OFFSET_4K (0x00001000) #define DESCRIPTOR_FAULT (0x00000000) /* Attributes enumerations */ /* Region size attributes */ typedef enum { SECTION, PAGE_4k, PAGE_64k, } mmu_region_size_Type; /* Region type attributes */ typedef enum { NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED } mmu_memory_Type; /* Region cacheability attributes */ typedef enum { NON_CACHEABLE, WB_WA, WT, WB_NO_WA, } mmu_cacheability_Type; /* Region parity check attributes */ typedef enum { ECC_DISABLED, ECC_ENABLED, } mmu_ecc_check_Type; /* Region execution attributes */ typedef enum { EXECUTE, NON_EXECUTE, } mmu_execute_Type; /* Region global attributes */ typedef enum { GLOBAL, NON_GLOBAL, } mmu_global_Type; /* Region shareability attributes */ typedef enum { NON_SHARED, SHARED, } mmu_shared_Type; /* Region security attributes */ typedef enum { SECURE, NON_SECURE, } mmu_secure_Type; /* Region access attributes */ typedef enum { NO_ACCESS, RW, READ, } mmu_access_Type; /* Memory Region definition */ typedef struct RegionStruct { mmu_region_size_Type rg_t; mmu_memory_Type mem_t; uint8_t domain; mmu_cacheability_Type inner_norm_t; mmu_cacheability_Type outer_norm_t; mmu_ecc_check_Type e_t; mmu_execute_Type xn_t; mmu_global_Type g_t; mmu_secure_Type sec_t; mmu_access_Type priv_t; mmu_access_Type user_t; mmu_shared_Type sh_t; } mmu_region_attributes_Type; //Following macros define the descriptors and attributes //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = WB_WA; \ region.outer_norm_t = WB_WA; \ region.mem_t = NORMAL; \ region.sec_t = SECURE; \ region.xn_t = EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = NORMAL; \ region.sec_t = SECURE; \ region.xn_t = EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = WB_WA; \ region.outer_norm_t = WB_WA; \ region.mem_t = NORMAL; \ region.sec_t = SECURE; \ region.xn_t = EXECUTE; \ region.priv_t = READ; \ region.user_t = READ; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Normal_RO. Sect_Normal_Cod, but not executable #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = WB_WA; \ region.outer_norm_t = WB_WA; \ region.mem_t = NORMAL; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = READ; \ region.user_t = READ; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = WB_WA; \ region.outer_norm_t = WB_WA; \ region.mem_t = NORMAL; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = STRONGLY_ORDERED; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = STRONGLY_ORDERED; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = READ; \ region.user_t = READ; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Sect_Device_RW. Sect_Device_RO, but writeable #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = STRONGLY_ORDERED; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetSectionDescriptor(&descriptor_l1, region); //Page_4k_Device_RW. Shared device, not executable, rw, domain 0 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = SHARED_DEVICE; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); //Page_64k_Device_RW. Shared device, not executable, rw, domain 0 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ region.domain = 0x0; \ region.e_t = ECC_DISABLED; \ region.g_t = GLOBAL; \ region.inner_norm_t = NON_CACHEABLE; \ region.outer_norm_t = NON_CACHEABLE; \ region.mem_t = SHARED_DEVICE; \ region.sec_t = SECURE; \ region.xn_t = NON_EXECUTE; \ region.priv_t = RW; \ region.user_t = RW; \ region.sh_t = NON_SHARED; \ MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); /** \brief Set section execution-never attribute \param [out] descriptor_l1 L1 descriptor. \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. \return 0 */ __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) { *descriptor_l1 &= SECTION_XN_MASK; *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); return 0; } /** \brief Set section domain \param [out] descriptor_l1 L1 descriptor. \param [in] domain Section domain \return 0 */ __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) { *descriptor_l1 &= SECTION_DOMAIN_MASK; *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); return 0; } /** \brief Set section parity check \param [out] descriptor_l1 L1 descriptor. \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED \return 0 */ __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) { *descriptor_l1 &= SECTION_P_MASK; *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); return 0; } /** \brief Set section access privileges \param [out] descriptor_l1 L1 descriptor. \param [in] user User Level Access: NO_ACCESS, RW, READ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ \param [in] afe Access flag enable \return 0 */ __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) { uint32_t ap = 0; if (afe == 0) { //full access if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } else if ((priv == RW) && (user == READ)) { ap = 0x2; } else if ((priv == RW) && (user == RW)) { ap = 0x3; } else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } else if ((priv == READ) && (user == READ)) { ap = 0x7; } } else { //Simplified access if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } else if ((priv == RW) && (user == RW)) { ap = 0x3; } else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } else if ((priv == READ) && (user == READ)) { ap = 0x7; } } *descriptor_l1 &= SECTION_AP_MASK; *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; return 0; } /** \brief Set section shareability \param [out] descriptor_l1 L1 descriptor. \param [in] s_bit Section shareability: NON_SHARED, SHARED \return 0 */ __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) { *descriptor_l1 &= SECTION_S_MASK; *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); return 0; } /** \brief Set section Global attribute \param [out] descriptor_l1 L1 descriptor. \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL \return 0 */ __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) { *descriptor_l1 &= SECTION_NG_MASK; *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); return 0; } /** \brief Set section Security attribute \param [out] descriptor_l1 L1 descriptor. \param [in] s_bit Section Security attribute: SECURE, NON_SECURE \return 0 */ __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) { *descriptor_l1 &= SECTION_NS_MASK; *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); return 0; } /* Page 4k or 64k */ /** \brief Set 4k/64k page execution-never attribute \param [out] descriptor_l2 L2 descriptor. \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. \param [in] page Page size: PAGE_4k, PAGE_64k, \return 0 */ __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) { if (page == PAGE_4k) { *descriptor_l2 &= PAGE_XN_4K_MASK; *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); } else { *descriptor_l2 &= PAGE_XN_64K_MASK; *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); } return 0; } /** \brief Set 4k/64k page domain \param [out] descriptor_l1 L1 descriptor. \param [in] domain Page domain \return 0 */ __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) { *descriptor_l1 &= PAGE_DOMAIN_MASK; *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); return 0; } /** \brief Set 4k/64k page parity check \param [out] descriptor_l1 L1 descriptor. \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED \return 0 */ __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) { *descriptor_l1 &= SECTION_P_MASK; *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); return 0; } /** \brief Set 4k/64k page access privileges \param [out] descriptor_l2 L2 descriptor. \param [in] user User Level Access: NO_ACCESS, RW, READ \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ \param [in] afe Access flag enable \return 0 */ __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) { uint32_t ap = 0; if (afe == 0) { //full access if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } else if ((priv == RW) && (user == READ)) { ap = 0x2; } else if ((priv == RW) && (user == RW)) { ap = 0x3; } else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } else if ((priv == READ) && (user == READ)) { ap = 0x6; } } else { //Simplified access if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } else if ((priv == RW) && (user == RW)) { ap = 0x3; } else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } else if ((priv == READ) && (user == READ)) { ap = 0x7; } } *descriptor_l2 &= PAGE_AP_MASK; *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; return 0; } /** \brief Set 4k/64k page shareability \param [out] descriptor_l2 L2 descriptor. \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED \return 0 */ __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) { *descriptor_l2 &= PAGE_S_MASK; *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); return 0; } /** \brief Set 4k/64k page Global attribute \param [out] descriptor_l2 L2 descriptor. \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL \return 0 */ __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) { *descriptor_l2 &= PAGE_NG_MASK; *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); return 0; } /** \brief Set 4k/64k page Security attribute \param [out] descriptor_l1 L1 descriptor. \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE \return 0 */ __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) { *descriptor_l1 &= PAGE_NS_MASK; *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); return 0; } /** \brief Set Section memory attributes \param [out] descriptor_l1 L1 descriptor. \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, \return 0 */ __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) { *descriptor_l1 &= SECTION_TEXCB_MASK; if (STRONGLY_ORDERED == mem) { return 0; } else if (SHARED_DEVICE == mem) { *descriptor_l1 |= (1 << SECTION_B_SHIFT); } else if (NON_SHARED_DEVICE == mem) { *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); } else if (NORMAL == mem) { *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; switch(inner) { case NON_CACHEABLE: break; case WB_WA: *descriptor_l1 |= (1 << SECTION_B_SHIFT); break; case WT: *descriptor_l1 |= 1 << SECTION_C_SHIFT; break; case WB_NO_WA: *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); break; } switch(outer) { case NON_CACHEABLE: break; case WB_WA: *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); break; case WT: *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; break; case WB_NO_WA: *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); break; } } return 0; } /** \brief Set 4k/64k page memory attributes \param [out] descriptor_l2 L2 descriptor. \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, \param [in] page Page size \return 0 */ __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) { *descriptor_l2 &= PAGE_4K_TEXCB_MASK; if (page == PAGE_64k) { //same as section MMU_MemorySection(descriptor_l2, mem, outer, inner); } else { if (STRONGLY_ORDERED == mem) { return 0; } else if (SHARED_DEVICE == mem) { *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); } else if (NON_SHARED_DEVICE == mem) { *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); } else if (NORMAL == mem) { *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; switch(inner) { case NON_CACHEABLE: break; case WB_WA: *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); break; case WT: *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; break; case WB_NO_WA: *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); break; } switch(outer) { case NON_CACHEABLE: break; case WB_WA: *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); break; case WT: *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; break; case WB_NO_WA: *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); break; } } } return 0; } /** \brief Create a L1 section descriptor \param [out] descriptor L1 descriptor \param [in] reg Section attributes \return 0 */ __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) { *descriptor = 0; MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); MMU_XNSection(descriptor,reg.xn_t); MMU_DomainSection(descriptor, reg.domain); MMU_PSection(descriptor, reg.e_t); MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1); MMU_SharedSection(descriptor,reg.sh_t); MMU_GlobalSection(descriptor,reg.g_t); MMU_SecureSection(descriptor,reg.sec_t); *descriptor &= SECTION_MASK; *descriptor |= SECTION_DESCRIPTOR; return 0; } /** \brief Create a L1 and L2 4k/64k page descriptor \param [out] descriptor L1 descriptor \param [out] descriptor2 L2 descriptor \param [in] reg 4k/64k page attributes \return 0 */ __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) { *descriptor = 0; *descriptor2 = 0; switch (reg.rg_t) { case PAGE_4k: MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); MMU_DomainPage(descriptor, reg.domain); MMU_PPage(descriptor, reg.e_t); MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); MMU_SharedPage(descriptor2,reg.sh_t); MMU_GlobalPage(descriptor2,reg.g_t); MMU_SecurePage(descriptor,reg.sec_t); *descriptor &= PAGE_L1_MASK; *descriptor |= PAGE_L1_DESCRIPTOR; *descriptor2 &= PAGE_L2_4K_MASK; *descriptor2 |= PAGE_L2_4K_DESC; break; case PAGE_64k: MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); MMU_DomainPage(descriptor, reg.domain); MMU_PPage(descriptor, reg.e_t); MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1); MMU_SharedPage(descriptor2,reg.sh_t); MMU_GlobalPage(descriptor2,reg.g_t); MMU_SecurePage(descriptor,reg.sec_t); *descriptor &= PAGE_L1_MASK; *descriptor |= PAGE_L1_DESCRIPTOR; *descriptor2 &= PAGE_L2_64K_MASK; *descriptor2 |= PAGE_L2_64K_DESC; break; case SECTION: //error break; } return 0; } /** \brief Create a 1MB Section \param [in] ttb Translation table base address \param [in] base_address Section base address \param [in] count Number of sections to create \param [in] descriptor_l1 L1 descriptor (region attributes) */ __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) { uint32_t offset; uint32_t entry; uint32_t i; offset = base_address >> 20; entry = (base_address & 0xFFF00000) | descriptor_l1; //4 bytes aligned ttb = ttb + offset; for (i = 0; i < count; i++ ) { //4 bytes aligned *ttb++ = entry; entry += OFFSET_1M; } } /** \brief Create a 4k page entry \param [in] ttb L1 table base address \param [in] base_address 4k base address \param [in] count Number of 4k pages to create \param [in] descriptor_l1 L1 descriptor (region attributes) \param [in] ttb_l2 L2 table base address \param [in] descriptor_l2 L2 descriptor (region attributes) */ __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) { uint32_t offset, offset2; uint32_t entry, entry2; uint32_t i; offset = base_address >> 20; entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; //4 bytes aligned ttb += offset; //create l1_entry *ttb = entry; offset2 = (base_address & 0xff000) >> 12; ttb_l2 += offset2; entry2 = (base_address & 0xFFFFF000) | descriptor_l2; for (i = 0; i < count; i++ ) { //4 bytes aligned *ttb_l2++ = entry2; entry2 += OFFSET_4K; } } /** \brief Create a 64k page entry \param [in] ttb L1 table base address \param [in] base_address 64k base address \param [in] count Number of 64k pages to create \param [in] descriptor_l1 L1 descriptor (region attributes) \param [in] ttb_l2 L2 table base address \param [in] descriptor_l2 L2 descriptor (region attributes) */ __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) { uint32_t offset, offset2; uint32_t entry, entry2; uint32_t i,j; offset = base_address >> 20; entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; //4 bytes aligned ttb += offset; //create l1_entry *ttb = entry; offset2 = (base_address & 0xff000) >> 12; ttb_l2 += offset2; entry2 = (base_address & 0xFFFF0000) | descriptor_l2; for (i = 0; i < count; i++ ) { //create 16 entries for (j = 0; j < 16; j++) { //4 bytes aligned *ttb_l2++ = entry2; } entry2 += OFFSET_64K; } } /** \brief Enable MMU */ __STATIC_INLINE void MMU_Enable(void) { // Set M bit 0 to enable the MMU // Set AFE bit to enable simplified access permissions model // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); __ISB(); } /** \brief Disable MMU */ __STATIC_INLINE void MMU_Disable(void) { // Clear M bit 0 to disable the MMU __set_SCTLR( __get_SCTLR() & ~1); __ISB(); } /** \brief Invalidate entire unified TLB */ __STATIC_INLINE void MMU_InvalidateTLB(void) { __set_TLBIALL(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new state } #ifdef __cplusplus } #endif #endif /* __CORE_CA_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h ================================================ /**************************************************************************//** * @file irq_ctrl.h * @brief Interrupt Controller API header file * @version V1.1.0 * @date 03. March 2020 ******************************************************************************/ /* * Copyright (c) 2017-2020 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef IRQ_CTRL_H_ #define IRQ_CTRL_H_ #include #ifndef IRQHANDLER_T #define IRQHANDLER_T /// Interrupt handler data type typedef void (*IRQHandler_t) (void); #endif #ifndef IRQN_ID_T #define IRQN_ID_T /// Interrupt ID number data type typedef int32_t IRQn_ID_t; #endif /* Interrupt mode bit-masks */ #define IRQ_MODE_TRIG_Pos (0U) #define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) #define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt #define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt #define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt #define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt #define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt #define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt #define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt #define IRQ_MODE_TYPE_Pos (3U) #define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) #define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line #define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line #define IRQ_MODE_DOMAIN_Pos (4U) #define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) #define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain #define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain #define IRQ_MODE_CPU_Pos (5U) #define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) #define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs #define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 #define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 #define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 #define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 #define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 #define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 #define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 #define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 // Encoding in some early GIC implementations #define IRQ_MODE_MODEL_Pos (13U) #define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) #define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model #define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model #define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error /* Interrupt priority bit-masks */ #define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask #define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error /// Initialize interrupt controller. /// \return 0 on success, -1 on error. int32_t IRQ_Initialize (void); /// Register interrupt handler. /// \param[in] irqn interrupt ID number /// \param[in] handler interrupt handler function address /// \return 0 on success, -1 on error. int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); /// Get the registered interrupt handler. /// \param[in] irqn interrupt ID number /// \return registered interrupt handler function address. IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); /// Enable interrupt. /// \param[in] irqn interrupt ID number /// \return 0 on success, -1 on error. int32_t IRQ_Enable (IRQn_ID_t irqn); /// Disable interrupt. /// \param[in] irqn interrupt ID number /// \return 0 on success, -1 on error. int32_t IRQ_Disable (IRQn_ID_t irqn); /// Get interrupt enable state. /// \param[in] irqn interrupt ID number /// \return 0 - interrupt is disabled, 1 - interrupt is enabled. uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); /// Configure interrupt request mode. /// \param[in] irqn interrupt ID number /// \param[in] mode mode configuration /// \return 0 on success, -1 on error. int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); /// Get interrupt mode configuration. /// \param[in] irqn interrupt ID number /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. uint32_t IRQ_GetMode (IRQn_ID_t irqn); /// Get ID number of current interrupt request (IRQ). /// \return interrupt ID number. IRQn_ID_t IRQ_GetActiveIRQ (void); /// Get ID number of current fast interrupt request (FIQ). /// \return interrupt ID number. IRQn_ID_t IRQ_GetActiveFIQ (void); /// Signal end of interrupt processing. /// \param[in] irqn interrupt ID number /// \return 0 on success, -1 on error. int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); /// Set interrupt pending flag. /// \param[in] irqn interrupt ID number /// \return 0 on success, -1 on error. int32_t IRQ_SetPending (IRQn_ID_t irqn); /// Get interrupt pending flag. /// \param[in] irqn interrupt ID number /// \return 0 - interrupt is not pending, 1 - interrupt is pending. uint32_t IRQ_GetPending (IRQn_ID_t irqn); /// Clear interrupt pending flag. /// \param[in] irqn interrupt ID number /// \return 0 on success, -1 on error. int32_t IRQ_ClearPending (IRQn_ID_t irqn); /// Set interrupt priority value. /// \param[in] irqn interrupt ID number /// \param[in] priority interrupt priority value /// \return 0 on success, -1 on error. int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); /// Get interrupt priority. /// \param[in] irqn interrupt ID number /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. uint32_t IRQ_GetPriority (IRQn_ID_t irqn); /// Set priority masking threshold. /// \param[in] priority priority masking threshold value /// \return 0 on success, -1 on error. int32_t IRQ_SetPriorityMask (uint32_t priority); /// Get priority masking threshold /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. uint32_t IRQ_GetPriorityMask (void); /// Set priority grouping field split point /// \param[in] bits number of MSB bits included in the group priority field comparison /// \return 0 on success, -1 on error. int32_t IRQ_SetPriorityGroupBits (uint32_t bits); /// Get priority grouping field split point /// \return current number of MSB bits included in the group priority field comparison with /// optional IRQ_PRIORITY_ERROR bit set. uint32_t IRQ_GetPriorityGroupBits (void); #endif // IRQ_CTRL_H_ ================================================ FILE: external/CMSIS_5/CMSIS/Core_A/Source/irq_ctrl_gic.c ================================================ /**************************************************************************//** * @file irq_ctrl_gic.c * @brief Interrupt controller handling implementation for GIC * @version V1.2.0 * @date 30. October 2022 ******************************************************************************/ /* * Copyright (c) 2017-2022 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include #include "RTE_Components.h" #include CMSIS_device_header #include "irq_ctrl.h" #if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) /// Number of implemented interrupt lines #ifndef IRQ_GIC_LINE_COUNT #define IRQ_GIC_LINE_COUNT (1020U) #endif #ifndef IRQ_GIC_EXTERN_IRQ_TABLE static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; #else extern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT]; #endif static uint32_t IRQ_ID0; /// Initialize interrupt controller. __WEAK int32_t IRQ_Initialize (void) { #ifndef IRQ_GIC_EXTERN_IRQ_TABLE uint32_t i; for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { IRQTable[i] = (IRQHandler_t)NULL; } GIC_Enable(); #endif return (0); } /// Register interrupt handler. __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { int32_t status; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { IRQTable[irqn] = handler; status = 0; } else { status = -1; } return (status); } /// The Interrupt Handler. __WEAK void IRQ_Handler (void) { IRQn_Type irqn = GIC_AcknowledgePending (); if (irqn < (IRQn_Type)IRQ_GIC_LINE_COUNT) { IRQTable[irqn](); } GIC_EndInterrupt (irqn); } /// Get the registered interrupt handler. __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { IRQHandler_t h; // Ignore CPUID field (software generated interrupts) irqn &= 0x3FFU; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { h = IRQTable[irqn]; } else { h = (IRQHandler_t)0; } return (h); } /// Enable interrupt. __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_EnableIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } /// Disable interrupt. __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_DisableIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } /// Get interrupt enable state. __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { uint32_t enable; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { enable = GIC_GetEnableIRQ((IRQn_Type)irqn); } else { enable = 0U; } return (enable); } /// Configure interrupt request mode. __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { uint32_t val; uint8_t cfg; uint8_t secure; uint8_t cpu; int32_t status = 0; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { // Check triggering mode val = (mode & IRQ_MODE_TRIG_Msk); if (val == IRQ_MODE_TRIG_LEVEL) { cfg = 0x00U; } else if (val == IRQ_MODE_TRIG_EDGE) { cfg = 0x02U; } else { cfg = 0x00U; status = -1; } val = (mode & IRQ_MODE_MODEL_Msk); if (val == IRQ_MODE_MODEL_1N) { cfg |= 1; // 1-N model } // Check interrupt type val = mode & IRQ_MODE_TYPE_Msk; if (val != IRQ_MODE_TYPE_IRQ) { status = -1; } // Check interrupt domain val = mode & IRQ_MODE_DOMAIN_Msk; if (val == IRQ_MODE_DOMAIN_NONSECURE) { secure = 0U; } else { // Check security extensions support val = GIC_DistributorInfo() & (1UL << 10U); if (val != 0U) { // Security extensions are supported secure = 1U; } else { secure = 0U; status = -1; } } // Check interrupt CPU targets val = mode & IRQ_MODE_CPU_Msk; if (val == IRQ_MODE_CPU_ALL) { cpu = 0xFFU; } else { cpu = (uint8_t)(val >> IRQ_MODE_CPU_Pos); } // Apply configuration if no mode error if (status == 0) { GIC_SetConfiguration((IRQn_Type)irqn, cfg); GIC_SetTarget ((IRQn_Type)irqn, cpu); if (secure != 0U) { GIC_SetGroup ((IRQn_Type)irqn, secure); } } } return (status); } /// Get interrupt mode configuration. __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { uint32_t mode; uint32_t val; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { mode = IRQ_MODE_TYPE_IRQ; // Get trigger mode val = GIC_GetConfiguration((IRQn_Type)irqn); if ((val & 2U) != 0U) { // Corresponding interrupt is edge triggered mode |= IRQ_MODE_TRIG_EDGE; } else { // Corresponding interrupt is level triggered mode |= IRQ_MODE_TRIG_LEVEL; } if (val & 1U) { mode |= IRQ_MODE_MODEL_1N; } // Get interrupt CPU targets mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; } else { mode = IRQ_MODE_ERROR; } return (mode); } /// Get ID number of current interrupt request (IRQ). __WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { IRQn_ID_t irqn; uint32_t prio; /* Dummy read to avoid GIC 390 errata 801120 */ GIC_GetHighPendingIRQ(); irqn = GIC_AcknowledgePending(); __DSB(); /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ /* The following workaround code is for a single-core system. It would be */ /* different in a multi-core system. */ /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ /* so unlock it, otherwise service the interrupt as normal. */ /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ /* so will not occur here. */ if ((irqn == 0) || (irqn >= 0x3FE)) { /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ prio = GIC_GetPriority((IRQn_Type)0); GIC_SetPriority ((IRQn_Type)0, prio); __DSB(); if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { /* If the ID is 0, is active and has not been seen before */ IRQ_ID0 = 1U; } /* End of Workaround GIC 390 errata 733075 */ } return (irqn); } /// Get ID number of current fast interrupt request (FIQ). __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { return ((IRQn_ID_t)-1); } /// Signal end of interrupt processing. __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { int32_t status; IRQn_Type irq = (IRQn_Type)irqn; irqn &= 0x3FFU; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_EndInterrupt (irq); if (irqn == 0) { IRQ_ID0 = 0U; } status = 0; } else { status = -1; } return (status); } /// Set interrupt pending flag. __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_SetPendingIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } /// Get interrupt pending flag. __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { uint32_t pending; if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); } else { pending = 0U; } return (pending & 1U); } /// Clear interrupt pending flag. __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { int32_t status; if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_ClearPendingIRQ ((IRQn_Type)irqn); status = 0; } else { status = -1; } return (status); } /// Set interrupt priority value. __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { int32_t status; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { GIC_SetPriority ((IRQn_Type)irqn, priority); status = 0; } else { status = -1; } return (status); } /// Get interrupt priority. __WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { uint32_t priority; if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { priority = GIC_GetPriority ((IRQn_Type)irqn); } else { priority = IRQ_PRIORITY_ERROR; } return (priority); } /// Set priority masking threshold. __WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { GIC_SetInterfacePriorityMask (priority); return (0); } /// Get priority masking threshold __WEAK uint32_t IRQ_GetPriorityMask (void) { return GIC_GetInterfacePriorityMask(); } /// Set priority grouping field split point __WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { int32_t status; if (bits == IRQ_PRIORITY_Msk) { bits = 7U; } if (bits < 8U) { GIC_SetBinaryPoint (7U - bits); status = 0; } else { status = -1; } return (status); } /// Get priority grouping field split point __WEAK uint32_t IRQ_GetPriorityGroupBits (void) { uint32_t bp; bp = GIC_GetBinaryPoint() & 0x07U; return (7U - bp); } #endif ================================================ FILE: external/CMSIS_5/CMSIS/DSP/README.md ================================================ # CMSIS-DSP ![GitHub release (latest by date including pre-releases)](https://img.shields.io/github/v/release/ARM-software/CMSIS-DSP?include_prereleases) ![GitHub](https://img.shields.io/github/license/ARM-software/CMSIS-DSP) This CMSIS component has been moved into its own realm, please find it at [ARM-software/CMSIS-DSP](https://github.com/ARM-software/CMSIS-DSP). ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/CmdLineBuild.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/build_revisionHistory.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild_install.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild_uv.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuildgen.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/ccmerge.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmake.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmsis.css ================================================ /* The standard CSS for doxygen */ body, table, div, p, dl { font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; 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} dt { font-weight: bold; } div.multicol { -moz-column-gap: 1em; -webkit-column-gap: 1em; -moz-column-count: 3; -webkit-column-count: 3; } p.startli, p.startdd, p.starttd { margin-top: 2px; } p.endli { margin-bottom: 0px; } p.enddd { margin-bottom: 4px; } p.endtd { margin-bottom: 2px; } /* @end */ caption { font-weight: bold; } span.legend { font-size: 70%; text-align: center; } h3.version { font-size: 90%; text-align: center; } div.qindex, div.navtab{ background-color: #EBEFF6; border: 1px solid #A2B4D8; text-align: center; } div.qindex, div.navpath { width: 100%; line-height: 140%; } div.navtab { margin-right: 15px; } /* @group Link Styling */ a { color: #3A568E; font-weight: normal; text-decoration: none; } .contents a:visited { color: #4464A5; } a:hover { text-decoration: underline; } a.qindex { font-weight: bold; } a.qindexHL { font-weight: bold; background-color: #9AAED5; color: #ffffff; border: 1px double #849CCC; } .contents a.qindexHL:visited { color: #ffffff; } a.el { font-weight: bold; } a.elRef { } a.code, a.code:visited { color: #4665A2; } a.codeRef, a.codeRef:visited { color: #4665A2; } /* @end */ dl.el { margin-left: -1cm; } pre.fragment { border: 1px solid #C4CFE5; background-color: #FBFCFD; padding: 4px 6px; margin: 4px 8px 4px 2px; overflow: auto; word-wrap: break-word; font-size: 9pt; line-height: 125%; font-family: monospace, fixed; font-size: 105%; } div.fragment { padding: 4px; margin: 4px; background-color: #FBFCFD; border: 1px solid #C3CFE6; } div.line { font-family: monospace, fixed; font-size: 13px; line-height: 1.0; text-wrap: unrestricted; white-space: -moz-pre-wrap; /* Moz */ white-space: -pre-wrap; /* Opera 4-6 */ white-space: -o-pre-wrap; /* Opera 7 */ white-space: pre-wrap; /* CSS3 */ word-wrap: break-word; /* IE 5.5+ */ text-indent: -53px; padding-left: 53px; padding-bottom: 0px; margin: 0px; } span.lineno { padding-right: 4px; text-align: right; border-right: 2px solid #0F0; background-color: #E8E8E8; white-space: pre; } span.lineno a { background-color: #D8D8D8; } span.lineno a:hover { background-color: #C8C8C8; } div.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px; padding: 0.2em; border: solid thin #333; border-radius: 0.5em; -webkit-border-radius: .5em; -moz-border-radius: .5em; box-shadow: 2px 2px 3px #999; -webkit-box-shadow: 2px 2px 3px #999; -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); } div.groupHeader { margin-left: 16px; margin-top: 12px; font-weight: bold; } div.groupText { margin-left: 16px; font-style: italic; } body { background-color: white; color: black; margin: 0; } div.contents { margin-top: 10px; margin-left: 12px; margin-right: 8px; } td.indexkey { background-color: #EBEFF6; font-weight: bold; border: 1px solid #C3CFE6; margin: 2px 0px 2px 0; padding: 2px 10px; white-space: nowrap; vertical-align: top; } td.indexvalue { background-color: #EBEFF6; border: 1px solid #C3CFE6; padding: 2px 10px; margin: 2px 0px; } tr.memlist { background-color: #EDF1F7; } p.formulaDsp { text-align: center; } img.formulaDsp { } img.formulaInl { vertical-align: middle; } div.center { text-align: center; margin-top: 0px; margin-bottom: 0px; padding: 0px; } div.center img { border: 0px; } address.footer { text-align: right; padding-right: 12px; } img.footer { border: 0px; vertical-align: middle; } /* @group Code Colorization */ span.keyword { color: #008000 } span.keywordtype { color: #604020 } span.keywordflow { color: #e08000 } span.comment { color: #800000 } span.preprocessor { color: #806020 } span.stringliteral { color: #002080 } span.charliteral { color: #008080 } span.vhdldigit { color: #ff00ff } span.vhdlchar { color: #000000 } span.vhdlkeyword { color: #700070 } span.vhdllogic { color: #ff0000 } blockquote { background-color: #F7F8FB; border-left: 2px solid #9AAED5; margin: 0 24px 0 4px; padding: 0 12px 0 16px; } /* @end */ /* .search { color: #003399; font-weight: bold; } form.search { margin-bottom: 0px; margin-top: 0px; } input.search { font-size: 75%; color: #000080; font-weight: normal; background-color: #e8eef2; } */ td.tiny { font-size: 75%; } .dirtab { padding: 4px; border-collapse: collapse; border: 1px solid #A2B4D8; } th.dirtab { background: #EBEFF6; font-weight: bold; } hr { height: 0px; border: none; border-top: 1px solid #4769AD; } hr.footer { height: 1px; } /* @group Member Descriptions */ table.memberdecls { border-spacing: 0px; padding: 0px; } .memberdecls td { -webkit-transition-property: background-color, box-shadow; -webkit-transition-duration: 0.5s; -moz-transition-property: background-color, box-shadow; -moz-transition-duration: 0.5s; -ms-transition-property: background-color, box-shadow; -ms-transition-duration: 0.5s; -o-transition-property: background-color, box-shadow; -o-transition-duration: 0.5s; transition-property: background-color, box-shadow; transition-duration: 0.5s; } .memberdecls td.glow { background-color: cyan; box-shadow: 0 0 15px cyan; } .mdescLeft, .mdescRight, .memItemLeft, .memItemRight, .memTemplItemLeft, .memTemplItemRight, .memTemplParams { background-color: #F9FAFC; border: none; margin: 4px; padding: 1px 0 0 8px; } .mdescLeft, .mdescRight { padding: 0px 8px 4px 8px; color: #555; } .memItemLeft, .memItemRight, .memTemplParams { border-top: 1px solid #C3CFE6; } .memItemLeft, .memTemplItemLeft { white-space: nowrap; } .memItemRight { width: 100%; } .memTemplParams { color: #4464A5; white-space: nowrap; } /* @end */ /* @group Member Details */ /* Styles for detailed member documentation */ .memtemplate { font-size: 80%; color: #4464A5; font-weight: normal; margin-left: 9px; } .memnav { background-color: #EBEFF6; border: 1px solid #A2B4D8; text-align: center; margin: 2px; margin-right: 15px; padding: 2px; } .mempage { width: 100%; } .memitem { padding: 0; margin-bottom: 10px; margin-right: 5px; -webkit-transition: box-shadow 0.5s linear; -moz-transition: box-shadow 0.5s linear; -ms-transition: box-shadow 0.5s linear; -o-transition: box-shadow 0.5s linear; transition: box-shadow 0.5s linear; } .memitem.glow { box-shadow: 0 0 15px cyan; } .memname { font-weight: bold; margin-left: 6px; } .memname td { vertical-align: bottom; } .memproto, dl.reflist dt { border-top: 1px solid #A7B8DA; border-left: 1px solid #A7B8DA; border-right: 1px solid #A7B8DA; padding: 6px 0px 6px 0px; color: #233456; font-weight: bold; text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); background-image:url('nav_f.png'); background-repeat:repeat-x; background-color: #E2E7F3; /* opera specific markup */ box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); border-top-right-radius: 4px; border-top-left-radius: 4px; /* firefox specific markup */ -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; -moz-border-radius-topright: 4px; -moz-border-radius-topleft: 4px; /* webkit specific markup */ -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); -webkit-border-top-right-radius: 4px; -webkit-border-top-left-radius: 4px; } .memdoc, dl.reflist dd { border-bottom: 1px solid #A7B8DA; border-left: 1px solid #A7B8DA; border-right: 1px solid #A7B8DA; padding: 6px 10px 2px 10px; background-color: #FBFCFD; border-top-width: 0; background-image:url('nav_g.png'); background-repeat:repeat-x; background-color: #FFFFFF; /* opera specific markup */ border-bottom-left-radius: 4px; border-bottom-right-radius: 4px; box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); /* firefox specific markup */ -moz-border-radius-bottomleft: 4px; -moz-border-radius-bottomright: 4px; -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; /* webkit specific markup */ -webkit-border-bottom-left-radius: 4px; -webkit-border-bottom-right-radius: 4px; -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); } dl.reflist dt { padding: 5px; } dl.reflist dd { margin: 0px 0px 10px 0px; padding: 5px; } .paramkey { text-align: right; } .paramtype { white-space: nowrap; } .paramname { color: #602020; white-space: nowrap; } .paramname em { font-style: normal; } .params, .retval, .exception, .tparams { margin-left: 0px; padding-left: 0px; } .params .paramname, .retval .paramname { font-weight: bold; vertical-align: top; } .params .paramtype { font-style: italic; vertical-align: top; } .params .paramdir { font-family: "courier new",courier,monospace; vertical-align: top; } table.mlabels { border-spacing: 0px; } td.mlabels-left { width: 100%; padding: 0px; } td.mlabels-right { vertical-align: bottom; padding: 0px; white-space: nowrap; } span.mlabels { margin-left: 8px; } span.mlabel { background-color: #708CC4; border-top:1px solid #5072B7; border-left:1px solid #5072B7; border-right:1px solid #C3CFE6; border-bottom:1px solid #C3CFE6; text-shadow: none; color: white; margin-right: 4px; padding: 2px 3px; border-radius: 3px; font-size: 7pt; white-space: nowrap; } /* @end */ /* these are for tree view when not used as main index */ div.directory { margin: 10px 0px; border-top: 1px solid #A8B8D9; border-bottom: 1px solid #A8B8D9; width: 100%; } .directory table { border-collapse:collapse; } .directory td { margin: 0px; padding: 0px; vertical-align: top; } .directory td.entry { white-space: nowrap; padding-right: 6px; } .directory td.entry a { outline:none; } .directory td.desc { width: 100%; padding-left: 6px; padding-right: 6px; border-left: 1px solid rgba(0,0,0,0.05); } .directory tr.even { padding-left: 6px; background-color: #F7F8FB; } .directory img { vertical-align: -30%; } .directory .levels { white-space: nowrap; width: 100%; text-align: right; font-size: 9pt; } .directory .levels span { cursor: pointer; padding-left: 2px; padding-right: 2px; color: #3A568E; } div.dynheader { margin-top: 8px; -webkit-touch-callout: none; -webkit-user-select: none; -khtml-user-select: none; -moz-user-select: none; -ms-user-select: none; user-select: none; } address { font-style: normal; color: #293C63; } table.doxtable { border-collapse:collapse; margin-top: 4px; margin-bottom: 4px; } table.doxtable td, table.doxtable th { border: 1px solid #2B4069; padding: 3px 7px 2px; } table.doxtable th { background-color: #EBEFF6; color: #000000; font-size: 110%; padding-bottom: 4px; padding-top: 5px; } table.fieldtable { width: 100%; margin-bottom: 10px; border: 1px solid #A7B8DA; border-spacing: 0px; -moz-border-radius: 4px; -webkit-border-radius: 4px; border-radius: 4px; -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); } .fieldtable td, .fieldtable th { padding: 3px 7px 2px; } .fieldtable td.fieldtype, .fieldtable td.fieldname { white-space: nowrap; border-right: 1px solid #A7B8DA; border-bottom: 1px solid #A7B8DA; vertical-align: top; } .fieldtable td.fielddoc { border-bottom: 1px solid #A7B8DA; width: 100%; } .fieldtable tr:last-child td { border-bottom: none; } .fieldtable th { background-image:url('nav_f.png'); background-repeat:repeat-x; background-color: #E2E7F3; font-size: 90%; color: #233456; padding-bottom: 4px; padding-top: 5px; text-align:left; -moz-border-radius-topleft: 4px; -moz-border-radius-topright: 4px; -webkit-border-top-left-radius: 4px; -webkit-border-top-right-radius: 4px; border-top-left-radius: 4px; border-top-right-radius: 4px; border-bottom: 1px solid #A7B8DA; } .tabsearch { top: 0px; left: 10px; height: 36px; background-image: url('tab_b.png'); z-index: 101; overflow: hidden; font-size: 13px; } .navpath ul { font-size: 11px; background-image:url('tab_b.png'); background-repeat:repeat-x; height:30px; line-height:30px; color:#889FCE; border:solid 1px #C1CDE5; overflow:hidden; margin:0px; padding:0px; } .navpath li { list-style-type:none; float:left; padding-left:10px; padding-right:15px; background-image:url('bc_s.png'); background-repeat:no-repeat; background-position:right; color:#344D7E; } .navpath li.navelem a { height:32px; display:block; text-decoration: none; outline: none; } .navpath li.navelem a:hover { color:#6583BF; } .navpath li.footer { list-style-type:none; float:right; padding-left:10px; padding-right:15px; background-image:none; background-repeat:no-repeat; background-position:right; color:#344D7E; font-size: 8pt; } div.summary { float: right; font-size: 8pt; padding-right: 5px; width: 50%; text-align: right; } div.summary a { white-space: nowrap; } div.ingroups { margin-left: 5px; font-size: 8pt; padding-left: 5px; width: 50%; text-align: left; } div.ingroups a { white-space: nowrap; } div.header { background-image:url('nav_h.png'); background-repeat:repeat-x; background-color: #F9FAFC; margin: 0px; border-bottom: 1px solid #C3CFE6; } div.headertitle { padding: 5px 5px 5px 7px; } dl { padding: 0 0 0 10px; } /* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ dl.section { margin-left: 0px; padding-left: 0px; } dl.note { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #D0C000; } dl.warning, dl.attention { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #FF0000; } dl.pre, dl.post, dl.invariant { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #00D000; } dl.deprecated { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #505050; } dl.todo { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #00C0E0; } dl.test { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #3030E0; } dl.bug { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #C08050; } dl.section dd { margin-bottom: 6px; } #projectlogo { text-align: center; vertical-align: bottom; border-collapse: separate; } #projectlogo img { border: 0px none; } #projectname { font: 300% Tahoma, Arial,sans-serif; margin: 0px; padding: 2px 0px; } #projectbrief { font: 120% Tahoma, Arial,sans-serif; margin: 0px; padding: 0px; } #projectnumber { font: 50% Tahoma, Arial,sans-serif; margin: 0px; padding: 0px; } #titlearea { padding: 0px; margin: 0px; width: 100%; border-bottom: 1px solid #5072B7; } .image { text-align: left; } .dotgraph { text-align: center; } .mscgraph { text-align: center; } .caption { font-weight: bold; } div.zoom { border: 1px solid #8EA4D0; } dl.citelist { margin-bottom:50px; } dl.citelist dt { color:#314877; float:left; font-weight:bold; margin-right:10px; padding:5px; } dl.citelist dd { margin:2px 0; padding:5px 0; } div.toc { padding: 14px 25px; background-color: #F4F6FA; border: 1px solid #D7DFEE; border-radius: 7px 7px 7px 7px; float: right; height: auto; margin: 0 20px 10px 10px; width: 200px; } div.toc li { background: url("bdwn.png") no-repeat scroll 0 5px transparent; font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; margin-top: 5px; padding-left: 10px; padding-top: 2px; } div.toc h3 { font: bold 12px/1.2 Arial,FreeSans,sans-serif; color: #4464A5; border-bottom: 0 none; margin: 0; } div.toc ul { list-style: none outside none; border: medium none; padding: 0px; } div.toc li.level1 { margin-left: 0px; } div.toc li.level2 { margin-left: 15px; } div.toc li.level3 { margin-left: 30px; } div.toc li.level4 { margin-left: 45px; } .inherit_header { font-weight: bold; color: gray; cursor: pointer; -webkit-touch-callout: none; -webkit-user-select: none; -khtml-user-select: none; -moz-user-select: none; -ms-user-select: none; user-select: none; } .inherit_header td { padding: 6px 0px 2px 5px; } .inherit { display: none; } tr.heading h2 { margin-top: 12px; margin-bottom: 4px; } @media print { #top { display: none; } #side-nav { display: none; } #nav-path { display: none; } body { overflow:visible; } h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } .summary { display: none; } .memitem { page-break-inside: avoid; } #doc-content { margin-left:0 !important; height:auto !important; width:auto !important; overflow:inherit; display:inline; } } ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmsis_footer.js ================================================ function writeFooter() { document.write('Generated on Wed Apr 13 2022 14:13:49 for CMSIS-Pack Version 1.7.2 by Arm Ltd. All rights reserved.'); }; ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cp_init.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cp_install.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cprjFormat_pg.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/cprj_types.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/doxygen.css ================================================ /* The standard CSS for doxygen 1.8.6 */ body, table, div, p, dl { font: 400 14px/22px Roboto,sans-serif; } /* @group Heading Levels */ h1.groupheader { font-size: 150%; } .title { font: 400 14px/28px Roboto,sans-serif; font-size: 150%; font-weight: bold; margin: 10px 2px; } h2.groupheader { border-bottom: 1px solid #879ECB; color: #354C7B; font-size: 150%; font-weight: normal; margin-top: 1.75em; padding-top: 8px; padding-bottom: 4px; width: 100%; } h3.groupheader { font-size: 100%; } h1, h2, h3, h4, h5, h6 { -webkit-transition: text-shadow 0.5s linear; -moz-transition: text-shadow 0.5s linear; -ms-transition: text-shadow 0.5s linear; -o-transition: text-shadow 0.5s linear; transition: text-shadow 0.5s linear; margin-right: 15px; } h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { text-shadow: 0 0 15px cyan; } dt { font-weight: bold; } div.multicol { -moz-column-gap: 1em; -webkit-column-gap: 1em; -moz-column-count: 3; -webkit-column-count: 3; } p.startli, p.startdd { margin-top: 2px; } p.starttd { margin-top: 0px; } p.endli { margin-bottom: 0px; } p.enddd { margin-bottom: 4px; } p.endtd { margin-bottom: 2px; } /* @end */ caption { font-weight: bold; } span.legend { font-size: 70%; text-align: center; } h3.version { font-size: 90%; text-align: center; } div.qindex, div.navtab{ background-color: #EBEFF6; border: 1px solid #A3B4D7; text-align: center; } div.qindex, div.navpath { width: 100%; line-height: 140%; } div.navtab { margin-right: 15px; } /* @group Link Styling */ a { color: #3D578C; font-weight: normal; text-decoration: none; } .contents a:visited { color: #4665A2; } a:hover { text-decoration: underline; } a.qindex { font-weight: bold; } a.qindexHL { font-weight: bold; background-color: #9CAFD4; color: #ffffff; border: 1px double #869DCA; } .contents a.qindexHL:visited { color: #ffffff; } a.el { font-weight: bold; } a.elRef { } a.code, a.code:visited, a.line, a.line:visited { color: #4665A2; } a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { color: #4665A2; } /* @end */ dl.el { margin-left: -1cm; } pre.fragment { border: 1px solid #C4CFE5; background-color: #FBFCFD; padding: 4px 6px; margin: 4px 8px 4px 2px; overflow: auto; word-wrap: break-word; font-size: 9pt; line-height: 125%; font-family: monospace, fixed; font-size: 105%; } div.fragment { padding: 4px 6px; margin: 4px 8px 4px 2px; background-color: #FBFCFD; border: 1px solid #C4CFE5; } div.line { font-family: monospace, fixed; font-size: 13px; min-height: 13px; line-height: 1.0; text-wrap: unrestricted; white-space: -moz-pre-wrap; /* Moz */ white-space: -pre-wrap; /* Opera 4-6 */ white-space: -o-pre-wrap; /* Opera 7 */ white-space: pre-wrap; /* CSS3 */ word-wrap: break-word; /* IE 5.5+ */ text-indent: -53px; padding-left: 53px; padding-bottom: 0px; margin: 0px; -webkit-transition-property: background-color, box-shadow; -webkit-transition-duration: 0.5s; -moz-transition-property: background-color, box-shadow; -moz-transition-duration: 0.5s; -ms-transition-property: background-color, box-shadow; -ms-transition-duration: 0.5s; -o-transition-property: background-color, box-shadow; -o-transition-duration: 0.5s; transition-property: background-color, box-shadow; transition-duration: 0.5s; } div.line.glow { background-color: cyan; box-shadow: 0 0 10px cyan; } span.lineno { padding-right: 4px; text-align: right; border-right: 2px solid #0F0; background-color: #E8E8E8; white-space: pre; } span.lineno a { background-color: #D8D8D8; } span.lineno a:hover { background-color: #C8C8C8; } div.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px; padding: 0.2em; border: solid thin #333; border-radius: 0.5em; -webkit-border-radius: .5em; -moz-border-radius: .5em; box-shadow: 2px 2px 3px #999; -webkit-box-shadow: 2px 2px 3px #999; -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); } div.groupHeader { margin-left: 16px; margin-top: 12px; font-weight: bold; } div.groupText { margin-left: 16px; font-style: italic; } body { background-color: white; color: black; margin: 0; } div.contents { margin-top: 10px; margin-left: 12px; margin-right: 8px; } td.indexkey { background-color: #EBEFF6; font-weight: bold; border: 1px solid #C4CFE5; margin: 2px 0px 2px 0; padding: 2px 10px; white-space: nowrap; vertical-align: top; } td.indexvalue { background-color: #EBEFF6; border: 1px solid #C4CFE5; padding: 2px 10px; margin: 2px 0px; } tr.memlist { background-color: #EEF1F7; } p.formulaDsp { text-align: center; } img.formulaDsp { } img.formulaInl { vertical-align: middle; } div.center { text-align: center; margin-top: 0px; margin-bottom: 0px; padding: 0px; } div.center img { border: 0px; } address.footer { text-align: right; padding-right: 12px; } img.footer { border: 0px; vertical-align: middle; } /* @group Code Colorization */ span.keyword { color: #008000 } span.keywordtype { color: #604020 } span.keywordflow { color: #e08000 } span.comment { color: #800000 } span.preprocessor { color: #806020 } span.stringliteral { color: #002080 } span.charliteral { color: #008080 } span.vhdldigit { color: #ff00ff } span.vhdlchar { color: #000000 } span.vhdlkeyword { color: #700070 } span.vhdllogic { color: #ff0000 } blockquote { background-color: #F7F8FB; border-left: 2px solid #9CAFD4; margin: 0 24px 0 4px; padding: 0 12px 0 16px; } /* @end */ /* .search { color: #003399; font-weight: bold; } form.search { margin-bottom: 0px; margin-top: 0px; } input.search { font-size: 75%; color: #000080; font-weight: normal; background-color: #e8eef2; } */ td.tiny { font-size: 75%; } .dirtab { padding: 4px; border-collapse: collapse; border: 1px solid #A3B4D7; } th.dirtab { background: #EBEFF6; font-weight: bold; } hr { height: 0px; border: none; border-top: 1px solid #4A6AAA; } hr.footer { height: 1px; } /* @group Member Descriptions */ table.memberdecls { border-spacing: 0px; padding: 0px; } .memberdecls td, .fieldtable tr { -webkit-transition-property: background-color, box-shadow; -webkit-transition-duration: 0.5s; -moz-transition-property: background-color, box-shadow; -moz-transition-duration: 0.5s; -ms-transition-property: background-color, box-shadow; -ms-transition-duration: 0.5s; -o-transition-property: background-color, box-shadow; -o-transition-duration: 0.5s; transition-property: background-color, box-shadow; transition-duration: 0.5s; } .memberdecls td.glow, .fieldtable tr.glow { background-color: cyan; box-shadow: 0 0 15px cyan; } .mdescLeft, .mdescRight, .memItemLeft, .memItemRight, .memTemplItemLeft, .memTemplItemRight, .memTemplParams { background-color: #F9FAFC; border: none; margin: 4px; padding: 1px 0 0 8px; } .mdescLeft, .mdescRight { padding: 0px 8px 4px 8px; color: #555; } .memSeparator { border-bottom: 1px solid #DEE4F0; line-height: 1px; margin: 0px; padding: 0px; } .memItemLeft, .memTemplItemLeft { white-space: nowrap; } .memItemRight { width: 100%; } .memTemplParams { color: #4665A2; white-space: nowrap; font-size: 80%; } /* @end */ /* @group Member Details */ /* Styles for detailed member documentation */ .memtemplate { font-size: 80%; color: #4665A2; font-weight: normal; margin-left: 9px; } .memnav { background-color: #EBEFF6; border: 1px solid #A3B4D7; text-align: center; margin: 2px; margin-right: 15px; padding: 2px; } .mempage { width: 100%; } .memitem { padding: 0; margin-bottom: 10px; margin-right: 5px; -webkit-transition: box-shadow 0.5s linear; -moz-transition: box-shadow 0.5s linear; -ms-transition: box-shadow 0.5s linear; -o-transition: box-shadow 0.5s linear; transition: box-shadow 0.5s linear; display: table !important; width: 100%; } .memitem.glow { box-shadow: 0 0 15px cyan; } .memname { font-weight: bold; margin-left: 6px; } .memname td { vertical-align: bottom; } .memproto, dl.reflist dt { border-top: 1px solid #A8B8D9; border-left: 1px solid #A8B8D9; border-right: 1px solid #A8B8D9; padding: 6px 0px 6px 0px; color: #253555; font-weight: bold; text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); background-image:url('nav_f.png'); background-repeat:repeat-x; background-color: #E2E8F2; /* opera specific markup */ box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); border-top-right-radius: 4px; border-top-left-radius: 4px; /* firefox specific markup */ -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; -moz-border-radius-topright: 4px; -moz-border-radius-topleft: 4px; /* webkit specific markup */ -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); -webkit-border-top-right-radius: 4px; -webkit-border-top-left-radius: 4px; } .memdoc, dl.reflist dd { border-bottom: 1px solid #A8B8D9; border-left: 1px solid #A8B8D9; border-right: 1px solid #A8B8D9; padding: 6px 10px 2px 10px; background-color: #FBFCFD; border-top-width: 0; background-image:url('nav_g.png'); background-repeat:repeat-x; background-color: #FFFFFF; /* opera specific markup */ border-bottom-left-radius: 4px; border-bottom-right-radius: 4px; box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); /* firefox specific markup */ -moz-border-radius-bottomleft: 4px; -moz-border-radius-bottomright: 4px; -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; /* webkit specific markup */ -webkit-border-bottom-left-radius: 4px; -webkit-border-bottom-right-radius: 4px; -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); } dl.reflist dt { padding: 5px; } dl.reflist dd { margin: 0px 0px 10px 0px; padding: 5px; } .paramkey { text-align: right; } .paramtype { white-space: nowrap; } .paramname { color: #602020; white-space: nowrap; } .paramname em { font-style: normal; } .paramname code { line-height: 14px; } .params, .retval, .exception, .tparams { margin-left: 0px; padding-left: 0px; } .params .paramname, .retval .paramname { font-weight: bold; vertical-align: top; } .params .paramtype { font-style: italic; vertical-align: top; } .params .paramdir { font-family: "courier new",courier,monospace; vertical-align: top; } table.mlabels { border-spacing: 0px; } td.mlabels-left { width: 100%; padding: 0px; } td.mlabels-right { vertical-align: bottom; padding: 0px; white-space: nowrap; } span.mlabels { margin-left: 8px; } span.mlabel { background-color: #728DC1; border-top:1px solid #5373B4; border-left:1px solid #5373B4; border-right:1px solid #C4CFE5; border-bottom:1px solid #C4CFE5; text-shadow: none; color: white; margin-right: 4px; padding: 2px 3px; border-radius: 3px; font-size: 7pt; white-space: nowrap; vertical-align: middle; } /* @end */ /* these are for tree view when not used as main index */ div.directory { margin: 10px 0px; border-top: 1px solid #A8B8D9; border-bottom: 1px solid #A8B8D9; width: 100%; } .directory table { border-collapse:collapse; } .directory td { margin: 0px; padding: 0px; vertical-align: top; } .directory td.entry { white-space: nowrap; padding-right: 6px; padding-top: 3px; } .directory td.entry a { outline:none; } .directory td.entry a img { border: none; } .directory td.desc { width: 100%; padding-left: 6px; padding-right: 6px; padding-top: 3px; border-left: 1px solid rgba(0,0,0,0.05); } .directory tr.even { padding-left: 6px; background-color: #F7F8FB; } .directory img { vertical-align: -30%; } .directory .levels { white-space: nowrap; width: 100%; text-align: right; font-size: 9pt; } .directory .levels span { cursor: pointer; padding-left: 2px; padding-right: 2px; color: #3D578C; } div.dynheader { margin-top: 8px; -webkit-touch-callout: none; -webkit-user-select: none; -khtml-user-select: none; -moz-user-select: none; -ms-user-select: none; user-select: none; } address { font-style: normal; color: #2A3D61; } table.doxtable { border-collapse:collapse; margin-top: 4px; margin-bottom: 4px; } table.doxtable td, table.doxtable th { border: 1px solid #2D4068; padding: 3px 7px 2px; } table.doxtable th { background-color: #374F7F; color: #FFFFFF; font-size: 110%; padding-bottom: 4px; padding-top: 5px; } table.fieldtable { /*width: 100%;*/ margin-bottom: 10px; border: 1px solid #A8B8D9; border-spacing: 0px; -moz-border-radius: 4px; -webkit-border-radius: 4px; border-radius: 4px; -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); } .fieldtable td, .fieldtable th { padding: 3px 7px 2px; } .fieldtable td.fieldtype, .fieldtable td.fieldname { white-space: nowrap; border-right: 1px solid #A8B8D9; border-bottom: 1px solid #A8B8D9; vertical-align: top; } .fieldtable td.fieldname { padding-top: 3px; } .fieldtable td.fielddoc { border-bottom: 1px solid #A8B8D9; /*width: 100%;*/ } .fieldtable td.fielddoc p:first-child { margin-top: 0px; } .fieldtable td.fielddoc p:last-child { margin-bottom: 2px; } .fieldtable tr:last-child td { border-bottom: none; } .fieldtable th { background-image:url('nav_f.png'); background-repeat:repeat-x; background-color: #E2E8F2; font-size: 90%; color: #253555; padding-bottom: 4px; padding-top: 5px; text-align:left; -moz-border-radius-topleft: 4px; -moz-border-radius-topright: 4px; -webkit-border-top-left-radius: 4px; -webkit-border-top-right-radius: 4px; border-top-left-radius: 4px; border-top-right-radius: 4px; border-bottom: 1px solid #A8B8D9; } .tabsearch { top: 0px; left: 10px; height: 36px; background-image: url('tab_b.png'); z-index: 101; overflow: hidden; font-size: 13px; } .navpath ul { font-size: 11px; background-image:url('tab_b.png'); background-repeat:repeat-x; background-position: 0 -5px; height:30px; line-height:30px; color:#8AA0CC; border:solid 1px #C2CDE4; overflow:hidden; margin:0px; padding:0px; } .navpath li { list-style-type:none; float:left; padding-left:10px; padding-right:15px; background-image:url('bc_s.png'); background-repeat:no-repeat; background-position:right; color:#364D7C; } .navpath li.navelem a { height:32px; display:block; text-decoration: none; outline: none; color: #283A5D; font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); text-decoration: none; } .navpath li.navelem a:hover { color:#6884BD; } .navpath li.footer { list-style-type:none; float:right; padding-left:10px; padding-right:15px; background-image:none; background-repeat:no-repeat; background-position:right; color:#364D7C; font-size: 8pt; } div.summary { float: right; font-size: 8pt; padding-right: 5px; width: 50%; text-align: right; } div.summary a { white-space: nowrap; } div.ingroups { font-size: 8pt; width: 50%; text-align: left; } div.ingroups a { white-space: nowrap; } div.header { background-image:url('nav_h.png'); background-repeat:repeat-x; background-color: #F9FAFC; margin: 0px; border-bottom: 1px solid #C4CFE5; } div.headertitle { padding: 5px 5px 5px 10px; } dl { padding: 0 0 0 10px; } /* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ dl.section { margin-left: 0px; padding-left: 0px; } dl.note { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #D0C000; } dl.warning, dl.attention { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #FF0000; } dl.pre, dl.post, dl.invariant { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #00D000; } dl.deprecated { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #505050; } dl.todo { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #00C0E0; } dl.test { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #3030E0; } dl.bug { margin-left:-7px; padding-left: 3px; border-left:4px solid; border-color: #C08050; } dl.section dd { margin-bottom: 6px; } #projectlogo { text-align: center; vertical-align: bottom; border-collapse: separate; } #projectlogo img { border: 0px none; } #projectname { font: 300% Tahoma, Arial,sans-serif; margin: 0px; padding: 2px 0px; } #projectbrief { font: 120% Tahoma, Arial,sans-serif; margin: 0px; padding: 0px; } #projectnumber { font: 50% Tahoma, Arial,sans-serif; margin: 0px; padding: 0px; } #titlearea { padding: 0px; margin: 0px; width: 100%; border-bottom: 1px solid #5373B4; } .image { text-align: center; } .dotgraph { text-align: center; } .mscgraph { text-align: center; } .diagraph { text-align: center; } .caption { font-weight: bold; } div.zoom { border: 1px solid #90A5CE; } dl.citelist { margin-bottom:50px; } dl.citelist dt { color:#334975; float:left; font-weight:bold; margin-right:10px; padding:5px; } dl.citelist dd { margin:2px 0; padding:5px 0; } div.toc { padding: 14px 25px; background-color: #F4F6FA; border: 1px solid #D8DFEE; border-radius: 7px 7px 7px 7px; float: right; height: auto; margin: 0 20px 10px 10px; width: 200px; } div.toc li { background: url("bdwn.png") no-repeat scroll 0 5px transparent; font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; margin-top: 5px; padding-left: 10px; padding-top: 2px; } div.toc h3 { font: bold 12px/1.2 Arial,FreeSans,sans-serif; color: #4665A2; border-bottom: 0 none; margin: 0; } div.toc ul { list-style: none outside none; border: medium none; padding: 0px; } div.toc li.level1 { margin-left: 0px; } div.toc li.level2 { margin-left: 15px; } div.toc li.level3 { margin-left: 30px; } div.toc li.level4 { margin-left: 45px; } .inherit_header { font-weight: bold; color: gray; cursor: pointer; -webkit-touch-callout: none; -webkit-user-select: none; -khtml-user-select: none; -moz-user-select: none; -ms-user-select: none; user-select: none; } .inherit_header td { padding: 6px 0px 2px 5px; } .inherit { display: none; } tr.heading h2 { margin-top: 12px; margin-bottom: 4px; } /* tooltip related style info */ .ttc { position: absolute; display: none; } #powerTip { cursor: default; white-space: nowrap; background-color: white; border: 1px solid gray; border-radius: 4px 4px 4px 4px; box-shadow: 1px 1px 7px gray; display: none; font-size: smaller; max-width: 80%; opacity: 0.9; padding: 1ex 1em 1em; position: absolute; z-index: 2147483647; } #powerTip div.ttdoc { color: grey; font-style: italic; } #powerTip div.ttname a { font-weight: bold; } #powerTip div.ttname { font-weight: bold; } #powerTip div.ttdeci { color: #006318; } #powerTip div { margin: 0px; padding: 0px; font: 12px/16px Roboto,sans-serif; } #powerTip:before, #powerTip:after { content: ""; position: absolute; margin: 0px; } #powerTip.n:after, #powerTip.n:before, #powerTip.s:after, #powerTip.s:before, #powerTip.w:after, #powerTip.w:before, #powerTip.e:after, #powerTip.e:before, #powerTip.ne:after, #powerTip.ne:before, #powerTip.se:after, #powerTip.se:before, #powerTip.nw:after, #powerTip.nw:before, #powerTip.sw:after, #powerTip.sw:before { border: solid transparent; content: " "; height: 0; width: 0; position: absolute; } #powerTip.n:after, #powerTip.s:after, #powerTip.w:after, #powerTip.e:after, #powerTip.nw:after, #powerTip.ne:after, #powerTip.sw:after, #powerTip.se:after { border-color: rgba(255, 255, 255, 0); } #powerTip.n:before, #powerTip.s:before, #powerTip.w:before, #powerTip.e:before, #powerTip.nw:before, #powerTip.ne:before, #powerTip.sw:before, #powerTip.se:before { border-color: rgba(128, 128, 128, 0); } #powerTip.n:after, #powerTip.n:before, #powerTip.ne:after, #powerTip.ne:before, #powerTip.nw:after, #powerTip.nw:before { top: 100%; } #powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { border-top-color: #ffffff; border-width: 10px; margin: 0px -10px; } #powerTip.n:before { border-top-color: #808080; border-width: 11px; margin: 0px -11px; } #powerTip.n:after, #powerTip.n:before { left: 50%; } #powerTip.nw:after, #powerTip.nw:before { right: 14px; } #powerTip.ne:after, #powerTip.ne:before { left: 14px; } #powerTip.s:after, #powerTip.s:before, #powerTip.se:after, #powerTip.se:before, #powerTip.sw:after, #powerTip.sw:before { bottom: 100%; } #powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { border-bottom-color: #ffffff; border-width: 10px; margin: 0px -10px; } #powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { border-bottom-color: #808080; border-width: 11px; margin: 0px -11px; } #powerTip.s:after, #powerTip.s:before { left: 50%; } #powerTip.sw:after, #powerTip.sw:before { right: 14px; } #powerTip.se:after, #powerTip.se:before { left: 14px; } #powerTip.e:after, #powerTip.e:before { left: 100%; } #powerTip.e:after { border-left-color: #ffffff; border-width: 10px; top: 50%; margin-top: -10px; } #powerTip.e:before { border-left-color: #808080; border-width: 11px; top: 50%; margin-top: -11px; } #powerTip.w:after, #powerTip.w:before { right: 100%; } #powerTip.w:after { border-right-color: #ffffff; border-width: 10px; top: 50%; margin-top: -10px; } #powerTip.w:before { border-right-color: #808080; border-width: 11px; top: 50%; margin-top: -11px; } @media print { #top { display: none; } #side-nav { display: none; } #nav-path { display: none; } body { overflow:visible; } h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } .summary { display: none; } .memitem { page-break-inside: avoid; } #doc-content { margin-left:0 !important; height:auto !important; width:auto !important; overflow:inherit; display:inline; } } ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/dynsections.js ================================================ function toggleVisibility(linkObj) { var base = $(linkObj).attr('id'); var summary = $('#'+base+'-summary'); var content = $('#'+base+'-content'); var trigger = $('#'+base+'-trigger'); var src=$(trigger).attr('src'); if (content.is(':visible')===true) { content.hide(); summary.show(); $(linkObj).addClass('closed').removeClass('opened'); $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); } else { content.show(); summary.hide(); $(linkObj).removeClass('closed').addClass('opened'); $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); } return false; } function updateStripes() { $('table.directory tr'). removeClass('even').filter(':visible:even').addClass('even'); } function toggleLevel(level) { $('table.directory tr').each(function(){ var l = this.id.split('_').length-1; var i = $('#img'+this.id.substring(3)); var a = $('#arr'+this.id.substring(3)); if (l Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_components.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_cprj.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_created.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_files.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_info.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_layers.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_packages.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_target.html ================================================ Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds If the automatic redirection is failing, click here or try to find corresponding topic described in Open-CMSIS-Pack resources. ================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/Build/html/index.html ================================================ Overview CMSIS-Build: Overview
CMSIS-Build  Version 0.10.0 (beta)
Tools, software frameworks, and work flows for productivity with CMSIS based projects
Overview

CMSIS-Build is now replaced with the CMSIS-Toolbox that is a set of tools for creating and building projects that are based on software packs.

Content of this documentation is now provided here and individual pages are redirected to the corresponding pages in CMSIS-Toolbox documents.

Components of CMSIS-Toolbox

The CMSIS-Toolbox is developed under the Linaro Open-CMSIS-Pack project and contains these tools:

  • cpackget download, add and remove software packs.
  • csolution to create and manage complex applications with user source files and content from software packs
  • cbuild controls the build process that translates a project to a executable binary image.
  • packgen to create a software pack from a CMake based software repository.
  • packchk to validate a software pack

The CMSIS-Toolbox can be used as stand-alone tools with command line interface (CLI) but will be integrated into several other Arm tool solutions such as:

Development Workflow

The following diagram shows the development workflow using the CMSIS-Toolbox.

CMSIS-Toolbox.png
Diagram: CMSIS-Toolbox Development Workflow

A solution that manages several related projects and projects can be composed using an intuitive *.yml format. This solution and project files are then translated using csolution CLI tool to the *.CPRJ project file format.

The individual *.CPRJ project files can be imported to an IDE or by using cbuild translated into executable binary images.

The *.CPRJ Project Format describes the input file format that is used by cbuild.

Revision History

Version Description
replaced by CMSIS-Toolbox now contains the cbuild (aka CMSIS-Build) CLI tool.
0.10.0 (beta) CMake back-end and support for more Cortex-M processors including ArmV8.1M architecture.
0.9.0 (beta) Support for multiple compilers and commands for layer management
0.1.0 (alpha) Release for alpha review
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g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*! * jQuery UI Widget 1.8.18 * * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) * Dual licensed under the MIT or GPL Version 2 licenses. * http://jquery.org/license * * http://docs.jquery.com/UI/Widget */ (function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*! * jQuery UI Mouse 1.8.18 * * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) * Dual licensed under the MIT or GPL Version 2 licenses. * http://jquery.org/license * * http://docs.jquery.com/UI/Mouse * * Depends: * jquery.ui.widget.js */ (function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var 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CMSIS DSP Software Library

CMSIS-DSP is now in its GitHub project at ARM-software/CMSIS-DSP.

Content of this documentation is now provided here and individual pages are redirected to the corresponding pages in CMSIS-DSP documentation.
================================================ FILE: external/CMSIS_5/CMSIS/DoxyGen/DSP/html/index.html.bak ================================================ CMSIS DSP Software Library CMSIS-DSP: CMSIS DSP Software Library
CMSIS-DSP  
CMSIS DSP Software Library
CMSIS DSP Software Library

Introduction

This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M and Cortex-A processor based devices.

The library is divided into a number of functions each covering a specific category:

  • Basic math functions
  • Fast math functions
  • Complex math functions
  • Filtering functions
  • Matrix functions
  • Transform functions
  • Motor control functions
  • Statistical functions
  • Support functions
  • Interpolation functions
  • Support Vector Machine functions (SVM)
  • Bayes classifier functions
  • Distance functions
  • Quaternion functions

The library has generally separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.

The library is providing vectorized versions of most algorthms for Helium and of most f32 algorithms for Neon.

When using a vectorized version, provide a little bit of padding after the end of a buffer (3 words) because the vectorized code may read a little bit after the end of a buffer. You don't have to modify your buffers but just ensure that the end of buffer + padding is not outside of a memory region.

Using the Library

The library is released in source form. It is strongly advised to compile the library using -Ofast to have the best performances.

The library functions are declared in the public file arm_math.h which is placed in the Include folder. Simply include this file. If you don't want to include everything, you can also rely on headers in Include/dsp folder and use only what you need.

Examples

The library ships with a number of examples which demonstrate how to use the library functions.

Toolchain Support

The library is now tested on Fast Models building with cmake. Core M0, M4, M7, M33, M55, A32 are tested.

Preprocessor Macros

Each library project have different preprocessor macros.

  • ARM_MATH_BIG_ENDIAN:

Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

  • ARM_MATH_MATRIX_CHECK:

Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices

  • ARM_MATH_ROUNDING:

Define macro ARM_MATH_ROUNDING for rounding on support functions

  • ARM_MATH_LOOPUNROLL:

Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions

  • ARM_MATH_NEON:

Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. It is not enabled by default when Neon is available because performances are dependent on the compiler and target architecture.

  • ARM_MATH_NEON_EXPERIMENTAL:

Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of of some DSP functions. Experimental Neon versions currently do not have better performances than the scalar versions.

  • ARM_MATH_HELIUM:

It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.

  • ARM_MATH_HELIUM_EXPERIMENTAL:

Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined. Enable some vector versions which may have worse performance than scalar depending on the core / compiler configuration.

  • ARM_MATH_MVEF:

Select Helium versions of the f32 algorithms. It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.

  • ARM_MATH_MVEI:

Select Helium versions of the int and fixed point algorithms.

  • ARM_MATH_MVE_FLOAT16:

MVE Float16 implementations of some algorithms (Requires MVE extension).

  • DISABLEFLOAT16:

Disable float16 algorithms when __fp16 is not supported for a specific compiler / core configuration. This is only valid for scalar. When vector architecture is supporting f16 then it can't be disabled.

  • ARM_MATH_AUTOVECTORIZE:

With Helium or Neon, disable the use of vectorized code with C intrinsics and use pure C instead. The vectorization is then done by the compiler.

CMSIS-DSP in ARM::CMSIS Pack

The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:

File/Folder Content
CMSIS\Documentation\DSP This documentation
CMSIS\DSP\Examples Example projects demonstrating the usage of the library functions
CMSIS\DSP\ComputeLibrary Small Neon kernels when building on Cortex-A
CMSIS\DSP\Include include files for using and building the lib
CMSIS\DSP\PrivateInclude private include files for building the lib
CMSIS\DSP\Source source files

Revision History of CMSIS-DSP

Please refer to Revision History.

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g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*! * jQuery UI Widget 1.8.18 * * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) * Dual licensed under the MIT or GPL Version 2 licenses. * http://jquery.org/license * * http://docs.jquery.com/UI/Widget */ (function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*! * jQuery UI Mouse 1.8.18 * * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) * Dual licensed under the MIT or GPL Version 2 licenses. * http://jquery.org/license * * http://docs.jquery.com/UI/Mouse * * Depends: * jquery.ui.widget.js */ (function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var 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CMSIS-Pack Documentation

CMSIS-Pack is now part of the Open-CMSIS-Pack project at www.open-cmsis-pack.org.

Content of this documentation is now provided here and individual pages are redirected to the corresponding pages in Open-CMSIS-Pack specification.
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true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return 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k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(hl.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var 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t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null; p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var o={width:parseInt(p.element.css("width"),10),height:parseInt(p.element.css("height"),10),top:parseInt(p.element.css("top"),10),left:parseInt(p.element.css("left"),10)};if(h&&h.length){c(h[0]).css({width:o.width,height:o.height})}p._updateCache(o);p._propagate("resize",i)}})}});c.ui.plugin.add("resizable","containment",{start:function(f,r){var t=c(this).data("resizable"),j=t.options,l=t.element;var g=j.containment,k=(g instanceof c)?g.get(0):(/parent/.test(g))?l.parent().get(0):g;if(!k){return}t.containerElement=c(k);if(/document/.test(g)||g==document){t.containerOffset={left:0,top:0};t.containerPosition={left:0,top:0};t.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var 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t=c(this).data("resizable"),i=t.options,f=t.containerSize,p=t.containerOffset,m=t.size,n=t.position,r=t._aspectRatio||g.shiftKey,e={top:0,left:0},h=t.containerElement;if(h[0]!=document&&(/static/).test(h.css("position"))){e=p}if(n.left<(t._helper?p.left:0)){t.size.width=t.size.width+(t._helper?(t.position.left-p.left):(t.position.left-e.left));if(r){t.size.height=t.size.width/i.aspectRatio}t.position.left=i.helper?p.left:0}if(n.top<(t._helper?p.top:0)){t.size.height=t.size.height+(t._helper?(t.position.top-p.top):t.position.top);if(r){t.size.width=t.size.height*i.aspectRatio}t.position.top=t._helper?p.top:0}t.offset.left=t.parentData.left+t.position.left;t.offset.top=t.parentData.top+t.position.top;var l=Math.abs((t._helper?t.offset.left-e.left:(t.offset.left-e.left))+t.sizeDiff.width),s=Math.abs((t._helper?t.offset.top-e.top:(t.offset.top-p.top))+t.sizeDiff.height);var k=t.containerElement.get(0)==t.element.parent().get(0),j=/relative|absolute/.test(t.containerElement.css("position"));if(k&&j){l-=t.parentData.left}if(l+t.size.width>=t.parentData.width){t.size.width=t.parentData.width-l;if(r){t.size.height=t.size.width/t.aspectRatio}}if(s+t.size.height>=t.parentData.height){t.size.height=t.parentData.height-s;if(r){t.size.width=t.size.height*t.aspectRatio}}},stop:function(f,n){var q=c(this).data("resizable"),g=q.options,l=q.position,m=q.containerOffset,e=q.containerPosition,i=q.containerElement;var j=c(q.helper),r=j.offset(),p=j.outerWidth()-q.sizeDiff.width,k=j.outerHeight()-q.sizeDiff.height;if(q._helper&&!g.animate&&(/relative/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}if(q._helper&&!g.animate&&(/static/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}}});c.ui.plugin.add("resizable","ghost",{start:function(g,h){var e=c(this).data("resizable"),i=e.options,f=e.size;e.ghost=e.originalElement.clone();e.ghost.css({opacity:0.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof i.ghost=="string"?i.ghost:"");e.ghost.appendTo(e.helper)},resize:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost){e.ghost.css({position:"relative",height:e.size.height,width:e.size.width})}},stop:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost&&e.helper){e.helper.get(0).removeChild(e.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(e,m){var p=c(this).data("resizable"),h=p.options,k=p.size,i=p.originalSize,j=p.originalPosition,n=p.axis,l=h._aspectRatio||e.shiftKey;h.grid=typeof h.grid=="number"?[h.grid,h.grid]:h.grid;var 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