[
  {
    "path": ".gitignore",
    "content": "*.csv\n*.mpf\n*.qpf\n*.qsf\n*.v.bak\n*.wlf\n*.cr.mti\n.DS_Store\n\nconfigs/\ndb/\nincremental_db/\noutput_files/\nsimulation/\nwork/\ninstructions/ready_instructions.txt\n"
  },
  {
    "path": "README.md",
    "content": "# MIPS-pipeline-processor\n\nThanks for visiting this repository!\n\nDeveloped during the Fall 2017 Computer Architecture Laboratory course at the University of Tehran, \nthis project is an implementation of a pipelined MIPS processor featuring hazard detection as well as forwarding.\nThis implementation is based on a limited ISA, the details for which are present in `docs/MIPS_ISA.png`.\nThis code is synthesizable and can be run on an FPGA. We used Altera DE2 units for testing purposes. The implemtation has been verified using a relatively complex test program (found in `instructions/example_source_code.txt`).\n\n![MIPS pipelened processor](https://github.com/mhyousefi/MIPS-pipeline-processor/blob/master/docs/MIPS_diagram.png?raw=true)\n\n## Getting Started\n\nDownload or clone the project, write your machine code to run (there already exists a default test program in the instruction memory),\ncompile the Verilog files and and run testbench.v in a Verilog simulation environment such as ModelSim from Mentor Graphics.\n\n### Instruction format\n\nInstructions should be provided to the instruction memory in reset time. We avoided the `readmemb` and `readmemh` functions to \nkeep the code synthesizable. The instruction memory cells are 8 bits long, whereas each instruction is 32 bits long. \nTherefore, each instruction takes up four memory cells, as shown bellow.\n\nFor example, an add instruction: `10000000001000000000000000001010` or `Addi r1,r0,10` will need to be given as \n\n```\ninstMem[0] <= 8'b10000000;\ninstMem[1] <= 8'b00100000;\ninstMem[2] <= 8'b00000000;\ninstMem[3] <= 8'b00001010;\n```\n\n### Converting your raw machine codes\n\nA python script is provided under the `instructions/rearrange_instructions.py` directory which simply takes your \nmachine code (in a specified format) and converts it to the format illustrated above.\n\n### Enable/disable forwarding\n\nAn instance of the top-level circuit is taken in `testbench.v`. \nThe inputs of the `MIPS_Processor` include `clk`, `rst`, and `forwarding_EN`.\nForwarding will be enabled if `forwarding_EN` is set to 1, and disabled otherwise.\n\n## Under the hood\n\nThere are five pipeline stages: \n\n1. Instruction Fetch\n2. Instruction Decode\n3. Execution\n4. Memory\n5. Write Back\n\n### Modular design\n\nAll modules are organized under the `modules` directory.\nThe top level description can be found under `topLevelCircuit.v`. It contains a **modular design** of the processor and \nencompasses five pipe stages and four pipe registers, the description for which are present under `modules/pipeStages` and \n`modules/pipeRegisters` respectively. The register file, the hazard detection and the forwarding units are also instantiated\nin `topLevelCircuit.v`. Pipe stages are made of and encapsulate other supporting modules.\n\n### Constants\n\n`defines.v` contains project-wide constants for **opcodes**, **execution commands**, and **branch condition commands**. \nIt also contains constants for wire widths and memory specifications. You can change memory size values to suit your needs.\n\n### Wire naming convention\n\nTo maintain conformity, most wire names follow the format {wire description}_{wire stage}, where the second part describes \nthe stage where the wire is located. For example, `MEM_W_EN_ID` is the memory write enable signal present in the instruction decode stage.\n\n## Contributions\n\nContributions are welcomed, both general improvements as well as new features such as a more realistic memory heirarchy or branch prediction. However, please follow the coding styles and the naming convention. Another useful contribution would be more comprehensive testing and verification and bug report.\n"
  },
  {
    "path": "alteraDE2SimulationFiles/7segConv.v",
    "content": "module sevenSegConv (num, out1, out2);\n  input [31:0] num;\n  output [6:0] out1, out2;\n\n  wire [31:0] numLower = num / 10;\n  wire [31:0] numUpper = num % 10;\n\n  assign out1 = (numLower == 32'd0) ? 7'b1000000:\n               (numLower == 32'd1) ? 7'b1001111:\n               (numLower == 32'd2) ? 7'b0100100:\n               (numLower == 32'd3) ? 7'b0110000:\n               (numLower == 32'd4) ? 7'b0011001:\n               (numLower == 32'd5) ? 7'b0010010:\n               (numLower == 32'd6) ? 7'b0000010:\n               (numLower == 32'd7) ? 7'b1111000:\n               (numLower == 32'd8) ? 7'b0000000:\n               (numLower == 32'd9) ? 7'b0010000: 7'b1111111;\n\n assign out2 = (numUpper == 32'd0) ? 7'b1000000:\n              (numUpper == 32'd1) ? 7'b1001111:\n              (numUpper == 32'd2) ? 7'b0100100:\n              (numUpper == 32'd3) ? 7'b0110000:\n              (numUpper == 32'd4) ? 7'b0011001:\n              (numUpper == 32'd5) ? 7'b0010010:\n              (numUpper == 32'd6) ? 7'b0000010:\n              (numUpper == 32'd7) ? 7'b1111000:\n              (numUpper == 32'd8) ? 7'b0000000:\n              (numUpper == 32'd9) ? 7'b0010000: 7'b1111111;\nendmodule // sevenSegConv\n"
  },
  {
    "path": "alteraDE2SimulationFiles/DE2_TOP.V",
    "content": "module DE2_TOP\n\t(\n\t\t////////////////////\tClock Input\t \t////////////////////\n\t\tCLOCK_27,\t\t\t\t\t\t//\t27 MHz\n\t\tCLOCK_50,\t\t\t\t\t\t//\t50 MHz\n\t\tEXT_CLOCK,\t\t\t\t\t\t//\tExternal Clock\n\t\t////////////////////\tPush Button\t\t////////////////////\n\t\tKEY,\t\t\t\t\t\t\t//\tPushbutton[3:0]\n\t\t////////////////////\tDPDT Switch\t\t////////////////////\n\t\tSW,\t\t\t\t\t\t\t\t//\tToggle Switch[17:0]\n\t\t////////////////////\t7-SEG Dispaly\t////////////////////\n\t\tHEX0,\t\t\t\t\t\t\t//\tSeven Segment Digit 0\n\t\tHEX1,\t\t\t\t\t\t\t//\tSeven Segment Digit 1\n\t\tHEX2,\t\t\t\t\t\t\t//\tSeven Segment Digit 2\n\t\tHEX3,\t\t\t\t\t\t\t//\tSeven Segment Digit 3\n\t\tHEX4,\t\t\t\t\t\t\t//\tSeven Segment Digit 4\n\t\tHEX5,\t\t\t\t\t\t\t//\tSeven Segment Digit 5\n\t\tHEX6,\t\t\t\t\t\t\t//\tSeven Segment Digit 6\n\t\tHEX7,\t\t\t\t\t\t\t//\tSeven Segment Digit 7\n\t\t////////////////////////\tLED\t\t////////////////////////\n\t\tLEDG,\t\t\t\t\t\t\t//\tLED Green[8:0]\n\t\tLEDR,\t\t\t\t\t\t\t//\tLED Red[17:0]\n\t\t////////////////////////\tUART\t////////////////////////\n\t\tUART_TXD,\t\t\t\t\t\t//\tUART Transmitter\n\t\tUART_RXD,\t\t\t\t\t\t//\tUART Receiver\n\t\t////////////////////////\tIRDA\t////////////////////////\n\t\t// IRDA_TXD,\t\t\t\t\t\t//\tIRDA Transmitter\n\t\t// IRDA_RXD,\t\t\t\t\t\t//\tIRDA Receiver\n\t\t/////////////////////\tSDRAM Interface\t\t////////////////\n\t\tDRAM_DQ,\t\t\t\t\t\t//\tSDRAM Data bus 16 Bits\n\t\tDRAM_ADDR,\t\t\t\t\t\t//\tSDRAM Address bus 12 Bits\n\t\tDRAM_LDQM,\t\t\t\t\t\t//\tSDRAM Low-byte Data Mask\n\t\tDRAM_UDQM,\t\t\t\t\t\t//\tSDRAM High-byte Data Mask\n\t\tDRAM_WE_N,\t\t\t\t\t\t//\tSDRAM Write Enable\n\t\tDRAM_CAS_N,\t\t\t\t\t\t//\tSDRAM Column Address Strobe\n\t\tDRAM_RAS_N,\t\t\t\t\t\t//\tSDRAM Row Address Strobe\n\t\tDRAM_CS_N,\t\t\t\t\t\t//\tSDRAM Chip Select\n\t\tDRAM_BA_0,\t\t\t\t\t\t//\tSDRAM Bank Address 0\n\t\tDRAM_BA_1,\t\t\t\t\t\t//\tSDRAM Bank Address 0\n\t\tDRAM_CLK,\t\t\t\t\t\t//\tSDRAM Clock\n\t\tDRAM_CKE,\t\t\t\t\t\t//\tSDRAM Clock Enable\n\t\t////////////////////\tFlash Interface\t\t////////////////\n\t\tFL_DQ,\t\t\t\t\t\t\t//\tFLASH Data bus 8 Bits\n\t\tFL_ADDR,\t\t\t\t\t\t//\tFLASH Address bus 22 Bits\n\t\tFL_WE_N,\t\t\t\t\t\t//\tFLASH Write Enable\n\t\tFL_RST_N,\t\t\t\t\t\t//\tFLASH Reset\n\t\tFL_OE_N,\t\t\t\t\t\t//\tFLASH Output Enable\n\t\tFL_CE_N,\t\t\t\t\t\t//\tFLASH Chip Enable\n\t\t////////////////////\tSRAM Interface\t\t////////////////\n\t\tSRAM_DQ,\t\t\t\t\t\t//\tSRAM Data bus 16 Bits\n\t\tSRAM_ADDR,\t\t\t\t\t\t//\tSRAM Address bus 18 Bits\n\t\tSRAM_UB_N,\t\t\t\t\t\t//\tSRAM High-byte Data Mask\n\t\tSRAM_LB_N,\t\t\t\t\t\t//\tSRAM Low-byte Data Mask\n\t\tSRAM_WE_N,\t\t\t\t\t\t//\tSRAM Write Enable\n\t\tSRAM_CE_N,\t\t\t\t\t\t//\tSRAM Chip Enable\n\t\tSRAM_OE_N,\t\t\t\t\t\t//\tSRAM Output Enable\n\t\t////////////////////\tISP1362 Interface\t////////////////\n\t\tOTG_DATA,\t\t\t\t\t\t//\tISP1362 Data bus 16 Bits\n\t\tOTG_ADDR,\t\t\t\t\t\t//\tISP1362 Address 2 Bits\n\t\tOTG_CS_N,\t\t\t\t\t\t//\tISP1362 Chip Select\n\t\tOTG_RD_N,\t\t\t\t\t\t//\tISP1362 Write\n\t\tOTG_WR_N,\t\t\t\t\t\t//\tISP1362 Read\n\t\tOTG_RST_N,\t\t\t\t\t\t//\tISP1362 Reset\n\t\tOTG_FSPEED,\t\t\t\t\t\t//\tUSB Full Speed,\t0 = Enable, Z = Disable\n\t\tOTG_LSPEED,\t\t\t\t\t\t//\tUSB Low Speed, \t0 = Enable, Z = Disable\n\t\tOTG_INT0,\t\t\t\t\t\t//\tISP1362 Interrupt 0\n\t\tOTG_INT1,\t\t\t\t\t\t//\tISP1362 Interrupt 1\n\t\tOTG_DREQ0,\t\t\t\t\t\t//\tISP1362 DMA Request 0\n\t\tOTG_DREQ1,\t\t\t\t\t\t//\tISP1362 DMA Request 1\n\t\tOTG_DACK0_N,\t\t\t\t\t//\tISP1362 DMA Acknowledge 0\n\t\tOTG_DACK1_N,\t\t\t\t\t//\tISP1362 DMA Acknowledge 1\n\t\t////////////////////\tLCD Module 16X2\t\t////////////////\n\t\tLCD_ON,\t\t\t\t\t\t\t//\tLCD Power ON/OFF\n\t\tLCD_BLON,\t\t\t\t\t\t//\tLCD Back Light ON/OFF\n\t\tLCD_RW,\t\t\t\t\t\t\t//\tLCD Read/Write Select, 0 = Write, 1 = Read\n\t\tLCD_EN,\t\t\t\t\t\t\t//\tLCD Enable\n\t\tLCD_RS,\t\t\t\t\t\t\t//\tLCD Command/Data Select, 0 = Command, 1 = Data\n\t\tLCD_DATA,\t\t\t\t\t\t//\tLCD Data bus 8 bits\n\t\t////////////////////\tSD_Card Interface\t////////////////\n\t\t//SD_DAT,\t\t\t\t\t\t\t//\tSD Card Data\n\t\tSD_WP_N,\t\t\t\t\t\t   //\tSD Write protect\n\t\tSD_CMD,\t\t\t\t\t\t\t//\tSD Card Command Signal\n\t\tSD_CLK,\t\t\t\t\t\t\t//\tSD Card Clock\n\t\t////////////////////\tUSB JTAG link\t////////////////////\n\t\tTDI,  \t\t\t\t\t\t\t// CPLD -> FPGA (data in)\n\t\tTCK,  \t\t\t\t\t\t\t// CPLD -> FPGA (clk)\n\t\tTCS,  \t\t\t\t\t\t\t// CPLD -> FPGA (CS)\n\t   TDO,  \t\t\t\t\t\t\t// FPGA -> CPLD (data out)\n\t\t////////////////////\tI2C\t\t////////////////////////////\n\t\tI2C_SDAT,\t\t\t\t\t\t//\tI2C Data\n\t\tI2C_SCLK,\t\t\t\t\t\t//\tI2C Clock\n\t\t////////////////////\tPS2\t\t////////////////////////////\n\t\tPS2_DAT,\t\t\t\t\t\t//\tPS2 Data\n\t\tPS2_CLK,\t\t\t\t\t\t//\tPS2 Clock\n\t\t////////////////////\tVGA\t\t////////////////////////////\n\t\tVGA_CLK,   \t\t\t\t\t\t//\tVGA Clock\n\t\tVGA_HS,\t\t\t\t\t\t\t//\tVGA H_SYNC\n\t\tVGA_VS,\t\t\t\t\t\t\t//\tVGA V_SYNC\n\t\tVGA_BLANK,\t\t\t\t\t\t//\tVGA BLANK\n\t\tVGA_SYNC,\t\t\t\t\t\t//\tVGA SYNC\n\t\tVGA_R,   \t\t\t\t\t\t//\tVGA Red[9:0]\n\t\tVGA_G,\t \t\t\t\t\t\t//\tVGA Green[9:0]\n\t\tVGA_B,  \t\t\t\t\t\t//\tVGA Blue[9:0]\n\t\t////////////\tEthernet Interface\t////////////////////////\n\t\tENET_DATA,\t\t\t\t\t\t//\tDM9000A DATA bus 16Bits\n\t\tENET_CMD,\t\t\t\t\t\t//\tDM9000A Command/Data Select, 0 = Command, 1 = Data\n\t\tENET_CS_N,\t\t\t\t\t\t//\tDM9000A Chip Select\n\t\tENET_WR_N,\t\t\t\t\t\t//\tDM9000A Write\n\t\tENET_RD_N,\t\t\t\t\t\t//\tDM9000A Read\n\t\tENET_RST_N,\t\t\t\t\t\t//\tDM9000A Reset\n\t\tENET_INT,\t\t\t\t\t\t//\tDM9000A Interrupt\n\t\tENET_CLK,\t\t\t\t\t\t//\tDM9000A Clock 25 MHz\n\t\t////////////////\tAudio CODEC\t\t////////////////////////\n\t\tAUD_ADCLRCK,\t\t\t\t\t//\tAudio CODEC ADC LR Clock\n\t\tAUD_ADCDAT,\t\t\t\t\t\t//\tAudio CODEC ADC Data\n\t\tAUD_DACLRCK,\t\t\t\t\t//\tAudio CODEC DAC LR Clock\n\t\tAUD_DACDAT,\t\t\t\t\t\t//\tAudio CODEC DAC Data\n\t\tAUD_BCLK,\t\t\t\t\t\t//\tAudio CODEC Bit-Stream Clock\n\t\tAUD_XCK,\t\t\t\t\t\t//\tAudio CODEC Chip Clock\n\t\t////////////////\tTV Decoder\t\t////////////////////////\n\t\tTD_DATA,    \t\t\t\t\t//\tTV Decoder Data bus 8 bits\n\t\tTD_HS,\t\t\t\t\t\t\t//\tTV Decoder H_SYNC\n\t\tTD_VS,\t\t\t\t\t\t\t//\tTV Decoder V_SYNC\n\t\tTD_RESET,\t\t\t\t\t\t//\tTV Decoder Reset\n\t\tTD_CLK27,                  //\tTV Decoder 27MHz CLK\n\t\t////////////////////\tGPIO\t////////////////////////////\n\t\tGPIO_0,\t\t\t\t\t\t\t//\tGPIO Connection 0\n\t\tGPIO_1\t\t\t\t\t\t\t//\tGPIO Connection 1\n\t);\n\n////////////////////////\tClock Input\t \t////////////////////////\ninput\t\t   \tCLOCK_27;\t\t\t\t//\t27 MHz\ninput\t\t   \tCLOCK_50;\t\t\t\t//\t50 MHz\ninput\t\t\t   EXT_CLOCK;\t\t\t\t//\tExternal Clock\n////////////////////////\tPush Button\t\t////////////////////////\ninput\t   [3:0]\tKEY;\t\t\t\t\t//\tPushbutton[3:0]\n////////////////////////\tDPDT Switch\t\t////////////////////////\ninput\t  [17:0]\tSW;\t\t\t\t\t\t//\tToggle Switch[17:0]\n////////////////////////\t7-SEG Dispaly\t////////////////////////\noutput\t[6:0]\tHEX0;\t\t\t\t\t//\tSeven Segment Digit 0\noutput\t[6:0]\tHEX1;\t\t\t\t\t//\tSeven Segment Digit 1\noutput\t[6:0]\tHEX2;\t\t\t\t\t//\tSeven Segment Digit 2\noutput\t[6:0]\tHEX3;\t\t\t\t\t//\tSeven Segment Digit 3\noutput\t[6:0]\tHEX4;\t\t\t\t\t//\tSeven Segment Digit 4\noutput\t[6:0]\tHEX5;\t\t\t\t\t//\tSeven Segment Digit 5\noutput\t[6:0]\tHEX6;\t\t\t\t\t//\tSeven Segment Digit 6\noutput\t[6:0]\tHEX7;\t\t\t\t\t//\tSeven Segment Digit 7\n////////////////////////////\tLED\t\t////////////////////////////\noutput\t[8:0]\tLEDG;\t\t\t\t\t//\tLED Green[8:0]\noutput  [17:0]\tLEDR;\t\t\t\t\t//\tLED Red[17:0]\n////////////////////////////\tUART\t////////////////////////////\noutput\t\t\tUART_TXD;\t\t\t\t//\tUART Transmitter\ninput\t\t\t   UART_RXD;\t\t\t\t//\tUART Receiver\n////////////////////////////\tIRDA\t////////////////////////////\n//output\t\t\tIRDA_TXD;\t\t\t\t//\tIRDA Transmitter\n//input\t\t\t   IRDA_RXD;\t\t\t\t//\tIRDA Receiver\n///////////////////////\t\tSDRAM Interface\t////////////////////////\ninout\t  [15:0]\tDRAM_DQ;\t\t\t\t//\tSDRAM Data bus 16 Bits\noutput  [11:0]\tDRAM_ADDR;\t\t\t\t//\tSDRAM Address bus 12 Bits\noutput\t\t\tDRAM_LDQM;\t\t\t\t//\tSDRAM Low-byte Data Mask\noutput\t\t\tDRAM_UDQM;\t\t\t\t//\tSDRAM High-byte Data Mask\noutput\t\t\tDRAM_WE_N;\t\t\t\t//\tSDRAM Write Enable\noutput\t\t\tDRAM_CAS_N;\t\t\t\t//\tSDRAM Column Address Strobe\noutput\t\t\tDRAM_RAS_N;\t\t\t\t//\tSDRAM Row Address Strobe\noutput\t\t\tDRAM_CS_N;\t\t\t\t//\tSDRAM Chip Select\noutput\t\t\tDRAM_BA_0;\t\t\t\t//\tSDRAM Bank Address 0\noutput\t\t\tDRAM_BA_1;\t\t\t\t//\tSDRAM Bank Address 0\noutput\t\t\tDRAM_CLK;\t\t\t\t//\tSDRAM Clock\noutput\t\t\tDRAM_CKE;\t\t\t\t//\tSDRAM Clock Enable\n////////////////////////\tFlash Interface\t////////////////////////\ninout\t  [7:0]\tFL_DQ;\t\t\t\t\t//\tFLASH Data bus 8 Bits\noutput [21:0]\tFL_ADDR;\t\t\t\t//\tFLASH Address bus 22 Bits\noutput\t\t\tFL_WE_N;\t\t\t\t//\tFLASH Write Enable\noutput\t\t\tFL_RST_N;\t\t\t\t//\tFLASH Reset\noutput\t\t\tFL_OE_N;\t\t\t\t//\tFLASH Output Enable\noutput\t\t\tFL_CE_N;\t\t\t\t//\tFLASH Chip Enable\n////////////////////////\tSRAM Interface\t////////////////////////\ninout\t [15:0]\tSRAM_DQ;\t\t\t\t//\tSRAM Data bus 16 Bits\noutput [17:0]\tSRAM_ADDR;\t\t\t\t//\tSRAM Address bus 18 Bits\noutput\t\t\tSRAM_UB_N;\t\t\t\t//\tSRAM High-byte Data Mask\noutput\t\t\tSRAM_LB_N;\t\t\t\t//\tSRAM Low-byte Data Mask\noutput\t\t\tSRAM_WE_N;\t\t\t\t//\tSRAM Write Enable\noutput\t\t\tSRAM_CE_N;\t\t\t\t//\tSRAM Chip Enable\noutput\t\t\tSRAM_OE_N;\t\t\t\t//\tSRAM Output Enable\n////////////////////\tISP1362 Interface\t////////////////////////\ninout\t [15:0]\tOTG_DATA;\t\t\t\t//\tISP1362 Data bus 16 Bits\noutput  [1:0]\tOTG_ADDR;\t\t\t\t//\tISP1362 Address 2 Bits\noutput\t\t\tOTG_CS_N;\t\t\t\t//\tISP1362 Chip Select\noutput\t\t\tOTG_RD_N;\t\t\t\t//\tISP1362 Write\noutput\t\t\tOTG_WR_N;\t\t\t\t//\tISP1362 Read\noutput\t\t\tOTG_RST_N;\t\t\t\t//\tISP1362 Reset\noutput\t\t\tOTG_FSPEED;\t\t\t\t//\tUSB Full Speed,\t0 = Enable, Z = Disable\noutput\t\t\tOTG_LSPEED;\t\t\t\t//\tUSB Low Speed, \t0 = Enable, Z = Disable\ninput\t\t\t   OTG_INT0;\t\t\t\t//\tISP1362 Interrupt 0\ninput\t\t\t   OTG_INT1;\t\t\t\t//\tISP1362 Interrupt 1\ninput\t\t\t   OTG_DREQ0;\t\t\t\t//\tISP1362 DMA Request 0\ninput\t\t\t   OTG_DREQ1;\t\t\t\t//\tISP1362 DMA Request 1\noutput\t\t\tOTG_DACK0_N;\t\t\t//\tISP1362 DMA Acknowledge 0\noutput\t\t\tOTG_DACK1_N;\t\t\t//\tISP1362 DMA Acknowledge 1\n////////////////////\tLCD Module 16X2\t////////////////////////////\ninout\t  [7:0]\tLCD_DATA;\t\t\t\t//\tLCD Data bus 8 bits\noutput\t\t\tLCD_ON;\t\t\t\t\t//\tLCD Power ON/OFF\noutput\t\t\tLCD_BLON;\t\t\t\t//\tLCD Back Light ON/OFF\noutput\t\t\tLCD_RW;\t\t\t\t\t//\tLCD Read/Write Select, 0 = Write, 1 = Read\noutput\t\t\tLCD_EN;\t\t\t\t\t//\tLCD Enable\noutput\t\t\tLCD_RS;\t\t\t\t\t//\tLCD Command/Data Select, 0 = Command, 1 = Data\n////////////////////\tSD Card Interface\t////////////////////////\n//inout\t [3:0]\tSD_DAT;\t\t\t\t\t//\tSD Card Data\ninput\t\t\t   SD_WP_N;\t\t\t\t   //\tSD write protect\ninout\t\t\t   SD_CMD;\t\t\t\t\t//\tSD Card Command Signal\noutput\t\t\tSD_CLK;\t\t\t\t\t//\tSD Card Clock\n////////////////////////\tI2C\t\t////////////////////////////////\ninout\t\t\t   I2C_SDAT;\t\t\t\t//\tI2C Data\noutput\t\t\tI2C_SCLK;\t\t\t\t//\tI2C Clock\n////////////////////////\tPS2\t\t////////////////////////////////\ninput\t\t \t   PS2_DAT;\t\t\t\t//\tPS2 Data\ninput\t\t\t   PS2_CLK;\t\t\t\t//\tPS2 Clock\n////////////////////\tUSB JTAG link\t////////////////////////////\ninput  \t\t\tTDI;\t\t\t\t\t// CPLD -> FPGA (data in)\ninput  \t\t\tTCK;\t\t\t\t\t// CPLD -> FPGA (clk)\ninput  \t\t\tTCS;\t\t\t\t\t// CPLD -> FPGA (CS)\noutput \t\t\tTDO;\t\t\t\t\t// FPGA -> CPLD (data out)\n////////////////////////\tVGA\t\t\t////////////////////////////\noutput\t\t\tVGA_CLK;   \t\t\t\t//\tVGA Clock\noutput\t\t\tVGA_HS;\t\t\t\t\t//\tVGA H_SYNC\noutput\t\t\tVGA_VS;\t\t\t\t\t//\tVGA V_SYNC\noutput\t\t\tVGA_BLANK;\t\t\t\t//\tVGA BLANK\noutput\t\t\tVGA_SYNC;\t\t\t\t//\tVGA SYNC\noutput\t[9:0]\tVGA_R;   \t\t\t\t//\tVGA Red[9:0]\noutput\t[9:0]\tVGA_G;\t \t\t\t\t//\tVGA Green[9:0]\noutput\t[9:0]\tVGA_B;   \t\t\t\t//\tVGA Blue[9:0]\n////////////////\tEthernet Interface\t////////////////////////////\ninout\t[15:0]\tENET_DATA;\t\t\t\t//\tDM9000A DATA bus 16Bits\noutput\t\t\tENET_CMD;\t\t\t\t//\tDM9000A Command/Data Select, 0 = Command, 1 = Data\noutput\t\t\tENET_CS_N;\t\t\t\t//\tDM9000A Chip Select\noutput\t\t\tENET_WR_N;\t\t\t\t//\tDM9000A Write\noutput\t\t\tENET_RD_N;\t\t\t\t//\tDM9000A Read\noutput\t\t\tENET_RST_N;\t\t\t\t//\tDM9000A Reset\ninput\t\t\t   ENET_INT;\t\t\t\t//\tDM9000A Interrupt\noutput\t\t\tENET_CLK;\t\t\t\t//\tDM9000A Clock 25 MHz\n////////////////////\tAudio CODEC\t\t////////////////////////////\ninout\t\t\t   AUD_ADCLRCK;\t\t\t//\tAudio CODEC ADC LR Clock\ninput\t\t\t   AUD_ADCDAT;\t\t\t\t//\tAudio CODEC ADC Data\ninout\t\t\t   AUD_DACLRCK;\t\t\t//\tAudio CODEC DAC LR Clock\noutput\t\t\tAUD_DACDAT;\t\t\t\t//\tAudio CODEC DAC Data\ninout\t\t\t   AUD_BCLK;\t\t\t\t//\tAudio CODEC Bit-Stream Clock\noutput\t\t\tAUD_XCK;\t\t\t\t//\tAudio CODEC Chip Clock\n////////////////////\tTV Devoder\t\t////////////////////////////\ninput\t [7:0]\tTD_DATA;    \t\t\t//\tTV Decoder Data bus 8 bits\ninput\t\t\t   TD_HS;\t\t\t\t\t//\tTV Decoder H_SYNC\ninput\t\t\t   TD_VS;\t\t\t\t\t//\tTV Decoder V_SYNC\noutput\t\t\tTD_RESET;\t\t\t\t//\tTV Decoder Reset\ninput          TD_CLK27;            //\tTV Decoder 27MHz CLK\n////////////////////////\tGPIO\t////////////////////////////////\ninout\t[35:0]\tGPIO_0;\t\t\t\t\t//\tGPIO Connection 0\ninout\t[35:0]\tGPIO_1;\t\t\t\t\t//\tGPIO Connection 1\n\twire clock = CLOCK_50;\n\twire [31:0] PC_IF, PC_ID, PC_EXE, PC_MEM;\n\twire [31:0] inst_IF, inst_ID;\n\twire [31:0] reg1_ID, reg2_ID, ST_value_EXE, ST_value_EXE2MEM, ST_value_MEM;\n\twire [31:0] val1_ID, val1_EXE;\n\twire [31:0] val2_ID, val2_EXE;\n\twire [31:0] ALURes_EXE, ALURes_MEM, ALURes_WB;\n\twire [31:0] dataMem_out_MEM, dataMem_out_WB;\n\twire [31:0] WB_result;\n\twire [4:0] dest_EXE, dest_MEM, dest_WB; // dest_ID = instruction[25:21] thus nothing declared\n\twire [4:0] src1_ID, src2_regFile_ID, src2_forw_ID, src2_forw_EXE, src1_forw_EXE;\n\twire [3:0] EXE_CMD_ID, EXE_CMD_EXE;\n\twire [1:0] val1_sel, val2_sel, ST_val_sel;\n\twire [1:0] branch_comm;\n\twire Br_Taken_ID, IF_Flush, Br_Taken_EXE;\n\twire MEM_R_EN_ID, MEM_R_EN_EXE, MEM_R_EN_MEM, MEM_R_EN_WB;\n\twire MEM_W_EN_ID, MEM_W_EN_EXE, MEM_W_EN_MEM;\n\twire WB_EN_ID, WB_EN_EXE, WB_EN_MEM, WB_EN_WB;\n\twire hazard_detected, is_imm, ST_or_BNE;\n\n\tregFile regFile(\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t.src1(src1_ID),\n\t\t.src2(src2_regFile_ID),\n\t\t.dest(dest_WB),\n\t\t.writeVal(WB_result),\n\t\t.writeEn(WB_EN_WB),\n\t\t// OUTPUTS\n\t\t.reg1(reg1_ID),\n\t\t.reg2(reg2_ID)\n\t);\n\n\thazard_detection hazard (\n\t\t// INPUTS\n\t\t.forward_EN(SW[1]),\n\t\t.is_imm(is_imm),\n\t\t.ST_or_BNE(ST_or_BNE),\n\t\t.src1_ID(src1_ID),\n\t\t.src2_ID(src2_regFile_ID),\n\t\t.dest_EXE(dest_EXE),\n\t\t.dest_MEM(dest_MEM),\n\t\t.WB_EN_EXE(WB_EN_EXE),\n\t\t.WB_EN_MEM(WB_EN_MEM),\n\t\t.MEM_R_EN_EXE(MEM_R_EN_EXE),\n\t\t// OUTPUTS\n\t\t.branch_comm(branch_comm),\n\t\t.hazard_detected(hazard_detected)\n\t);\n\n\tforwarding_EXE forwrding_EXE (\n\t\t.src1_EXE(src1_forw_EXE),\n\t\t.src2_EXE(src2_forw_EXE),\n\t\t.ST_src_EXE(dest_EXE),\n\t\t.dest_MEM(dest_MEM),\n\t\t.dest_WB(dest_WB),\n\t\t.WB_EN_MEM(WB_EN_MEM),\n\t\t.WB_EN_WB(WB_EN_WB),\n\t\t.val1_sel(val1_sel),\n\t\t.val2_sel(val2_sel),\n\t\t.ST_val_sel(ST_val_sel)\n\t);\n\n\t//###########################\n\t//##### PIPLINE STAGES ######\n\t//###########################\n\tIFStage IFStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t.freeze(hazard_detected),\n\t\t.brTaken(Br_Taken_ID),\n\t\t.brOffset(val2_ID),\n\t\t// OUTPUTS\n\t\t.instruction(inst_IF),\n\t\t.PC(PC_IF)\n\t);\n\n\tIDStage IDStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t.hazard_detected_in(hazard_detected),\n\t\t.instruction(inst_ID),\n\t\t.reg1(reg1_ID),\n\t\t.reg2(reg2_ID),\n\t\t// OUTPUTS\n\t\t.src1(src1_ID),\n\t\t.src2_reg_file(src2_regFile_ID),\n\t\t.src2_forw(src2_forw_ID),\n\t\t.val1(val1_ID),\n\t\t.val2(val2_ID),\n\t\t.brTaken(Br_Taken_ID),\n\t\t.EXE_CMD(EXE_CMD_ID),\n\t\t.MEM_R_EN(MEM_R_EN_ID),\n\t\t.MEM_W_EN(MEM_W_EN_ID),\n\t\t.WB_EN(WB_EN_ID),\n\t\t.is_imm_out(is_imm),\n\t\t.ST_or_BNE_out(ST_or_BNE),\n\t\t.branch_comm(branch_comm)\n\t);\n\n\tEXEStage EXEStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.EXE_CMD(EXE_CMD_EXE),\n\t\t.val1_sel(val1_sel),\n\t\t.val2_sel(val2_sel),\n\t\t.ST_val_sel(ST_val_sel),\n\t\t.val1(val1_EXE),\n\t\t.val2(val2_EXE),\n\t\t.ALU_res_MEM(ALURes_MEM),\n\t\t.result_WB(WB_result),\n\t\t.ST_value_in(ST_value_EXE),\n\t\t// OUTPUTS\n\t\t.ALUResult(ALURes_EXE),\n\t\t.ST_value_out(ST_value_EXE2MEM)\n\t);\n\n\tMEMStage MEMStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t.MEM_R_EN(MEM_R_EN_MEM),\n\t\t.MEM_W_EN(MEM_W_EN_MEM),\n\t\t.ALU_res(ALURes_MEM),\n\t\t.ST_value(ST_value_MEM),\n\t\t// OUTPUTS\n\t\t.dataMem_out(dataMem_out_MEM)\n\t);\n\n\tWBStage WBStage (\n\t\t// INPUTS\n\t\t.MEM_R_EN(MEM_R_EN_WB),\n\t\t.memData(dataMem_out_WB),\n\t\t.aluRes(ALURes_WB),\n\t\t// OUTPUTS\n\t\t.WB_res(WB_result)\n\t);\n\n\t//###########################\n\t//#### PIPLINE REISTERS #####\n\t//###########################\n\tIF2ID IF2IDReg (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t.flush(IF_Flush),\n\t\t.freeze(hazard_detected),\n\t\t.PCIn(PC_IF),\n\t\t.instructionIn(inst_IF),\n\t\t// OUTPUTS\n\t\t.PC(PC_ID),\n\t\t.instruction(inst_ID)\n\t);\n\n\tID2EXE ID2EXEReg (\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t// INPUTS\n\t\t.destIn(inst_ID[25:21]),\n\t\t.src1_in(src1_ID),\n\t\t.src2_in(src2_forw_ID),\n\t\t.reg2In(reg2_ID),\n\t\t.val1In(val1_ID),\n\t\t.val2In(val2_ID),\n\t\t.PCIn(PC_ID),\n\t\t.EXE_CMD_IN(EXE_CMD_ID),\n\t\t.MEM_R_EN_IN(MEM_R_EN_ID),\n\t\t.MEM_W_EN_IN(MEM_W_EN_ID),\n\t\t.WB_EN_IN(WB_EN_ID),\n\t\t.brTaken_in(Br_Taken_ID),\n\t\t// OUTPUTS\n\t\t.src1_out(src1_forw_EXE),\n\t\t.src2_out(src2_forw_EXE),\n\t\t.dest(dest_EXE),\n\t\t.ST_value(ST_value_EXE),\n\t\t.val1(val1_EXE),\n\t\t.val2(val2_EXE),\n\t\t.PC(PC_EXE),\n\t\t.EXE_CMD(EXE_CMD_EXE),\n\t\t.MEM_R_EN(MEM_R_EN_EXE),\n\t\t.MEM_W_EN(MEM_W_EN_EXE),\n\t\t.WB_EN(WB_EN_EXE),\n\t\t.brTaken_out(Br_Taken_EXE)\n\t);\n\n\tEXE2MEM EXE2MEMReg (\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t// INPUTS\n\t\t.WB_EN_IN(WB_EN_EXE),\n\t\t.MEM_R_EN_IN(MEM_R_EN_EXE),\n\t\t.MEM_W_EN_IN(MEM_W_EN_EXE),\n\t\t.PCIn(PC_EXE),\n\t\t.ALUResIn(ALURes_EXE),\n\t\t.STValIn(ST_value_EXE2MEM),\n\t\t.destIn(dest_EXE),\n\t\t// OUTPUTS\n\t\t.WB_EN(WB_EN_MEM),\n\t\t.MEM_R_EN(MEM_R_EN_MEM),\n\t\t.MEM_W_EN(MEM_W_EN_MEM),\n\t\t.PC(PC_MEM),\n\t\t.ALURes(ALURes_MEM),\n\t\t.STVal(ST_value_MEM),\n\t\t.dest(dest_MEM)\n\t);\n\n\tMEM2WB MEM2WB(\n\t\t.clk(clock),\n\t\t.rst(SW[0]),\n\t\t// INPUTS\n\t\t.WB_EN_IN(WB_EN_MEM),\n\t\t.MEM_R_EN_IN(MEM_R_EN_MEM),\n\t\t.ALUResIn(ALURes_MEM),\n\t\t.memReadValIn(dataMem_out_MEM),\n\t\t.destIn(dest_MEM),\n\t\t// OUTPUTS\n\t\t.WB_EN(WB_EN_WB),\n\t\t.MEM_R_EN(MEM_R_EN_WB),\n\t\t.ALURes(ALURes_WB),\n\t\t.memReadVal(dataMem_out_WB),\n\t\t.dest(dest_WB)\n\t);\n\n\tassign IF_Flush = Br_Taken_ID;\nendmodule\n"
  },
  {
    "path": "defines.v",
    "content": "// Wire widths\n`define WORD_LEN 32\n`define REG_FILE_ADDR_LEN 5\n`define EXE_CMD_LEN 4\n`define FORW_SEL_LEN 2\n`define OP_CODE_LEN 6\n\n// Memory constants\n`define DATA_MEM_SIZE 1024\n`define INSTR_MEM_SIZE 1024\n`define REG_FILE_SIZE 32\n`define MEM_CELL_SIZE 8\n\n// To be used inside controller.v\n`define OP_NOP 6'b000000\n`define OP_ADD 6'b000001\n`define OP_SUB 6'b000011\n`define OP_AND 6'b000101\n`define OP_OR 6'b000110\n`define OP_NOR 6'b000111\n`define OP_XOR 6'b001000\n`define OP_SLA 6'b001001\n`define OP_SLL 6'b001010\n`define OP_SRA 6'b001011\n`define OP_SRL 6'b001100\n`define OP_ADDI 6'b100000\n`define OP_SUBI 6'b100001\n`define OP_LD 6'b100100\n`define OP_ST 6'b100101\n`define OP_BEZ 6'b101000\n`define OP_BNE 6'b101001\n`define OP_JMP 6'b101010\n\n// To be used in side ALU\n`define EXE_ADD 4'b0000\n`define EXE_SUB 4'b0010\n`define EXE_AND 4'b0100\n`define EXE_OR 4'b0101\n`define EXE_NOR 4'b0110\n`define EXE_XOR 4'b0111\n`define EXE_SLA 4'b1000\n`define EXE_SLL 4'b1000\n`define EXE_SRA 4'b1001\n`define EXE_SRL 4'b1010\n`define EXE_NO_OPERATION 4'b1111 // for NOP, BEZ, BNQ, JMP\n\n// To be used in conditionChecker\n`define COND_JUMP 2'b10\n`define COND_BEZ 2'b11\n`define COND_BNE 2'b01\n`define COND_NOTHING 2'b00\n"
  },
  {
    "path": "instructions/example_source_code.txt",
    "content": "10000000001000000000000000001010; Addi r1,r0,10\t\t*** (1 begins) performing basic arithmetic operations\n00000100010000000000100000000000; Add  r2,r0,r1\t\t***\n00001100011000000000100000000000; sub r3,r0,r1\t\t***\n00010100100000100001100000000000; And r4,r2,r3\t\t***\n10000100101000000000001000110100; Subi r5,r0,564\t\t***\n00011000101001010001100000000000; or r5,r5,r3\t\t***\n00011100110001010000000000000000; nor  r6,r5,r0\t\t***\n00100000000001010000100000000000; xor r0,r5,r1\t\t***\n00100000111001010000100000000000; xor r7,r5,r1\t\t***\n00100100111001000001000000000000; sla r7,r4,r2\t\t***\n00101001000000110001000000000000; sll r8,r3,r2\t\t***\n00101101001001100001000000000000; sra r9,r6,r2\t\t***\n00110001010001100001000000000000; srl r10,r6,r2\t\t*** (1 ends)\n10000000001000000000010000000000; Addi r1,r0,1024\t\t*** (2 begins) exchanging some data with the memory\n10010100010000010000000000000000; st r2,r1,0\t\t***\n10010001011000010000000000000000; ld r11,r1,0\t\t***\n10010100011000010000000000000100; st r3,r1,4\t\t***\n10010100100000010000000000001000; st r4,r1,8\t\t***\n10010100101000010000000000001100; st r5,r1,12\t\t***\n10010100110000010000000000010000; st r6,r1,16\t\t***\n10010100111000010000000000010100; st r7,r1,20\t\t***\n10010101000000010000000000011000; st r8,r1,24\t\t***\n10010101001000010000000000011100; st r9,r1,28\t\t***\n10010101010000010000000000100000; st r10,r1,32\t\t***\n10010101011000010000000000100100; st r11,r1,36\t\t*** (2 ends)\n10000000001000000000000000000011; Addi  r1,r0,3\t\t*** =====> BUBBLE SORT BEGINS\n10000000100000000000010000000000; Addi r4,r0,1024\t\t***\n10000000010000000000000000000000; Addi  r2,r0,0\t\t***\n10000000011000000000000000000001; Addi  r3,r0,1 \t\t*** (outer loop begins)\n10000001001000000000000000000010; Addi  r9,r0,2 \t\t*** (inner loop begins)\n00101001000000110100100000000000; sll r8,r3,r9\t\t*** (3 begins) loading two consecutive numbers to compare\n00000101000001000100000000000000; Add  r8,r4,r8\t\t***\n10010000101010000000000000000000; ld r5,r8,0 \t\t***\n10010000110010001111111111111100; ld r6,r8,-4 \t\t***\n00001101001001010011000000000000; sub  r9,r5,r6 \t\t***\n10000001010000001000000000000000; Addi  r10,r0,0x8000\t***\n10000001011000000000000000010000; Addi r11,r0,16\t\t***\n00101001010010100101100000000000; sll r10,r10,r11\t\t***\n00010101001010010101000000000000; And r9,r9,r10\t\t*** (3 ends)\n10100000000010010000000000000010; Bez r9,2 \t\t*** (4 begins) swapping the two loaded numbers if needed\n10010100101010001111111111111100; st r5,r8,-4 \t\t***\n10010100110010000000000000000000; st r6,r8,0 \t\t*** (4 ends)\n10000000011000110000000000000001; Addi  r3,r3,1\t\t*** R3++\n10100100011000011111111111110001; BNE r3,r1,-15 \t\t*** (inner loop ends)\n10000000010000100000000000000001; Addi  r2,r2,1\t\t*** R2++\n10100100010000011111111111101110; BNE r2,r1,-18 \t\t*** (outer loop ends) =====> BUBBLE SORT ENDS\n10000000001000000000010000000000; Addi  r1,r0,1024 \t*** (5 begins) storing some register inside memory\n10010000010000010000000000000000; ld r2,r1,0\t\t***\n10010000011000010000000000000100; ld r3,r1,4\t\t***\n10010000100000010000000000001000; ld r4,r1,8\t\t***\n10010000101000010000000000001100; ld r5,r1,12\t\t***\n10010000110000010000000000010000; ld r6,r1,16\t\t***\n10010000111000010000000000010100; ld r7,r1,20\t\t***\n10010001000000010000000000011000; ld r8,r1,24\t\t***\n10010001001000010000000000011100; ld r9,r1,28\t\t***\n10010001010000010000000000100000; ld r10,r1,32\t\t***\n10010001011000010000000000100100; ld r11,r1,36\t\t*** (5 ends)\n10101000000000001111111111111111; JMP  -1 \t\t\t*** will keep jumping to itself\n"
  },
  {
    "path": "instructions/rearrange_instructions.py",
    "content": "#!/usr/bin/env python\n# -*- coding: utf-8 -*-\n\n# Rearranging instructions from a source file to a format suitable for the always statement under instructionMem.v\n# There is an example source code under this directory\n# In drafting your own code, make sure you follow the ISA in this project\n\nDESTINATION_FILE_NAME = \"ready_instructions.txt\"\nINSTR_MEM_ARRAY_NAME = \"instMem\"\n\nline_count = int(raw_input(\"Enter the number of instructions to rearrange: \"))\nsource_file_name = raw_input(\"Enter the source file name: \")\n\ninstructions = []\n\nwith open(source_file_name, \"r\") as instr_file:\n    for i in range(line_count):\n        instructions.append(instr_file.readline()[:-1])\n\nwith open(DESTINATION_FILE_NAME, \"w\") as dest_file:\n    for i in range(len(instructions)):\n        instr = instructions[i]\n        dest_file.write(INSTR_MEM_ARRAY_NAME + \"[\" + str(i*4)   + \"] <= 8'b\" + instr[0:8] + \"; // ==> \" + instr[34:] + \"\\n\")\n        dest_file.write(INSTR_MEM_ARRAY_NAME + \"[\" + str(i*4+1) + \"] <= 8'b\" + instr[8:16] + \";\\n\")\n        dest_file.write(INSTR_MEM_ARRAY_NAME + \"[\" + str(i*4+2) + \"] <= 8'b\" + instr[16:24] + \";\\n\")\n        dest_file.write(INSTR_MEM_ARRAY_NAME + \"[\" + str(i*4+3) + \"] <= 8'b\" + instr[24:32] + \";\\n\\n\")\n\n\nprint \"💡💡💡 ==> instructions reformatted for instruction memory.\"\nprint \"To run them, copy and paste the content of ready_instructions.txt under the reset if statement in the instructionMem.v always statement.\"\n"
  },
  {
    "path": "modules/ALU.v",
    "content": "`include \"defines.v\"\n\nmodule ALU (val1, val2, EXE_CMD, aluOut);\n  input [`WORD_LEN-1:0] val1, val2;\n  input [`EXE_CMD_LEN-1:0] EXE_CMD;\n  output reg [`WORD_LEN-1:0] aluOut;\n\n  always @ ( * ) begin\n    case (EXE_CMD)\n      `EXE_ADD: aluOut <= val1 + val2;\n      `EXE_SUB: aluOut <= val1 - val2;\n      `EXE_AND: aluOut <= val1 & val2;\n      `EXE_OR: aluOut <= val1 | val2;\n      `EXE_NOR: aluOut <= ~(val1 | val2);\n      `EXE_XOR: aluOut <= val1 ^ val2;\n      `EXE_SLA: aluOut <= val1 << val2;\n      `EXE_SLL: aluOut <= val1 <<< val2;\n      `EXE_SRA: aluOut <= val1 >> val2;\n      `EXE_SRL: aluOut <= val1 >>> val2;\n      default: aluOut <= 0;\n    endcase\n  end\nendmodule // ALU\n"
  },
  {
    "path": "modules/adder.v",
    "content": "`include \"defines.v\"\n\nmodule adder (in1, in2, out);\n  input [`WORD_LEN-1:0] in1, in2;\n  output [`WORD_LEN-1:0] out;\n\n  assign out = in1 + in2;\nendmodule // adder\n"
  },
  {
    "path": "modules/controlUnit/conditionChecker.v",
    "content": "`include \"defines.v\"\n\nmodule conditionChecker (reg1, reg2, cuBranchComm, brCond);\n  input [`WORD_LEN-1: 0] reg1, reg2;\n  input [1:0] cuBranchComm;\n  output reg brCond;\n\n  always @ ( * ) begin\n    case (cuBranchComm)\n      `COND_JUMP: brCond <= 1;\n      `COND_BEZ: brCond <= (reg1 == 0) ? 1 : 0;\n      `COND_BNE: brCond <= (reg1 != reg2) ? 1 : 0;\n      default: brCond <= 0;\n    endcase\n  end\nendmodule // conditionChecker\n"
  },
  {
    "path": "modules/controlUnit/controller.v",
    "content": "`include \"defines.v\"\n\nmodule controller (opCode, branchEn, EXE_CMD, Branch_command, Is_Imm, ST_or_BNE, WB_EN, MEM_R_EN, MEM_W_EN, hazard_detected);\n  input hazard_detected;\n  input [`OP_CODE_LEN-1:0] opCode;\n  output reg branchEn;\n  output reg [`EXE_CMD_LEN-1:0] EXE_CMD;\n  output reg [1:0] Branch_command;\n  output reg Is_Imm, ST_or_BNE, WB_EN, MEM_R_EN, MEM_W_EN;\n\n  always @ ( * ) begin\n    if (hazard_detected == 0) begin\n      {branchEn, EXE_CMD, Branch_command, Is_Imm, ST_or_BNE, WB_EN, MEM_R_EN, MEM_W_EN} <= 0;\n      case (opCode)\n        // operations writing to the register file\n        `OP_ADD: begin EXE_CMD <= `EXE_ADD; WB_EN <= 1; end\n        `OP_SUB: begin EXE_CMD <= `EXE_SUB; WB_EN <= 1; end\n        `OP_AND: begin EXE_CMD <= `EXE_AND; WB_EN <= 1; end\n        `OP_OR:  begin EXE_CMD <= `EXE_OR;  WB_EN <= 1; end\n        `OP_NOR: begin EXE_CMD <= `EXE_NOR; WB_EN <= 1; end\n        `OP_XOR: begin EXE_CMD <= `EXE_XOR; WB_EN <= 1; end\n        `OP_SLA: begin EXE_CMD <= `EXE_SLA; WB_EN <= 1; end\n        `OP_SLL: begin EXE_CMD <= `EXE_SLL; WB_EN <= 1; end\n        `OP_SRA: begin EXE_CMD <= `EXE_SRA; WB_EN <= 1; end\n        `OP_SRL: begin EXE_CMD <= `EXE_SRL; WB_EN <= 1; end\n        // operations using an immediate value embedded in the instruction\n        `OP_ADDI: begin EXE_CMD <= `EXE_ADD; WB_EN <= 1; Is_Imm <= 1; end\n        `OP_SUBI: begin EXE_CMD <= `EXE_SUB; WB_EN <= 1; Is_Imm <= 1; end\n        // memory operations\n        `OP_LD: begin EXE_CMD <= `EXE_ADD; WB_EN <= 1; Is_Imm <= 1; ST_or_BNE <= 1; MEM_R_EN <= 1; end\n        `OP_ST: begin EXE_CMD <= `EXE_ADD; Is_Imm <= 1; MEM_W_EN <= 1; ST_or_BNE <= 1; end\n        // branch operations\n        `OP_BEZ: begin EXE_CMD <= `EXE_NO_OPERATION; Is_Imm <= 1; Branch_command <= `COND_BEZ; branchEn <= 1; end\n        `OP_BNE: begin EXE_CMD <= `EXE_NO_OPERATION; Is_Imm <= 1; Branch_command <= `COND_BNE; branchEn <= 1; ST_or_BNE <= 1; end\n        `OP_JMP: begin EXE_CMD <= `EXE_NO_OPERATION; Is_Imm <= 1; Branch_command <= `COND_JUMP; branchEn <= 1; end\n        default: {branchEn, EXE_CMD, Branch_command, Is_Imm, ST_or_BNE, WB_EN, MEM_R_EN, MEM_W_EN} <= 0;\n      endcase\n    end\n\n    else if (hazard_detected ==  1) begin\n      // preventing any writes to the register file or the memory\n      {EXE_CMD, WB_EN, MEM_W_EN} <= 0;\n    end\n  end\nendmodule // controller\n"
  },
  {
    "path": "modules/hazard_forwarding/forwarding.v",
    "content": "`include \"defines.v\"\n\nmodule forwarding_EXE (src1_EXE, src2_EXE, ST_src_EXE, dest_MEM, dest_WB, WB_EN_MEM, WB_EN_WB, val1_sel, val2_sel, ST_val_sel);\n  input [`REG_FILE_ADDR_LEN-1:0] src1_EXE, src2_EXE, ST_src_EXE;\n  input [`REG_FILE_ADDR_LEN-1:0] dest_MEM, dest_WB;\n  input WB_EN_MEM, WB_EN_WB;\n  output reg [`FORW_SEL_LEN-1:0] val1_sel, val2_sel, ST_val_sel;\n\n  always @ ( * ) begin\n    // initializing sel signals to 0\n    // they will change to enable forwrding if needed.\n    {val1_sel, val2_sel, ST_val_sel} <= 0;\n\n    // determining forwarding control signal for store value (ST_val)\n    if (WB_EN_MEM && ST_src_EXE == dest_MEM) ST_val_sel <= 2'd1;\n    else if (WB_EN_WB && ST_src_EXE == dest_WB) ST_val_sel <= 2'd2;\n\n    // determining forwarding control signal for ALU val1\n    if (WB_EN_MEM && src1_EXE == dest_MEM) val1_sel <= 2'd1;\n    else if (WB_EN_WB && src1_EXE == dest_WB) val1_sel <= 2'd2;\n\n    // determining forwarding control signal for ALU val2\n    if (WB_EN_MEM && src2_EXE == dest_MEM) val2_sel <= 2'd1;\n    else if (WB_EN_WB && src2_EXE == dest_WB) val2_sel <= 2'd2;\n  end\nendmodule // forwarding\n"
  },
  {
    "path": "modules/hazard_forwarding/hazardDetection.v",
    "content": "`include \"defines.v\"\n\nmodule hazard_detection(forward_EN, is_imm, ST_or_BNE, src1_ID, src2_ID, dest_EXE, WB_EN_EXE, dest_MEM, WB_EN_MEM, MEM_R_EN_EXE, branch_comm, hazard_detected);\n  input [`REG_FILE_ADDR_LEN-1:0] src1_ID, src2_ID;\n  input [`REG_FILE_ADDR_LEN-1:0] dest_EXE, dest_MEM;\n  input [1:0] branch_comm;\n  input forward_EN, WB_EN_EXE, WB_EN_MEM, is_imm, ST_or_BNE, MEM_R_EN_EXE;\n  output hazard_detected;\n\n  wire src2_is_valid, exe_has_hazard, mem_has_hazard, hazard, instr_is_branch;\n\n  assign src2_is_valid =  (~is_imm) || ST_or_BNE;\n\n  assign exe_has_hazard = WB_EN_EXE && (src1_ID == dest_EXE || (src2_is_valid && src2_ID == dest_EXE));\n  assign mem_has_hazard = WB_EN_MEM && (src1_ID == dest_MEM || (src2_is_valid && src2_ID == dest_MEM));\n\n  assign hazard = (exe_has_hazard || mem_has_hazard);\n  assign instr_is_branch = (branch_comm == `COND_BEZ || branch_comm == `COND_BNE);\n\n  assign hazard_detected = ~forward_EN ? hazard : (instr_is_branch && hazard) || (MEM_R_EN_EXE && mem_has_hazard);\nendmodule // hazard_detection\n"
  },
  {
    "path": "modules/memoryModules/dataMem.v",
    "content": "`include \"defines.v\"\n\nmodule dataMem (clk, rst, writeEn, readEn, address, dataIn, dataOut);\n  input clk, rst, readEn, writeEn;\n  input [`WORD_LEN-1:0] address, dataIn;\n  output [`WORD_LEN-1:0] dataOut;\n\n  integer i;\n  reg [`MEM_CELL_SIZE-1:0] dataMem [0:`DATA_MEM_SIZE-1];\n  wire [`WORD_LEN-1:0] base_address;\n\n  always @ (posedge clk) begin\n    if (rst)\n      for (i = 0; i < `DATA_MEM_SIZE; i = i + 1)\n        dataMem[i] <= 0;\n    else if (writeEn)\n      {dataMem[base_address], dataMem[base_address + 1], dataMem[base_address + 2], dataMem[base_address + 3]} <= dataIn;\n  end\n\n  assign base_address = ((address & 32'b11111111111111111111101111111111) >> 2) << 2;\n  assign dataOut = (address < 1024) ? 0 : {dataMem[base_address], dataMem[base_address + 1], dataMem[base_address + 2], dataMem[base_address + 3]};\nendmodule // dataMem\n"
  },
  {
    "path": "modules/memoryModules/instructionMem.v",
    "content": "`include \"defines.v\"\n\nmodule instructionMem (rst, addr, instruction);\n  input rst;\n  input [`WORD_LEN-1:0] addr;\n  output [`WORD_LEN-1:0] instruction;\n\n  wire [$clog2(`INSTR_MEM_SIZE)-1:0] address = addr[$clog2(`INSTR_MEM_SIZE)-1:0];\n  reg [`MEM_CELL_SIZE-1:0] instMem [0:`INSTR_MEM_SIZE-1];\n\n  always @ (*) begin\n  \tif (rst) begin\n        // No nop added in between instructions since there is a hazard detection unit\n\n        instMem[0] <= 8'b10000000; //-- Addi\tr1,r0,10\n        instMem[1] <= 8'b00100000;\n        instMem[2] <= 8'b00000000;\n        instMem[3] <= 8'b00001010;\n\n        instMem[4] <= 8'b00000100; //-- Add \tr2,r0,r1\n        instMem[5] <= 8'b01000000;\n        instMem[6] <= 8'b00001000;\n        instMem[7] <= 8'b00000000;\n\n        instMem[8] <= 8'b00001100; //-- sub\tr3,r0,r1\n        instMem[9] <= 8'b01100000;\n        instMem[10] <= 8'b00001000;\n        instMem[11] <= 8'b00000000;\n\n        instMem[12] <= 8'b00010100; //-- And\tr4,r2,r3\n        instMem[13] <= 8'b10000010;\n        instMem[14] <= 8'b00011000;\n        instMem[15] <= 8'b00000000;\n\n        instMem[16] <= 8'b10000100; //-- Subi\tr5,r0,564\n        instMem[17] <= 8'b10100000;\n        instMem[18] <= 8'b00000010;\n        instMem[19] <= 8'b00110100;\n\n        instMem[20] <= 8'b00011000; //-- or\tr5,r5,r3\n        instMem[21] <= 8'b10100101;\n        instMem[22] <= 8'b00011000;\n        instMem[23] <= 8'b00000000;\n\n        instMem[24] <= 8'b00011100; //-- nor \tr6,r5,r0\n        instMem[25] <= 8'b11000101;\n        instMem[26] <= 8'b00000000;\n        instMem[27] <= 8'b00000000;\n\n        instMem[28] <= 8'b00100000; //-- xor\tr0,r5,r1\n        instMem[29] <= 8'b00000101;\n        instMem[30] <= 8'b00001000;\n        instMem[31] <= 8'b00000000;\n\n        instMem[32] <= 8'b00100000; //-- xor\tr7,r5,r0\n        instMem[33] <= 8'b11100101;\n        instMem[34] <= 8'b00001000;\n        instMem[35] <= 8'b00000000;\n\n        instMem[36] <= 8'b00100100; //-- sla\tr7,r4,r2\n        instMem[37] <= 8'b11100100;\n        instMem[38] <= 8'b00010000;\n        instMem[39] <= 8'b00000000;\n\n        instMem[40] <= 8'b00101001; //-- sll\tr8,r3,r2\n        instMem[41] <= 8'b00000011;\n        instMem[42] <= 8'b00010000;\n        instMem[43] <= 8'b00000000;\n\n        instMem[44] <= 8'b00101101; //-- sra\tr9,r6,r2\n        instMem[45] <= 8'b00100110;\n        instMem[46] <= 8'b00010000;\n        instMem[47] <= 8'b00000000;\n\n        instMem[48] <= 8'b00110001; //-- srl\tr10,r6,r2\n        instMem[49] <= 8'b01000110;\n        instMem[50] <= 8'b00010000;\n        instMem[51] <= 8'b00000000;\n\n        instMem[52] <= 8'b10000000; //-- Addi \tr1,r0,1024\n        instMem[53] <= 8'b00100000;\n        instMem[54] <= 8'b00000100;\n        instMem[55] <= 8'b00000000;\n\n        instMem[56] <= 8'b10010100; //-- st\tr2,r1,0\n        instMem[57] <= 8'b01000001;\n        instMem[58] <= 8'b00000000;\n        instMem[59] <= 8'b00000000;\n\n        instMem[60] <= 8'b10010001; //-- ld\tr11,r1,0\n        instMem[61] <= 8'b01100001;\n        instMem[62] <= 8'b00000000;\n        instMem[63] <= 8'b00000000;\n\n        instMem[64] <= 8'b10010100; //-- st\tr3,r1,4\n        instMem[65] <= 8'b01100001;\n        instMem[66] <= 8'b00000000;\n        instMem[67] <= 8'b00000100;\n\n        instMem[68] <= 8'b10010100; //-- st\tr4,r1,8\n        instMem[69] <= 8'b10000001;\n        instMem[70] <= 8'b00000000;\n        instMem[71] <= 8'b00001000;\n\n        instMem[72] <= 8'b10010100; //-- st\tr5,r1,12\n        instMem[73] <= 8'b10100001;\n        instMem[74] <= 8'b00000000;\n        instMem[75] <= 8'b00001100;\n\n        instMem[76] <= 8'b10010100; //-- st\tr6,r1,16\n        instMem[77] <= 8'b11000001;\n        instMem[78] <= 8'b00000000;\n        instMem[79] <= 8'b00010000;\n\n        instMem[80] <= 8'b10010100; //-- st\tr7,r1,20\n        instMem[81] <= 8'b11100001;\n        instMem[82] <= 8'b00000000;\n        instMem[83] <= 8'b00010100;\n\n        instMem[84] <= 8'b10010101; //-- st\tr8,r1,24\n        instMem[85] <= 8'b00000001;\n        instMem[86] <= 8'b00000000;\n        instMem[87] <= 8'b00011000;\n\n        instMem[88] <= 8'b10010101; //-- st\tr9,r1,28\n        instMem[89] <= 8'b00100001;\n        instMem[90] <= 8'b00000000;\n        instMem[91] <= 8'b00011100;\n\n        instMem[92] <= 8'b10010101; //-- st\tr10,r1,32\n        instMem[93] <= 8'b01000001;\n        instMem[94] <= 8'b00000000;\n        instMem[95] <= 8'b00100000;\n\n        instMem[96] <= 8'b10010101; //-- st\tr11,r1,36\n        instMem[97] <= 8'b01100001;\n        instMem[98] <= 8'b00000000;\n        instMem[99] <= 8'b00100100;\n\n        instMem[100] <= 8'b10000000; //-- Addi \tr1,r0,3\n        instMem[101] <= 8'b00100000;\n        instMem[102] <= 8'b00000000;\n        instMem[103] <= 8'b00000011;\n\n        instMem[104] <= 8'b10000000; //-- Addi\tr4,r0,1024\n        instMem[105] <= 8'b10000000;\n        instMem[106] <= 8'b00000100;\n        instMem[107] <= 8'b00000000;\n\n        instMem[108] <= 8'b10000000; //-- Addi \tr2,r0,0\n        instMem[109] <= 8'b01000000;\n        instMem[110] <= 8'b00000000;\n        instMem[111] <= 8'b00000000;\n\n        instMem[112] <= 8'b10000000; //-- Addi \tr3,r0,1\n        instMem[113] <= 8'b01100000;\n        instMem[114] <= 8'b00000000;\n        instMem[115] <= 8'b00000001;\n\n        instMem[116] <= 8'b10000001; //-- Addi \tr9,r0,2\n        instMem[117] <= 8'b00100000;\n        instMem[118] <= 8'b00000000;\n        instMem[119] <= 8'b00000010;\n\n        instMem[120] <= 8'b00101001; //-- sll\tr8,r3,r9\n        instMem[121] <= 8'b00000011;\n        instMem[122] <= 8'b01001000;\n        instMem[123] <= 8'b00000000;\n\n        instMem[124] <= 8'b00000101; //-- Add \tr8,r4,r8\n        instMem[125] <= 8'b00000100;\n        instMem[126] <= 8'b01000000;\n        instMem[127] <= 8'b00000000;\n\n        instMem[128] <= 8'b10010000; //-- ld\tr5,r8,0\n        instMem[129] <= 8'b10101000;\n        instMem[130] <= 8'b00000000;\n        instMem[131] <= 8'b00000000;\n\n        instMem[132] <= 8'b10010000; //-- ld\tr6,r8,-4\n        instMem[133] <= 8'b11001000;\n        instMem[134] <= 8'b11111111;\n        instMem[135] <= 8'b11111100;\n\n        instMem[136] <= 8'b00001101; //-- sub \tr9,r5,r6\n        instMem[137] <= 8'b00100101;\n        instMem[138] <= 8'b00110000;\n        instMem[139] <= 8'b00000000;\n\n        instMem[140] <= 8'b10000001; //-- Addi \tr10,r0,0x8000\n        instMem[141] <= 8'b01000000;\n        instMem[142] <= 8'b10000000;\n        instMem[143] <= 8'b00000000;\n\n        instMem[144] <= 8'b10000001; //-- Addi\tr11,r0,16\n        instMem[145] <= 8'b01100000;\n        instMem[146] <= 8'b00000000;\n        instMem[147] <= 8'b00010000;\n\n        instMem[148] <= 8'b00101001; //-- sll\tr10,r10,r11\n        instMem[149] <= 8'b01001010;\n        instMem[150] <= 8'b01011000;\n        instMem[151] <= 8'b00000000;\n\n        instMem[152] <= 8'b00010101; //-- And \tr9,r9,r10\n        instMem[153] <= 8'b00101001;\n        instMem[154] <= 8'b01010000;\n        instMem[155] <= 8'b00000000;\n\n        instMem[156] <= 8'b10100000; //-- Bez\tr9,2\n        instMem[157] <= 8'b00001001;\n        instMem[158] <= 8'b00000000;\n        instMem[159] <= 8'b00000010;\n\n        instMem[160] <= 8'b10010100; //-- st\tr5,r8,-4\n        instMem[161] <= 8'b10101000;\n        instMem[162] <= 8'b11111111;\n        instMem[163] <= 8'b11111100;\n\n        instMem[164] <= 8'b10010100; //-- st\tr6,r8,0\n        instMem[165] <= 8'b11001000;\n        instMem[166] <= 8'b00000000;\n        instMem[167] <= 8'b00000000;\n\n        instMem[168] <= 8'b10000000; //-- Addi \tr3,r3,1\n        instMem[169] <= 8'b01100011;\n        instMem[170] <= 8'b00000000;\n        instMem[171] <= 8'b00000001;\n\n        instMem[172] <= 8'b10100100; //-- BNE\tr3,r1,-15\n        instMem[173] <= 8'b01100001;\n        instMem[174] <= 8'b11111111;\n        instMem[175] <= 8'b11110001;\n\n        instMem[176] <= 8'b10000000; //-- Addi \tr2,r2,1\n        instMem[177] <= 8'b01000010;\n        instMem[178] <= 8'b00000000;\n        instMem[179] <= 8'b00000001;\n\n        instMem[180] <= 8'b10100100; //-- BNE\tr2,r1,-18\n        instMem[181] <= 8'b01000001;\n        instMem[182] <= 8'b11111111;\n        instMem[183] <= 8'b11101110;\n\n        instMem[184] <= 8'b10000000; //-- Addi \tr1,r0,1024\n        instMem[185] <= 8'b00100000;\n        instMem[186] <= 8'b00000100;\n        instMem[187] <= 8'b00000000;\n\n        instMem[188] <= 8'b10010000; //-- ld\tr2,r1,0\n        instMem[189] <= 8'b01000001;\n        instMem[190] <= 8'b00000000;\n        instMem[191] <= 8'b00000000;\n\n        instMem[192] <= 8'b10010000; //-- ld\tr3,r1,4\n        instMem[193] <= 8'b01100001;\n        instMem[194] <= 8'b00000000;\n        instMem[195] <= 8'b00000100;\n\n        instMem[196] <= 8'b10010000; //-- ld\tr4,r1,8\n        instMem[197] <= 8'b10000001;\n        instMem[198] <= 8'b00000000;\n        instMem[199] <= 8'b00001000;\n\n        instMem[200] <= 8'b10010000; //-- ld\tr5,r1,12\n        instMem[201] <= 8'b10100001;\n        instMem[202] <= 8'b00000000;\n        instMem[203] <= 8'b00001100;\n\n        instMem[204] <= 8'b10010000; //-- ld\tr6,r1,16\n        instMem[205] <= 8'b11000001;\n        instMem[206] <= 8'b00000000;\n        instMem[207] <= 8'b00010000;\n\n        instMem[208] <= 8'b10010000; //-- ld\tr7,r1,20\n        instMem[209] <= 8'b11100001;\n        instMem[210] <= 8'b00000000;\n        instMem[211] <= 8'b00010100;\n\n        instMem[212] <= 8'b10010001; //-- ld\tr8,r1,24\n        instMem[213] <= 8'b00000001;\n        instMem[214] <= 8'b00000000;\n        instMem[215] <= 8'b00011000;\n\n        instMem[216] <= 8'b10010001; //-- ld\tr9,r1,28\n        instMem[217] <= 8'b00100001;\n        instMem[218] <= 8'b00000000;\n        instMem[219] <= 8'b00011100;\n\n        instMem[220] <= 8'b10010001; //-- ld\tr10,r1,32\n        instMem[221] <= 8'b01000001;\n        instMem[222] <= 8'b00000000;\n        instMem[223] <= 8'b00100000;\n\n        instMem[224] <= 8'b10010001; //-- ld\tr11,r1,36\n        instMem[225] <= 8'b01100001;\n        instMem[226] <= 8'b00000000;\n        instMem[227] <= 8'b00100100;\n\n        instMem[228] <= 8'b10101000; //-- JMP \t-1\n        instMem[229] <= 8'b00000000;\n        instMem[230] <= 8'b11111111;\n        instMem[231] <= 8'b11111111;\n\n        instMem[232] <= 8'b00000000; //-- NOPE\n        instMem[233] <= 8'b00000000;\n        instMem[234] <= 8'b00000000;\n        instMem[235] <= 8'b00000000;\n      end\n    end\n\n  assign instruction = {instMem[address], instMem[address + 1], instMem[address + 2], instMem[address + 3]};\nendmodule // insttructionMem\n"
  },
  {
    "path": "modules/memoryModules/regFile.v",
    "content": "`include \"defines.v\"\n\nmodule regFile (clk, rst, src1, src2, dest, writeVal, writeEn, reg1, reg2);\n  input clk, rst, writeEn;\n  input [`REG_FILE_ADDR_LEN-1:0] src1, src2, dest;\n  input [`WORD_LEN-1:0] writeVal;\n  output [`WORD_LEN-1:0] reg1, reg2;\n\n  reg [`WORD_LEN-1:0] regMem [0:`REG_FILE_SIZE-1];\n  integer i;\n\n  always @ (negedge clk) begin\n    if (rst) begin\n      for (i = 0; i < `WORD_LEN; i = i + 1)\n        regMem[i] <= 0;\n\t    end\n\n    else if (writeEn) regMem[dest] <= writeVal;\n    regMem[0] <= 0;\n  end\n\n  assign reg1 = (regMem[src1]);\n  assign reg2 = (regMem[src2]);\nendmodule // regFile\n"
  },
  {
    "path": "modules/mux.v",
    "content": "`include \"defines.v\"\n\nmodule mux #(parameter integer LENGTH) (in1, in2, sel, out);\n  input sel;\n  input [LENGTH-1:0] in1, in2;\n  output [LENGTH-1:0] out;\n\n  assign out = (sel == 0) ? in1 : in2;\nendmodule // mxu\n\nmodule mux_3input #(parameter integer LENGTH) (in1, in2, in3, sel, out);\n  input [LENGTH-1:0] in1, in2, in3;\n  input [1:0] sel;\n  output [LENGTH-1:0] out;\n\n  assign out = (sel == 2'd0) ? in1 :\n               (sel == 2'd1) ? in2 : in3;\nendmodule // mux\n"
  },
  {
    "path": "modules/pipeRegisters/EXE2MEM.v",
    "content": "`include \"defines.v\"\n\nmodule EXE2MEM (clk, rst, WB_EN_IN, MEM_R_EN_IN, MEM_W_EN_IN, PCIn, ALUResIn, STValIn, destIn,\n                          WB_EN,    MEM_R_EN,    MEM_W_EN,    PC,   ALURes,   STVal,   dest);\n  input clk, rst;\n  // TO BE REGISTERED FOR ID STAGE\n  input WB_EN_IN, MEM_R_EN_IN, MEM_W_EN_IN;\n  input [`REG_FILE_ADDR_LEN-1:0] destIn;\n  input [`WORD_LEN-1:0] PCIn, ALUResIn, STValIn;\n  // REGISTERED VALUES FOR ID STAGE\n  output reg WB_EN, MEM_R_EN, MEM_W_EN;\n  output reg [`REG_FILE_ADDR_LEN-1:0] dest;\n  output reg [`WORD_LEN-1:0] PC, ALURes, STVal;\n\n  always @ (posedge clk) begin\n    if (rst) begin\n      {WB_EN, MEM_R_EN, MEM_W_EN, PC, ALURes, STVal, dest} <= 0;\n    end\n    else begin\n      WB_EN <= WB_EN_IN;\n      MEM_R_EN <= MEM_R_EN_IN;\n      MEM_W_EN <= MEM_W_EN_IN;\n      PC <= PCIn;\n      ALURes <= ALUResIn;\n      STVal <= STValIn;\n      dest <= destIn;\n    end\n  end\nendmodule // EXE2MEM\n"
  },
  {
    "path": "modules/pipeRegisters/ID2EXE.v",
    "content": "`include \"defines.v\"\n\nmodule ID2EXE (clk, rst, destIn, reg2In, val1In, val2In, PCIn, EXE_CMD_IN, MEM_R_EN_IN, MEM_W_EN_IN, WB_EN_IN, brTaken_in, src1_in, src2_in,\n                         dest,   ST_value,   val1,   val2,   PC,  EXE_CMD,    MEM_R_EN,    MEM_W_EN,    WB_EN, brTaken_out, src1_out, src2_out);\n  input clk, rst;\n  // TO BE REGISTERED FOR ID STAGE\n  input MEM_R_EN_IN, MEM_W_EN_IN, WB_EN_IN, brTaken_in;\n  input [`EXE_CMD_LEN-1:0] EXE_CMD_IN;\n  input [`REG_FILE_ADDR_LEN-1:0] destIn, src1_in, src2_in;\n  input [`WORD_LEN-1:0] reg2In, val1In, val2In, PCIn;\n  // REGISTERED VALUES FOR ID STAGE\n  output reg MEM_R_EN, MEM_W_EN, WB_EN, brTaken_out;\n  output reg [`EXE_CMD_LEN-1:0] EXE_CMD;\n  output reg [`REG_FILE_ADDR_LEN-1:0] dest, src1_out, src2_out;\n  output reg [`WORD_LEN-1:0] ST_value, val1, val2, PC;\n\n  always @ (posedge clk) begin\n    if (rst) begin\n      {MEM_R_EN, MEM_R_EN, WB_EN, EXE_CMD, dest, ST_value, val1, val2, PC, brTaken_out, src1_out, src2_out} <= 0;\n    end\n    else begin\n      MEM_R_EN <= MEM_R_EN_IN;\n      MEM_W_EN <= MEM_W_EN_IN;\n      WB_EN <= WB_EN_IN;\n      EXE_CMD <= EXE_CMD_IN;\n      dest <= destIn;\n      ST_value <= reg2In;\n      val1 <= val1In;\n      val2 <= val2In;\n      PC <= PCIn;\n      brTaken_out <= brTaken_in;\n      src1_out <= src1_in;\n      src2_out <= src2_in;\n    end\n  end\nendmodule // ID2EXE\n"
  },
  {
    "path": "modules/pipeRegisters/IF2ID.v",
    "content": "`include \"defines.v\"\n\nmodule IF2ID (clk, rst, flush, freeze, PCIn, instructionIn, PC, instruction);\n  input clk, rst, flush, freeze;\n  input [`WORD_LEN-1:0] PCIn, instructionIn;\n  output reg [`WORD_LEN-1:0] PC, instruction;\n\n  always @ (posedge clk) begin\n    if (rst) begin\n      PC <= 0;\n      instruction <= 0;\n    end\n    else begin\n      if (~freeze) begin\n        if (flush) begin\n          instruction <= 0;\n          PC <= 0;\n        end\n        else begin\n          instruction <= instructionIn;\n          PC <= PCIn;\n        end\n      end\n    end\n  end\nendmodule // IF2ID\n"
  },
  {
    "path": "modules/pipeRegisters/MEM2WB.v",
    "content": "`include \"defines.v\"\n\nmodule MEM2WB (clk, rst, WB_EN_IN, MEM_R_EN_IN, ALUResIn, memReadValIn, destIn,\n                         WB_EN,    MEM_R_EN,    ALURes,   memReadVal,   dest);\n  input clk, rst;\n  // TO BE REGISTERED FOR ID STAGE\n  input WB_EN_IN, MEM_R_EN_IN;\n  input [`REG_FILE_ADDR_LEN-1:0] destIn;\n  input [`WORD_LEN-1:0] ALUResIn, memReadValIn;\n  // REGISTERED VALUES FOR ID STAGE\n  output reg WB_EN, MEM_R_EN;\n  output reg [`REG_FILE_ADDR_LEN-1:0] dest;\n  output reg [`WORD_LEN-1:0] ALURes, memReadVal;\n\n  always @ (posedge clk) begin\n    if (rst) begin\n      {WB_EN, MEM_R_EN, dest, ALURes, memReadVal} <= 0;\n    end\n    else begin\n      WB_EN <= WB_EN_IN;\n      MEM_R_EN <= MEM_R_EN_IN;\n      dest <= destIn;\n      ALURes <= ALUResIn;\n      memReadVal <= memReadValIn;\n    end\n  end\nendmodule // MEM2WB\n"
  },
  {
    "path": "modules/pipeStages/EXEStage.v",
    "content": "`include \"defines.v\"\n\nmodule EXEStage (clk, EXE_CMD, val1_sel, val2_sel, ST_val_sel, val1, val2, ALU_res_MEM, result_WB, ST_value_in, ALUResult, ST_value_out);\n  input clk;\n  input [`FORW_SEL_LEN-1:0] val1_sel, val2_sel, ST_val_sel;\n  input [`EXE_CMD_LEN-1:0] EXE_CMD;\n  input [`WORD_LEN-1:0] val1, val2, ALU_res_MEM, result_WB, ST_value_in;\n  output [`WORD_LEN-1:0] ALUResult, ST_value_out;\n\n  wire [`WORD_LEN-1:0] ALU_val1, ALU_val2;\n\n  mux_3input #(.LENGTH(`WORD_LEN)) mux_val1 (\n    .in1(val1),\n    .in2(ALU_res_MEM),\n    .in3(result_WB),\n    .sel(val1_sel),\n    .out(ALU_val1)\n  );\n\n  mux_3input #(.LENGTH(`WORD_LEN)) mux_val2 (\n    .in1(val2),\n    .in2(ALU_res_MEM),\n    .in3(result_WB),\n    .sel(val2_sel),\n    .out(ALU_val2)\n  );\n\n  mux_3input #(.LENGTH(`WORD_LEN)) mux_ST_value (\n    .in1(ST_value_in),\n    .in2(ALU_res_MEM),\n    .in3(result_WB),\n    .sel(ST_val_sel),\n    .out(ST_value_out)\n  );\n\n  ALU ALU(\n    .val1(ALU_val1),\n    .val2(ALU_val2),\n    .EXE_CMD(EXE_CMD),\n    .aluOut(ALUResult)\n  );\nendmodule // EXEStage\n"
  },
  {
    "path": "modules/pipeStages/IDStage.v",
    "content": "`include \"defines.v\"\n\nmodule IDStage (clk, rst, hazard_detected_in, is_imm_out, ST_or_BNE_out, instruction, reg1, reg2, src1, src2_reg_file, src2_forw, val1, val2, brTaken, EXE_CMD, MEM_R_EN, MEM_W_EN, WB_EN, branch_comm);\n  input clk, rst, hazard_detected_in;\n  input [`WORD_LEN-1:0] instruction, reg1, reg2;\n  output brTaken, MEM_R_EN, MEM_W_EN, WB_EN, is_imm_out, ST_or_BNE_out;\n  output [1:0] branch_comm;\n  output [`EXE_CMD_LEN-1:0] EXE_CMD;\n  output [`REG_FILE_ADDR_LEN-1:0] src1, src2_reg_file, src2_forw;\n  output [`WORD_LEN-1:0] val1, val2;\n\n  wire CU2and, Cond2and;\n  wire [1:0] CU2Cond;\n  wire Is_Imm, ST_or_BNE;\n  wire [`WORD_LEN-1:0] signExt2Mux;\n\n  controller controller(\n    // INPUT\n    .opCode(instruction[31:26]),\n    .branchEn(CU2and),\n    // OUTPUT\n    .EXE_CMD(EXE_CMD),\n    .Branch_command(CU2Cond),\n    .Is_Imm(Is_Imm),\n    .ST_or_BNE(ST_or_BNE),\n    .WB_EN(WB_EN),\n    .MEM_R_EN(MEM_R_EN),\n    .MEM_W_EN(MEM_W_EN),\n    .hazard_detected(hazard_detected_in)\n  );\n\n  mux #(.LENGTH(`REG_FILE_ADDR_LEN)) mux_src2 ( // determins the register source 2 for register file\n    .in1(instruction[15:11]),\n    .in2(instruction[25:21]),\n    .sel(ST_or_BNE),\n    .out(src2_reg_file)\n  );\n\n  mux #(.LENGTH(`WORD_LEN)) mux_val2 ( // determins whether val2 is from the reg file or the immediate value\n    .in1(reg2),\n    .in2(signExt2Mux),\n    .sel(Is_Imm),\n    .out(val2)\n  );\n\n  mux #(.LENGTH(`REG_FILE_ADDR_LEN)) mux_src2_forw ( // determins the value of register source 2 for forwarding\n    .in1(instruction[15:11]), // src2 = instruction[15:11]\n    .in2(5'd0),\n    .sel(Is_Imm),\n    .out(src2_forw)\n  );\n\n  signExtend signExtend(\n    .in(instruction[15:0]),\n    .out(signExt2Mux)\n  );\n\n  conditionChecker conditionChecker (\n    .reg1(reg1),\n    .reg2(reg2),\n    .cuBranchComm(CU2Cond),\n    .brCond(Cond2and)\n  );\n\n  assign brTaken = CU2and && Cond2and;\n  assign val1 = reg1;\n  assign src1 = instruction[20:16];\n  assign is_imm_out = Is_Imm;\n  assign ST_or_BNE_out = ST_or_BNE;\n  assign branch_comm = CU2Cond;\nendmodule // IDStage\n"
  },
  {
    "path": "modules/pipeStages/IFStage.v",
    "content": "`include \"defines.v\"\n\nmodule IFStage (clk, rst, brTaken, brOffset, freeze, PC, instruction);\n  input clk, rst, brTaken, freeze;\n  input [`WORD_LEN-1:0] brOffset;\n  output [`WORD_LEN-1:0] PC, instruction;\n\n  wire [`WORD_LEN-1:0] adderIn1, adderOut, brOffserTimes4;\n\n  mux #(.LENGTH(`WORD_LEN)) adderInput (\n    .in1(32'd4),\n    .in2(brOffserTimes4),\n    .sel(brTaken),\n    .out(adderIn1)\n  );\n\n  adder add4 (\n    .in1(adderIn1),\n    .in2(PC),\n    .out(adderOut)\n  );\n\n  register PCReg (\n    .clk(clk),\n    .rst(rst),\n    .writeEn(~freeze),\n    .regIn(adderOut),\n    .regOut(PC)\n  );\n\n  instructionMem instructions (\n    .rst(rst),\n    .addr(PC),\n    .instruction(instruction)\n  );\n\n  assign brOffserTimes4 = brOffset << 2;\nendmodule // IFStage\n"
  },
  {
    "path": "modules/pipeStages/MEMStage.v",
    "content": "`include \"defines.v\"\n\nmodule MEMStage (clk, rst, MEM_R_EN, MEM_W_EN, ALU_res, ST_value, dataMem_out);\n  input clk, rst, MEM_R_EN, MEM_W_EN;\n  input [`WORD_LEN-1:0] ALU_res, ST_value;\n  output [`WORD_LEN-1:0]  dataMem_out;\n\n  dataMem dataMem (\n    .clk(clk),\n    .rst(rst),\n    .writeEn(MEM_W_EN),\n    .readEn(MEM_R_EN),\n    .address(ALU_res),\n    .dataIn(ST_value),\n    .dataOut(dataMem_out)\n  );\nendmodule // MEMStage\n"
  },
  {
    "path": "modules/pipeStages/WBStage.v",
    "content": "`include \"defines.v\"\n\nmodule WBStage (MEM_R_EN, memData, aluRes, WB_res);\n  input MEM_R_EN;\n  input [`WORD_LEN-1:0] memData, aluRes;\n  output [`WORD_LEN-1:0] WB_res;\n\n  assign WB_res = (MEM_R_EN) ? memData : aluRes;\nendmodule // WBStage\n"
  },
  {
    "path": "modules/register.v",
    "content": "`include \"defines.v\"\n\nmodule register (clk, rst, writeEn, regIn, regOut);\n  input clk, rst, writeEn;\n  input [`WORD_LEN-1:0] regIn;\n  output reg [`WORD_LEN-1:0] regOut;\n\n  always @ (posedge clk) begin\n    if (rst == 1) regOut <= 0;\n    else if (writeEn) regOut <= regIn;\n  end\nendmodule // register\n"
  },
  {
    "path": "modules/signExtend.v",
    "content": "`include \"defines.v\"\n\nmodule signExtend (in, out);\n  input [15:0] in;\n  output [`WORD_LEN-1:0] out;\n\n  assign out = (in[15] == 1) ? {16'b1111111111111111, in} : {16'b0000000000000000, in};\nendmodule // signExtend\n"
  },
  {
    "path": "testbench.v",
    "content": "`timescale 1ns/1ns\n\nmodule testbench ();\n  reg clk,rst, forwarding_EN;\n  MIPS_Processor top_module (clk, rst, forwarding_EN);\n\n  initial begin\n    clk=1;\n    repeat(5000) #50 clk=~clk ;\n  end\n\n  initial begin\n    rst = 1;\n    forwarding_EN = 0;\n    #100\n    rst = 0;\n  end\nendmodule // test\n"
  },
  {
    "path": "topLevelCircuit.v",
    "content": "`include \"defines.v\"\n\nmodule MIPS_Processor (input CLOCK_50, input rst, input forward_EN);\n\twire clock = CLOCK_50;\n\twire [`WORD_LEN-1:0] PC_IF, PC_ID, PC_EXE, PC_MEM;\n\twire [`WORD_LEN-1:0] inst_IF, inst_ID;\n\twire [`WORD_LEN-1:0] reg1_ID, reg2_ID, ST_value_EXE, ST_value_EXE2MEM, ST_value_MEM;\n\twire [`WORD_LEN-1:0] val1_ID, val1_EXE;\n\twire [`WORD_LEN-1:0] val2_ID, val2_EXE;\n\twire [`WORD_LEN-1:0] ALURes_EXE, ALURes_MEM, ALURes_WB;\n\twire [`WORD_LEN-1:0] dataMem_out_MEM, dataMem_out_WB;\n\twire [`WORD_LEN-1:0] WB_result;\n\twire [`REG_FILE_ADDR_LEN-1:0] dest_EXE, dest_MEM, dest_WB; // dest_ID = instruction[25:21] thus nothing declared\n\twire [`REG_FILE_ADDR_LEN-1:0] src1_ID, src2_regFile_ID, src2_forw_ID, src2_forw_EXE, src1_forw_EXE;\n\twire [`EXE_CMD_LEN-1:0] EXE_CMD_ID, EXE_CMD_EXE;\n\twire [`FORW_SEL_LEN-1:0] val1_sel, val2_sel, ST_val_sel;\n\twire [1:0] branch_comm;\n\twire Br_Taken_ID, IF_Flush, Br_Taken_EXE;\n\twire MEM_R_EN_ID, MEM_R_EN_EXE, MEM_R_EN_MEM, MEM_R_EN_WB;\n\twire MEM_W_EN_ID, MEM_W_EN_EXE, MEM_W_EN_MEM;\n\twire WB_EN_ID, WB_EN_EXE, WB_EN_MEM, WB_EN_WB;\n\twire hazard_detected, is_imm, ST_or_BNE;\n\n\tregFile regFile(\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t.src1(src1_ID),\n\t\t.src2(src2_regFile_ID),\n\t\t.dest(dest_WB),\n\t\t.writeVal(WB_result),\n\t\t.writeEn(WB_EN_WB),\n\t\t// OUTPUTS\n\t\t.reg1(reg1_ID),\n\t\t.reg2(reg2_ID)\n\t);\n\n\thazard_detection hazard (\n\t\t// INPUTS\n\t\t.forward_EN(forward_EN),\n\t\t.is_imm(is_imm),\n\t\t.ST_or_BNE(ST_or_BNE),\n\t\t.src1_ID(src1_ID),\n\t\t.src2_ID(src2_regFile_ID),\n\t\t.dest_EXE(dest_EXE),\n\t\t.dest_MEM(dest_MEM),\n\t\t.WB_EN_EXE(WB_EN_EXE),\n\t\t.WB_EN_MEM(WB_EN_MEM),\n\t\t.MEM_R_EN_EXE(MEM_R_EN_EXE),\n\t\t// OUTPUTS\n\t\t.branch_comm(branch_comm),\n\t\t.hazard_detected(hazard_detected)\n\t);\n\n\tforwarding_EXE forwrding_EXE (\n\t\t.src1_EXE(src1_forw_EXE),\n\t\t.src2_EXE(src2_forw_EXE),\n\t\t.ST_src_EXE(dest_EXE),\n\t\t.dest_MEM(dest_MEM),\n\t\t.dest_WB(dest_WB),\n\t\t.WB_EN_MEM(WB_EN_MEM),\n\t\t.WB_EN_WB(WB_EN_WB),\n\t\t.val1_sel(val1_sel),\n\t\t.val2_sel(val2_sel),\n\t\t.ST_val_sel(ST_val_sel)\n\t);\n\n\t//###########################\n\t//##### PIPLINE STAGES ######\n\t//###########################\n\tIFStage IFStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t.freeze(hazard_detected),\n\t\t.brTaken(Br_Taken_ID),\n\t\t.brOffset(val2_ID),\n\t\t// OUTPUTS\n\t\t.instruction(inst_IF),\n\t\t.PC(PC_IF)\n\t);\n\n\tIDStage IDStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t.hazard_detected_in(hazard_detected),\n\t\t.instruction(inst_ID),\n\t\t.reg1(reg1_ID),\n\t\t.reg2(reg2_ID),\n\t\t// OUTPUTS\n\t\t.src1(src1_ID),\n\t\t.src2_reg_file(src2_regFile_ID),\n\t\t.src2_forw(src2_forw_ID),\n\t\t.val1(val1_ID),\n\t\t.val2(val2_ID),\n\t\t.brTaken(Br_Taken_ID),\n\t\t.EXE_CMD(EXE_CMD_ID),\n\t\t.MEM_R_EN(MEM_R_EN_ID),\n\t\t.MEM_W_EN(MEM_W_EN_ID),\n\t\t.WB_EN(WB_EN_ID),\n\t\t.is_imm_out(is_imm),\n\t\t.ST_or_BNE_out(ST_or_BNE),\n\t\t.branch_comm(branch_comm)\n\t);\n\n\tEXEStage EXEStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.EXE_CMD(EXE_CMD_EXE),\n\t\t.val1_sel(val1_sel),\n\t\t.val2_sel(val2_sel),\n\t\t.ST_val_sel(ST_val_sel),\n\t\t.val1(val1_EXE),\n\t\t.val2(val2_EXE),\n\t\t.ALU_res_MEM(ALURes_MEM),\n\t\t.result_WB(WB_result),\n\t\t.ST_value_in(ST_value_EXE),\n\t\t// OUTPUTS\n\t\t.ALUResult(ALURes_EXE),\n\t\t.ST_value_out(ST_value_EXE2MEM)\n\t);\n\n\tMEMStage MEMStage (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t.MEM_R_EN(MEM_R_EN_MEM),\n\t\t.MEM_W_EN(MEM_W_EN_MEM),\n\t\t.ALU_res(ALURes_MEM),\n\t\t.ST_value(ST_value_MEM),\n\t\t// OUTPUTS\n\t\t.dataMem_out(dataMem_out_MEM)\n\t);\n\n\tWBStage WBStage (\n\t\t// INPUTS\n\t\t.MEM_R_EN(MEM_R_EN_WB),\n\t\t.memData(dataMem_out_WB),\n\t\t.aluRes(ALURes_WB),\n\t\t// OUTPUTS\n\t\t.WB_res(WB_result)\n\t);\n\n\t//############################\n\t//#### PIPLINE REGISTERS #####\n\t//############################\n\tIF2ID IF2IDReg (\n\t\t// INPUTS\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t.flush(IF_Flush),\n\t\t.freeze(hazard_detected),\n\t\t.PCIn(PC_IF),\n\t\t.instructionIn(inst_IF),\n\t\t// OUTPUTS\n\t\t.PC(PC_ID),\n\t\t.instruction(inst_ID)\n\t);\n\n\tID2EXE ID2EXEReg (\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t// INPUTS\n\t\t.destIn(inst_ID[25:21]),\n\t\t.src1_in(src1_ID),\n\t\t.src2_in(src2_forw_ID),\n\t\t.reg2In(reg2_ID),\n\t\t.val1In(val1_ID),\n\t\t.val2In(val2_ID),\n\t\t.PCIn(PC_ID),\n\t\t.EXE_CMD_IN(EXE_CMD_ID),\n\t\t.MEM_R_EN_IN(MEM_R_EN_ID),\n\t\t.MEM_W_EN_IN(MEM_W_EN_ID),\n\t\t.WB_EN_IN(WB_EN_ID),\n\t\t.brTaken_in(Br_Taken_ID),\n\t\t// OUTPUTS\n\t\t.src1_out(src1_forw_EXE),\n\t\t.src2_out(src2_forw_EXE),\n\t\t.dest(dest_EXE),\n\t\t.ST_value(ST_value_EXE),\n\t\t.val1(val1_EXE),\n\t\t.val2(val2_EXE),\n\t\t.PC(PC_EXE),\n\t\t.EXE_CMD(EXE_CMD_EXE),\n\t\t.MEM_R_EN(MEM_R_EN_EXE),\n\t\t.MEM_W_EN(MEM_W_EN_EXE),\n\t\t.WB_EN(WB_EN_EXE),\n\t\t.brTaken_out(Br_Taken_EXE)\n\t);\n\n\tEXE2MEM EXE2MEMReg (\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t// INPUTS\n\t\t.WB_EN_IN(WB_EN_EXE),\n\t\t.MEM_R_EN_IN(MEM_R_EN_EXE),\n\t\t.MEM_W_EN_IN(MEM_W_EN_EXE),\n\t\t.PCIn(PC_EXE),\n\t\t.ALUResIn(ALURes_EXE),\n\t\t.STValIn(ST_value_EXE2MEM),\n\t\t.destIn(dest_EXE),\n\t\t// OUTPUTS\n\t\t.WB_EN(WB_EN_MEM),\n\t\t.MEM_R_EN(MEM_R_EN_MEM),\n\t\t.MEM_W_EN(MEM_W_EN_MEM),\n\t\t.PC(PC_MEM),\n\t\t.ALURes(ALURes_MEM),\n\t\t.STVal(ST_value_MEM),\n\t\t.dest(dest_MEM)\n\t);\n\n\tMEM2WB MEM2WB(\n\t\t.clk(clock),\n\t\t.rst(rst),\n\t\t// INPUTS\n\t\t.WB_EN_IN(WB_EN_MEM),\n\t\t.MEM_R_EN_IN(MEM_R_EN_MEM),\n\t\t.ALUResIn(ALURes_MEM),\n\t\t.memReadValIn(dataMem_out_MEM),\n\t\t.destIn(dest_MEM),\n\t\t// OUTPUTS\n\t\t.WB_EN(WB_EN_WB),\n\t\t.MEM_R_EN(MEM_R_EN_WB),\n\t\t.ALURes(ALURes_WB),\n\t\t.memReadVal(dataMem_out_WB),\n\t\t.dest(dest_WB)\n\t);\n\n\tassign IF_Flush = Br_Taken_ID;\nendmodule\n"
  }
]